1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2022 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
52 #include "amd64-ravenscar-thread.h"
54 /* Note that the AMD64 architecture was previously known as x86-64.
55 The latter is (forever) engraved into the canonical system name as
56 returned by config.guess, and used as the name for the AMD64 port
57 of GNU/Linux. The BSD's have renamed their ports to amd64; they
58 don't like to shout. For GDB we prefer the amd64_-prefix over the
59 x86_64_-prefix since it's so much easier to type. */
61 /* Register information. */
63 static const char * const amd64_register_names
[] =
65 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
67 /* %r8 is indeed register number 8. */
68 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
69 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
71 /* %st0 is register number 24. */
72 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
73 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
75 /* %xmm0 is register number 40. */
76 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
77 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
81 static const char * const amd64_ymm_names
[] =
83 "ymm0", "ymm1", "ymm2", "ymm3",
84 "ymm4", "ymm5", "ymm6", "ymm7",
85 "ymm8", "ymm9", "ymm10", "ymm11",
86 "ymm12", "ymm13", "ymm14", "ymm15"
89 static const char * const amd64_ymm_avx512_names
[] =
91 "ymm16", "ymm17", "ymm18", "ymm19",
92 "ymm20", "ymm21", "ymm22", "ymm23",
93 "ymm24", "ymm25", "ymm26", "ymm27",
94 "ymm28", "ymm29", "ymm30", "ymm31"
97 static const char * const amd64_ymmh_names
[] =
99 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
100 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
101 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
102 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
105 static const char * const amd64_ymmh_avx512_names
[] =
107 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
108 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
109 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
110 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
113 static const char * const amd64_mpx_names
[] =
115 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
118 static const char * const amd64_k_names
[] =
120 "k0", "k1", "k2", "k3",
121 "k4", "k5", "k6", "k7"
124 static const char * const amd64_zmmh_names
[] =
126 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
127 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
128 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
129 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
130 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
131 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
132 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
133 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
136 static const char * const amd64_zmm_names
[] =
138 "zmm0", "zmm1", "zmm2", "zmm3",
139 "zmm4", "zmm5", "zmm6", "zmm7",
140 "zmm8", "zmm9", "zmm10", "zmm11",
141 "zmm12", "zmm13", "zmm14", "zmm15",
142 "zmm16", "zmm17", "zmm18", "zmm19",
143 "zmm20", "zmm21", "zmm22", "zmm23",
144 "zmm24", "zmm25", "zmm26", "zmm27",
145 "zmm28", "zmm29", "zmm30", "zmm31"
148 static const char * const amd64_xmm_avx512_names
[] = {
149 "xmm16", "xmm17", "xmm18", "xmm19",
150 "xmm20", "xmm21", "xmm22", "xmm23",
151 "xmm24", "xmm25", "xmm26", "xmm27",
152 "xmm28", "xmm29", "xmm30", "xmm31"
155 static const char * const amd64_pkeys_names
[] = {
159 /* DWARF Register Number Mapping as defined in the System V psABI,
162 static int amd64_dwarf_regmap
[] =
164 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
165 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
166 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
167 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
169 /* Frame Pointer Register RBP. */
172 /* Stack Pointer Register RSP. */
175 /* Extended Integer Registers 8 - 15. */
176 AMD64_R8_REGNUM
, /* %r8 */
177 AMD64_R9_REGNUM
, /* %r9 */
178 AMD64_R10_REGNUM
, /* %r10 */
179 AMD64_R11_REGNUM
, /* %r11 */
180 AMD64_R12_REGNUM
, /* %r12 */
181 AMD64_R13_REGNUM
, /* %r13 */
182 AMD64_R14_REGNUM
, /* %r14 */
183 AMD64_R15_REGNUM
, /* %r15 */
185 /* Return Address RA. Mapped to RIP. */
188 /* SSE Registers 0 - 7. */
189 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
190 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
191 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
192 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
194 /* Extended SSE Registers 8 - 15. */
195 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
196 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
197 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
198 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
200 /* Floating Point Registers 0-7. */
201 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
202 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
203 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
204 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
206 /* MMX Registers 0 - 7.
207 We have to handle those registers specifically, as their register
208 number within GDB depends on the target (or they may even not be
209 available at all). */
210 -1, -1, -1, -1, -1, -1, -1, -1,
212 /* Control and Status Flags Register. */
215 /* Selector Registers. */
225 /* Segment Base Address Registers. */
231 /* Special Selector Registers. */
235 /* Floating Point Control Registers. */
241 static const int amd64_dwarf_regmap_len
=
242 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
244 /* Convert DWARF register number REG to the appropriate register
245 number used by GDB. */
248 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
250 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
251 int ymm0_regnum
= tdep
->ymm0_regnum
;
254 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
255 regnum
= amd64_dwarf_regmap
[reg
];
258 && i386_xmm_regnum_p (gdbarch
, regnum
))
259 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
264 /* Map architectural register numbers to gdb register numbers. */
266 static const int amd64_arch_regmap
[16] =
268 AMD64_RAX_REGNUM
, /* %rax */
269 AMD64_RCX_REGNUM
, /* %rcx */
270 AMD64_RDX_REGNUM
, /* %rdx */
271 AMD64_RBX_REGNUM
, /* %rbx */
272 AMD64_RSP_REGNUM
, /* %rsp */
273 AMD64_RBP_REGNUM
, /* %rbp */
274 AMD64_RSI_REGNUM
, /* %rsi */
275 AMD64_RDI_REGNUM
, /* %rdi */
276 AMD64_R8_REGNUM
, /* %r8 */
277 AMD64_R9_REGNUM
, /* %r9 */
278 AMD64_R10_REGNUM
, /* %r10 */
279 AMD64_R11_REGNUM
, /* %r11 */
280 AMD64_R12_REGNUM
, /* %r12 */
281 AMD64_R13_REGNUM
, /* %r13 */
282 AMD64_R14_REGNUM
, /* %r14 */
283 AMD64_R15_REGNUM
/* %r15 */
286 static const int amd64_arch_regmap_len
=
287 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
293 amd64_arch_reg_to_regnum (int reg
)
295 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
297 return amd64_arch_regmap
[reg
];
300 /* Register names for byte pseudo-registers. */
302 static const char * const amd64_byte_names
[] =
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
314 static const char * const amd64_word_names
[] =
316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
320 /* Register names for dword pseudo-registers. */
322 static const char * const amd64_dword_names
[] =
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
329 /* Return the name of register REGNUM. */
332 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
334 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
335 if (i386_byte_regnum_p (gdbarch
, regnum
))
336 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
337 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
338 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
339 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
341 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
342 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
343 else if (i386_word_regnum_p (gdbarch
, regnum
))
344 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
345 else if (i386_dword_regnum_p (gdbarch
, regnum
))
346 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
348 return i386_pseudo_register_name (gdbarch
, regnum
);
351 static struct value
*
352 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
353 readable_regcache
*regcache
,
356 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
358 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
359 VALUE_LVAL (result_value
) = lval_register
;
360 VALUE_REGNUM (result_value
) = regnum
;
361 gdb_byte
*buf
= value_contents_raw (result_value
).data ();
363 if (i386_byte_regnum_p (gdbarch
, regnum
))
365 int gpnum
= regnum
- tdep
->al_regnum
;
367 /* Extract (always little endian). */
368 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
370 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
371 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
373 /* Special handling for AH, BH, CH, DH. */
374 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
375 if (status
== REG_VALID
)
376 memcpy (buf
, raw_buf
+ 1, 1);
378 mark_value_bytes_unavailable (result_value
, 0,
379 TYPE_LENGTH (value_type (result_value
)));
383 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
384 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
385 if (status
== REG_VALID
)
386 memcpy (buf
, raw_buf
, 1);
388 mark_value_bytes_unavailable (result_value
, 0,
389 TYPE_LENGTH (value_type (result_value
)));
392 else if (i386_dword_regnum_p (gdbarch
, regnum
))
394 int gpnum
= regnum
- tdep
->eax_regnum
;
395 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
396 /* Extract (always little endian). */
397 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 mark_value_bytes_unavailable (result_value
, 0,
402 TYPE_LENGTH (value_type (result_value
)));
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
418 if (i386_byte_regnum_p (gdbarch
, regnum
))
420 int gpnum
= regnum
- tdep
->al_regnum
;
422 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
424 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
425 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
427 /* Read ... AH, BH, CH, DH. */
428 regcache
->raw_read (gpnum
, raw_buf
);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf
+ 1, buf
, 1);
432 regcache
->raw_write (gpnum
, raw_buf
);
436 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
439 regcache
->raw_read (gpnum
, raw_buf
);
440 /* ... Modify ... (always little endian). */
441 memcpy (raw_buf
, buf
, 1);
443 regcache
->raw_write (gpnum
, raw_buf
);
446 else if (i386_dword_regnum_p (gdbarch
, regnum
))
448 int gpnum
= regnum
- tdep
->eax_regnum
;
449 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
452 regcache
->raw_read (gpnum
, raw_buf
);
453 /* ... Modify ... (always little endian). */
454 memcpy (raw_buf
, buf
, 4);
456 regcache
->raw_write (gpnum
, raw_buf
);
459 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
462 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
465 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
466 struct agent_expr
*ax
, int regnum
)
468 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
470 if (i386_byte_regnum_p (gdbarch
, regnum
))
472 int gpnum
= regnum
- tdep
->al_regnum
;
474 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
475 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
477 ax_reg_mask (ax
, gpnum
);
480 else if (i386_dword_regnum_p (gdbarch
, regnum
))
482 int gpnum
= regnum
- tdep
->eax_regnum
;
484 ax_reg_mask (ax
, gpnum
);
488 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
493 /* Register classes as defined in the psABI. */
507 /* Return the union class of CLASS1 and CLASS2. See the psABI for
510 static enum amd64_reg_class
511 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
513 /* Rule (a): If both classes are equal, this is the resulting class. */
514 if (class1
== class2
)
517 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
518 is the other class. */
519 if (class1
== AMD64_NO_CLASS
)
521 if (class2
== AMD64_NO_CLASS
)
524 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
525 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
528 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
529 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
530 return AMD64_INTEGER
;
532 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
533 MEMORY is used as class. */
534 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
535 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
536 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
539 /* Rule (f): Otherwise class SSE is used. */
543 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
545 /* Return true if TYPE is a structure or union with unaligned fields. */
548 amd64_has_unaligned_fields (struct type
*type
)
550 if (type
->code () == TYPE_CODE_STRUCT
551 || type
->code () == TYPE_CODE_UNION
)
553 for (int i
= 0; i
< type
->num_fields (); i
++)
555 struct type
*subtype
= check_typedef (type
->field (i
).type ());
557 /* Ignore static fields, empty fields (for example nested
558 empty structures), and bitfields (these are handled by
560 if (field_is_static (&type
->field (i
))
561 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
562 && TYPE_LENGTH (subtype
) == 0)
563 || TYPE_FIELD_PACKED (type
, i
))
566 int bitpos
= type
->field (i
).loc_bitpos ();
571 int align
= type_align (subtype
);
573 error (_("could not determine alignment of type"));
575 int bytepos
= bitpos
/ 8;
576 if (bytepos
% align
!= 0)
579 if (amd64_has_unaligned_fields (subtype
))
587 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
588 structures and union types, and store the result in THECLASS. */
591 amd64_classify_aggregate_field (struct type
*type
, int i
,
592 enum amd64_reg_class theclass
[2],
593 unsigned int bitoffset
)
595 struct type
*subtype
= check_typedef (type
->field (i
).type ());
596 enum amd64_reg_class subclass
[2];
597 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
600 bitsize
= TYPE_LENGTH (subtype
) * 8;
602 /* Ignore static fields, or empty fields, for example nested
604 if (field_is_static (&type
->field (i
)) || bitsize
== 0)
607 int bitpos
= bitoffset
+ type
->field (i
).loc_bitpos ();
608 int pos
= bitpos
/ 64;
609 int endpos
= (bitpos
+ bitsize
- 1) / 64;
611 if (subtype
->code () == TYPE_CODE_STRUCT
612 || subtype
->code () == TYPE_CODE_UNION
)
614 /* Each field of an object is classified recursively. */
616 for (j
= 0; j
< subtype
->num_fields (); j
++)
617 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
621 gdb_assert (pos
== 0 || pos
== 1);
623 amd64_classify (subtype
, subclass
);
624 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
625 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
626 /* This is a bit of an odd case: We have a field that would
627 normally fit in one of the two eightbytes, except that
628 it is placed in a way that this field straddles them.
629 This has been seen with a structure containing an array.
631 The ABI is a bit unclear in this case, but we assume that
632 this field's class (stored in subclass[0]) must also be merged
633 into class[1]. In other words, our field has a piece stored
634 in the second eight-byte, and thus its class applies to
635 the second eight-byte as well.
637 In the case where the field length exceeds 8 bytes,
638 it should not be necessary to merge the field class
639 into class[1]. As LEN > 8, subclass[1] is necessarily
640 different from AMD64_NO_CLASS. If subclass[1] is equal
641 to subclass[0], then the normal class[1]/subclass[1]
642 merging will take care of everything. For subclass[1]
643 to be different from subclass[0], I can only see the case
644 where we have a SSE/SSEUP or X87/X87UP pair, which both
645 use up all 16 bytes of the aggregate, and are already
646 handled just fine (because each portion sits on its own
648 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
650 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
653 /* Classify TYPE according to the rules for aggregate (structures and
654 arrays) and union types, and store the result in CLASS. */
657 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
659 /* 1. If the size of an object is larger than two times eight bytes, or
660 it is a non-trivial C++ object, or it has unaligned fields, then it
663 It is important that the trivially_copyable check is before the
664 unaligned fields check, as C++ classes with virtual base classes
665 will have fields (for the virtual base classes) with non-constant
666 loc_bitpos attributes, which will cause an assert to trigger within
667 the unaligned field check. As classes with virtual bases are not
668 trivially copyable, checking that first avoids this problem. */
669 if (TYPE_LENGTH (type
) > 16
670 || !language_pass_by_reference (type
).trivially_copyable
671 || amd64_has_unaligned_fields (type
))
673 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
677 /* 2. Both eightbytes get initialized to class NO_CLASS. */
678 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
680 /* 3. Each field of an object is classified recursively so that
681 always two fields are considered. The resulting class is
682 calculated according to the classes of the fields in the
685 if (type
->code () == TYPE_CODE_ARRAY
)
687 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
689 /* All fields in an array have the same type. */
690 amd64_classify (subtype
, theclass
);
691 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
692 theclass
[1] = theclass
[0];
698 /* Structure or union. */
699 gdb_assert (type
->code () == TYPE_CODE_STRUCT
700 || type
->code () == TYPE_CODE_UNION
);
702 for (i
= 0; i
< type
->num_fields (); i
++)
703 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
706 /* 4. Then a post merger cleanup is done: */
708 /* Rule (a): If one of the classes is MEMORY, the whole argument is
710 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
711 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
713 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
715 if (theclass
[0] == AMD64_SSEUP
)
716 theclass
[0] = AMD64_SSE
;
717 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
718 theclass
[1] = AMD64_SSE
;
721 /* Classify TYPE, and store the result in CLASS. */
724 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
726 enum type_code code
= type
->code ();
727 int len
= TYPE_LENGTH (type
);
729 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
731 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
732 long, long long, and pointers are in the INTEGER class. Similarly,
733 range types, used by languages such as Ada, are also in the INTEGER
735 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
736 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
737 || code
== TYPE_CODE_CHAR
738 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
739 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
740 theclass
[0] = AMD64_INTEGER
;
742 /* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and
743 __m64 are in class SSE. */
744 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
745 && (len
== 2 || len
== 4 || len
== 8))
747 theclass
[0] = AMD64_SSE
;
749 /* Arguments of types __float128, _Decimal128 and __m128 are split into
750 two halves. The least significant ones belong to class SSE, the most
751 significant one to class SSEUP. */
752 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
753 /* FIXME: __float128, __m128. */
754 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
756 /* The 64-bit mantissa of arguments of type long double belongs to
757 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
759 else if (code
== TYPE_CODE_FLT
&& len
== 16)
760 /* Class X87 and X87UP. */
761 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
763 /* Arguments of complex T - where T is one of the types _Float16, float or
764 double - get treated as if they are implemented as:
772 else if (code
== TYPE_CODE_COMPLEX
&& (len
== 8 || len
== 4))
773 theclass
[0] = AMD64_SSE
;
774 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
775 theclass
[0] = theclass
[1] = AMD64_SSE
;
777 /* A variable of type complex long double is classified as type
779 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
780 theclass
[0] = AMD64_COMPLEX_X87
;
783 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
784 || code
== TYPE_CODE_UNION
)
785 amd64_classify_aggregate (type
, theclass
);
788 static enum return_value_convention
789 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
790 struct type
*type
, struct regcache
*regcache
,
791 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
793 enum amd64_reg_class theclass
[2];
794 int len
= TYPE_LENGTH (type
);
795 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
796 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
801 gdb_assert (!(readbuf
&& writebuf
));
803 /* 1. Classify the return type with the classification algorithm. */
804 amd64_classify (type
, theclass
);
806 /* 2. If the type has class MEMORY, then the caller provides space
807 for the return value and passes the address of this storage in
808 %rdi as if it were the first argument to the function. In effect,
809 this address becomes a hidden first argument.
811 On return %rax will contain the address that has been passed in
812 by the caller in %rdi. */
813 if (theclass
[0] == AMD64_MEMORY
)
815 /* As indicated by the comment above, the ABI guarantees that we
816 can always find the return value just after the function has
823 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
824 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
827 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
830 /* 8. If the class is COMPLEX_X87, the real part of the value is
831 returned in %st0 and the imaginary part in %st1. */
832 if (theclass
[0] == AMD64_COMPLEX_X87
)
836 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
837 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
842 i387_return_value (gdbarch
, regcache
);
843 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
844 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
846 /* Fix up the tag word such that both %st(0) and %st(1) are
848 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
851 return RETURN_VALUE_REGISTER_CONVENTION
;
854 gdb_assert (theclass
[1] != AMD64_MEMORY
);
855 gdb_assert (len
<= 16);
857 for (i
= 0; len
> 0; i
++, len
-= 8)
865 /* 3. If the class is INTEGER, the next available register
866 of the sequence %rax, %rdx is used. */
867 regnum
= integer_regnum
[integer_reg
++];
871 /* 4. If the class is SSE, the next available SSE register
872 of the sequence %xmm0, %xmm1 is used. */
873 regnum
= sse_regnum
[sse_reg
++];
877 /* 5. If the class is SSEUP, the eightbyte is passed in the
878 upper half of the last used SSE register. */
879 gdb_assert (sse_reg
> 0);
880 regnum
= sse_regnum
[sse_reg
- 1];
885 /* 6. If the class is X87, the value is returned on the X87
886 stack in %st0 as 80-bit x87 number. */
887 regnum
= AMD64_ST0_REGNUM
;
889 i387_return_value (gdbarch
, regcache
);
893 /* 7. If the class is X87UP, the value is returned together
894 with the previous X87 value in %st0. */
895 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
896 regnum
= AMD64_ST0_REGNUM
;
905 gdb_assert (!"Unexpected register class.");
908 gdb_assert (regnum
!= -1);
911 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
914 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
918 return RETURN_VALUE_REGISTER_CONVENTION
;
923 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
924 CORE_ADDR sp
, function_call_return_method return_method
)
926 static int integer_regnum
[] =
928 AMD64_RDI_REGNUM
, /* %rdi */
929 AMD64_RSI_REGNUM
, /* %rsi */
930 AMD64_RDX_REGNUM
, /* %rdx */
931 AMD64_RCX_REGNUM
, /* %rcx */
932 AMD64_R8_REGNUM
, /* %r8 */
933 AMD64_R9_REGNUM
/* %r9 */
935 static int sse_regnum
[] =
937 /* %xmm0 ... %xmm7 */
938 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
939 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
940 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
941 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
943 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
944 int num_stack_args
= 0;
945 int num_elements
= 0;
951 /* Reserve a register for the "hidden" argument. */
952 if (return_method
== return_method_struct
)
955 for (i
= 0; i
< nargs
; i
++)
957 struct type
*type
= value_type (args
[i
]);
958 int len
= TYPE_LENGTH (type
);
959 enum amd64_reg_class theclass
[2];
960 int needed_integer_regs
= 0;
961 int needed_sse_regs
= 0;
964 /* Classify argument. */
965 amd64_classify (type
, theclass
);
967 /* Calculate the number of integer and SSE registers needed for
969 for (j
= 0; j
< 2; j
++)
971 if (theclass
[j
] == AMD64_INTEGER
)
972 needed_integer_regs
++;
973 else if (theclass
[j
] == AMD64_SSE
)
977 /* Check whether enough registers are available, and if the
978 argument should be passed in registers at all. */
979 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
980 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
981 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
983 /* The argument will be passed on the stack. */
984 num_elements
+= ((len
+ 7) / 8);
985 stack_args
[num_stack_args
++] = args
[i
];
989 /* The argument will be passed in registers. */
990 const gdb_byte
*valbuf
= value_contents (args
[i
]).data ();
993 gdb_assert (len
<= 16);
995 for (j
= 0; len
> 0; j
++, len
-= 8)
1000 switch (theclass
[j
])
1003 regnum
= integer_regnum
[integer_reg
++];
1007 regnum
= sse_regnum
[sse_reg
++];
1011 gdb_assert (sse_reg
> 0);
1012 regnum
= sse_regnum
[sse_reg
- 1];
1016 case AMD64_NO_CLASS
:
1020 gdb_assert (!"Unexpected register class.");
1023 gdb_assert (regnum
!= -1);
1024 memset (buf
, 0, sizeof buf
);
1025 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1026 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1031 /* Allocate space for the arguments on the stack. */
1032 sp
-= num_elements
* 8;
1034 /* The psABI says that "The end of the input argument area shall be
1035 aligned on a 16 byte boundary." */
1038 /* Write out the arguments to the stack. */
1039 for (i
= 0; i
< num_stack_args
; i
++)
1041 struct type
*type
= value_type (stack_args
[i
]);
1042 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]).data ();
1043 int len
= TYPE_LENGTH (type
);
1045 write_memory (sp
+ element
* 8, valbuf
, len
);
1046 element
+= ((len
+ 7) / 8);
1049 /* The psABI says that "For calls that may call functions that use
1050 varargs or stdargs (prototype-less calls or calls to functions
1051 containing ellipsis (...) in the declaration) %al is used as
1052 hidden argument to specify the number of SSE registers used. */
1053 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1058 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1059 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1060 int nargs
, struct value
**args
, CORE_ADDR sp
,
1061 function_call_return_method return_method
,
1062 CORE_ADDR struct_addr
)
1064 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1067 /* BND registers can be in arbitrary values at the moment of the
1068 inferior call. This can cause boundary violations that are not
1069 due to a real bug or even desired by the user. The best to be done
1070 is set the BND registers to allow access to the whole memory, INIT
1071 state, before pushing the inferior call. */
1072 i387_reset_bnd_regs (gdbarch
, regcache
);
1074 /* Pass arguments. */
1075 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1077 /* Pass "hidden" argument". */
1078 if (return_method
== return_method_struct
)
1080 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1081 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1084 /* Store return address. */
1086 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1087 write_memory (sp
, buf
, 8);
1089 /* Finally, update the stack pointer... */
1090 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1091 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1093 /* ...and fake a frame pointer. */
1094 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1099 /* Displaced instruction handling. */
1101 /* A partially decoded instruction.
1102 This contains enough details for displaced stepping purposes. */
1106 /* The number of opcode bytes. */
1108 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1110 int enc_prefix_offset
;
1111 /* The offset to the first opcode byte. */
1113 /* The offset to the modrm byte or -1 if not present. */
1116 /* The raw instruction. */
1120 struct amd64_displaced_step_copy_insn_closure
1121 : public displaced_step_copy_insn_closure
1123 amd64_displaced_step_copy_insn_closure (int insn_buf_len
)
1124 : insn_buf (insn_buf_len
, 0)
1127 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1132 /* Details of the instruction. */
1133 struct amd64_insn insn_details
;
1135 /* The possibly modified insn. */
1136 gdb::byte_vector insn_buf
;
1139 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1140 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1141 at which point delete these in favor of libopcodes' versions). */
1143 static const unsigned char onebyte_has_modrm
[256] = {
1144 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1145 /* ------------------------------- */
1146 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1147 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1148 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1149 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1150 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1151 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1152 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1153 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1154 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1155 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1156 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1157 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1158 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1159 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1160 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1161 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1162 /* ------------------------------- */
1163 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1166 static const unsigned char twobyte_has_modrm
[256] = {
1167 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1168 /* ------------------------------- */
1169 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1170 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1171 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1172 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1173 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1174 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1175 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1176 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1177 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1178 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1179 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1180 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1181 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1182 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1183 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1184 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1185 /* ------------------------------- */
1186 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1189 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1192 rex_prefix_p (gdb_byte pfx
)
1194 return REX_PREFIX_P (pfx
);
1197 /* True if PFX is the start of the 2-byte VEX prefix. */
1200 vex2_prefix_p (gdb_byte pfx
)
1205 /* True if PFX is the start of the 3-byte VEX prefix. */
1208 vex3_prefix_p (gdb_byte pfx
)
1213 /* Skip the legacy instruction prefixes in INSN.
1214 We assume INSN is properly sentineled so we don't have to worry
1215 about falling off the end of the buffer. */
1218 amd64_skip_prefixes (gdb_byte
*insn
)
1224 case DATA_PREFIX_OPCODE
:
1225 case ADDR_PREFIX_OPCODE
:
1226 case CS_PREFIX_OPCODE
:
1227 case DS_PREFIX_OPCODE
:
1228 case ES_PREFIX_OPCODE
:
1229 case FS_PREFIX_OPCODE
:
1230 case GS_PREFIX_OPCODE
:
1231 case SS_PREFIX_OPCODE
:
1232 case LOCK_PREFIX_OPCODE
:
1233 case REPE_PREFIX_OPCODE
:
1234 case REPNE_PREFIX_OPCODE
:
1246 /* Return an integer register (other than RSP) that is unused as an input
1248 In order to not require adding a rex prefix if the insn doesn't already
1249 have one, the result is restricted to RAX ... RDI, sans RSP.
1250 The register numbering of the result follows architecture ordering,
1254 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1256 /* 1 bit for each reg */
1257 int used_regs_mask
= 0;
1259 /* There can be at most 3 int regs used as inputs in an insn, and we have
1260 7 to choose from (RAX ... RDI, sans RSP).
1261 This allows us to take a conservative approach and keep things simple.
1262 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1263 that implicitly specify RAX. */
1266 used_regs_mask
|= 1 << EAX_REG_NUM
;
1267 /* Similarily avoid RDX, implicit operand in divides. */
1268 used_regs_mask
|= 1 << EDX_REG_NUM
;
1270 used_regs_mask
|= 1 << ESP_REG_NUM
;
1272 /* If the opcode is one byte long and there's no ModRM byte,
1273 assume the opcode specifies a register. */
1274 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1275 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1277 /* Mark used regs in the modrm/sib bytes. */
1278 if (details
->modrm_offset
!= -1)
1280 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1281 int mod
= MODRM_MOD_FIELD (modrm
);
1282 int reg
= MODRM_REG_FIELD (modrm
);
1283 int rm
= MODRM_RM_FIELD (modrm
);
1284 int have_sib
= mod
!= 3 && rm
== 4;
1286 /* Assume the reg field of the modrm byte specifies a register. */
1287 used_regs_mask
|= 1 << reg
;
1291 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1292 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1293 used_regs_mask
|= 1 << base
;
1294 used_regs_mask
|= 1 << idx
;
1298 used_regs_mask
|= 1 << rm
;
1302 gdb_assert (used_regs_mask
< 256);
1303 gdb_assert (used_regs_mask
!= 255);
1305 /* Finally, find a free reg. */
1309 for (i
= 0; i
< 8; ++i
)
1311 if (! (used_regs_mask
& (1 << i
)))
1315 /* We shouldn't get here. */
1316 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1320 /* Extract the details of INSN that we need. */
1323 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1325 gdb_byte
*start
= insn
;
1328 details
->raw_insn
= insn
;
1330 details
->opcode_len
= -1;
1331 details
->enc_prefix_offset
= -1;
1332 details
->opcode_offset
= -1;
1333 details
->modrm_offset
= -1;
1335 /* Skip legacy instruction prefixes. */
1336 insn
= amd64_skip_prefixes (insn
);
1338 /* Skip REX/VEX instruction encoding prefixes. */
1339 if (rex_prefix_p (*insn
))
1341 details
->enc_prefix_offset
= insn
- start
;
1344 else if (vex2_prefix_p (*insn
))
1346 /* Don't record the offset in this case because this prefix has
1347 no REX.B equivalent. */
1350 else if (vex3_prefix_p (*insn
))
1352 details
->enc_prefix_offset
= insn
- start
;
1356 details
->opcode_offset
= insn
- start
;
1358 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1360 /* Two or three-byte opcode. */
1362 need_modrm
= twobyte_has_modrm
[*insn
];
1364 /* Check for three-byte opcode. */
1374 details
->opcode_len
= 3;
1377 details
->opcode_len
= 2;
1383 /* One-byte opcode. */
1384 need_modrm
= onebyte_has_modrm
[*insn
];
1385 details
->opcode_len
= 1;
1391 details
->modrm_offset
= insn
- start
;
1395 /* Update %rip-relative addressing in INSN.
1397 %rip-relative addressing only uses a 32-bit displacement.
1398 32 bits is not enough to be guaranteed to cover the distance between where
1399 the real instruction is and where its copy is.
1400 Convert the insn to use base+disp addressing.
1401 We set base = pc + insn_length so we can leave disp unchanged. */
1404 fixup_riprel (struct gdbarch
*gdbarch
,
1405 amd64_displaced_step_copy_insn_closure
*dsc
,
1406 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1408 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1409 int modrm_offset
= insn_details
->modrm_offset
;
1410 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1413 int arch_tmp_regno
, tmp_regno
;
1414 ULONGEST orig_value
;
1416 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1419 /* Compute the rip-relative address. */
1420 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1421 dsc
->insn_buf
.size (), from
);
1422 rip_base
= from
+ insn_length
;
1424 /* We need a register to hold the address.
1425 Pick one not used in the insn.
1426 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1427 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1428 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1430 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1431 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1433 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1434 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1436 if (insn_details
->enc_prefix_offset
!= -1)
1438 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1439 if (rex_prefix_p (pfx
[0]))
1441 else if (vex3_prefix_p (pfx
[0]))
1442 pfx
[1] |= VEX3_NOT_B
;
1444 gdb_assert_not_reached ("unhandled prefix");
1447 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1448 dsc
->tmp_regno
= tmp_regno
;
1449 dsc
->tmp_save
= orig_value
;
1452 /* Convert the ModRM field to be base+disp. */
1453 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1454 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1456 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1458 displaced_debug_printf ("%%rip-relative addressing used.");
1459 displaced_debug_printf ("using temp reg %d, old value %s, new value %s",
1460 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1461 paddress (gdbarch
, rip_base
));
1465 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1466 amd64_displaced_step_copy_insn_closure
*dsc
,
1467 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1469 const struct amd64_insn
*details
= &dsc
->insn_details
;
1471 if (details
->modrm_offset
!= -1)
1473 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1475 if ((modrm
& 0xc7) == 0x05)
1477 /* The insn uses rip-relative addressing.
1479 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1484 displaced_step_copy_insn_closure_up
1485 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1486 CORE_ADDR from
, CORE_ADDR to
,
1487 struct regcache
*regs
)
1489 int len
= gdbarch_max_insn_length (gdbarch
);
1490 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1491 continually watch for running off the end of the buffer. */
1492 int fixup_sentinel_space
= len
;
1493 std::unique_ptr
<amd64_displaced_step_copy_insn_closure
> dsc
1494 (new amd64_displaced_step_copy_insn_closure (len
+ fixup_sentinel_space
));
1495 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1496 struct amd64_insn
*details
= &dsc
->insn_details
;
1498 read_memory (from
, buf
, len
);
1500 /* Set up the sentinel space so we don't have to worry about running
1501 off the end of the buffer. An excessive number of leading prefixes
1502 could otherwise cause this. */
1503 memset (buf
+ len
, 0, fixup_sentinel_space
);
1505 amd64_get_insn_details (buf
, details
);
1507 /* GDB may get control back after the insn after the syscall.
1508 Presumably this is a kernel bug.
1509 If this is a syscall, make sure there's a nop afterwards. */
1513 if (amd64_syscall_p (details
, &syscall_length
))
1514 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1517 /* Modify the insn to cope with the address where it will be executed from.
1518 In particular, handle any rip-relative addressing. */
1519 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1521 write_memory (to
, buf
, len
);
1523 displaced_debug_printf ("copy %s->%s: %s",
1524 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1525 displaced_step_dump_bytes (buf
, len
).c_str ());
1527 /* This is a work around for a problem with g++ 4.8. */
1528 return displaced_step_copy_insn_closure_up (dsc
.release ());
1532 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1534 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1536 if (insn
[0] == 0xff)
1538 /* jump near, absolute indirect (/4) */
1539 if ((insn
[1] & 0x38) == 0x20)
1542 /* jump far, absolute indirect (/5) */
1543 if ((insn
[1] & 0x38) == 0x28)
1550 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1553 amd64_jmp_p (const struct amd64_insn
*details
)
1555 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1557 /* jump short, relative. */
1558 if (insn
[0] == 0xeb)
1561 /* jump near, relative. */
1562 if (insn
[0] == 0xe9)
1565 return amd64_absolute_jmp_p (details
);
1569 amd64_absolute_call_p (const struct amd64_insn
*details
)
1571 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1573 if (insn
[0] == 0xff)
1575 /* Call near, absolute indirect (/2) */
1576 if ((insn
[1] & 0x38) == 0x10)
1579 /* Call far, absolute indirect (/3) */
1580 if ((insn
[1] & 0x38) == 0x18)
1588 amd64_ret_p (const struct amd64_insn
*details
)
1590 /* NOTE: gcc can emit "repz ; ret". */
1591 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1595 case 0xc2: /* ret near, pop N bytes */
1596 case 0xc3: /* ret near */
1597 case 0xca: /* ret far, pop N bytes */
1598 case 0xcb: /* ret far */
1599 case 0xcf: /* iret */
1608 amd64_call_p (const struct amd64_insn
*details
)
1610 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1612 if (amd64_absolute_call_p (details
))
1615 /* call near, relative */
1616 if (insn
[0] == 0xe8)
1622 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1623 length in bytes. Otherwise, return zero. */
1626 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1628 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1630 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1639 /* Classify the instruction at ADDR using PRED.
1640 Throw an error if the memory can't be read. */
1643 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1644 int (*pred
) (const struct amd64_insn
*))
1646 struct amd64_insn details
;
1648 int len
, classification
;
1650 len
= gdbarch_max_insn_length (gdbarch
);
1651 buf
= (gdb_byte
*) alloca (len
);
1653 read_code (addr
, buf
, len
);
1654 amd64_get_insn_details (buf
, &details
);
1656 classification
= pred (&details
);
1658 return classification
;
1661 /* The gdbarch insn_is_call method. */
1664 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1666 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1669 /* The gdbarch insn_is_ret method. */
1672 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1674 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1677 /* The gdbarch insn_is_jump method. */
1680 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1682 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1685 /* Fix up the state of registers and memory after having single-stepped
1686 a displaced instruction. */
1689 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1690 struct displaced_step_copy_insn_closure
*dsc_
,
1691 CORE_ADDR from
, CORE_ADDR to
,
1692 struct regcache
*regs
)
1694 amd64_displaced_step_copy_insn_closure
*dsc
1695 = (amd64_displaced_step_copy_insn_closure
*) dsc_
;
1696 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1697 /* The offset we applied to the instruction's address. */
1698 ULONGEST insn_offset
= to
- from
;
1699 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1700 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1702 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
1703 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1706 /* If we used a tmp reg, restore it. */
1710 displaced_debug_printf ("restoring reg %d to %s",
1711 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1712 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1715 /* The list of issues to contend with here is taken from
1716 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1717 Yay for Free Software! */
1719 /* Relocate the %rip back to the program's instruction stream,
1722 /* Except in the case of absolute or indirect jump or call
1723 instructions, or a return instruction, the new rip is relative to
1724 the displaced instruction; make it relative to the original insn.
1725 Well, signal handler returns don't need relocation either, but we use the
1726 value of %rip to recognize those; see below. */
1727 if (! amd64_absolute_jmp_p (insn_details
)
1728 && ! amd64_absolute_call_p (insn_details
)
1729 && ! amd64_ret_p (insn_details
))
1734 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1736 /* A signal trampoline system call changes the %rip, resuming
1737 execution of the main program after the signal handler has
1738 returned. That makes them like 'return' instructions; we
1739 shouldn't relocate %rip.
1741 But most system calls don't, and we do need to relocate %rip.
1743 Our heuristic for distinguishing these cases: if stepping
1744 over the system call instruction left control directly after
1745 the instruction, the we relocate --- control almost certainly
1746 doesn't belong in the displaced copy. Otherwise, we assume
1747 the instruction has put control where it belongs, and leave
1748 it unrelocated. Goodness help us if there are PC-relative
1750 if (amd64_syscall_p (insn_details
, &insn_len
)
1751 && orig_rip
!= to
+ insn_len
1752 /* GDB can get control back after the insn after the syscall.
1753 Presumably this is a kernel bug.
1754 Fixup ensures its a nop, we add one to the length for it. */
1755 && orig_rip
!= to
+ insn_len
+ 1)
1756 displaced_debug_printf ("syscall changed %%rip; not relocating");
1759 ULONGEST rip
= orig_rip
- insn_offset
;
1761 /* If we just stepped over a breakpoint insn, we don't backup
1762 the pc on purpose; this is to match behaviour without
1765 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1767 displaced_debug_printf ("relocated %%rip from %s to %s",
1768 paddress (gdbarch
, orig_rip
),
1769 paddress (gdbarch
, rip
));
1773 /* If the instruction was PUSHFL, then the TF bit will be set in the
1774 pushed value, and should be cleared. We'll leave this for later,
1775 since GDB already messes up the TF flag when stepping over a
1778 /* If the instruction was a call, the return address now atop the
1779 stack is the address following the copied instruction. We need
1780 to make it the address following the original instruction. */
1781 if (amd64_call_p (insn_details
))
1785 const ULONGEST retaddr_len
= 8;
1787 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1788 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1789 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1790 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1792 displaced_debug_printf ("relocated return addr at %s to %s",
1793 paddress (gdbarch
, rsp
),
1794 paddress (gdbarch
, retaddr
));
1798 /* If the instruction INSN uses RIP-relative addressing, return the
1799 offset into the raw INSN where the displacement to be adjusted is
1800 found. Returns 0 if the instruction doesn't use RIP-relative
1804 rip_relative_offset (struct amd64_insn
*insn
)
1806 if (insn
->modrm_offset
!= -1)
1808 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1810 if ((modrm
& 0xc7) == 0x05)
1812 /* The displacement is found right after the ModRM byte. */
1813 return insn
->modrm_offset
+ 1;
1821 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1823 target_write_memory (*to
, buf
, len
);
1828 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1829 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1831 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1832 int len
= gdbarch_max_insn_length (gdbarch
);
1833 /* Extra space for sentinels. */
1834 int fixup_sentinel_space
= len
;
1835 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1836 struct amd64_insn insn_details
;
1838 LONGEST rel32
, newrel
;
1842 read_memory (oldloc
, buf
, len
);
1844 /* Set up the sentinel space so we don't have to worry about running
1845 off the end of the buffer. An excessive number of leading prefixes
1846 could otherwise cause this. */
1847 memset (buf
+ len
, 0, fixup_sentinel_space
);
1850 amd64_get_insn_details (insn
, &insn_details
);
1852 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1854 /* Skip legacy instruction prefixes. */
1855 insn
= amd64_skip_prefixes (insn
);
1857 /* Adjust calls with 32-bit relative addresses as push/jump, with
1858 the address pushed being the location where the original call in
1859 the user program would return to. */
1860 if (insn
[0] == 0xe8)
1862 gdb_byte push_buf
[32];
1866 /* Where "ret" in the original code will return to. */
1867 ret_addr
= oldloc
+ insn_length
;
1869 /* If pushing an address higher than or equal to 0x80000000,
1870 avoid 'pushq', as that sign extends its 32-bit operand, which
1871 would be incorrect. */
1872 if (ret_addr
<= 0x7fffffff)
1874 push_buf
[0] = 0x68; /* pushq $... */
1875 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1880 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1881 push_buf
[i
++] = 0x83;
1882 push_buf
[i
++] = 0xec;
1883 push_buf
[i
++] = 0x08;
1885 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1886 push_buf
[i
++] = 0x04;
1887 push_buf
[i
++] = 0x24;
1888 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1889 ret_addr
& 0xffffffff);
1892 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1893 push_buf
[i
++] = 0x44;
1894 push_buf
[i
++] = 0x24;
1895 push_buf
[i
++] = 0x04;
1896 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1900 gdb_assert (i
<= sizeof (push_buf
));
1901 /* Push the push. */
1902 append_insns (to
, i
, push_buf
);
1904 /* Convert the relative call to a relative jump. */
1907 /* Adjust the destination offset. */
1908 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1909 newrel
= (oldloc
- *to
) + rel32
;
1910 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1912 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1913 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1914 hex_string (newrel
), paddress (gdbarch
, *to
));
1916 /* Write the adjusted jump into its displaced location. */
1917 append_insns (to
, 5, insn
);
1921 offset
= rip_relative_offset (&insn_details
);
1924 /* Adjust jumps with 32-bit relative addresses. Calls are
1925 already handled above. */
1926 if (insn
[0] == 0xe9)
1928 /* Adjust conditional jumps. */
1929 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1935 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1936 newrel
= (oldloc
- *to
) + rel32
;
1937 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1938 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1939 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1940 hex_string (newrel
), paddress (gdbarch
, *to
));
1943 /* Write the adjusted instruction into its displaced location. */
1944 append_insns (to
, insn_length
, buf
);
1948 /* The maximum number of saved registers. This should include %rip. */
1949 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1951 struct amd64_frame_cache
1956 CORE_ADDR sp_offset
;
1959 /* Saved registers. */
1960 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1964 /* Do we have a frame? */
1968 /* Initialize a frame cache. */
1971 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1978 cache
->sp_offset
= -8;
1981 /* Saved registers. We initialize these to -1 since zero is a valid
1982 offset (that's where %rbp is supposed to be stored).
1983 The values start out as being offsets, and are later converted to
1984 addresses (at which point -1 is interpreted as an address, still meaning
1986 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1987 cache
->saved_regs
[i
] = -1;
1988 cache
->saved_sp
= 0;
1989 cache
->saved_sp_reg
= -1;
1991 /* Frameless until proven otherwise. */
1992 cache
->frameless_p
= 1;
1995 /* Allocate and initialize a frame cache. */
1997 static struct amd64_frame_cache
*
1998 amd64_alloc_frame_cache (void)
2000 struct amd64_frame_cache
*cache
;
2002 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
2003 amd64_init_frame_cache (cache
);
2007 /* GCC 4.4 and later, can put code in the prologue to realign the
2008 stack pointer. Check whether PC points to such code, and update
2009 CACHE accordingly. Return the first instruction after the code
2010 sequence or CURRENT_PC, whichever is smaller. If we don't
2011 recognize the code, return PC. */
2014 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2015 struct amd64_frame_cache
*cache
)
2017 /* There are 2 code sequences to re-align stack before the frame
2020 1. Use a caller-saved saved register:
2026 2. Use a callee-saved saved register:
2033 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2035 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2036 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2041 int offset
, offset_and
;
2043 if (target_read_code (pc
, buf
, sizeof buf
))
2046 /* Check caller-saved saved register. The first instruction has
2047 to be "leaq 8(%rsp), %reg". */
2048 if ((buf
[0] & 0xfb) == 0x48
2053 /* MOD must be binary 10 and R/M must be binary 100. */
2054 if ((buf
[2] & 0xc7) != 0x44)
2057 /* REG has register number. */
2058 reg
= (buf
[2] >> 3) & 7;
2060 /* Check the REX.R bit. */
2068 /* Check callee-saved saved register. The first instruction
2069 has to be "pushq %reg". */
2071 if ((buf
[0] & 0xf8) == 0x50)
2073 else if ((buf
[0] & 0xf6) == 0x40
2074 && (buf
[1] & 0xf8) == 0x50)
2076 /* Check the REX.B bit. */
2077 if ((buf
[0] & 1) != 0)
2086 reg
+= buf
[offset
] & 0x7;
2090 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2091 if ((buf
[offset
] & 0xfb) != 0x48
2092 || buf
[offset
+ 1] != 0x8d
2093 || buf
[offset
+ 3] != 0x24
2094 || buf
[offset
+ 4] != 0x10)
2097 /* MOD must be binary 10 and R/M must be binary 100. */
2098 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2101 /* REG has register number. */
2102 r
= (buf
[offset
+ 2] >> 3) & 7;
2104 /* Check the REX.R bit. */
2105 if (buf
[offset
] == 0x4c)
2108 /* Registers in pushq and leaq have to be the same. */
2115 /* Rigister can't be %rsp nor %rbp. */
2116 if (reg
== 4 || reg
== 5)
2119 /* The next instruction has to be "andq $-XXX, %rsp". */
2120 if (buf
[offset
] != 0x48
2121 || buf
[offset
+ 2] != 0xe4
2122 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2125 offset_and
= offset
;
2126 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2128 /* The next instruction has to be "pushq -8(%reg)". */
2130 if (buf
[offset
] == 0xff)
2132 else if ((buf
[offset
] & 0xf6) == 0x40
2133 && buf
[offset
+ 1] == 0xff)
2135 /* Check the REX.B bit. */
2136 if ((buf
[offset
] & 0x1) != 0)
2143 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2145 if (buf
[offset
+ 1] != 0xf8
2146 || (buf
[offset
] & 0xf8) != 0x70)
2149 /* R/M has register. */
2150 r
+= buf
[offset
] & 7;
2152 /* Registers in leaq and pushq have to be the same. */
2156 if (current_pc
> pc
+ offset_and
)
2157 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2159 return std::min (pc
+ offset
+ 2, current_pc
);
2162 /* Similar to amd64_analyze_stack_align for x32. */
2165 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2166 struct amd64_frame_cache
*cache
)
2168 /* There are 2 code sequences to re-align stack before the frame
2171 1. Use a caller-saved saved register:
2179 [addr32] leal 8(%rsp), %reg
2181 [addr32] pushq -8(%reg)
2183 2. Use a callee-saved saved register:
2193 [addr32] leal 16(%rsp), %reg
2195 [addr32] pushq -8(%reg)
2197 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2199 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2200 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2202 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2204 0x83 0xe4 0xf0 andl $-16, %esp
2205 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2210 int offset
, offset_and
;
2212 if (target_read_memory (pc
, buf
, sizeof buf
))
2215 /* Skip optional addr32 prefix. */
2216 offset
= buf
[0] == 0x67 ? 1 : 0;
2218 /* Check caller-saved saved register. The first instruction has
2219 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2220 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2221 && buf
[offset
+ 1] == 0x8d
2222 && buf
[offset
+ 3] == 0x24
2223 && buf
[offset
+ 4] == 0x8)
2225 /* MOD must be binary 10 and R/M must be binary 100. */
2226 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2229 /* REG has register number. */
2230 reg
= (buf
[offset
+ 2] >> 3) & 7;
2232 /* Check the REX.R bit. */
2233 if ((buf
[offset
] & 0x4) != 0)
2240 /* Check callee-saved saved register. The first instruction
2241 has to be "pushq %reg". */
2243 if ((buf
[offset
] & 0xf6) == 0x40
2244 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2246 /* Check the REX.B bit. */
2247 if ((buf
[offset
] & 1) != 0)
2252 else if ((buf
[offset
] & 0xf8) != 0x50)
2256 reg
+= buf
[offset
] & 0x7;
2260 /* Skip optional addr32 prefix. */
2261 if (buf
[offset
] == 0x67)
2264 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2265 "leal 16(%rsp), %reg". */
2266 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2267 || buf
[offset
+ 1] != 0x8d
2268 || buf
[offset
+ 3] != 0x24
2269 || buf
[offset
+ 4] != 0x10)
2272 /* MOD must be binary 10 and R/M must be binary 100. */
2273 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2276 /* REG has register number. */
2277 r
= (buf
[offset
+ 2] >> 3) & 7;
2279 /* Check the REX.R bit. */
2280 if ((buf
[offset
] & 0x4) != 0)
2283 /* Registers in pushq and leaq have to be the same. */
2290 /* Rigister can't be %rsp nor %rbp. */
2291 if (reg
== 4 || reg
== 5)
2294 /* The next instruction may be "andq $-XXX, %rsp" or
2295 "andl $-XXX, %esp". */
2296 if (buf
[offset
] != 0x48)
2299 if (buf
[offset
+ 2] != 0xe4
2300 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2303 offset_and
= offset
;
2304 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2306 /* Skip optional addr32 prefix. */
2307 if (buf
[offset
] == 0x67)
2310 /* The next instruction has to be "pushq -8(%reg)". */
2312 if (buf
[offset
] == 0xff)
2314 else if ((buf
[offset
] & 0xf6) == 0x40
2315 && buf
[offset
+ 1] == 0xff)
2317 /* Check the REX.B bit. */
2318 if ((buf
[offset
] & 0x1) != 0)
2325 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2327 if (buf
[offset
+ 1] != 0xf8
2328 || (buf
[offset
] & 0xf8) != 0x70)
2331 /* R/M has register. */
2332 r
+= buf
[offset
] & 7;
2334 /* Registers in leaq and pushq have to be the same. */
2338 if (current_pc
> pc
+ offset_and
)
2339 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2341 return std::min (pc
+ offset
+ 2, current_pc
);
2344 /* Do a limited analysis of the prologue at PC and update CACHE
2345 accordingly. Bail out early if CURRENT_PC is reached. Return the
2346 address where the analysis stopped.
2348 We will handle only functions beginning with:
2351 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2353 or (for the X32 ABI):
2356 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2358 The `endbr64` instruction can be found before these sequences, and will be
2361 Any function that doesn't start with one of these sequences will be
2362 assumed to have no prologue and thus no valid frame pointer in
2366 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2367 CORE_ADDR pc
, CORE_ADDR current_pc
,
2368 struct amd64_frame_cache
*cache
)
2370 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2371 /* The `endbr64` instruction. */
2372 static const gdb_byte endbr64
[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
2373 /* There are two variations of movq %rsp, %rbp. */
2374 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2375 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2376 /* Ditto for movl %esp, %ebp. */
2377 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2378 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2383 if (current_pc
<= pc
)
2386 if (gdbarch_ptr_bit (gdbarch
) == 32)
2387 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2389 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2391 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2393 /* Check for the `endbr64` instruction, skip it if found. */
2394 if (op
== endbr64
[0])
2396 read_code (pc
+ 1, buf
, 3);
2398 if (memcmp (buf
, &endbr64
[1], 3) == 0)
2401 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2404 if (current_pc
<= pc
)
2407 if (op
== 0x55) /* pushq %rbp */
2409 /* Take into account that we've executed the `pushq %rbp' that
2410 starts this instruction sequence. */
2411 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2412 cache
->sp_offset
+= 8;
2414 /* If that's all, return now. */
2415 if (current_pc
<= pc
+ 1)
2418 read_code (pc
+ 1, buf
, 3);
2420 /* Check for `movq %rsp, %rbp'. */
2421 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2422 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2424 /* OK, we actually have a frame. */
2425 cache
->frameless_p
= 0;
2429 /* For X32, also check for `movl %esp, %ebp'. */
2430 if (gdbarch_ptr_bit (gdbarch
) == 32)
2432 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2433 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2435 /* OK, we actually have a frame. */
2436 cache
->frameless_p
= 0;
2447 /* Work around false termination of prologue - GCC PR debug/48827.
2449 START_PC is the first instruction of a function, PC is its minimal already
2450 determined advanced address. Function returns PC if it has nothing to do.
2454 <-- here is 0 lines advance - the false prologue end marker.
2455 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2456 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2457 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2458 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2459 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2460 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2461 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2462 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2466 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2468 struct symtab_and_line start_pc_sal
, next_sal
;
2469 gdb_byte buf
[4 + 8 * 7];
2475 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2476 if (start_pc_sal
.symtab
== NULL
2477 || producer_is_gcc_ge_4 (SYMTAB_COMPUNIT
2478 (start_pc_sal
.symtab
)->producer ()) < 6
2479 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2482 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2483 if (next_sal
.line
!= start_pc_sal
.line
)
2486 /* START_PC can be from overlayed memory, ignored here. */
2487 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2491 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2498 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2500 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2501 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2502 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2506 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2508 /* 8-bit displacement. */
2512 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2514 /* 32-bit displacement. */
2522 if (offset
- 4 != buf
[3])
2525 return next_sal
.end
;
2528 /* Return PC of first real instruction. */
2531 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2533 struct amd64_frame_cache cache
;
2535 CORE_ADDR func_addr
;
2537 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2539 CORE_ADDR post_prologue_pc
2540 = skip_prologue_using_sal (gdbarch
, func_addr
);
2541 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2543 /* LLVM backend (Clang/Flang) always emits a line note before the
2544 prologue and another one after. We trust clang and newer Intel
2545 compilers to emit usable line notes. */
2546 if (post_prologue_pc
2548 && cust
->producer () != nullptr
2549 && (producer_is_llvm (cust
->producer ())
2550 || producer_is_icc_ge_19 (cust
->producer ()))))
2551 return std::max (start_pc
, post_prologue_pc
);
2554 amd64_init_frame_cache (&cache
);
2555 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2557 if (cache
.frameless_p
)
2560 return amd64_skip_xmm_prologue (pc
, start_pc
);
2564 /* Normal frames. */
2567 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2568 struct amd64_frame_cache
*cache
)
2570 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2571 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2575 cache
->pc
= get_frame_func (this_frame
);
2577 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2580 if (cache
->frameless_p
)
2582 /* We didn't find a valid frame. If we're at the start of a
2583 function, or somewhere half-way its prologue, the function's
2584 frame probably hasn't been fully setup yet. Try to
2585 reconstruct the base address for the stack frame by looking
2586 at the stack pointer. For truly "frameless" functions this
2589 if (cache
->saved_sp_reg
!= -1)
2591 /* Stack pointer has been saved. */
2592 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2593 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2595 /* We're halfway aligning the stack. */
2596 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2597 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2599 /* This will be added back below. */
2600 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2604 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2605 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2611 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2612 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2615 /* Now that we have the base address for the stack frame we can
2616 calculate the value of %rsp in the calling frame. */
2617 cache
->saved_sp
= cache
->base
+ 16;
2619 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2620 frame we find it at the same offset from the reconstructed base
2621 address. If we're halfway aligning the stack, %rip is handled
2622 differently (see above). */
2623 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2624 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2626 /* Adjust all the saved registers such that they contain addresses
2627 instead of offsets. */
2628 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2629 if (cache
->saved_regs
[i
] != -1)
2630 cache
->saved_regs
[i
] += cache
->base
;
2635 static struct amd64_frame_cache
*
2636 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2638 struct amd64_frame_cache
*cache
;
2641 return (struct amd64_frame_cache
*) *this_cache
;
2643 cache
= amd64_alloc_frame_cache ();
2644 *this_cache
= cache
;
2648 amd64_frame_cache_1 (this_frame
, cache
);
2650 catch (const gdb_exception_error
&ex
)
2652 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2659 static enum unwind_stop_reason
2660 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2663 struct amd64_frame_cache
*cache
=
2664 amd64_frame_cache (this_frame
, this_cache
);
2667 return UNWIND_UNAVAILABLE
;
2669 /* This marks the outermost frame. */
2670 if (cache
->base
== 0)
2671 return UNWIND_OUTERMOST
;
2673 return UNWIND_NO_REASON
;
2677 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2678 struct frame_id
*this_id
)
2680 struct amd64_frame_cache
*cache
=
2681 amd64_frame_cache (this_frame
, this_cache
);
2684 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2685 else if (cache
->base
== 0)
2687 /* This marks the outermost frame. */
2691 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2694 static struct value
*
2695 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2698 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2699 struct amd64_frame_cache
*cache
=
2700 amd64_frame_cache (this_frame
, this_cache
);
2702 gdb_assert (regnum
>= 0);
2704 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2705 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2707 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2708 return frame_unwind_got_memory (this_frame
, regnum
,
2709 cache
->saved_regs
[regnum
]);
2711 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2714 static const struct frame_unwind amd64_frame_unwind
=
2718 amd64_frame_unwind_stop_reason
,
2719 amd64_frame_this_id
,
2720 amd64_frame_prev_register
,
2722 default_frame_sniffer
2725 /* Generate a bytecode expression to get the value of the saved PC. */
2728 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2729 struct agent_expr
*ax
, struct axs_value
*value
,
2732 /* The following sequence assumes the traditional use of the base
2734 ax_reg (ax
, AMD64_RBP_REGNUM
);
2736 ax_simple (ax
, aop_add
);
2737 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2738 value
->kind
= axs_lvalue_memory
;
2742 /* Signal trampolines. */
2744 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2745 64-bit variants. This would require using identical frame caches
2746 on both platforms. */
2748 static struct amd64_frame_cache
*
2749 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2751 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2752 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2753 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2754 struct amd64_frame_cache
*cache
;
2760 return (struct amd64_frame_cache
*) *this_cache
;
2762 cache
= amd64_alloc_frame_cache ();
2766 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2767 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2769 addr
= tdep
->sigcontext_addr (this_frame
);
2770 gdb_assert (tdep
->sc_reg_offset
);
2771 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2772 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2773 if (tdep
->sc_reg_offset
[i
] != -1)
2774 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2778 catch (const gdb_exception_error
&ex
)
2780 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2784 *this_cache
= cache
;
2788 static enum unwind_stop_reason
2789 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2792 struct amd64_frame_cache
*cache
=
2793 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2796 return UNWIND_UNAVAILABLE
;
2798 return UNWIND_NO_REASON
;
2802 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2803 void **this_cache
, struct frame_id
*this_id
)
2805 struct amd64_frame_cache
*cache
=
2806 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2809 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2810 else if (cache
->base
== 0)
2812 /* This marks the outermost frame. */
2816 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2819 static struct value
*
2820 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2821 void **this_cache
, int regnum
)
2823 /* Make sure we've initialized the cache. */
2824 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2826 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2830 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2831 struct frame_info
*this_frame
,
2834 gdbarch
*arch
= get_frame_arch (this_frame
);
2835 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (arch
);
2837 /* We shouldn't even bother if we don't have a sigcontext_addr
2839 if (tdep
->sigcontext_addr
== NULL
)
2842 if (tdep
->sigtramp_p
!= NULL
)
2844 if (tdep
->sigtramp_p (this_frame
))
2848 if (tdep
->sigtramp_start
!= 0)
2850 CORE_ADDR pc
= get_frame_pc (this_frame
);
2852 gdb_assert (tdep
->sigtramp_end
!= 0);
2853 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2860 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2864 amd64_sigtramp_frame_unwind_stop_reason
,
2865 amd64_sigtramp_frame_this_id
,
2866 amd64_sigtramp_frame_prev_register
,
2868 amd64_sigtramp_frame_sniffer
2873 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2875 struct amd64_frame_cache
*cache
=
2876 amd64_frame_cache (this_frame
, this_cache
);
2881 static const struct frame_base amd64_frame_base
=
2883 &amd64_frame_unwind
,
2884 amd64_frame_base_address
,
2885 amd64_frame_base_address
,
2886 amd64_frame_base_address
2889 /* Normal frames, but in a function epilogue. */
2891 /* Implement the stack_frame_destroyed_p gdbarch method.
2893 The epilogue is defined here as the 'ret' instruction, which will
2894 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2895 the function's stack frame. */
2898 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2901 struct compunit_symtab
*cust
;
2903 cust
= find_pc_compunit_symtab (pc
);
2904 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2907 if (target_read_memory (pc
, &insn
, 1))
2908 return 0; /* Can't read memory at pc. */
2910 if (insn
!= 0xc3) /* 'ret' instruction. */
2917 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2918 struct frame_info
*this_frame
,
2919 void **this_prologue_cache
)
2921 if (frame_relative_level (this_frame
) == 0)
2922 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2923 get_frame_pc (this_frame
));
2928 static struct amd64_frame_cache
*
2929 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2931 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2933 struct amd64_frame_cache
*cache
;
2937 return (struct amd64_frame_cache
*) *this_cache
;
2939 cache
= amd64_alloc_frame_cache ();
2940 *this_cache
= cache
;
2944 /* Cache base will be %esp plus cache->sp_offset (-8). */
2945 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2946 cache
->base
= extract_unsigned_integer (buf
, 8,
2947 byte_order
) + cache
->sp_offset
;
2949 /* Cache pc will be the frame func. */
2950 cache
->pc
= get_frame_pc (this_frame
);
2952 /* The saved %esp will be at cache->base plus 16. */
2953 cache
->saved_sp
= cache
->base
+ 16;
2955 /* The saved %eip will be at cache->base plus 8. */
2956 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2960 catch (const gdb_exception_error
&ex
)
2962 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2969 static enum unwind_stop_reason
2970 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2973 struct amd64_frame_cache
*cache
2974 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2977 return UNWIND_UNAVAILABLE
;
2979 return UNWIND_NO_REASON
;
2983 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2985 struct frame_id
*this_id
)
2987 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2991 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2993 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2996 static const struct frame_unwind amd64_epilogue_frame_unwind
=
3000 amd64_epilogue_frame_unwind_stop_reason
,
3001 amd64_epilogue_frame_this_id
,
3002 amd64_frame_prev_register
,
3004 amd64_epilogue_frame_sniffer
3007 static struct frame_id
3008 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3012 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
3014 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
3017 /* 16 byte align the SP per frame requirements. */
3020 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3022 return sp
& -(CORE_ADDR
)16;
3026 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3027 in the floating-point register set REGSET to register cache
3028 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3031 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3032 int regnum
, const void *fpregs
, size_t len
)
3034 struct gdbarch
*gdbarch
= regcache
->arch ();
3035 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3037 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3038 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3041 /* Collect register REGNUM from the register cache REGCACHE and store
3042 it in the buffer specified by FPREGS and LEN as described by the
3043 floating-point register set REGSET. If REGNUM is -1, do this for
3044 all registers in REGSET. */
3047 amd64_collect_fpregset (const struct regset
*regset
,
3048 const struct regcache
*regcache
,
3049 int regnum
, void *fpregs
, size_t len
)
3051 struct gdbarch
*gdbarch
= regcache
->arch ();
3052 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3054 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3055 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3058 const struct regset amd64_fpregset
=
3060 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3064 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3065 %rdi. We expect its value to be a pointer to the jmp_buf structure
3066 from which we extract the address that we will land at. This
3067 address is copied into PC. This routine returns non-zero on
3071 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3075 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3076 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3077 int jb_pc_offset
= tdep
->jb_pc_offset
;
3078 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3080 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3081 longjmp will land. */
3082 if (jb_pc_offset
== -1)
3085 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3086 jb_addr
= extract_typed_address
3087 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3088 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3091 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3096 static const int amd64_record_regmap
[] =
3098 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3099 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3100 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3101 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3102 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3103 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3106 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3109 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3111 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3117 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3118 const target_desc
*default_tdesc
)
3120 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3121 const struct target_desc
*tdesc
= info
.target_desc
;
3122 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3123 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3124 static const char *const stap_register_indirection_prefixes
[] = { "(",
3126 static const char *const stap_register_indirection_suffixes
[] = { ")",
3129 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3130 floating-point registers. */
3131 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3132 tdep
->fpregset
= &amd64_fpregset
;
3134 if (! tdesc_has_registers (tdesc
))
3135 tdesc
= default_tdesc
;
3136 tdep
->tdesc
= tdesc
;
3138 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3139 tdep
->register_names
= amd64_register_names
;
3141 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3143 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3144 tdep
->k_register_names
= amd64_k_names
;
3145 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3146 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3148 tdep
->num_zmm_regs
= 32;
3149 tdep
->num_xmm_avx512_regs
= 16;
3150 tdep
->num_ymm_avx512_regs
= 16;
3152 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3153 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3154 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3155 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3158 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3160 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3161 tdep
->num_ymm_regs
= 16;
3162 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3165 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3167 tdep
->mpx_register_names
= amd64_mpx_names
;
3168 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3169 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3172 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3174 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3177 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3179 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3180 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3181 tdep
->num_pkeys_regs
= 1;
3184 tdep
->num_byte_regs
= 20;
3185 tdep
->num_word_regs
= 16;
3186 tdep
->num_dword_regs
= 16;
3187 /* Avoid wiring in the MMX registers for now. */
3188 tdep
->num_mmx_regs
= 0;
3190 set_gdbarch_pseudo_register_read_value (gdbarch
,
3191 amd64_pseudo_register_read_value
);
3192 set_gdbarch_pseudo_register_write (gdbarch
,
3193 amd64_pseudo_register_write
);
3194 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3195 amd64_ax_pseudo_register_collect
);
3197 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3199 /* AMD64 has an FPU and 16 SSE registers. */
3200 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3201 tdep
->num_xmm_regs
= 16;
3203 /* This is what all the fuss is about. */
3204 set_gdbarch_long_bit (gdbarch
, 64);
3205 set_gdbarch_long_long_bit (gdbarch
, 64);
3206 set_gdbarch_ptr_bit (gdbarch
, 64);
3208 /* In contrast to the i386, on AMD64 a `long double' actually takes
3209 up 128 bits, even though it's still based on the i387 extended
3210 floating-point format which has only 80 significant bits. */
3211 set_gdbarch_long_double_bit (gdbarch
, 128);
3213 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3215 /* Register numbers of various important registers. */
3216 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3217 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3218 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3219 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3221 /* The "default" register numbering scheme for AMD64 is referred to
3222 as the "DWARF Register Number Mapping" in the System V psABI.
3223 The preferred debugging format for all known AMD64 targets is
3224 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3225 DWARF-1), but we provide the same mapping just in case. This
3226 mapping is also used for stabs, which GCC does support. */
3227 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3228 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3230 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3231 be in use on any of the supported AMD64 targets. */
3233 /* Call dummy code. */
3234 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3235 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3236 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3238 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3239 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3240 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3242 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3244 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3246 tdep
->record_regmap
= amd64_record_regmap
;
3248 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3250 /* Hook the function epilogue frame unwinder. This unwinder is
3251 appended to the list first, so that it supercedes the other
3252 unwinders in function epilogues. */
3253 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3255 /* Hook the prologue-based frame unwinders. */
3256 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3257 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3258 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3260 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3262 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3264 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3266 /* SystemTap variables and functions. */
3267 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3268 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3269 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3270 stap_register_indirection_prefixes
);
3271 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3272 stap_register_indirection_suffixes
);
3273 set_gdbarch_stap_is_single_operand (gdbarch
,
3274 i386_stap_is_single_operand
);
3275 set_gdbarch_stap_parse_special_token (gdbarch
,
3276 i386_stap_parse_special_token
);
3277 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3278 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3279 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3281 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3282 amd64_in_indirect_branch_thunk
);
3284 register_amd64_ravenscar_ops (gdbarch
);
3287 /* Initialize ARCH for x86-64, no osabi. */
3290 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3292 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3296 static struct type
*
3297 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3299 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3301 switch (regnum
- tdep
->eax_regnum
)
3303 case AMD64_RBP_REGNUM
: /* %ebp */
3304 case AMD64_RSP_REGNUM
: /* %esp */
3305 return builtin_type (gdbarch
)->builtin_data_ptr
;
3306 case AMD64_RIP_REGNUM
: /* %eip */
3307 return builtin_type (gdbarch
)->builtin_func_ptr
;
3310 return i386_pseudo_register_type (gdbarch
, regnum
);
3314 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3315 const target_desc
*default_tdesc
)
3317 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3319 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3321 tdep
->num_dword_regs
= 17;
3322 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3324 set_gdbarch_long_bit (gdbarch
, 32);
3325 set_gdbarch_ptr_bit (gdbarch
, 32);
3328 /* Initialize ARCH for x64-32, no osabi. */
3331 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3333 amd64_x32_init_abi (info
, arch
,
3334 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3337 /* Return the target description for a specified XSAVE feature mask. */
3339 const struct target_desc
*
3340 amd64_target_description (uint64_t xcr0
, bool segments
)
3342 static target_desc
*amd64_tdescs \
3343 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3344 target_desc
**tdesc
;
3346 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3347 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3348 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3349 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3353 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3359 void _initialize_amd64_tdep ();
3361 _initialize_amd64_tdep ()
3363 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3364 amd64_none_init_abi
);
3365 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3366 amd64_x32_none_init_abi
);
3370 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3371 sense that the instruction pointer and data pointer are simply
3372 64-bit offsets into the code segment and the data segment instead
3373 of a selector offset pair. The functions below store the upper 32
3374 bits of these pointers (instead of just the 16-bits of the segment
3377 /* Fill register REGNUM in REGCACHE with the appropriate
3378 floating-point or SSE register value from *FXSAVE. If REGNUM is
3379 -1, do this for all registers. This function masks off any of the
3380 reserved bits in *FXSAVE. */
3383 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3386 struct gdbarch
*gdbarch
= regcache
->arch ();
3387 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3389 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3392 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3394 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3396 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3397 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3398 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3399 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3403 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3406 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3409 struct gdbarch
*gdbarch
= regcache
->arch ();
3410 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3412 i387_supply_xsave (regcache
, regnum
, xsave
);
3415 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3417 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3420 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3422 /* If the FISEG and FOSEG registers have not been initialised yet
3423 (their CLEAR_BV bit is set) then their default values of zero will
3424 have already been setup by I387_SUPPLY_XSAVE. */
3425 if (!(clear_bv
& X86_XSTATE_X87
))
3427 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3428 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3429 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3430 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3435 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3436 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3437 all registers. This function doesn't touch any of the reserved
3441 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3444 struct gdbarch
*gdbarch
= regcache
->arch ();
3445 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3446 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3448 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3450 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3452 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3453 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3454 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3455 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3459 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3462 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3463 void *xsave
, int gcore
)
3465 struct gdbarch
*gdbarch
= regcache
->arch ();
3466 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3467 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3469 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3471 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3473 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3474 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3476 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3477 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),