1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2016 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/amd64-mpx.c"
47 #include "features/i386/amd64-avx512.c"
49 #include "features/i386/x32.c"
50 #include "features/i386/x32-avx.c"
51 #include "features/i386/x32-avx512.c"
56 /* Note that the AMD64 architecture was previously known as x86-64.
57 The latter is (forever) engraved into the canonical system name as
58 returned by config.guess, and used as the name for the AMD64 port
59 of GNU/Linux. The BSD's have renamed their ports to amd64; they
60 don't like to shout. For GDB we prefer the amd64_-prefix over the
61 x86_64_-prefix since it's so much easier to type. */
63 /* Register information. */
65 static const char *amd64_register_names
[] =
67 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
69 /* %r8 is indeed register number 8. */
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
73 /* %st0 is register number 24. */
74 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
75 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
77 /* %xmm0 is register number 40. */
78 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
79 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
83 static const char *amd64_ymm_names
[] =
85 "ymm0", "ymm1", "ymm2", "ymm3",
86 "ymm4", "ymm5", "ymm6", "ymm7",
87 "ymm8", "ymm9", "ymm10", "ymm11",
88 "ymm12", "ymm13", "ymm14", "ymm15"
91 static const char *amd64_ymm_avx512_names
[] =
93 "ymm16", "ymm17", "ymm18", "ymm19",
94 "ymm20", "ymm21", "ymm22", "ymm23",
95 "ymm24", "ymm25", "ymm26", "ymm27",
96 "ymm28", "ymm29", "ymm30", "ymm31"
99 static const char *amd64_ymmh_names
[] =
101 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
102 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
103 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
104 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
107 static const char *amd64_ymmh_avx512_names
[] =
109 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
110 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
111 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
112 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
115 static const char *amd64_mpx_names
[] =
117 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
120 static const char *amd64_k_names
[] =
122 "k0", "k1", "k2", "k3",
123 "k4", "k5", "k6", "k7"
126 static const char *amd64_zmmh_names
[] =
128 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
129 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
130 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
131 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
132 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
133 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
134 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
135 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
138 static const char *amd64_zmm_names
[] =
140 "zmm0", "zmm1", "zmm2", "zmm3",
141 "zmm4", "zmm5", "zmm6", "zmm7",
142 "zmm8", "zmm9", "zmm10", "zmm11",
143 "zmm12", "zmm13", "zmm14", "zmm15",
144 "zmm16", "zmm17", "zmm18", "zmm19",
145 "zmm20", "zmm21", "zmm22", "zmm23",
146 "zmm24", "zmm25", "zmm26", "zmm27",
147 "zmm28", "zmm29", "zmm30", "zmm31"
150 static const char *amd64_xmm_avx512_names
[] = {
151 "xmm16", "xmm17", "xmm18", "xmm19",
152 "xmm20", "xmm21", "xmm22", "xmm23",
153 "xmm24", "xmm25", "xmm26", "xmm27",
154 "xmm28", "xmm29", "xmm30", "xmm31"
157 /* DWARF Register Number Mapping as defined in the System V psABI,
160 static int amd64_dwarf_regmap
[] =
162 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
163 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
164 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
165 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
167 /* Frame Pointer Register RBP. */
170 /* Stack Pointer Register RSP. */
173 /* Extended Integer Registers 8 - 15. */
174 AMD64_R8_REGNUM
, /* %r8 */
175 AMD64_R9_REGNUM
, /* %r9 */
176 AMD64_R10_REGNUM
, /* %r10 */
177 AMD64_R11_REGNUM
, /* %r11 */
178 AMD64_R12_REGNUM
, /* %r12 */
179 AMD64_R13_REGNUM
, /* %r13 */
180 AMD64_R14_REGNUM
, /* %r14 */
181 AMD64_R15_REGNUM
, /* %r15 */
183 /* Return Address RA. Mapped to RIP. */
186 /* SSE Registers 0 - 7. */
187 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
188 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
189 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
190 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
192 /* Extended SSE Registers 8 - 15. */
193 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
194 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
195 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
196 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
198 /* Floating Point Registers 0-7. */
199 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
200 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
201 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
202 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
204 /* MMX Registers 0 - 7.
205 We have to handle those registers specifically, as their register
206 number within GDB depends on the target (or they may even not be
207 available at all). */
208 -1, -1, -1, -1, -1, -1, -1, -1,
210 /* Control and Status Flags Register. */
213 /* Selector Registers. */
223 /* Segment Base Address Registers. */
229 /* Special Selector Registers. */
233 /* Floating Point Control Registers. */
239 static const int amd64_dwarf_regmap_len
=
240 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
242 /* Convert DWARF register number REG to the appropriate register
243 number used by GDB. */
246 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 int ymm0_regnum
= tdep
->ymm0_regnum
;
252 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
253 regnum
= amd64_dwarf_regmap
[reg
];
256 && i386_xmm_regnum_p (gdbarch
, regnum
))
257 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
262 /* Map architectural register numbers to gdb register numbers. */
264 static const int amd64_arch_regmap
[16] =
266 AMD64_RAX_REGNUM
, /* %rax */
267 AMD64_RCX_REGNUM
, /* %rcx */
268 AMD64_RDX_REGNUM
, /* %rdx */
269 AMD64_RBX_REGNUM
, /* %rbx */
270 AMD64_RSP_REGNUM
, /* %rsp */
271 AMD64_RBP_REGNUM
, /* %rbp */
272 AMD64_RSI_REGNUM
, /* %rsi */
273 AMD64_RDI_REGNUM
, /* %rdi */
274 AMD64_R8_REGNUM
, /* %r8 */
275 AMD64_R9_REGNUM
, /* %r9 */
276 AMD64_R10_REGNUM
, /* %r10 */
277 AMD64_R11_REGNUM
, /* %r11 */
278 AMD64_R12_REGNUM
, /* %r12 */
279 AMD64_R13_REGNUM
, /* %r13 */
280 AMD64_R14_REGNUM
, /* %r14 */
281 AMD64_R15_REGNUM
/* %r15 */
284 static const int amd64_arch_regmap_len
=
285 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
287 /* Convert architectural register number REG to the appropriate register
288 number used by GDB. */
291 amd64_arch_reg_to_regnum (int reg
)
293 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
295 return amd64_arch_regmap
[reg
];
298 /* Register names for byte pseudo-registers. */
300 static const char *amd64_byte_names
[] =
302 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
303 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
304 "ah", "bh", "ch", "dh"
307 /* Number of lower byte registers. */
308 #define AMD64_NUM_LOWER_BYTE_REGS 16
310 /* Register names for word pseudo-registers. */
312 static const char *amd64_word_names
[] =
314 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
315 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
318 /* Register names for dword pseudo-registers. */
320 static const char *amd64_dword_names
[] =
322 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
323 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
327 /* Return the name of register REGNUM. */
330 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
333 if (i386_byte_regnum_p (gdbarch
, regnum
))
334 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
335 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
336 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
337 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
338 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
339 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
341 else if (i386_word_regnum_p (gdbarch
, regnum
))
342 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
343 else if (i386_dword_regnum_p (gdbarch
, regnum
))
344 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
346 return i386_pseudo_register_name (gdbarch
, regnum
);
349 static struct value
*
350 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
351 struct regcache
*regcache
,
354 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
356 enum register_status status
;
357 struct value
*result_value
;
360 result_value
= allocate_value (register_type (gdbarch
, regnum
));
361 VALUE_LVAL (result_value
) = lval_register
;
362 VALUE_REGNUM (result_value
) = regnum
;
363 buf
= value_contents_raw (result_value
);
365 if (i386_byte_regnum_p (gdbarch
, regnum
))
367 int gpnum
= regnum
- tdep
->al_regnum
;
369 /* Extract (always little endian). */
370 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
372 /* Special handling for AH, BH, CH, DH. */
373 status
= regcache_raw_read (regcache
,
374 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
376 if (status
== REG_VALID
)
377 memcpy (buf
, raw_buf
+ 1, 1);
379 mark_value_bytes_unavailable (result_value
, 0,
380 TYPE_LENGTH (value_type (result_value
)));
384 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
385 if (status
== REG_VALID
)
386 memcpy (buf
, raw_buf
, 1);
388 mark_value_bytes_unavailable (result_value
, 0,
389 TYPE_LENGTH (value_type (result_value
)));
392 else if (i386_dword_regnum_p (gdbarch
, regnum
))
394 int gpnum
= regnum
- tdep
->eax_regnum
;
395 /* Extract (always little endian). */
396 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
397 if (status
== REG_VALID
)
398 memcpy (buf
, raw_buf
, 4);
400 mark_value_bytes_unavailable (result_value
, 0,
401 TYPE_LENGTH (value_type (result_value
)));
404 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
411 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
412 struct regcache
*regcache
,
413 int regnum
, const gdb_byte
*buf
)
415 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
416 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
418 if (i386_byte_regnum_p (gdbarch
, regnum
))
420 int gpnum
= regnum
- tdep
->al_regnum
;
422 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
424 /* Read ... AH, BH, CH, DH. */
425 regcache_raw_read (regcache
,
426 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
427 /* ... Modify ... (always little endian). */
428 memcpy (raw_buf
+ 1, buf
, 1);
430 regcache_raw_write (regcache
,
431 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
436 regcache_raw_read (regcache
, gpnum
, raw_buf
);
437 /* ... Modify ... (always little endian). */
438 memcpy (raw_buf
, buf
, 1);
440 regcache_raw_write (regcache
, gpnum
, raw_buf
);
443 else if (i386_dword_regnum_p (gdbarch
, regnum
))
445 int gpnum
= regnum
- tdep
->eax_regnum
;
448 regcache_raw_read (regcache
, gpnum
, raw_buf
);
449 /* ... Modify ... (always little endian). */
450 memcpy (raw_buf
, buf
, 4);
452 regcache_raw_write (regcache
, gpnum
, raw_buf
);
455 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
458 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
461 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
462 struct agent_expr
*ax
, int regnum
)
464 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
466 if (i386_byte_regnum_p (gdbarch
, regnum
))
468 int gpnum
= regnum
- tdep
->al_regnum
;
470 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
471 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
473 ax_reg_mask (ax
, gpnum
);
476 else if (i386_dword_regnum_p (gdbarch
, regnum
))
478 int gpnum
= regnum
- tdep
->eax_regnum
;
480 ax_reg_mask (ax
, gpnum
);
484 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
489 /* Register classes as defined in the psABI. */
503 /* Return the union class of CLASS1 and CLASS2. See the psABI for
506 static enum amd64_reg_class
507 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
509 /* Rule (a): If both classes are equal, this is the resulting class. */
510 if (class1
== class2
)
513 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
514 is the other class. */
515 if (class1
== AMD64_NO_CLASS
)
517 if (class2
== AMD64_NO_CLASS
)
520 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
521 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
524 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
525 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
526 return AMD64_INTEGER
;
528 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
529 MEMORY is used as class. */
530 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
531 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
532 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
535 /* Rule (f): Otherwise class SSE is used. */
539 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
541 /* Return non-zero if TYPE is a non-POD structure or union type. */
544 amd64_non_pod_p (struct type
*type
)
546 /* ??? A class with a base class certainly isn't POD, but does this
547 catch all non-POD structure types? */
548 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
554 /* Classify TYPE according to the rules for aggregate (structures and
555 arrays) and union types, and store the result in CLASS. */
558 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
560 /* 1. If the size of an object is larger than two eightbytes, or in
561 C++, is a non-POD structure or union type, or contains
562 unaligned fields, it has class memory. */
563 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
565 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
569 /* 2. Both eightbytes get initialized to class NO_CLASS. */
570 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
572 /* 3. Each field of an object is classified recursively so that
573 always two fields are considered. The resulting class is
574 calculated according to the classes of the fields in the
577 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
579 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
581 /* All fields in an array have the same type. */
582 amd64_classify (subtype
, theclass
);
583 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
584 theclass
[1] = theclass
[0];
590 /* Structure or union. */
591 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
592 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
594 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
596 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
597 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
598 enum amd64_reg_class subclass
[2];
599 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
603 bitsize
= TYPE_LENGTH (subtype
) * 8;
604 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
606 /* Ignore static fields. */
607 if (field_is_static (&TYPE_FIELD (type
, i
)))
610 gdb_assert (pos
== 0 || pos
== 1);
612 amd64_classify (subtype
, subclass
);
613 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
614 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
615 /* This is a bit of an odd case: We have a field that would
616 normally fit in one of the two eightbytes, except that
617 it is placed in a way that this field straddles them.
618 This has been seen with a structure containing an array.
620 The ABI is a bit unclear in this case, but we assume that
621 this field's class (stored in subclass[0]) must also be merged
622 into class[1]. In other words, our field has a piece stored
623 in the second eight-byte, and thus its class applies to
624 the second eight-byte as well.
626 In the case where the field length exceeds 8 bytes,
627 it should not be necessary to merge the field class
628 into class[1]. As LEN > 8, subclass[1] is necessarily
629 different from AMD64_NO_CLASS. If subclass[1] is equal
630 to subclass[0], then the normal class[1]/subclass[1]
631 merging will take care of everything. For subclass[1]
632 to be different from subclass[0], I can only see the case
633 where we have a SSE/SSEUP or X87/X87UP pair, which both
634 use up all 16 bytes of the aggregate, and are already
635 handled just fine (because each portion sits on its own
637 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
639 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
643 /* 4. Then a post merger cleanup is done: */
645 /* Rule (a): If one of the classes is MEMORY, the whole argument is
647 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
648 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
650 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
652 if (theclass
[0] == AMD64_SSEUP
)
653 theclass
[0] = AMD64_SSE
;
654 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
655 theclass
[1] = AMD64_SSE
;
658 /* Classify TYPE, and store the result in CLASS. */
661 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
663 enum type_code code
= TYPE_CODE (type
);
664 int len
= TYPE_LENGTH (type
);
666 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
668 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
669 long, long long, and pointers are in the INTEGER class. Similarly,
670 range types, used by languages such as Ada, are also in the INTEGER
672 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
673 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
674 || code
== TYPE_CODE_CHAR
675 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
676 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
677 theclass
[0] = AMD64_INTEGER
;
679 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
681 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
682 && (len
== 4 || len
== 8))
684 theclass
[0] = AMD64_SSE
;
686 /* Arguments of types __float128, _Decimal128 and __m128 are split into
687 two halves. The least significant ones belong to class SSE, the most
688 significant one to class SSEUP. */
689 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
690 /* FIXME: __float128, __m128. */
691 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
693 /* The 64-bit mantissa of arguments of type long double belongs to
694 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
696 else if (code
== TYPE_CODE_FLT
&& len
== 16)
697 /* Class X87 and X87UP. */
698 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
700 /* Arguments of complex T where T is one of the types float or
701 double get treated as if they are implemented as:
709 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
710 theclass
[0] = AMD64_SSE
;
711 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
712 theclass
[0] = theclass
[1] = AMD64_SSE
;
714 /* A variable of type complex long double is classified as type
716 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
717 theclass
[0] = AMD64_COMPLEX_X87
;
720 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
721 || code
== TYPE_CODE_UNION
)
722 amd64_classify_aggregate (type
, theclass
);
725 static enum return_value_convention
726 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
727 struct type
*type
, struct regcache
*regcache
,
728 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
730 enum amd64_reg_class theclass
[2];
731 int len
= TYPE_LENGTH (type
);
732 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
733 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
738 gdb_assert (!(readbuf
&& writebuf
));
740 /* 1. Classify the return type with the classification algorithm. */
741 amd64_classify (type
, theclass
);
743 /* 2. If the type has class MEMORY, then the caller provides space
744 for the return value and passes the address of this storage in
745 %rdi as if it were the first argument to the function. In effect,
746 this address becomes a hidden first argument.
748 On return %rax will contain the address that has been passed in
749 by the caller in %rdi. */
750 if (theclass
[0] == AMD64_MEMORY
)
752 /* As indicated by the comment above, the ABI guarantees that we
753 can always find the return value just after the function has
760 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
761 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
764 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
767 /* 8. If the class is COMPLEX_X87, the real part of the value is
768 returned in %st0 and the imaginary part in %st1. */
769 if (theclass
[0] == AMD64_COMPLEX_X87
)
773 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
774 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
779 i387_return_value (gdbarch
, regcache
);
780 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
781 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
783 /* Fix up the tag word such that both %st(0) and %st(1) are
785 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
788 return RETURN_VALUE_REGISTER_CONVENTION
;
791 gdb_assert (theclass
[1] != AMD64_MEMORY
);
792 gdb_assert (len
<= 16);
794 for (i
= 0; len
> 0; i
++, len
-= 8)
802 /* 3. If the class is INTEGER, the next available register
803 of the sequence %rax, %rdx is used. */
804 regnum
= integer_regnum
[integer_reg
++];
808 /* 4. If the class is SSE, the next available SSE register
809 of the sequence %xmm0, %xmm1 is used. */
810 regnum
= sse_regnum
[sse_reg
++];
814 /* 5. If the class is SSEUP, the eightbyte is passed in the
815 upper half of the last used SSE register. */
816 gdb_assert (sse_reg
> 0);
817 regnum
= sse_regnum
[sse_reg
- 1];
822 /* 6. If the class is X87, the value is returned on the X87
823 stack in %st0 as 80-bit x87 number. */
824 regnum
= AMD64_ST0_REGNUM
;
826 i387_return_value (gdbarch
, regcache
);
830 /* 7. If the class is X87UP, the value is returned together
831 with the previous X87 value in %st0. */
832 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
833 regnum
= AMD64_ST0_REGNUM
;
842 gdb_assert (!"Unexpected register class.");
845 gdb_assert (regnum
!= -1);
848 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
851 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
855 return RETURN_VALUE_REGISTER_CONVENTION
;
860 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
861 struct value
**args
, CORE_ADDR sp
, int struct_return
)
863 static int integer_regnum
[] =
865 AMD64_RDI_REGNUM
, /* %rdi */
866 AMD64_RSI_REGNUM
, /* %rsi */
867 AMD64_RDX_REGNUM
, /* %rdx */
868 AMD64_RCX_REGNUM
, /* %rcx */
869 AMD64_R8_REGNUM
, /* %r8 */
870 AMD64_R9_REGNUM
/* %r9 */
872 static int sse_regnum
[] =
874 /* %xmm0 ... %xmm7 */
875 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
876 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
877 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
878 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
880 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
881 int num_stack_args
= 0;
882 int num_elements
= 0;
888 /* Reserve a register for the "hidden" argument. */
892 for (i
= 0; i
< nargs
; i
++)
894 struct type
*type
= value_type (args
[i
]);
895 int len
= TYPE_LENGTH (type
);
896 enum amd64_reg_class theclass
[2];
897 int needed_integer_regs
= 0;
898 int needed_sse_regs
= 0;
901 /* Classify argument. */
902 amd64_classify (type
, theclass
);
904 /* Calculate the number of integer and SSE registers needed for
906 for (j
= 0; j
< 2; j
++)
908 if (theclass
[j
] == AMD64_INTEGER
)
909 needed_integer_regs
++;
910 else if (theclass
[j
] == AMD64_SSE
)
914 /* Check whether enough registers are available, and if the
915 argument should be passed in registers at all. */
916 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
917 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
918 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
920 /* The argument will be passed on the stack. */
921 num_elements
+= ((len
+ 7) / 8);
922 stack_args
[num_stack_args
++] = args
[i
];
926 /* The argument will be passed in registers. */
927 const gdb_byte
*valbuf
= value_contents (args
[i
]);
930 gdb_assert (len
<= 16);
932 for (j
= 0; len
> 0; j
++, len
-= 8)
940 regnum
= integer_regnum
[integer_reg
++];
944 regnum
= sse_regnum
[sse_reg
++];
948 gdb_assert (sse_reg
> 0);
949 regnum
= sse_regnum
[sse_reg
- 1];
954 gdb_assert (!"Unexpected register class.");
957 gdb_assert (regnum
!= -1);
958 memset (buf
, 0, sizeof buf
);
959 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
960 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
965 /* Allocate space for the arguments on the stack. */
966 sp
-= num_elements
* 8;
968 /* The psABI says that "The end of the input argument area shall be
969 aligned on a 16 byte boundary." */
972 /* Write out the arguments to the stack. */
973 for (i
= 0; i
< num_stack_args
; i
++)
975 struct type
*type
= value_type (stack_args
[i
]);
976 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
977 int len
= TYPE_LENGTH (type
);
979 write_memory (sp
+ element
* 8, valbuf
, len
);
980 element
+= ((len
+ 7) / 8);
983 /* The psABI says that "For calls that may call functions that use
984 varargs or stdargs (prototype-less calls or calls to functions
985 containing ellipsis (...) in the declaration) %al is used as
986 hidden argument to specify the number of SSE registers used. */
987 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
992 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
993 struct regcache
*regcache
, CORE_ADDR bp_addr
,
994 int nargs
, struct value
**args
, CORE_ADDR sp
,
995 int struct_return
, CORE_ADDR struct_addr
)
997 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1000 /* Pass arguments. */
1001 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
1003 /* Pass "hidden" argument". */
1006 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1007 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
1010 /* Store return address. */
1012 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1013 write_memory (sp
, buf
, 8);
1015 /* Finally, update the stack pointer... */
1016 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1017 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
1019 /* ...and fake a frame pointer. */
1020 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
1025 /* Displaced instruction handling. */
1027 /* A partially decoded instruction.
1028 This contains enough details for displaced stepping purposes. */
1032 /* The number of opcode bytes. */
1034 /* The offset of the rex prefix or -1 if not present. */
1036 /* The offset to the first opcode byte. */
1038 /* The offset to the modrm byte or -1 if not present. */
1041 /* The raw instruction. */
1045 struct displaced_step_closure
1047 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1052 /* Details of the instruction. */
1053 struct amd64_insn insn_details
;
1055 /* Amount of space allocated to insn_buf. */
1058 /* The possibly modified insn.
1059 This is a variable-length field. */
1060 gdb_byte insn_buf
[1];
1063 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1064 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1065 at which point delete these in favor of libopcodes' versions). */
1067 static const unsigned char onebyte_has_modrm
[256] = {
1068 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1069 /* ------------------------------- */
1070 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1071 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1072 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1073 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1074 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1075 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1076 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1077 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1078 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1079 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1080 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1081 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1082 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1083 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1084 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1085 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1086 /* ------------------------------- */
1087 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1090 static const unsigned char twobyte_has_modrm
[256] = {
1091 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1092 /* ------------------------------- */
1093 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1094 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1095 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1096 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1097 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1098 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1099 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1100 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1101 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1102 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1103 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1104 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1105 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1106 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1107 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1108 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1109 /* ------------------------------- */
1110 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1113 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1116 rex_prefix_p (gdb_byte pfx
)
1118 return REX_PREFIX_P (pfx
);
1121 /* Skip the legacy instruction prefixes in INSN.
1122 We assume INSN is properly sentineled so we don't have to worry
1123 about falling off the end of the buffer. */
1126 amd64_skip_prefixes (gdb_byte
*insn
)
1132 case DATA_PREFIX_OPCODE
:
1133 case ADDR_PREFIX_OPCODE
:
1134 case CS_PREFIX_OPCODE
:
1135 case DS_PREFIX_OPCODE
:
1136 case ES_PREFIX_OPCODE
:
1137 case FS_PREFIX_OPCODE
:
1138 case GS_PREFIX_OPCODE
:
1139 case SS_PREFIX_OPCODE
:
1140 case LOCK_PREFIX_OPCODE
:
1141 case REPE_PREFIX_OPCODE
:
1142 case REPNE_PREFIX_OPCODE
:
1154 /* Return an integer register (other than RSP) that is unused as an input
1156 In order to not require adding a rex prefix if the insn doesn't already
1157 have one, the result is restricted to RAX ... RDI, sans RSP.
1158 The register numbering of the result follows architecture ordering,
1162 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1164 /* 1 bit for each reg */
1165 int used_regs_mask
= 0;
1167 /* There can be at most 3 int regs used as inputs in an insn, and we have
1168 7 to choose from (RAX ... RDI, sans RSP).
1169 This allows us to take a conservative approach and keep things simple.
1170 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1171 that implicitly specify RAX. */
1174 used_regs_mask
|= 1 << EAX_REG_NUM
;
1175 /* Similarily avoid RDX, implicit operand in divides. */
1176 used_regs_mask
|= 1 << EDX_REG_NUM
;
1178 used_regs_mask
|= 1 << ESP_REG_NUM
;
1180 /* If the opcode is one byte long and there's no ModRM byte,
1181 assume the opcode specifies a register. */
1182 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1183 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1185 /* Mark used regs in the modrm/sib bytes. */
1186 if (details
->modrm_offset
!= -1)
1188 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1189 int mod
= MODRM_MOD_FIELD (modrm
);
1190 int reg
= MODRM_REG_FIELD (modrm
);
1191 int rm
= MODRM_RM_FIELD (modrm
);
1192 int have_sib
= mod
!= 3 && rm
== 4;
1194 /* Assume the reg field of the modrm byte specifies a register. */
1195 used_regs_mask
|= 1 << reg
;
1199 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1200 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1201 used_regs_mask
|= 1 << base
;
1202 used_regs_mask
|= 1 << idx
;
1206 used_regs_mask
|= 1 << rm
;
1210 gdb_assert (used_regs_mask
< 256);
1211 gdb_assert (used_regs_mask
!= 255);
1213 /* Finally, find a free reg. */
1217 for (i
= 0; i
< 8; ++i
)
1219 if (! (used_regs_mask
& (1 << i
)))
1223 /* We shouldn't get here. */
1224 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1228 /* Extract the details of INSN that we need. */
1231 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1233 gdb_byte
*start
= insn
;
1236 details
->raw_insn
= insn
;
1238 details
->opcode_len
= -1;
1239 details
->rex_offset
= -1;
1240 details
->opcode_offset
= -1;
1241 details
->modrm_offset
= -1;
1243 /* Skip legacy instruction prefixes. */
1244 insn
= amd64_skip_prefixes (insn
);
1246 /* Skip REX instruction prefix. */
1247 if (rex_prefix_p (*insn
))
1249 details
->rex_offset
= insn
- start
;
1253 details
->opcode_offset
= insn
- start
;
1255 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1257 /* Two or three-byte opcode. */
1259 need_modrm
= twobyte_has_modrm
[*insn
];
1261 /* Check for three-byte opcode. */
1271 details
->opcode_len
= 3;
1274 details
->opcode_len
= 2;
1280 /* One-byte opcode. */
1281 need_modrm
= onebyte_has_modrm
[*insn
];
1282 details
->opcode_len
= 1;
1288 details
->modrm_offset
= insn
- start
;
1292 /* Update %rip-relative addressing in INSN.
1294 %rip-relative addressing only uses a 32-bit displacement.
1295 32 bits is not enough to be guaranteed to cover the distance between where
1296 the real instruction is and where its copy is.
1297 Convert the insn to use base+disp addressing.
1298 We set base = pc + insn_length so we can leave disp unchanged. */
1301 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1302 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1304 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1305 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1306 int modrm_offset
= insn_details
->modrm_offset
;
1307 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1311 int arch_tmp_regno
, tmp_regno
;
1312 ULONGEST orig_value
;
1314 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1317 /* Compute the rip-relative address. */
1318 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1319 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1320 dsc
->max_len
, from
);
1321 rip_base
= from
+ insn_length
;
1323 /* We need a register to hold the address.
1324 Pick one not used in the insn.
1325 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1326 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1327 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1329 /* REX.B should be unset as we were using rip-relative addressing,
1330 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1331 if (insn_details
->rex_offset
!= -1)
1332 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1334 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1335 dsc
->tmp_regno
= tmp_regno
;
1336 dsc
->tmp_save
= orig_value
;
1339 /* Convert the ModRM field to be base+disp. */
1340 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1341 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1343 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1345 if (debug_displaced
)
1346 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1347 "displaced: using temp reg %d, old value %s, new value %s\n",
1348 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1349 paddress (gdbarch
, rip_base
));
1353 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1354 struct displaced_step_closure
*dsc
,
1355 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1357 const struct amd64_insn
*details
= &dsc
->insn_details
;
1359 if (details
->modrm_offset
!= -1)
1361 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1363 if ((modrm
& 0xc7) == 0x05)
1365 /* The insn uses rip-relative addressing.
1367 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1372 struct displaced_step_closure
*
1373 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1374 CORE_ADDR from
, CORE_ADDR to
,
1375 struct regcache
*regs
)
1377 int len
= gdbarch_max_insn_length (gdbarch
);
1378 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1379 continually watch for running off the end of the buffer. */
1380 int fixup_sentinel_space
= len
;
1381 struct displaced_step_closure
*dsc
1382 = ((struct displaced_step_closure
*)
1383 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1384 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1385 struct amd64_insn
*details
= &dsc
->insn_details
;
1388 dsc
->max_len
= len
+ fixup_sentinel_space
;
1390 read_memory (from
, buf
, len
);
1392 /* Set up the sentinel space so we don't have to worry about running
1393 off the end of the buffer. An excessive number of leading prefixes
1394 could otherwise cause this. */
1395 memset (buf
+ len
, 0, fixup_sentinel_space
);
1397 amd64_get_insn_details (buf
, details
);
1399 /* GDB may get control back after the insn after the syscall.
1400 Presumably this is a kernel bug.
1401 If this is a syscall, make sure there's a nop afterwards. */
1405 if (amd64_syscall_p (details
, &syscall_length
))
1406 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1409 /* Modify the insn to cope with the address where it will be executed from.
1410 In particular, handle any rip-relative addressing. */
1411 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1413 write_memory (to
, buf
, len
);
1415 if (debug_displaced
)
1417 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1418 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1419 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1426 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1428 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1430 if (insn
[0] == 0xff)
1432 /* jump near, absolute indirect (/4) */
1433 if ((insn
[1] & 0x38) == 0x20)
1436 /* jump far, absolute indirect (/5) */
1437 if ((insn
[1] & 0x38) == 0x28)
1444 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1447 amd64_jmp_p (const struct amd64_insn
*details
)
1449 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1451 /* jump short, relative. */
1452 if (insn
[0] == 0xeb)
1455 /* jump near, relative. */
1456 if (insn
[0] == 0xe9)
1459 return amd64_absolute_jmp_p (details
);
1463 amd64_absolute_call_p (const struct amd64_insn
*details
)
1465 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1467 if (insn
[0] == 0xff)
1469 /* Call near, absolute indirect (/2) */
1470 if ((insn
[1] & 0x38) == 0x10)
1473 /* Call far, absolute indirect (/3) */
1474 if ((insn
[1] & 0x38) == 0x18)
1482 amd64_ret_p (const struct amd64_insn
*details
)
1484 /* NOTE: gcc can emit "repz ; ret". */
1485 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1489 case 0xc2: /* ret near, pop N bytes */
1490 case 0xc3: /* ret near */
1491 case 0xca: /* ret far, pop N bytes */
1492 case 0xcb: /* ret far */
1493 case 0xcf: /* iret */
1502 amd64_call_p (const struct amd64_insn
*details
)
1504 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1506 if (amd64_absolute_call_p (details
))
1509 /* call near, relative */
1510 if (insn
[0] == 0xe8)
1516 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1517 length in bytes. Otherwise, return zero. */
1520 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1522 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1524 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1533 /* Classify the instruction at ADDR using PRED.
1534 Throw an error if the memory can't be read. */
1537 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1538 int (*pred
) (const struct amd64_insn
*))
1540 struct amd64_insn details
;
1542 int len
, classification
;
1544 len
= gdbarch_max_insn_length (gdbarch
);
1545 buf
= (gdb_byte
*) alloca (len
);
1547 read_code (addr
, buf
, len
);
1548 amd64_get_insn_details (buf
, &details
);
1550 classification
= pred (&details
);
1552 return classification
;
1555 /* The gdbarch insn_is_call method. */
1558 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1560 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1563 /* The gdbarch insn_is_ret method. */
1566 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1568 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1571 /* The gdbarch insn_is_jump method. */
1574 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1576 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1579 /* Fix up the state of registers and memory after having single-stepped
1580 a displaced instruction. */
1583 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1584 struct displaced_step_closure
*dsc
,
1585 CORE_ADDR from
, CORE_ADDR to
,
1586 struct regcache
*regs
)
1588 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1589 /* The offset we applied to the instruction's address. */
1590 ULONGEST insn_offset
= to
- from
;
1591 gdb_byte
*insn
= dsc
->insn_buf
;
1592 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1594 if (debug_displaced
)
1595 fprintf_unfiltered (gdb_stdlog
,
1596 "displaced: fixup (%s, %s), "
1597 "insn = 0x%02x 0x%02x ...\n",
1598 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1601 /* If we used a tmp reg, restore it. */
1605 if (debug_displaced
)
1606 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1607 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1608 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1611 /* The list of issues to contend with here is taken from
1612 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1613 Yay for Free Software! */
1615 /* Relocate the %rip back to the program's instruction stream,
1618 /* Except in the case of absolute or indirect jump or call
1619 instructions, or a return instruction, the new rip is relative to
1620 the displaced instruction; make it relative to the original insn.
1621 Well, signal handler returns don't need relocation either, but we use the
1622 value of %rip to recognize those; see below. */
1623 if (! amd64_absolute_jmp_p (insn_details
)
1624 && ! amd64_absolute_call_p (insn_details
)
1625 && ! amd64_ret_p (insn_details
))
1630 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1632 /* A signal trampoline system call changes the %rip, resuming
1633 execution of the main program after the signal handler has
1634 returned. That makes them like 'return' instructions; we
1635 shouldn't relocate %rip.
1637 But most system calls don't, and we do need to relocate %rip.
1639 Our heuristic for distinguishing these cases: if stepping
1640 over the system call instruction left control directly after
1641 the instruction, the we relocate --- control almost certainly
1642 doesn't belong in the displaced copy. Otherwise, we assume
1643 the instruction has put control where it belongs, and leave
1644 it unrelocated. Goodness help us if there are PC-relative
1646 if (amd64_syscall_p (insn_details
, &insn_len
)
1647 && orig_rip
!= to
+ insn_len
1648 /* GDB can get control back after the insn after the syscall.
1649 Presumably this is a kernel bug.
1650 Fixup ensures its a nop, we add one to the length for it. */
1651 && orig_rip
!= to
+ insn_len
+ 1)
1653 if (debug_displaced
)
1654 fprintf_unfiltered (gdb_stdlog
,
1655 "displaced: syscall changed %%rip; "
1656 "not relocating\n");
1660 ULONGEST rip
= orig_rip
- insn_offset
;
1662 /* If we just stepped over a breakpoint insn, we don't backup
1663 the pc on purpose; this is to match behaviour without
1666 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1668 if (debug_displaced
)
1669 fprintf_unfiltered (gdb_stdlog
,
1671 "relocated %%rip from %s to %s\n",
1672 paddress (gdbarch
, orig_rip
),
1673 paddress (gdbarch
, rip
));
1677 /* If the instruction was PUSHFL, then the TF bit will be set in the
1678 pushed value, and should be cleared. We'll leave this for later,
1679 since GDB already messes up the TF flag when stepping over a
1682 /* If the instruction was a call, the return address now atop the
1683 stack is the address following the copied instruction. We need
1684 to make it the address following the original instruction. */
1685 if (amd64_call_p (insn_details
))
1689 const ULONGEST retaddr_len
= 8;
1691 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1692 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1694 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1696 if (debug_displaced
)
1697 fprintf_unfiltered (gdb_stdlog
,
1698 "displaced: relocated return addr at %s "
1700 paddress (gdbarch
, rsp
),
1701 paddress (gdbarch
, retaddr
));
1705 /* If the instruction INSN uses RIP-relative addressing, return the
1706 offset into the raw INSN where the displacement to be adjusted is
1707 found. Returns 0 if the instruction doesn't use RIP-relative
1711 rip_relative_offset (struct amd64_insn
*insn
)
1713 if (insn
->modrm_offset
!= -1)
1715 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1717 if ((modrm
& 0xc7) == 0x05)
1719 /* The displacement is found right after the ModRM byte. */
1720 return insn
->modrm_offset
+ 1;
1728 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1730 target_write_memory (*to
, buf
, len
);
1735 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1736 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1738 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1739 int len
= gdbarch_max_insn_length (gdbarch
);
1740 /* Extra space for sentinels. */
1741 int fixup_sentinel_space
= len
;
1742 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1743 struct amd64_insn insn_details
;
1745 LONGEST rel32
, newrel
;
1749 read_memory (oldloc
, buf
, len
);
1751 /* Set up the sentinel space so we don't have to worry about running
1752 off the end of the buffer. An excessive number of leading prefixes
1753 could otherwise cause this. */
1754 memset (buf
+ len
, 0, fixup_sentinel_space
);
1757 amd64_get_insn_details (insn
, &insn_details
);
1759 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1761 /* Skip legacy instruction prefixes. */
1762 insn
= amd64_skip_prefixes (insn
);
1764 /* Adjust calls with 32-bit relative addresses as push/jump, with
1765 the address pushed being the location where the original call in
1766 the user program would return to. */
1767 if (insn
[0] == 0xe8)
1769 gdb_byte push_buf
[16];
1770 unsigned int ret_addr
;
1772 /* Where "ret" in the original code will return to. */
1773 ret_addr
= oldloc
+ insn_length
;
1774 push_buf
[0] = 0x68; /* pushq $... */
1775 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1776 /* Push the push. */
1777 append_insns (to
, 5, push_buf
);
1779 /* Convert the relative call to a relative jump. */
1782 /* Adjust the destination offset. */
1783 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1784 newrel
= (oldloc
- *to
) + rel32
;
1785 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1787 if (debug_displaced
)
1788 fprintf_unfiltered (gdb_stdlog
,
1789 "Adjusted insn rel32=%s at %s to"
1790 " rel32=%s at %s\n",
1791 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1792 hex_string (newrel
), paddress (gdbarch
, *to
));
1794 /* Write the adjusted jump into its displaced location. */
1795 append_insns (to
, 5, insn
);
1799 offset
= rip_relative_offset (&insn_details
);
1802 /* Adjust jumps with 32-bit relative addresses. Calls are
1803 already handled above. */
1804 if (insn
[0] == 0xe9)
1806 /* Adjust conditional jumps. */
1807 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1813 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1814 newrel
= (oldloc
- *to
) + rel32
;
1815 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1816 if (debug_displaced
)
1817 fprintf_unfiltered (gdb_stdlog
,
1818 "Adjusted insn rel32=%s at %s to"
1819 " rel32=%s at %s\n",
1820 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1821 hex_string (newrel
), paddress (gdbarch
, *to
));
1824 /* Write the adjusted instruction into its displaced location. */
1825 append_insns (to
, insn_length
, buf
);
1829 /* The maximum number of saved registers. This should include %rip. */
1830 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1832 struct amd64_frame_cache
1837 CORE_ADDR sp_offset
;
1840 /* Saved registers. */
1841 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1845 /* Do we have a frame? */
1849 /* Initialize a frame cache. */
1852 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1859 cache
->sp_offset
= -8;
1862 /* Saved registers. We initialize these to -1 since zero is a valid
1863 offset (that's where %rbp is supposed to be stored).
1864 The values start out as being offsets, and are later converted to
1865 addresses (at which point -1 is interpreted as an address, still meaning
1867 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1868 cache
->saved_regs
[i
] = -1;
1869 cache
->saved_sp
= 0;
1870 cache
->saved_sp_reg
= -1;
1872 /* Frameless until proven otherwise. */
1873 cache
->frameless_p
= 1;
1876 /* Allocate and initialize a frame cache. */
1878 static struct amd64_frame_cache
*
1879 amd64_alloc_frame_cache (void)
1881 struct amd64_frame_cache
*cache
;
1883 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1884 amd64_init_frame_cache (cache
);
1888 /* GCC 4.4 and later, can put code in the prologue to realign the
1889 stack pointer. Check whether PC points to such code, and update
1890 CACHE accordingly. Return the first instruction after the code
1891 sequence or CURRENT_PC, whichever is smaller. If we don't
1892 recognize the code, return PC. */
1895 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1896 struct amd64_frame_cache
*cache
)
1898 /* There are 2 code sequences to re-align stack before the frame
1901 1. Use a caller-saved saved register:
1907 2. Use a callee-saved saved register:
1914 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1916 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1917 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1922 int offset
, offset_and
;
1924 if (target_read_code (pc
, buf
, sizeof buf
))
1927 /* Check caller-saved saved register. The first instruction has
1928 to be "leaq 8(%rsp), %reg". */
1929 if ((buf
[0] & 0xfb) == 0x48
1934 /* MOD must be binary 10 and R/M must be binary 100. */
1935 if ((buf
[2] & 0xc7) != 0x44)
1938 /* REG has register number. */
1939 reg
= (buf
[2] >> 3) & 7;
1941 /* Check the REX.R bit. */
1949 /* Check callee-saved saved register. The first instruction
1950 has to be "pushq %reg". */
1952 if ((buf
[0] & 0xf8) == 0x50)
1954 else if ((buf
[0] & 0xf6) == 0x40
1955 && (buf
[1] & 0xf8) == 0x50)
1957 /* Check the REX.B bit. */
1958 if ((buf
[0] & 1) != 0)
1967 reg
+= buf
[offset
] & 0x7;
1971 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1972 if ((buf
[offset
] & 0xfb) != 0x48
1973 || buf
[offset
+ 1] != 0x8d
1974 || buf
[offset
+ 3] != 0x24
1975 || buf
[offset
+ 4] != 0x10)
1978 /* MOD must be binary 10 and R/M must be binary 100. */
1979 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1982 /* REG has register number. */
1983 r
= (buf
[offset
+ 2] >> 3) & 7;
1985 /* Check the REX.R bit. */
1986 if (buf
[offset
] == 0x4c)
1989 /* Registers in pushq and leaq have to be the same. */
1996 /* Rigister can't be %rsp nor %rbp. */
1997 if (reg
== 4 || reg
== 5)
2000 /* The next instruction has to be "andq $-XXX, %rsp". */
2001 if (buf
[offset
] != 0x48
2002 || buf
[offset
+ 2] != 0xe4
2003 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2006 offset_and
= offset
;
2007 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2009 /* The next instruction has to be "pushq -8(%reg)". */
2011 if (buf
[offset
] == 0xff)
2013 else if ((buf
[offset
] & 0xf6) == 0x40
2014 && buf
[offset
+ 1] == 0xff)
2016 /* Check the REX.B bit. */
2017 if ((buf
[offset
] & 0x1) != 0)
2024 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2026 if (buf
[offset
+ 1] != 0xf8
2027 || (buf
[offset
] & 0xf8) != 0x70)
2030 /* R/M has register. */
2031 r
+= buf
[offset
] & 7;
2033 /* Registers in leaq and pushq have to be the same. */
2037 if (current_pc
> pc
+ offset_and
)
2038 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2040 return min (pc
+ offset
+ 2, current_pc
);
2043 /* Similar to amd64_analyze_stack_align for x32. */
2046 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2047 struct amd64_frame_cache
*cache
)
2049 /* There are 2 code sequences to re-align stack before the frame
2052 1. Use a caller-saved saved register:
2060 [addr32] leal 8(%rsp), %reg
2062 [addr32] pushq -8(%reg)
2064 2. Use a callee-saved saved register:
2074 [addr32] leal 16(%rsp), %reg
2076 [addr32] pushq -8(%reg)
2078 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2080 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2081 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2083 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2085 0x83 0xe4 0xf0 andl $-16, %esp
2086 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2091 int offset
, offset_and
;
2093 if (target_read_memory (pc
, buf
, sizeof buf
))
2096 /* Skip optional addr32 prefix. */
2097 offset
= buf
[0] == 0x67 ? 1 : 0;
2099 /* Check caller-saved saved register. The first instruction has
2100 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2101 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2102 && buf
[offset
+ 1] == 0x8d
2103 && buf
[offset
+ 3] == 0x24
2104 && buf
[offset
+ 4] == 0x8)
2106 /* MOD must be binary 10 and R/M must be binary 100. */
2107 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2110 /* REG has register number. */
2111 reg
= (buf
[offset
+ 2] >> 3) & 7;
2113 /* Check the REX.R bit. */
2114 if ((buf
[offset
] & 0x4) != 0)
2121 /* Check callee-saved saved register. The first instruction
2122 has to be "pushq %reg". */
2124 if ((buf
[offset
] & 0xf6) == 0x40
2125 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2127 /* Check the REX.B bit. */
2128 if ((buf
[offset
] & 1) != 0)
2133 else if ((buf
[offset
] & 0xf8) != 0x50)
2137 reg
+= buf
[offset
] & 0x7;
2141 /* Skip optional addr32 prefix. */
2142 if (buf
[offset
] == 0x67)
2145 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2146 "leal 16(%rsp), %reg". */
2147 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2148 || buf
[offset
+ 1] != 0x8d
2149 || buf
[offset
+ 3] != 0x24
2150 || buf
[offset
+ 4] != 0x10)
2153 /* MOD must be binary 10 and R/M must be binary 100. */
2154 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2157 /* REG has register number. */
2158 r
= (buf
[offset
+ 2] >> 3) & 7;
2160 /* Check the REX.R bit. */
2161 if ((buf
[offset
] & 0x4) != 0)
2164 /* Registers in pushq and leaq have to be the same. */
2171 /* Rigister can't be %rsp nor %rbp. */
2172 if (reg
== 4 || reg
== 5)
2175 /* The next instruction may be "andq $-XXX, %rsp" or
2176 "andl $-XXX, %esp". */
2177 if (buf
[offset
] != 0x48)
2180 if (buf
[offset
+ 2] != 0xe4
2181 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2184 offset_and
= offset
;
2185 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2187 /* Skip optional addr32 prefix. */
2188 if (buf
[offset
] == 0x67)
2191 /* The next instruction has to be "pushq -8(%reg)". */
2193 if (buf
[offset
] == 0xff)
2195 else if ((buf
[offset
] & 0xf6) == 0x40
2196 && buf
[offset
+ 1] == 0xff)
2198 /* Check the REX.B bit. */
2199 if ((buf
[offset
] & 0x1) != 0)
2206 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2208 if (buf
[offset
+ 1] != 0xf8
2209 || (buf
[offset
] & 0xf8) != 0x70)
2212 /* R/M has register. */
2213 r
+= buf
[offset
] & 7;
2215 /* Registers in leaq and pushq have to be the same. */
2219 if (current_pc
> pc
+ offset_and
)
2220 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2222 return min (pc
+ offset
+ 2, current_pc
);
2225 /* Do a limited analysis of the prologue at PC and update CACHE
2226 accordingly. Bail out early if CURRENT_PC is reached. Return the
2227 address where the analysis stopped.
2229 We will handle only functions beginning with:
2232 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2234 or (for the X32 ABI):
2237 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2239 Any function that doesn't start with one of these sequences will be
2240 assumed to have no prologue and thus no valid frame pointer in
2244 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2245 CORE_ADDR pc
, CORE_ADDR current_pc
,
2246 struct amd64_frame_cache
*cache
)
2248 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2249 /* There are two variations of movq %rsp, %rbp. */
2250 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2251 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2252 /* Ditto for movl %esp, %ebp. */
2253 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2254 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2259 if (current_pc
<= pc
)
2262 if (gdbarch_ptr_bit (gdbarch
) == 32)
2263 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2265 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2267 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2269 if (op
== 0x55) /* pushq %rbp */
2271 /* Take into account that we've executed the `pushq %rbp' that
2272 starts this instruction sequence. */
2273 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2274 cache
->sp_offset
+= 8;
2276 /* If that's all, return now. */
2277 if (current_pc
<= pc
+ 1)
2280 read_code (pc
+ 1, buf
, 3);
2282 /* Check for `movq %rsp, %rbp'. */
2283 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2284 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2286 /* OK, we actually have a frame. */
2287 cache
->frameless_p
= 0;
2291 /* For X32, also check for `movq %esp, %ebp'. */
2292 if (gdbarch_ptr_bit (gdbarch
) == 32)
2294 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2295 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2297 /* OK, we actually have a frame. */
2298 cache
->frameless_p
= 0;
2309 /* Work around false termination of prologue - GCC PR debug/48827.
2311 START_PC is the first instruction of a function, PC is its minimal already
2312 determined advanced address. Function returns PC if it has nothing to do.
2316 <-- here is 0 lines advance - the false prologue end marker.
2317 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2318 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2319 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2320 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2321 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2322 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2323 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2324 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2328 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2330 struct symtab_and_line start_pc_sal
, next_sal
;
2331 gdb_byte buf
[4 + 8 * 7];
2337 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2338 if (start_pc_sal
.symtab
== NULL
2339 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2340 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2341 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2344 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2345 if (next_sal
.line
!= start_pc_sal
.line
)
2348 /* START_PC can be from overlayed memory, ignored here. */
2349 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2353 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2360 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2362 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2363 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2364 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2368 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2370 /* 8-bit displacement. */
2374 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2376 /* 32-bit displacement. */
2384 if (offset
- 4 != buf
[3])
2387 return next_sal
.end
;
2390 /* Return PC of first real instruction. */
2393 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2395 struct amd64_frame_cache cache
;
2397 CORE_ADDR func_addr
;
2399 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2401 CORE_ADDR post_prologue_pc
2402 = skip_prologue_using_sal (gdbarch
, func_addr
);
2403 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2405 /* Clang always emits a line note before the prologue and another
2406 one after. We trust clang to emit usable line notes. */
2407 if (post_prologue_pc
2409 && COMPUNIT_PRODUCER (cust
) != NULL
2410 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2411 return max (start_pc
, post_prologue_pc
);
2414 amd64_init_frame_cache (&cache
);
2415 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2417 if (cache
.frameless_p
)
2420 return amd64_skip_xmm_prologue (pc
, start_pc
);
2424 /* Normal frames. */
2427 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2428 struct amd64_frame_cache
*cache
)
2430 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2431 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2435 cache
->pc
= get_frame_func (this_frame
);
2437 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2440 if (cache
->frameless_p
)
2442 /* We didn't find a valid frame. If we're at the start of a
2443 function, or somewhere half-way its prologue, the function's
2444 frame probably hasn't been fully setup yet. Try to
2445 reconstruct the base address for the stack frame by looking
2446 at the stack pointer. For truly "frameless" functions this
2449 if (cache
->saved_sp_reg
!= -1)
2451 /* Stack pointer has been saved. */
2452 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2453 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2455 /* We're halfway aligning the stack. */
2456 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2457 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2459 /* This will be added back below. */
2460 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2464 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2465 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2471 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2472 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2475 /* Now that we have the base address for the stack frame we can
2476 calculate the value of %rsp in the calling frame. */
2477 cache
->saved_sp
= cache
->base
+ 16;
2479 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2480 frame we find it at the same offset from the reconstructed base
2481 address. If we're halfway aligning the stack, %rip is handled
2482 differently (see above). */
2483 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2484 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2486 /* Adjust all the saved registers such that they contain addresses
2487 instead of offsets. */
2488 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2489 if (cache
->saved_regs
[i
] != -1)
2490 cache
->saved_regs
[i
] += cache
->base
;
2495 static struct amd64_frame_cache
*
2496 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2498 struct amd64_frame_cache
*cache
;
2501 return (struct amd64_frame_cache
*) *this_cache
;
2503 cache
= amd64_alloc_frame_cache ();
2504 *this_cache
= cache
;
2508 amd64_frame_cache_1 (this_frame
, cache
);
2510 CATCH (ex
, RETURN_MASK_ERROR
)
2512 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2513 throw_exception (ex
);
2520 static enum unwind_stop_reason
2521 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2524 struct amd64_frame_cache
*cache
=
2525 amd64_frame_cache (this_frame
, this_cache
);
2528 return UNWIND_UNAVAILABLE
;
2530 /* This marks the outermost frame. */
2531 if (cache
->base
== 0)
2532 return UNWIND_OUTERMOST
;
2534 return UNWIND_NO_REASON
;
2538 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2539 struct frame_id
*this_id
)
2541 struct amd64_frame_cache
*cache
=
2542 amd64_frame_cache (this_frame
, this_cache
);
2545 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2546 else if (cache
->base
== 0)
2548 /* This marks the outermost frame. */
2552 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2555 static struct value
*
2556 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2559 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2560 struct amd64_frame_cache
*cache
=
2561 amd64_frame_cache (this_frame
, this_cache
);
2563 gdb_assert (regnum
>= 0);
2565 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2566 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2568 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2569 return frame_unwind_got_memory (this_frame
, regnum
,
2570 cache
->saved_regs
[regnum
]);
2572 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2575 static const struct frame_unwind amd64_frame_unwind
=
2578 amd64_frame_unwind_stop_reason
,
2579 amd64_frame_this_id
,
2580 amd64_frame_prev_register
,
2582 default_frame_sniffer
2585 /* Generate a bytecode expression to get the value of the saved PC. */
2588 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2589 struct agent_expr
*ax
, struct axs_value
*value
,
2592 /* The following sequence assumes the traditional use of the base
2594 ax_reg (ax
, AMD64_RBP_REGNUM
);
2596 ax_simple (ax
, aop_add
);
2597 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2598 value
->kind
= axs_lvalue_memory
;
2602 /* Signal trampolines. */
2604 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2605 64-bit variants. This would require using identical frame caches
2606 on both platforms. */
2608 static struct amd64_frame_cache
*
2609 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2611 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2613 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2614 struct amd64_frame_cache
*cache
;
2620 return (struct amd64_frame_cache
*) *this_cache
;
2622 cache
= amd64_alloc_frame_cache ();
2626 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2627 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2629 addr
= tdep
->sigcontext_addr (this_frame
);
2630 gdb_assert (tdep
->sc_reg_offset
);
2631 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2632 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2633 if (tdep
->sc_reg_offset
[i
] != -1)
2634 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2638 CATCH (ex
, RETURN_MASK_ERROR
)
2640 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2641 throw_exception (ex
);
2645 *this_cache
= cache
;
2649 static enum unwind_stop_reason
2650 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2653 struct amd64_frame_cache
*cache
=
2654 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2657 return UNWIND_UNAVAILABLE
;
2659 return UNWIND_NO_REASON
;
2663 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2664 void **this_cache
, struct frame_id
*this_id
)
2666 struct amd64_frame_cache
*cache
=
2667 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2670 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2671 else if (cache
->base
== 0)
2673 /* This marks the outermost frame. */
2677 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2680 static struct value
*
2681 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2682 void **this_cache
, int regnum
)
2684 /* Make sure we've initialized the cache. */
2685 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2687 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2691 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2692 struct frame_info
*this_frame
,
2695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2697 /* We shouldn't even bother if we don't have a sigcontext_addr
2699 if (tdep
->sigcontext_addr
== NULL
)
2702 if (tdep
->sigtramp_p
!= NULL
)
2704 if (tdep
->sigtramp_p (this_frame
))
2708 if (tdep
->sigtramp_start
!= 0)
2710 CORE_ADDR pc
= get_frame_pc (this_frame
);
2712 gdb_assert (tdep
->sigtramp_end
!= 0);
2713 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2720 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2723 amd64_sigtramp_frame_unwind_stop_reason
,
2724 amd64_sigtramp_frame_this_id
,
2725 amd64_sigtramp_frame_prev_register
,
2727 amd64_sigtramp_frame_sniffer
2732 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2734 struct amd64_frame_cache
*cache
=
2735 amd64_frame_cache (this_frame
, this_cache
);
2740 static const struct frame_base amd64_frame_base
=
2742 &amd64_frame_unwind
,
2743 amd64_frame_base_address
,
2744 amd64_frame_base_address
,
2745 amd64_frame_base_address
2748 /* Normal frames, but in a function epilogue. */
2750 /* Implement the stack_frame_destroyed_p gdbarch method.
2752 The epilogue is defined here as the 'ret' instruction, which will
2753 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2754 the function's stack frame. */
2757 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2760 struct compunit_symtab
*cust
;
2762 cust
= find_pc_compunit_symtab (pc
);
2763 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2766 if (target_read_memory (pc
, &insn
, 1))
2767 return 0; /* Can't read memory at pc. */
2769 if (insn
!= 0xc3) /* 'ret' instruction. */
2776 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2777 struct frame_info
*this_frame
,
2778 void **this_prologue_cache
)
2780 if (frame_relative_level (this_frame
) == 0)
2781 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2782 get_frame_pc (this_frame
));
2787 static struct amd64_frame_cache
*
2788 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2790 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2791 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2792 struct amd64_frame_cache
*cache
;
2796 return (struct amd64_frame_cache
*) *this_cache
;
2798 cache
= amd64_alloc_frame_cache ();
2799 *this_cache
= cache
;
2803 /* Cache base will be %esp plus cache->sp_offset (-8). */
2804 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2805 cache
->base
= extract_unsigned_integer (buf
, 8,
2806 byte_order
) + cache
->sp_offset
;
2808 /* Cache pc will be the frame func. */
2809 cache
->pc
= get_frame_pc (this_frame
);
2811 /* The saved %esp will be at cache->base plus 16. */
2812 cache
->saved_sp
= cache
->base
+ 16;
2814 /* The saved %eip will be at cache->base plus 8. */
2815 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2819 CATCH (ex
, RETURN_MASK_ERROR
)
2821 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2822 throw_exception (ex
);
2829 static enum unwind_stop_reason
2830 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2833 struct amd64_frame_cache
*cache
2834 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2837 return UNWIND_UNAVAILABLE
;
2839 return UNWIND_NO_REASON
;
2843 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2845 struct frame_id
*this_id
)
2847 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2851 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2853 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2856 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2859 amd64_epilogue_frame_unwind_stop_reason
,
2860 amd64_epilogue_frame_this_id
,
2861 amd64_frame_prev_register
,
2863 amd64_epilogue_frame_sniffer
2866 static struct frame_id
2867 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2871 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2873 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2876 /* 16 byte align the SP per frame requirements. */
2879 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2881 return sp
& -(CORE_ADDR
)16;
2885 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2886 in the floating-point register set REGSET to register cache
2887 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2890 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2891 int regnum
, const void *fpregs
, size_t len
)
2893 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2894 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2896 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2897 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2900 /* Collect register REGNUM from the register cache REGCACHE and store
2901 it in the buffer specified by FPREGS and LEN as described by the
2902 floating-point register set REGSET. If REGNUM is -1, do this for
2903 all registers in REGSET. */
2906 amd64_collect_fpregset (const struct regset
*regset
,
2907 const struct regcache
*regcache
,
2908 int regnum
, void *fpregs
, size_t len
)
2910 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2911 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2913 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2914 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2917 const struct regset amd64_fpregset
=
2919 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2923 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2924 %rdi. We expect its value to be a pointer to the jmp_buf structure
2925 from which we extract the address that we will land at. This
2926 address is copied into PC. This routine returns non-zero on
2930 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2934 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2935 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2936 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2938 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2939 longjmp will land. */
2940 if (jb_pc_offset
== -1)
2943 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2944 jb_addr
= extract_typed_address
2945 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2946 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2949 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2954 static const int amd64_record_regmap
[] =
2956 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2957 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2958 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2959 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2960 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2961 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2965 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2967 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2968 const struct target_desc
*tdesc
= info
.target_desc
;
2969 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
2970 static const char *const stap_register_prefixes
[] = { "%", NULL
};
2971 static const char *const stap_register_indirection_prefixes
[] = { "(",
2973 static const char *const stap_register_indirection_suffixes
[] = { ")",
2976 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2977 floating-point registers. */
2978 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2979 tdep
->fpregset
= &amd64_fpregset
;
2981 if (! tdesc_has_registers (tdesc
))
2982 tdesc
= tdesc_amd64
;
2983 tdep
->tdesc
= tdesc
;
2985 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2986 tdep
->register_names
= amd64_register_names
;
2988 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
2990 tdep
->zmmh_register_names
= amd64_zmmh_names
;
2991 tdep
->k_register_names
= amd64_k_names
;
2992 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
2993 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
2995 tdep
->num_zmm_regs
= 32;
2996 tdep
->num_xmm_avx512_regs
= 16;
2997 tdep
->num_ymm_avx512_regs
= 16;
2999 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3000 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3001 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3002 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3005 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3007 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3008 tdep
->num_ymm_regs
= 16;
3009 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3012 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3014 tdep
->mpx_register_names
= amd64_mpx_names
;
3015 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3016 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3019 tdep
->num_byte_regs
= 20;
3020 tdep
->num_word_regs
= 16;
3021 tdep
->num_dword_regs
= 16;
3022 /* Avoid wiring in the MMX registers for now. */
3023 tdep
->num_mmx_regs
= 0;
3025 set_gdbarch_pseudo_register_read_value (gdbarch
,
3026 amd64_pseudo_register_read_value
);
3027 set_gdbarch_pseudo_register_write (gdbarch
,
3028 amd64_pseudo_register_write
);
3029 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3030 amd64_ax_pseudo_register_collect
);
3032 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3034 /* AMD64 has an FPU and 16 SSE registers. */
3035 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3036 tdep
->num_xmm_regs
= 16;
3038 /* This is what all the fuss is about. */
3039 set_gdbarch_long_bit (gdbarch
, 64);
3040 set_gdbarch_long_long_bit (gdbarch
, 64);
3041 set_gdbarch_ptr_bit (gdbarch
, 64);
3043 /* In contrast to the i386, on AMD64 a `long double' actually takes
3044 up 128 bits, even though it's still based on the i387 extended
3045 floating-point format which has only 80 significant bits. */
3046 set_gdbarch_long_double_bit (gdbarch
, 128);
3048 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3050 /* Register numbers of various important registers. */
3051 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3052 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3053 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3054 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3056 /* The "default" register numbering scheme for AMD64 is referred to
3057 as the "DWARF Register Number Mapping" in the System V psABI.
3058 The preferred debugging format for all known AMD64 targets is
3059 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3060 DWARF-1), but we provide the same mapping just in case. This
3061 mapping is also used for stabs, which GCC does support. */
3062 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3063 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3065 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3066 be in use on any of the supported AMD64 targets. */
3068 /* Call dummy code. */
3069 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3070 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3071 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3073 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3074 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3075 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3077 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3079 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3081 tdep
->record_regmap
= amd64_record_regmap
;
3083 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3085 /* Hook the function epilogue frame unwinder. This unwinder is
3086 appended to the list first, so that it supercedes the other
3087 unwinders in function epilogues. */
3088 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3090 /* Hook the prologue-based frame unwinders. */
3091 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3092 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3093 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3095 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3097 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3099 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3101 /* SystemTap variables and functions. */
3102 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3103 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3104 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3105 stap_register_indirection_prefixes
);
3106 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3107 stap_register_indirection_suffixes
);
3108 set_gdbarch_stap_is_single_operand (gdbarch
,
3109 i386_stap_is_single_operand
);
3110 set_gdbarch_stap_parse_special_token (gdbarch
,
3111 i386_stap_parse_special_token
);
3112 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3113 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3114 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3118 static struct type
*
3119 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3123 switch (regnum
- tdep
->eax_regnum
)
3125 case AMD64_RBP_REGNUM
: /* %ebp */
3126 case AMD64_RSP_REGNUM
: /* %esp */
3127 return builtin_type (gdbarch
)->builtin_data_ptr
;
3128 case AMD64_RIP_REGNUM
: /* %eip */
3129 return builtin_type (gdbarch
)->builtin_func_ptr
;
3132 return i386_pseudo_register_type (gdbarch
, regnum
);
3136 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3139 const struct target_desc
*tdesc
= info
.target_desc
;
3141 amd64_init_abi (info
, gdbarch
);
3143 if (! tdesc_has_registers (tdesc
))
3145 tdep
->tdesc
= tdesc
;
3147 tdep
->num_dword_regs
= 17;
3148 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3150 set_gdbarch_long_bit (gdbarch
, 32);
3151 set_gdbarch_ptr_bit (gdbarch
, 32);
3154 /* Return the target description for a specified XSAVE feature mask. */
3156 const struct target_desc
*
3157 amd64_target_description (uint64_t xcr0
)
3159 switch (xcr0
& X86_XSTATE_ALL_MASK
)
3161 case X86_XSTATE_MPX_AVX512_MASK
:
3162 case X86_XSTATE_AVX512_MASK
:
3163 return tdesc_amd64_avx512
;
3164 case X86_XSTATE_MPX_MASK
:
3165 return tdesc_amd64_mpx
;
3166 case X86_XSTATE_AVX_MASK
:
3167 return tdesc_amd64_avx
;
3173 /* Provide a prototype to silence -Wmissing-prototypes. */
3174 void _initialize_amd64_tdep (void);
3177 _initialize_amd64_tdep (void)
3179 initialize_tdesc_amd64 ();
3180 initialize_tdesc_amd64_avx ();
3181 initialize_tdesc_amd64_mpx ();
3182 initialize_tdesc_amd64_avx512 ();
3184 initialize_tdesc_x32 ();
3185 initialize_tdesc_x32_avx ();
3186 initialize_tdesc_x32_avx512 ();
3190 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3191 sense that the instruction pointer and data pointer are simply
3192 64-bit offsets into the code segment and the data segment instead
3193 of a selector offset pair. The functions below store the upper 32
3194 bits of these pointers (instead of just the 16-bits of the segment
3197 /* Fill register REGNUM in REGCACHE with the appropriate
3198 floating-point or SSE register value from *FXSAVE. If REGNUM is
3199 -1, do this for all registers. This function masks off any of the
3200 reserved bits in *FXSAVE. */
3203 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3206 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3209 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3212 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3214 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3216 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3217 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3218 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3219 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3223 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3226 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3229 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3232 i387_supply_xsave (regcache
, regnum
, xsave
);
3235 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3237 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3239 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3240 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3242 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3243 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3248 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3249 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3250 all registers. This function doesn't touch any of the reserved
3254 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3257 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3258 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3259 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3261 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3263 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3265 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3266 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3267 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3268 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3272 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3275 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3276 void *xsave
, int gcore
)
3278 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3280 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3282 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3284 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3286 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3287 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3289 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3290 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),