1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 Contributed by Jiri Smid, SuSE Labs.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "opcode/i386.h"
26 #include "arch-utils.h"
28 #include "dummy-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
40 #include "gdb_assert.h"
42 #include "amd64-tdep.h"
43 #include "i387-tdep.h"
45 #include "features/i386/amd64.c"
46 #include "features/i386/amd64-avx.c"
48 /* Note that the AMD64 architecture was previously known as x86-64.
49 The latter is (forever) engraved into the canonical system name as
50 returned by config.guess, and used as the name for the AMD64 port
51 of GNU/Linux. The BSD's have renamed their ports to amd64; they
52 don't like to shout. For GDB we prefer the amd64_-prefix over the
53 x86_64_-prefix since it's so much easier to type. */
55 /* Register information. */
57 static const char *amd64_register_names
[] =
59 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
61 /* %r8 is indeed register number 8. */
62 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
63 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
65 /* %st0 is register number 24. */
66 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
67 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
69 /* %xmm0 is register number 40. */
70 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
71 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
75 static const char *amd64_ymm_names
[] =
77 "ymm0", "ymm1", "ymm2", "ymm3",
78 "ymm4", "ymm5", "ymm6", "ymm7",
79 "ymm8", "ymm9", "ymm10", "ymm11",
80 "ymm12", "ymm13", "ymm14", "ymm15"
83 static const char *amd64_ymmh_names
[] =
85 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
86 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
87 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
88 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
91 /* The registers used to pass integer arguments during a function call. */
92 static int amd64_dummy_call_integer_regs
[] =
94 AMD64_RDI_REGNUM
, /* %rdi */
95 AMD64_RSI_REGNUM
, /* %rsi */
96 AMD64_RDX_REGNUM
, /* %rdx */
97 AMD64_RCX_REGNUM
, /* %rcx */
102 /* DWARF Register Number Mapping as defined in the System V psABI,
105 static int amd64_dwarf_regmap
[] =
107 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
108 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
109 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
110 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
112 /* Frame Pointer Register RBP. */
115 /* Stack Pointer Register RSP. */
118 /* Extended Integer Registers 8 - 15. */
119 8, 9, 10, 11, 12, 13, 14, 15,
121 /* Return Address RA. Mapped to RIP. */
124 /* SSE Registers 0 - 7. */
125 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
126 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
127 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
128 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
130 /* Extended SSE Registers 8 - 15. */
131 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
132 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
133 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
134 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
136 /* Floating Point Registers 0-7. */
137 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
138 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
139 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
140 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
142 /* Control and Status Flags Register. */
145 /* Selector Registers. */
155 /* Segment Base Address Registers. */
161 /* Special Selector Registers. */
165 /* Floating Point Control Registers. */
171 static const int amd64_dwarf_regmap_len
=
172 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
174 /* Convert DWARF register number REG to the appropriate register
175 number used by GDB. */
178 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 int ymm0_regnum
= tdep
->ymm0_regnum
;
184 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
185 regnum
= amd64_dwarf_regmap
[reg
];
188 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
189 else if (ymm0_regnum
>= 0
190 && i386_xmm_regnum_p (gdbarch
, regnum
))
191 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
196 /* Map architectural register numbers to gdb register numbers. */
198 static const int amd64_arch_regmap
[16] =
200 AMD64_RAX_REGNUM
, /* %rax */
201 AMD64_RCX_REGNUM
, /* %rcx */
202 AMD64_RDX_REGNUM
, /* %rdx */
203 AMD64_RBX_REGNUM
, /* %rbx */
204 AMD64_RSP_REGNUM
, /* %rsp */
205 AMD64_RBP_REGNUM
, /* %rbp */
206 AMD64_RSI_REGNUM
, /* %rsi */
207 AMD64_RDI_REGNUM
, /* %rdi */
208 AMD64_R8_REGNUM
, /* %r8 */
209 AMD64_R9_REGNUM
, /* %r9 */
210 AMD64_R10_REGNUM
, /* %r10 */
211 AMD64_R11_REGNUM
, /* %r11 */
212 AMD64_R12_REGNUM
, /* %r12 */
213 AMD64_R13_REGNUM
, /* %r13 */
214 AMD64_R14_REGNUM
, /* %r14 */
215 AMD64_R15_REGNUM
/* %r15 */
218 static const int amd64_arch_regmap_len
=
219 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
221 /* Convert architectural register number REG to the appropriate register
222 number used by GDB. */
225 amd64_arch_reg_to_regnum (int reg
)
227 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
229 return amd64_arch_regmap
[reg
];
232 /* Register names for byte pseudo-registers. */
234 static const char *amd64_byte_names
[] =
236 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
237 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
238 "ah", "bh", "ch", "dh"
241 /* Number of lower byte registers. */
242 #define AMD64_NUM_LOWER_BYTE_REGS 16
244 /* Register names for word pseudo-registers. */
246 static const char *amd64_word_names
[] =
248 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
249 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
252 /* Register names for dword pseudo-registers. */
254 static const char *amd64_dword_names
[] =
256 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
257 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
260 /* Return the name of register REGNUM. */
263 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
265 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
266 if (i386_byte_regnum_p (gdbarch
, regnum
))
267 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
268 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
269 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
270 else if (i386_word_regnum_p (gdbarch
, regnum
))
271 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
272 else if (i386_dword_regnum_p (gdbarch
, regnum
))
273 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
275 return i386_pseudo_register_name (gdbarch
, regnum
);
279 amd64_pseudo_register_read (struct gdbarch
*gdbarch
,
280 struct regcache
*regcache
,
281 int regnum
, gdb_byte
*buf
)
283 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
286 if (i386_byte_regnum_p (gdbarch
, regnum
))
288 int gpnum
= regnum
- tdep
->al_regnum
;
290 /* Extract (always little endian). */
291 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
293 /* Special handling for AH, BH, CH, DH. */
294 regcache_raw_read (regcache
,
295 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
296 memcpy (buf
, raw_buf
+ 1, 1);
300 regcache_raw_read (regcache
, gpnum
, raw_buf
);
301 memcpy (buf
, raw_buf
, 1);
304 else if (i386_dword_regnum_p (gdbarch
, regnum
))
306 int gpnum
= regnum
- tdep
->eax_regnum
;
307 /* Extract (always little endian). */
308 regcache_raw_read (regcache
, gpnum
, raw_buf
);
309 memcpy (buf
, raw_buf
, 4);
312 i386_pseudo_register_read (gdbarch
, regcache
, regnum
, buf
);
316 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
317 struct regcache
*regcache
,
318 int regnum
, const gdb_byte
*buf
)
320 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
321 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
323 if (i386_byte_regnum_p (gdbarch
, regnum
))
325 int gpnum
= regnum
- tdep
->al_regnum
;
327 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
329 /* Read ... AH, BH, CH, DH. */
330 regcache_raw_read (regcache
,
331 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
332 /* ... Modify ... (always little endian). */
333 memcpy (raw_buf
+ 1, buf
, 1);
335 regcache_raw_write (regcache
,
336 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
341 regcache_raw_read (regcache
, gpnum
, raw_buf
);
342 /* ... Modify ... (always little endian). */
343 memcpy (raw_buf
, buf
, 1);
345 regcache_raw_write (regcache
, gpnum
, raw_buf
);
348 else if (i386_dword_regnum_p (gdbarch
, regnum
))
350 int gpnum
= regnum
- tdep
->eax_regnum
;
353 regcache_raw_read (regcache
, gpnum
, raw_buf
);
354 /* ... Modify ... (always little endian). */
355 memcpy (raw_buf
, buf
, 4);
357 regcache_raw_write (regcache
, gpnum
, raw_buf
);
360 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
365 /* Return the union class of CLASS1 and CLASS2. See the psABI for
368 static enum amd64_reg_class
369 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
371 /* Rule (a): If both classes are equal, this is the resulting class. */
372 if (class1
== class2
)
375 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
376 is the other class. */
377 if (class1
== AMD64_NO_CLASS
)
379 if (class2
== AMD64_NO_CLASS
)
382 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
383 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
386 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
387 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
388 return AMD64_INTEGER
;
390 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
391 MEMORY is used as class. */
392 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
393 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
394 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
397 /* Rule (f): Otherwise class SSE is used. */
401 /* Return non-zero if TYPE is a non-POD structure or union type. */
404 amd64_non_pod_p (struct type
*type
)
406 /* ??? A class with a base class certainly isn't POD, but does this
407 catch all non-POD structure types? */
408 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
414 /* Classify TYPE according to the rules for aggregate (structures and
415 arrays) and union types, and store the result in CLASS. */
418 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
420 int len
= TYPE_LENGTH (type
);
422 /* 1. If the size of an object is larger than two eightbytes, or in
423 C++, is a non-POD structure or union type, or contains
424 unaligned fields, it has class memory. */
425 if (len
> 16 || amd64_non_pod_p (type
))
427 class[0] = class[1] = AMD64_MEMORY
;
431 /* 2. Both eightbytes get initialized to class NO_CLASS. */
432 class[0] = class[1] = AMD64_NO_CLASS
;
434 /* 3. Each field of an object is classified recursively so that
435 always two fields are considered. The resulting class is
436 calculated according to the classes of the fields in the
439 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
441 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
443 /* All fields in an array have the same type. */
444 amd64_classify (subtype
, class);
445 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
452 /* Structure or union. */
453 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
454 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
456 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
458 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
459 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
460 enum amd64_reg_class subclass
[2];
461 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
465 bitsize
= TYPE_LENGTH (subtype
) * 8;
466 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
468 /* Ignore static fields. */
469 if (field_is_static (&TYPE_FIELD (type
, i
)))
472 gdb_assert (pos
== 0 || pos
== 1);
474 amd64_classify (subtype
, subclass
);
475 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
476 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
477 /* This is a bit of an odd case: We have a field that would
478 normally fit in one of the two eightbytes, except that
479 it is placed in a way that this field straddles them.
480 This has been seen with a structure containing an array.
482 The ABI is a bit unclear in this case, but we assume that
483 this field's class (stored in subclass[0]) must also be merged
484 into class[1]. In other words, our field has a piece stored
485 in the second eight-byte, and thus its class applies to
486 the second eight-byte as well.
488 In the case where the field length exceeds 8 bytes,
489 it should not be necessary to merge the field class
490 into class[1]. As LEN > 8, subclass[1] is necessarily
491 different from AMD64_NO_CLASS. If subclass[1] is equal
492 to subclass[0], then the normal class[1]/subclass[1]
493 merging will take care of everything. For subclass[1]
494 to be different from subclass[0], I can only see the case
495 where we have a SSE/SSEUP or X87/X87UP pair, which both
496 use up all 16 bytes of the aggregate, and are already
497 handled just fine (because each portion sits on its own
499 class[1] = amd64_merge_classes (class[1], subclass
[0]);
501 class[1] = amd64_merge_classes (class[1], subclass
[1]);
505 /* 4. Then a post merger cleanup is done: */
507 /* Rule (a): If one of the classes is MEMORY, the whole argument is
509 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
510 class[0] = class[1] = AMD64_MEMORY
;
512 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
514 if (class[0] == AMD64_SSEUP
)
515 class[0] = AMD64_SSE
;
516 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
517 class[1] = AMD64_SSE
;
520 /* Classify TYPE, and store the result in CLASS. */
523 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
525 enum type_code code
= TYPE_CODE (type
);
526 int len
= TYPE_LENGTH (type
);
528 class[0] = class[1] = AMD64_NO_CLASS
;
530 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
531 long, long long, and pointers are in the INTEGER class. Similarly,
532 range types, used by languages such as Ada, are also in the INTEGER
534 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
535 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
536 || code
== TYPE_CODE_CHAR
537 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
538 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
539 class[0] = AMD64_INTEGER
;
541 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
543 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
544 && (len
== 4 || len
== 8))
546 class[0] = AMD64_SSE
;
548 /* Arguments of types __float128, _Decimal128 and __m128 are split into
549 two halves. The least significant ones belong to class SSE, the most
550 significant one to class SSEUP. */
551 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
552 /* FIXME: __float128, __m128. */
553 class[0] = AMD64_SSE
, class[1] = AMD64_SSEUP
;
555 /* The 64-bit mantissa of arguments of type long double belongs to
556 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
558 else if (code
== TYPE_CODE_FLT
&& len
== 16)
559 /* Class X87 and X87UP. */
560 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
563 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
564 || code
== TYPE_CODE_UNION
)
565 amd64_classify_aggregate (type
, class);
568 static enum return_value_convention
569 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
570 struct type
*type
, struct regcache
*regcache
,
571 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
573 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
574 enum amd64_reg_class
class[2];
575 int len
= TYPE_LENGTH (type
);
576 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
577 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
582 gdb_assert (!(readbuf
&& writebuf
));
583 gdb_assert (tdep
->classify
);
585 /* 1. Classify the return type with the classification algorithm. */
586 tdep
->classify (type
, class);
588 /* 2. If the type has class MEMORY, then the caller provides space
589 for the return value and passes the address of this storage in
590 %rdi as if it were the first argument to the function. In effect,
591 this address becomes a hidden first argument.
593 On return %rax will contain the address that has been passed in
594 by the caller in %rdi. */
595 if (class[0] == AMD64_MEMORY
)
597 /* As indicated by the comment above, the ABI guarantees that we
598 can always find the return value just after the function has
605 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
606 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
609 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
612 gdb_assert (class[1] != AMD64_MEMORY
);
613 gdb_assert (len
<= 16);
615 for (i
= 0; len
> 0; i
++, len
-= 8)
623 /* 3. If the class is INTEGER, the next available register
624 of the sequence %rax, %rdx is used. */
625 regnum
= integer_regnum
[integer_reg
++];
629 /* 4. If the class is SSE, the next available SSE register
630 of the sequence %xmm0, %xmm1 is used. */
631 regnum
= sse_regnum
[sse_reg
++];
635 /* 5. If the class is SSEUP, the eightbyte is passed in the
636 upper half of the last used SSE register. */
637 gdb_assert (sse_reg
> 0);
638 regnum
= sse_regnum
[sse_reg
- 1];
643 /* 6. If the class is X87, the value is returned on the X87
644 stack in %st0 as 80-bit x87 number. */
645 regnum
= AMD64_ST0_REGNUM
;
647 i387_return_value (gdbarch
, regcache
);
651 /* 7. If the class is X87UP, the value is returned together
652 with the previous X87 value in %st0. */
653 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
654 regnum
= AMD64_ST0_REGNUM
;
663 gdb_assert (!"Unexpected register class.");
666 gdb_assert (regnum
!= -1);
669 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
672 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
676 return RETURN_VALUE_REGISTER_CONVENTION
;
681 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
682 struct value
**args
, CORE_ADDR sp
, int struct_return
)
684 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
685 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
686 int *integer_regs
= tdep
->call_dummy_integer_regs
;
687 int num_integer_regs
= tdep
->call_dummy_num_integer_regs
;
689 static int sse_regnum
[] =
691 /* %xmm0 ... %xmm7 */
692 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
693 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
694 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
695 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
697 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
698 /* An array that mirrors the stack_args array. For all arguments
699 that are passed by MEMORY, if that argument's address also needs
700 to be stored in a register, the ARG_ADDR_REGNO array will contain
701 that register number (or a negative value otherwise). */
702 int *arg_addr_regno
= alloca (nargs
* sizeof (int));
703 int num_stack_args
= 0;
704 int num_elements
= 0;
710 gdb_assert (tdep
->classify
);
712 /* Reserve a register for the "hidden" argument. */
716 for (i
= 0; i
< nargs
; i
++)
718 struct type
*type
= value_type (args
[i
]);
719 int len
= TYPE_LENGTH (type
);
720 enum amd64_reg_class
class[2];
721 int needed_integer_regs
= 0;
722 int needed_sse_regs
= 0;
725 /* Classify argument. */
726 tdep
->classify (type
, class);
728 /* Calculate the number of integer and SSE registers needed for
730 for (j
= 0; j
< 2; j
++)
732 if (class[j
] == AMD64_INTEGER
)
733 needed_integer_regs
++;
734 else if (class[j
] == AMD64_SSE
)
738 /* Check whether enough registers are available, and if the
739 argument should be passed in registers at all. */
740 if (integer_reg
+ needed_integer_regs
> num_integer_regs
741 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
742 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
744 /* The argument will be passed on the stack. */
745 num_elements
+= ((len
+ 7) / 8);
746 stack_args
[num_stack_args
] = args
[i
];
747 /* If this is an AMD64_MEMORY argument whose address must also
748 be passed in one of the integer registers, reserve that
749 register and associate this value to that register so that
750 we can store the argument address as soon as we know it. */
751 if (class[0] == AMD64_MEMORY
752 && tdep
->memory_args_by_pointer
753 && integer_reg
< tdep
->call_dummy_num_integer_regs
)
754 arg_addr_regno
[num_stack_args
] =
755 tdep
->call_dummy_integer_regs
[integer_reg
++];
757 arg_addr_regno
[num_stack_args
] = -1;
762 /* The argument will be passed in registers. */
763 const gdb_byte
*valbuf
= value_contents (args
[i
]);
766 gdb_assert (len
<= 16);
768 for (j
= 0; len
> 0; j
++, len
-= 8)
776 regnum
= integer_regs
[integer_reg
++];
780 regnum
= sse_regnum
[sse_reg
++];
784 gdb_assert (sse_reg
> 0);
785 regnum
= sse_regnum
[sse_reg
- 1];
790 gdb_assert (!"Unexpected register class.");
793 gdb_assert (regnum
!= -1);
794 memset (buf
, 0, sizeof buf
);
795 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
796 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
801 /* Allocate space for the arguments on the stack. */
802 sp
-= num_elements
* 8;
804 /* The psABI says that "The end of the input argument area shall be
805 aligned on a 16 byte boundary." */
808 /* Write out the arguments to the stack. */
809 for (i
= 0; i
< num_stack_args
; i
++)
811 struct type
*type
= value_type (stack_args
[i
]);
812 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
813 int len
= TYPE_LENGTH (type
);
814 CORE_ADDR arg_addr
= sp
+ element
* 8;
816 write_memory (arg_addr
, valbuf
, len
);
817 if (arg_addr_regno
[i
] >= 0)
819 /* We also need to store the address of that argument in
820 the given register. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
824 store_unsigned_integer (buf
, 8, byte_order
, arg_addr
);
825 regcache_cooked_write (regcache
, arg_addr_regno
[i
], buf
);
827 element
+= ((len
+ 7) / 8);
830 /* The psABI says that "For calls that may call functions that use
831 varargs or stdargs (prototype-less calls or calls to functions
832 containing ellipsis (...) in the declaration) %al is used as
833 hidden argument to specify the number of SSE registers used. */
834 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
839 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
840 struct regcache
*regcache
, CORE_ADDR bp_addr
,
841 int nargs
, struct value
**args
, CORE_ADDR sp
,
842 int struct_return
, CORE_ADDR struct_addr
)
844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
845 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
848 /* Pass arguments. */
849 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
851 /* Pass "hidden" argument". */
854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
855 /* The "hidden" argument is passed throught the first argument
857 const int arg_regnum
= tdep
->call_dummy_integer_regs
[0];
859 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
860 regcache_cooked_write (regcache
, arg_regnum
, buf
);
863 /* Reserve some memory on the stack for the integer-parameter registers,
864 if required by the ABI. */
865 if (tdep
->integer_param_regs_saved_in_caller_frame
)
866 sp
-= tdep
->call_dummy_num_integer_regs
* 8;
868 /* Store return address. */
870 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
871 write_memory (sp
, buf
, 8);
873 /* Finally, update the stack pointer... */
874 store_unsigned_integer (buf
, 8, byte_order
, sp
);
875 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
877 /* ...and fake a frame pointer. */
878 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
883 /* Displaced instruction handling. */
885 /* A partially decoded instruction.
886 This contains enough details for displaced stepping purposes. */
890 /* The number of opcode bytes. */
892 /* The offset of the rex prefix or -1 if not present. */
894 /* The offset to the first opcode byte. */
896 /* The offset to the modrm byte or -1 if not present. */
899 /* The raw instruction. */
903 struct displaced_step_closure
905 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
910 /* Details of the instruction. */
911 struct amd64_insn insn_details
;
913 /* Amount of space allocated to insn_buf. */
916 /* The possibly modified insn.
917 This is a variable-length field. */
918 gdb_byte insn_buf
[1];
921 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
922 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
923 at which point delete these in favor of libopcodes' versions). */
925 static const unsigned char onebyte_has_modrm
[256] = {
926 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
927 /* ------------------------------- */
928 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
929 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
930 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
931 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
932 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
933 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
934 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
935 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
936 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
937 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
938 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
939 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
940 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
941 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
942 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
943 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
944 /* ------------------------------- */
945 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
948 static const unsigned char twobyte_has_modrm
[256] = {
949 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
950 /* ------------------------------- */
951 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
952 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
953 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
954 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
955 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
956 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
957 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
958 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
959 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
960 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
961 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
962 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
963 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
964 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
965 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
966 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
967 /* ------------------------------- */
968 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
971 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
974 rex_prefix_p (gdb_byte pfx
)
976 return REX_PREFIX_P (pfx
);
979 /* Skip the legacy instruction prefixes in INSN.
980 We assume INSN is properly sentineled so we don't have to worry
981 about falling off the end of the buffer. */
984 amd64_skip_prefixes (gdb_byte
*insn
)
990 case DATA_PREFIX_OPCODE
:
991 case ADDR_PREFIX_OPCODE
:
992 case CS_PREFIX_OPCODE
:
993 case DS_PREFIX_OPCODE
:
994 case ES_PREFIX_OPCODE
:
995 case FS_PREFIX_OPCODE
:
996 case GS_PREFIX_OPCODE
:
997 case SS_PREFIX_OPCODE
:
998 case LOCK_PREFIX_OPCODE
:
999 case REPE_PREFIX_OPCODE
:
1000 case REPNE_PREFIX_OPCODE
:
1012 /* Return an integer register (other than RSP) that is unused as an input
1014 In order to not require adding a rex prefix if the insn doesn't already
1015 have one, the result is restricted to RAX ... RDI, sans RSP.
1016 The register numbering of the result follows architecture ordering,
1020 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1022 /* 1 bit for each reg */
1023 int used_regs_mask
= 0;
1025 /* There can be at most 3 int regs used as inputs in an insn, and we have
1026 7 to choose from (RAX ... RDI, sans RSP).
1027 This allows us to take a conservative approach and keep things simple.
1028 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1029 that implicitly specify RAX. */
1032 used_regs_mask
|= 1 << EAX_REG_NUM
;
1033 /* Similarily avoid RDX, implicit operand in divides. */
1034 used_regs_mask
|= 1 << EDX_REG_NUM
;
1036 used_regs_mask
|= 1 << ESP_REG_NUM
;
1038 /* If the opcode is one byte long and there's no ModRM byte,
1039 assume the opcode specifies a register. */
1040 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1041 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1043 /* Mark used regs in the modrm/sib bytes. */
1044 if (details
->modrm_offset
!= -1)
1046 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1047 int mod
= MODRM_MOD_FIELD (modrm
);
1048 int reg
= MODRM_REG_FIELD (modrm
);
1049 int rm
= MODRM_RM_FIELD (modrm
);
1050 int have_sib
= mod
!= 3 && rm
== 4;
1052 /* Assume the reg field of the modrm byte specifies a register. */
1053 used_regs_mask
|= 1 << reg
;
1057 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1058 int index
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1059 used_regs_mask
|= 1 << base
;
1060 used_regs_mask
|= 1 << index
;
1064 used_regs_mask
|= 1 << rm
;
1068 gdb_assert (used_regs_mask
< 256);
1069 gdb_assert (used_regs_mask
!= 255);
1071 /* Finally, find a free reg. */
1075 for (i
= 0; i
< 8; ++i
)
1077 if (! (used_regs_mask
& (1 << i
)))
1081 /* We shouldn't get here. */
1082 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1086 /* Extract the details of INSN that we need. */
1089 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1091 gdb_byte
*start
= insn
;
1094 details
->raw_insn
= insn
;
1096 details
->opcode_len
= -1;
1097 details
->rex_offset
= -1;
1098 details
->opcode_offset
= -1;
1099 details
->modrm_offset
= -1;
1101 /* Skip legacy instruction prefixes. */
1102 insn
= amd64_skip_prefixes (insn
);
1104 /* Skip REX instruction prefix. */
1105 if (rex_prefix_p (*insn
))
1107 details
->rex_offset
= insn
- start
;
1111 details
->opcode_offset
= insn
- start
;
1113 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1115 /* Two or three-byte opcode. */
1117 need_modrm
= twobyte_has_modrm
[*insn
];
1119 /* Check for three-byte opcode. */
1129 details
->opcode_len
= 3;
1132 details
->opcode_len
= 2;
1138 /* One-byte opcode. */
1139 need_modrm
= onebyte_has_modrm
[*insn
];
1140 details
->opcode_len
= 1;
1146 details
->modrm_offset
= insn
- start
;
1150 /* Update %rip-relative addressing in INSN.
1152 %rip-relative addressing only uses a 32-bit displacement.
1153 32 bits is not enough to be guaranteed to cover the distance between where
1154 the real instruction is and where its copy is.
1155 Convert the insn to use base+disp addressing.
1156 We set base = pc + insn_length so we can leave disp unchanged. */
1159 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1160 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1163 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1164 int modrm_offset
= insn_details
->modrm_offset
;
1165 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1169 int arch_tmp_regno
, tmp_regno
;
1170 ULONGEST orig_value
;
1172 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1175 /* Compute the rip-relative address. */
1176 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1177 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1178 dsc
->max_len
, from
);
1179 rip_base
= from
+ insn_length
;
1181 /* We need a register to hold the address.
1182 Pick one not used in the insn.
1183 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1184 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1185 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1187 /* REX.B should be unset as we were using rip-relative addressing,
1188 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1189 if (insn_details
->rex_offset
!= -1)
1190 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1192 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1193 dsc
->tmp_regno
= tmp_regno
;
1194 dsc
->tmp_save
= orig_value
;
1197 /* Convert the ModRM field to be base+disp. */
1198 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1199 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1201 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1203 if (debug_displaced
)
1204 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1205 "displaced: using temp reg %d, old value %s, new value %s\n",
1206 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1207 paddress (gdbarch
, rip_base
));
1211 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1212 struct displaced_step_closure
*dsc
,
1213 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1215 const struct amd64_insn
*details
= &dsc
->insn_details
;
1217 if (details
->modrm_offset
!= -1)
1219 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1221 if ((modrm
& 0xc7) == 0x05)
1223 /* The insn uses rip-relative addressing.
1225 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1230 struct displaced_step_closure
*
1231 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1232 CORE_ADDR from
, CORE_ADDR to
,
1233 struct regcache
*regs
)
1235 int len
= gdbarch_max_insn_length (gdbarch
);
1236 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to
1237 continually watch for running off the end of the buffer. */
1238 int fixup_sentinel_space
= len
;
1239 struct displaced_step_closure
*dsc
=
1240 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1241 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1242 struct amd64_insn
*details
= &dsc
->insn_details
;
1245 dsc
->max_len
= len
+ fixup_sentinel_space
;
1247 read_memory (from
, buf
, len
);
1249 /* Set up the sentinel space so we don't have to worry about running
1250 off the end of the buffer. An excessive number of leading prefixes
1251 could otherwise cause this. */
1252 memset (buf
+ len
, 0, fixup_sentinel_space
);
1254 amd64_get_insn_details (buf
, details
);
1256 /* GDB may get control back after the insn after the syscall.
1257 Presumably this is a kernel bug.
1258 If this is a syscall, make sure there's a nop afterwards. */
1262 if (amd64_syscall_p (details
, &syscall_length
))
1263 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1266 /* Modify the insn to cope with the address where it will be executed from.
1267 In particular, handle any rip-relative addressing. */
1268 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1270 write_memory (to
, buf
, len
);
1272 if (debug_displaced
)
1274 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1275 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1276 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1283 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1285 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1287 if (insn
[0] == 0xff)
1289 /* jump near, absolute indirect (/4) */
1290 if ((insn
[1] & 0x38) == 0x20)
1293 /* jump far, absolute indirect (/5) */
1294 if ((insn
[1] & 0x38) == 0x28)
1302 amd64_absolute_call_p (const struct amd64_insn
*details
)
1304 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1306 if (insn
[0] == 0xff)
1308 /* Call near, absolute indirect (/2) */
1309 if ((insn
[1] & 0x38) == 0x10)
1312 /* Call far, absolute indirect (/3) */
1313 if ((insn
[1] & 0x38) == 0x18)
1321 amd64_ret_p (const struct amd64_insn
*details
)
1323 /* NOTE: gcc can emit "repz ; ret". */
1324 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1328 case 0xc2: /* ret near, pop N bytes */
1329 case 0xc3: /* ret near */
1330 case 0xca: /* ret far, pop N bytes */
1331 case 0xcb: /* ret far */
1332 case 0xcf: /* iret */
1341 amd64_call_p (const struct amd64_insn
*details
)
1343 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1345 if (amd64_absolute_call_p (details
))
1348 /* call near, relative */
1349 if (insn
[0] == 0xe8)
1355 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1356 length in bytes. Otherwise, return zero. */
1359 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1361 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1363 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1372 /* Fix up the state of registers and memory after having single-stepped
1373 a displaced instruction. */
1376 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1377 struct displaced_step_closure
*dsc
,
1378 CORE_ADDR from
, CORE_ADDR to
,
1379 struct regcache
*regs
)
1381 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1382 /* The offset we applied to the instruction's address. */
1383 ULONGEST insn_offset
= to
- from
;
1384 gdb_byte
*insn
= dsc
->insn_buf
;
1385 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1387 if (debug_displaced
)
1388 fprintf_unfiltered (gdb_stdlog
,
1389 "displaced: fixup (%s, %s), "
1390 "insn = 0x%02x 0x%02x ...\n",
1391 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1394 /* If we used a tmp reg, restore it. */
1398 if (debug_displaced
)
1399 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1400 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1401 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1404 /* The list of issues to contend with here is taken from
1405 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1406 Yay for Free Software! */
1408 /* Relocate the %rip back to the program's instruction stream,
1411 /* Except in the case of absolute or indirect jump or call
1412 instructions, or a return instruction, the new rip is relative to
1413 the displaced instruction; make it relative to the original insn.
1414 Well, signal handler returns don't need relocation either, but we use the
1415 value of %rip to recognize those; see below. */
1416 if (! amd64_absolute_jmp_p (insn_details
)
1417 && ! amd64_absolute_call_p (insn_details
)
1418 && ! amd64_ret_p (insn_details
))
1423 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1425 /* A signal trampoline system call changes the %rip, resuming
1426 execution of the main program after the signal handler has
1427 returned. That makes them like 'return' instructions; we
1428 shouldn't relocate %rip.
1430 But most system calls don't, and we do need to relocate %rip.
1432 Our heuristic for distinguishing these cases: if stepping
1433 over the system call instruction left control directly after
1434 the instruction, the we relocate --- control almost certainly
1435 doesn't belong in the displaced copy. Otherwise, we assume
1436 the instruction has put control where it belongs, and leave
1437 it unrelocated. Goodness help us if there are PC-relative
1439 if (amd64_syscall_p (insn_details
, &insn_len
)
1440 && orig_rip
!= to
+ insn_len
1441 /* GDB can get control back after the insn after the syscall.
1442 Presumably this is a kernel bug.
1443 Fixup ensures its a nop, we add one to the length for it. */
1444 && orig_rip
!= to
+ insn_len
+ 1)
1446 if (debug_displaced
)
1447 fprintf_unfiltered (gdb_stdlog
,
1448 "displaced: syscall changed %%rip; "
1449 "not relocating\n");
1453 ULONGEST rip
= orig_rip
- insn_offset
;
1455 /* If we just stepped over a breakpoint insn, we don't backup
1456 the pc on purpose; this is to match behaviour without
1459 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1461 if (debug_displaced
)
1462 fprintf_unfiltered (gdb_stdlog
,
1464 "relocated %%rip from %s to %s\n",
1465 paddress (gdbarch
, orig_rip
),
1466 paddress (gdbarch
, rip
));
1470 /* If the instruction was PUSHFL, then the TF bit will be set in the
1471 pushed value, and should be cleared. We'll leave this for later,
1472 since GDB already messes up the TF flag when stepping over a
1475 /* If the instruction was a call, the return address now atop the
1476 stack is the address following the copied instruction. We need
1477 to make it the address following the original instruction. */
1478 if (amd64_call_p (insn_details
))
1482 const ULONGEST retaddr_len
= 8;
1484 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1485 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1486 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1487 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1489 if (debug_displaced
)
1490 fprintf_unfiltered (gdb_stdlog
,
1491 "displaced: relocated return addr at %s "
1493 paddress (gdbarch
, rsp
),
1494 paddress (gdbarch
, retaddr
));
1498 /* If the instruction INSN uses RIP-relative addressing, return the
1499 offset into the raw INSN where the displacement to be adjusted is
1500 found. Returns 0 if the instruction doesn't use RIP-relative
1504 rip_relative_offset (struct amd64_insn
*insn
)
1506 if (insn
->modrm_offset
!= -1)
1508 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1510 if ((modrm
& 0xc7) == 0x05)
1512 /* The displacement is found right after the ModRM byte. */
1513 return insn
->modrm_offset
+ 1;
1521 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1523 target_write_memory (*to
, buf
, len
);
1528 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1529 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1531 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1532 int len
= gdbarch_max_insn_length (gdbarch
);
1533 /* Extra space for sentinels. */
1534 int fixup_sentinel_space
= len
;
1535 gdb_byte
*buf
= xmalloc (len
+ fixup_sentinel_space
);
1536 struct amd64_insn insn_details
;
1538 LONGEST rel32
, newrel
;
1542 read_memory (oldloc
, buf
, len
);
1544 /* Set up the sentinel space so we don't have to worry about running
1545 off the end of the buffer. An excessive number of leading prefixes
1546 could otherwise cause this. */
1547 memset (buf
+ len
, 0, fixup_sentinel_space
);
1550 amd64_get_insn_details (insn
, &insn_details
);
1552 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1554 /* Skip legacy instruction prefixes. */
1555 insn
= amd64_skip_prefixes (insn
);
1557 /* Adjust calls with 32-bit relative addresses as push/jump, with
1558 the address pushed being the location where the original call in
1559 the user program would return to. */
1560 if (insn
[0] == 0xe8)
1562 gdb_byte push_buf
[16];
1563 unsigned int ret_addr
;
1565 /* Where "ret" in the original code will return to. */
1566 ret_addr
= oldloc
+ insn_length
;
1567 push_buf
[0] = 0x68; /* pushq $... */
1568 memcpy (&push_buf
[1], &ret_addr
, 4);
1569 /* Push the push. */
1570 append_insns (to
, 5, push_buf
);
1572 /* Convert the relative call to a relative jump. */
1575 /* Adjust the destination offset. */
1576 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1577 newrel
= (oldloc
- *to
) + rel32
;
1578 store_signed_integer (insn
+ 1, 4, newrel
, byte_order
);
1580 /* Write the adjusted jump into its displaced location. */
1581 append_insns (to
, 5, insn
);
1585 offset
= rip_relative_offset (&insn_details
);
1588 /* Adjust jumps with 32-bit relative addresses. Calls are
1589 already handled above. */
1590 if (insn
[0] == 0xe9)
1592 /* Adjust conditional jumps. */
1593 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1599 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1600 newrel
= (oldloc
- *to
) + rel32
;
1601 store_signed_integer (insn
+ offset
, 4, newrel
, byte_order
);
1602 if (debug_displaced
)
1603 fprintf_unfiltered (gdb_stdlog
,
1604 "Adjusted insn rel32=0x%s at 0x%s to"
1605 " rel32=0x%s at 0x%s\n",
1606 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1607 hex_string (newrel
), paddress (gdbarch
, *to
));
1610 /* Write the adjusted instruction into its displaced location. */
1611 append_insns (to
, insn_length
, buf
);
1615 /* The maximum number of saved registers. This should include %rip. */
1616 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1618 struct amd64_frame_cache
1622 CORE_ADDR sp_offset
;
1625 /* Saved registers. */
1626 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1630 /* Do we have a frame? */
1634 /* Initialize a frame cache. */
1637 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1643 cache
->sp_offset
= -8;
1646 /* Saved registers. We initialize these to -1 since zero is a valid
1647 offset (that's where %rbp is supposed to be stored).
1648 The values start out as being offsets, and are later converted to
1649 addresses (at which point -1 is interpreted as an address, still meaning
1651 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1652 cache
->saved_regs
[i
] = -1;
1653 cache
->saved_sp
= 0;
1654 cache
->saved_sp_reg
= -1;
1656 /* Frameless until proven otherwise. */
1657 cache
->frameless_p
= 1;
1660 /* Allocate and initialize a frame cache. */
1662 static struct amd64_frame_cache
*
1663 amd64_alloc_frame_cache (void)
1665 struct amd64_frame_cache
*cache
;
1667 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1668 amd64_init_frame_cache (cache
);
1672 /* GCC 4.4 and later, can put code in the prologue to realign the
1673 stack pointer. Check whether PC points to such code, and update
1674 CACHE accordingly. Return the first instruction after the code
1675 sequence or CURRENT_PC, whichever is smaller. If we don't
1676 recognize the code, return PC. */
1679 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1680 struct amd64_frame_cache
*cache
)
1682 /* There are 2 code sequences to re-align stack before the frame
1685 1. Use a caller-saved saved register:
1691 2. Use a callee-saved saved register:
1698 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1700 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1701 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1706 int offset
, offset_and
;
1708 if (target_read_memory (pc
, buf
, sizeof buf
))
1711 /* Check caller-saved saved register. The first instruction has
1712 to be "leaq 8(%rsp), %reg". */
1713 if ((buf
[0] & 0xfb) == 0x48
1718 /* MOD must be binary 10 and R/M must be binary 100. */
1719 if ((buf
[2] & 0xc7) != 0x44)
1722 /* REG has register number. */
1723 reg
= (buf
[2] >> 3) & 7;
1725 /* Check the REX.R bit. */
1733 /* Check callee-saved saved register. The first instruction
1734 has to be "pushq %reg". */
1736 if ((buf
[0] & 0xf8) == 0x50)
1738 else if ((buf
[0] & 0xf6) == 0x40
1739 && (buf
[1] & 0xf8) == 0x50)
1741 /* Check the REX.B bit. */
1742 if ((buf
[0] & 1) != 0)
1751 reg
+= buf
[offset
] & 0x7;
1755 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1756 if ((buf
[offset
] & 0xfb) != 0x48
1757 || buf
[offset
+ 1] != 0x8d
1758 || buf
[offset
+ 3] != 0x24
1759 || buf
[offset
+ 4] != 0x10)
1762 /* MOD must be binary 10 and R/M must be binary 100. */
1763 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1766 /* REG has register number. */
1767 r
= (buf
[offset
+ 2] >> 3) & 7;
1769 /* Check the REX.R bit. */
1770 if (buf
[offset
] == 0x4c)
1773 /* Registers in pushq and leaq have to be the same. */
1780 /* Rigister can't be %rsp nor %rbp. */
1781 if (reg
== 4 || reg
== 5)
1784 /* The next instruction has to be "andq $-XXX, %rsp". */
1785 if (buf
[offset
] != 0x48
1786 || buf
[offset
+ 2] != 0xe4
1787 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1790 offset_and
= offset
;
1791 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1793 /* The next instruction has to be "pushq -8(%reg)". */
1795 if (buf
[offset
] == 0xff)
1797 else if ((buf
[offset
] & 0xf6) == 0x40
1798 && buf
[offset
+ 1] == 0xff)
1800 /* Check the REX.B bit. */
1801 if ((buf
[offset
] & 0x1) != 0)
1808 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1810 if (buf
[offset
+ 1] != 0xf8
1811 || (buf
[offset
] & 0xf8) != 0x70)
1814 /* R/M has register. */
1815 r
+= buf
[offset
] & 7;
1817 /* Registers in leaq and pushq have to be the same. */
1821 if (current_pc
> pc
+ offset_and
)
1822 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
1824 return min (pc
+ offset
+ 2, current_pc
);
1827 /* Do a limited analysis of the prologue at PC and update CACHE
1828 accordingly. Bail out early if CURRENT_PC is reached. Return the
1829 address where the analysis stopped.
1831 We will handle only functions beginning with:
1834 movq %rsp, %rbp 0x48 0x89 0xe5
1836 Any function that doesn't start with this sequence will be assumed
1837 to have no prologue and thus no valid frame pointer in %rbp. */
1840 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
1841 CORE_ADDR pc
, CORE_ADDR current_pc
,
1842 struct amd64_frame_cache
*cache
)
1844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1845 static gdb_byte proto
[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */
1849 if (current_pc
<= pc
)
1852 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
1854 op
= read_memory_unsigned_integer (pc
, 1, byte_order
);
1856 if (op
== 0x55) /* pushq %rbp */
1858 /* Take into account that we've executed the `pushq %rbp' that
1859 starts this instruction sequence. */
1860 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
1861 cache
->sp_offset
+= 8;
1863 /* If that's all, return now. */
1864 if (current_pc
<= pc
+ 1)
1867 /* Check for `movq %rsp, %rbp'. */
1868 read_memory (pc
+ 1, buf
, 3);
1869 if (memcmp (buf
, proto
, 3) != 0)
1872 /* OK, we actually have a frame. */
1873 cache
->frameless_p
= 0;
1880 /* Return PC of first real instruction. */
1883 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1885 struct amd64_frame_cache cache
;
1888 amd64_init_frame_cache (&cache
);
1889 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
1891 if (cache
.frameless_p
)
1898 /* Normal frames. */
1900 static struct amd64_frame_cache
*
1901 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1903 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1904 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1905 struct amd64_frame_cache
*cache
;
1912 cache
= amd64_alloc_frame_cache ();
1913 *this_cache
= cache
;
1915 cache
->pc
= get_frame_func (this_frame
);
1917 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1920 if (cache
->saved_sp_reg
!= -1)
1922 /* Stack pointer has been saved. */
1923 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1924 cache
->saved_sp
= extract_unsigned_integer(buf
, 8, byte_order
);
1927 if (cache
->frameless_p
)
1929 /* We didn't find a valid frame. If we're at the start of a
1930 function, or somewhere half-way its prologue, the function's
1931 frame probably hasn't been fully setup yet. Try to
1932 reconstruct the base address for the stack frame by looking
1933 at the stack pointer. For truly "frameless" functions this
1936 if (cache
->saved_sp_reg
!= -1)
1938 /* We're halfway aligning the stack. */
1939 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
1940 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
1942 /* This will be added back below. */
1943 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
1947 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
1948 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
1954 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
1955 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
1958 /* Now that we have the base address for the stack frame we can
1959 calculate the value of %rsp in the calling frame. */
1960 cache
->saved_sp
= cache
->base
+ 16;
1962 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
1963 frame we find it at the same offset from the reconstructed base
1964 address. If we're halfway aligning the stack, %rip is handled
1965 differently (see above). */
1966 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
1967 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
1969 /* Adjust all the saved registers such that they contain addresses
1970 instead of offsets. */
1971 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1972 if (cache
->saved_regs
[i
] != -1)
1973 cache
->saved_regs
[i
] += cache
->base
;
1979 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1980 struct frame_id
*this_id
)
1982 struct amd64_frame_cache
*cache
=
1983 amd64_frame_cache (this_frame
, this_cache
);
1985 /* This marks the outermost frame. */
1986 if (cache
->base
== 0)
1989 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
1992 static struct value
*
1993 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1996 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1997 struct amd64_frame_cache
*cache
=
1998 amd64_frame_cache (this_frame
, this_cache
);
2000 gdb_assert (regnum
>= 0);
2002 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2003 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2005 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2006 return frame_unwind_got_memory (this_frame
, regnum
,
2007 cache
->saved_regs
[regnum
]);
2009 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2012 static const struct frame_unwind amd64_frame_unwind
=
2015 amd64_frame_this_id
,
2016 amd64_frame_prev_register
,
2018 default_frame_sniffer
2022 /* Signal trampolines. */
2024 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2025 64-bit variants. This would require using identical frame caches
2026 on both platforms. */
2028 static struct amd64_frame_cache
*
2029 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2031 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2033 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2034 struct amd64_frame_cache
*cache
;
2042 cache
= amd64_alloc_frame_cache ();
2044 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2045 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2047 addr
= tdep
->sigcontext_addr (this_frame
);
2048 gdb_assert (tdep
->sc_reg_offset
);
2049 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2050 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2051 if (tdep
->sc_reg_offset
[i
] != -1)
2052 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2054 *this_cache
= cache
;
2059 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2060 void **this_cache
, struct frame_id
*this_id
)
2062 struct amd64_frame_cache
*cache
=
2063 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2065 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2068 static struct value
*
2069 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2070 void **this_cache
, int regnum
)
2072 /* Make sure we've initialized the cache. */
2073 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2075 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2079 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2080 struct frame_info
*this_frame
,
2083 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2085 /* We shouldn't even bother if we don't have a sigcontext_addr
2087 if (tdep
->sigcontext_addr
== NULL
)
2090 if (tdep
->sigtramp_p
!= NULL
)
2092 if (tdep
->sigtramp_p (this_frame
))
2096 if (tdep
->sigtramp_start
!= 0)
2098 CORE_ADDR pc
= get_frame_pc (this_frame
);
2100 gdb_assert (tdep
->sigtramp_end
!= 0);
2101 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2108 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2111 amd64_sigtramp_frame_this_id
,
2112 amd64_sigtramp_frame_prev_register
,
2114 amd64_sigtramp_frame_sniffer
2119 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2121 struct amd64_frame_cache
*cache
=
2122 amd64_frame_cache (this_frame
, this_cache
);
2127 static const struct frame_base amd64_frame_base
=
2129 &amd64_frame_unwind
,
2130 amd64_frame_base_address
,
2131 amd64_frame_base_address
,
2132 amd64_frame_base_address
2135 /* Normal frames, but in a function epilogue. */
2137 /* The epilogue is defined here as the 'ret' instruction, which will
2138 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2139 the function's stack frame. */
2142 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2146 if (target_read_memory (pc
, &insn
, 1))
2147 return 0; /* Can't read memory at pc. */
2149 if (insn
!= 0xc3) /* 'ret' instruction. */
2156 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2157 struct frame_info
*this_frame
,
2158 void **this_prologue_cache
)
2160 if (frame_relative_level (this_frame
) == 0)
2161 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
2162 get_frame_pc (this_frame
));
2167 static struct amd64_frame_cache
*
2168 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2170 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2171 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2172 struct amd64_frame_cache
*cache
;
2178 cache
= amd64_alloc_frame_cache ();
2179 *this_cache
= cache
;
2181 /* Cache base will be %esp plus cache->sp_offset (-8). */
2182 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2183 cache
->base
= extract_unsigned_integer (buf
, 8,
2184 byte_order
) + cache
->sp_offset
;
2186 /* Cache pc will be the frame func. */
2187 cache
->pc
= get_frame_pc (this_frame
);
2189 /* The saved %esp will be at cache->base plus 16. */
2190 cache
->saved_sp
= cache
->base
+ 16;
2192 /* The saved %eip will be at cache->base plus 8. */
2193 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2199 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2201 struct frame_id
*this_id
)
2203 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2206 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2209 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2212 amd64_epilogue_frame_this_id
,
2213 amd64_frame_prev_register
,
2215 amd64_epilogue_frame_sniffer
2218 static struct frame_id
2219 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2223 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2225 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2228 /* 16 byte align the SP per frame requirements. */
2231 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2233 return sp
& -(CORE_ADDR
)16;
2237 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2238 in the floating-point register set REGSET to register cache
2239 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2242 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2243 int regnum
, const void *fpregs
, size_t len
)
2245 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2247 gdb_assert (len
== tdep
->sizeof_fpregset
);
2248 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2251 /* Collect register REGNUM from the register cache REGCACHE and store
2252 it in the buffer specified by FPREGS and LEN as described by the
2253 floating-point register set REGSET. If REGNUM is -1, do this for
2254 all registers in REGSET. */
2257 amd64_collect_fpregset (const struct regset
*regset
,
2258 const struct regcache
*regcache
,
2259 int regnum
, void *fpregs
, size_t len
)
2261 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2263 gdb_assert (len
== tdep
->sizeof_fpregset
);
2264 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2267 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2270 amd64_supply_xstateregset (const struct regset
*regset
,
2271 struct regcache
*regcache
, int regnum
,
2272 const void *xstateregs
, size_t len
)
2274 amd64_supply_xsave (regcache
, regnum
, xstateregs
);
2277 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2280 amd64_collect_xstateregset (const struct regset
*regset
,
2281 const struct regcache
*regcache
,
2282 int regnum
, void *xstateregs
, size_t len
)
2284 amd64_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2287 /* Return the appropriate register set for the core section identified
2288 by SECT_NAME and SECT_SIZE. */
2290 static const struct regset
*
2291 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
2292 const char *sect_name
, size_t sect_size
)
2294 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2296 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2298 if (tdep
->fpregset
== NULL
)
2299 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
2300 amd64_collect_fpregset
);
2302 return tdep
->fpregset
;
2305 if (strcmp (sect_name
, ".reg-xstate") == 0)
2307 if (tdep
->xstateregset
== NULL
)
2308 tdep
->xstateregset
= regset_alloc (gdbarch
,
2309 amd64_supply_xstateregset
,
2310 amd64_collect_xstateregset
);
2312 return tdep
->xstateregset
;
2315 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
2319 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2320 %rdi. We expect its value to be a pointer to the jmp_buf structure
2321 from which we extract the address that we will land at. This
2322 address is copied into PC. This routine returns non-zero on
2326 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2330 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2331 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2332 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2334 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2335 longjmp will land. */
2336 if (jb_pc_offset
== -1)
2339 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2340 jb_addr
= extract_typed_address
2341 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2342 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2345 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2350 static const int amd64_record_regmap
[] =
2352 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2353 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2354 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2355 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2356 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2357 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2361 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2364 const struct target_desc
*tdesc
= info
.target_desc
;
2366 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2367 floating-point registers. */
2368 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2370 if (! tdesc_has_registers (tdesc
))
2371 tdesc
= tdesc_amd64
;
2372 tdep
->tdesc
= tdesc
;
2374 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2375 tdep
->register_names
= amd64_register_names
;
2377 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2379 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2380 tdep
->num_ymm_regs
= 16;
2381 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2384 tdep
->num_byte_regs
= 20;
2385 tdep
->num_word_regs
= 16;
2386 tdep
->num_dword_regs
= 16;
2387 /* Avoid wiring in the MMX registers for now. */
2388 tdep
->num_mmx_regs
= 0;
2390 set_gdbarch_pseudo_register_read (gdbarch
,
2391 amd64_pseudo_register_read
);
2392 set_gdbarch_pseudo_register_write (gdbarch
,
2393 amd64_pseudo_register_write
);
2395 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
2397 /* AMD64 has an FPU and 16 SSE registers. */
2398 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2399 tdep
->num_xmm_regs
= 16;
2401 /* This is what all the fuss is about. */
2402 set_gdbarch_long_bit (gdbarch
, 64);
2403 set_gdbarch_long_long_bit (gdbarch
, 64);
2404 set_gdbarch_ptr_bit (gdbarch
, 64);
2406 /* In contrast to the i386, on AMD64 a `long double' actually takes
2407 up 128 bits, even though it's still based on the i387 extended
2408 floating-point format which has only 80 significant bits. */
2409 set_gdbarch_long_double_bit (gdbarch
, 128);
2411 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
2413 /* Register numbers of various important registers. */
2414 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
2415 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
2416 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
2417 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
2419 /* The "default" register numbering scheme for AMD64 is referred to
2420 as the "DWARF Register Number Mapping" in the System V psABI.
2421 The preferred debugging format for all known AMD64 targets is
2422 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2423 DWARF-1), but we provide the same mapping just in case. This
2424 mapping is also used for stabs, which GCC does support. */
2425 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2426 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2428 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2429 be in use on any of the supported AMD64 targets. */
2431 /* Call dummy code. */
2432 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
2433 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
2434 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
2435 tdep
->call_dummy_num_integer_regs
=
2436 ARRAY_SIZE (amd64_dummy_call_integer_regs
);
2437 tdep
->call_dummy_integer_regs
= amd64_dummy_call_integer_regs
;
2438 tdep
->classify
= amd64_classify
;
2440 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
2441 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
2442 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
2444 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
2446 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
2448 tdep
->record_regmap
= amd64_record_regmap
;
2450 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
2452 /* Hook the function epilogue frame unwinder. This unwinder is
2453 appended to the list first, so that it supercedes the other
2454 unwinders in function epilogues. */
2455 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
2457 /* Hook the prologue-based frame unwinders. */
2458 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
2459 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
2460 frame_base_set_default (gdbarch
, &amd64_frame_base
);
2462 /* If we have a register mapping, enable the generic core file support. */
2463 if (tdep
->gregset_reg_offset
)
2464 set_gdbarch_regset_from_core_section (gdbarch
,
2465 amd64_regset_from_core_section
);
2467 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
2469 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
2472 /* Provide a prototype to silence -Wmissing-prototypes. */
2473 void _initialize_amd64_tdep (void);
2476 _initialize_amd64_tdep (void)
2478 initialize_tdesc_amd64 ();
2479 initialize_tdesc_amd64_avx ();
2483 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2484 sense that the instruction pointer and data pointer are simply
2485 64-bit offsets into the code segment and the data segment instead
2486 of a selector offset pair. The functions below store the upper 32
2487 bits of these pointers (instead of just the 16-bits of the segment
2490 /* Fill register REGNUM in REGCACHE with the appropriate
2491 floating-point or SSE register value from *FXSAVE. If REGNUM is
2492 -1, do this for all registers. This function masks off any of the
2493 reserved bits in *FXSAVE. */
2496 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
2499 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2502 i387_supply_fxsave (regcache
, regnum
, fxsave
);
2504 if (fxsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2506 const gdb_byte
*regs
= fxsave
;
2508 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2509 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2510 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2511 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2515 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
2518 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
2521 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2522 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2524 i387_supply_xsave (regcache
, regnum
, xsave
);
2526 if (xsave
&& gdbarch_ptr_bit (gdbarch
) == 64)
2528 const gdb_byte
*regs
= xsave
;
2530 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2531 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
2533 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2534 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
2539 /* Fill register REGNUM (if it is a floating-point or SSE register) in
2540 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
2541 all registers. This function doesn't touch any of the reserved
2545 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
2548 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2549 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2550 gdb_byte
*regs
= fxsave
;
2552 i387_collect_fxsave (regcache
, regnum
, fxsave
);
2554 if (gdbarch_ptr_bit (gdbarch
) == 64)
2556 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2557 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
2558 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2559 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
2563 /* Similar to amd64_collect_fxsave, but but use XSAVE extended state. */
2566 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
2567 void *xsave
, int gcore
)
2569 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2570 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2571 gdb_byte
*regs
= xsave
;
2573 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
2575 if (gdbarch_ptr_bit (gdbarch
) == 64)
2577 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
2578 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
2580 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
2581 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),