1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
43 #include "features/i386/amd64.c"
44 #include "features/i386/amd64-avx.c"
45 #include "features/i386/amd64-mpx.c"
46 #include "features/i386/amd64-avx512.c"
48 #include "features/i386/x32.c"
49 #include "features/i386/x32-avx.c"
50 #include "features/i386/x32-avx512.c"
55 /* Note that the AMD64 architecture was previously known as x86-64.
56 The latter is (forever) engraved into the canonical system name as
57 returned by config.guess, and used as the name for the AMD64 port
58 of GNU/Linux. The BSD's have renamed their ports to amd64; they
59 don't like to shout. For GDB we prefer the amd64_-prefix over the
60 x86_64_-prefix since it's so much easier to type. */
62 /* Register information. */
64 static const char *amd64_register_names
[] =
66 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
68 /* %r8 is indeed register number 8. */
69 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
70 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
72 /* %st0 is register number 24. */
73 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
74 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
76 /* %xmm0 is register number 40. */
77 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
78 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
82 static const char *amd64_ymm_names
[] =
84 "ymm0", "ymm1", "ymm2", "ymm3",
85 "ymm4", "ymm5", "ymm6", "ymm7",
86 "ymm8", "ymm9", "ymm10", "ymm11",
87 "ymm12", "ymm13", "ymm14", "ymm15"
90 static const char *amd64_ymm_avx512_names
[] =
92 "ymm16", "ymm17", "ymm18", "ymm19",
93 "ymm20", "ymm21", "ymm22", "ymm23",
94 "ymm24", "ymm25", "ymm26", "ymm27",
95 "ymm28", "ymm29", "ymm30", "ymm31"
98 static const char *amd64_ymmh_names
[] =
100 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
101 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
102 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
103 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
106 static const char *amd64_ymmh_avx512_names
[] =
108 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
109 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
110 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
111 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
114 static const char *amd64_mpx_names
[] =
116 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
119 static const char *amd64_k_names
[] =
121 "k0", "k1", "k2", "k3",
122 "k4", "k5", "k6", "k7"
125 static const char *amd64_zmmh_names
[] =
127 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
128 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
129 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
130 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
131 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
132 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
133 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
134 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
137 static const char *amd64_zmm_names
[] =
139 "zmm0", "zmm1", "zmm2", "zmm3",
140 "zmm4", "zmm5", "zmm6", "zmm7",
141 "zmm8", "zmm9", "zmm10", "zmm11",
142 "zmm12", "zmm13", "zmm14", "zmm15",
143 "zmm16", "zmm17", "zmm18", "zmm19",
144 "zmm20", "zmm21", "zmm22", "zmm23",
145 "zmm24", "zmm25", "zmm26", "zmm27",
146 "zmm28", "zmm29", "zmm30", "zmm31"
149 static const char *amd64_xmm_avx512_names
[] = {
150 "xmm16", "xmm17", "xmm18", "xmm19",
151 "xmm20", "xmm21", "xmm22", "xmm23",
152 "xmm24", "xmm25", "xmm26", "xmm27",
153 "xmm28", "xmm29", "xmm30", "xmm31"
156 /* DWARF Register Number Mapping as defined in the System V psABI,
159 static int amd64_dwarf_regmap
[] =
161 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
162 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
163 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
164 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
166 /* Frame Pointer Register RBP. */
169 /* Stack Pointer Register RSP. */
172 /* Extended Integer Registers 8 - 15. */
173 AMD64_R8_REGNUM
, /* %r8 */
174 AMD64_R9_REGNUM
, /* %r9 */
175 AMD64_R10_REGNUM
, /* %r10 */
176 AMD64_R11_REGNUM
, /* %r11 */
177 AMD64_R12_REGNUM
, /* %r12 */
178 AMD64_R13_REGNUM
, /* %r13 */
179 AMD64_R14_REGNUM
, /* %r14 */
180 AMD64_R15_REGNUM
, /* %r15 */
182 /* Return Address RA. Mapped to RIP. */
185 /* SSE Registers 0 - 7. */
186 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
187 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
188 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
189 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
191 /* Extended SSE Registers 8 - 15. */
192 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
193 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
194 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
195 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
197 /* Floating Point Registers 0-7. */
198 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
199 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
200 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
201 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
203 /* MMX Registers 0 - 7.
204 We have to handle those registers specifically, as their register
205 number within GDB depends on the target (or they may even not be
206 available at all). */
207 -1, -1, -1, -1, -1, -1, -1, -1,
209 /* Control and Status Flags Register. */
212 /* Selector Registers. */
222 /* Segment Base Address Registers. */
228 /* Special Selector Registers. */
232 /* Floating Point Control Registers. */
238 static const int amd64_dwarf_regmap_len
=
239 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
241 /* Convert DWARF register number REG to the appropriate register
242 number used by GDB. */
245 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
248 int ymm0_regnum
= tdep
->ymm0_regnum
;
251 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
252 regnum
= amd64_dwarf_regmap
[reg
];
255 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
256 else if (ymm0_regnum
>= 0
257 && i386_xmm_regnum_p (gdbarch
, regnum
))
258 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap
[16] =
267 AMD64_RAX_REGNUM
, /* %rax */
268 AMD64_RCX_REGNUM
, /* %rcx */
269 AMD64_RDX_REGNUM
, /* %rdx */
270 AMD64_RBX_REGNUM
, /* %rbx */
271 AMD64_RSP_REGNUM
, /* %rsp */
272 AMD64_RBP_REGNUM
, /* %rbp */
273 AMD64_RSI_REGNUM
, /* %rsi */
274 AMD64_RDI_REGNUM
, /* %rdi */
275 AMD64_R8_REGNUM
, /* %r8 */
276 AMD64_R9_REGNUM
, /* %r9 */
277 AMD64_R10_REGNUM
, /* %r10 */
278 AMD64_R11_REGNUM
, /* %r11 */
279 AMD64_R12_REGNUM
, /* %r12 */
280 AMD64_R13_REGNUM
, /* %r13 */
281 AMD64_R14_REGNUM
, /* %r14 */
282 AMD64_R15_REGNUM
/* %r15 */
285 static const int amd64_arch_regmap_len
=
286 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg
)
294 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
296 return amd64_arch_regmap
[reg
];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names
[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names
[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names
[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 if (i386_byte_regnum_p (gdbarch
, regnum
))
335 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
336 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
337 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
338 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
339 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
340 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
342 else if (i386_word_regnum_p (gdbarch
, regnum
))
343 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
344 else if (i386_dword_regnum_p (gdbarch
, regnum
))
345 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
347 return i386_pseudo_register_name (gdbarch
, regnum
);
350 static struct value
*
351 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
352 struct regcache
*regcache
,
355 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 enum register_status status
;
358 struct value
*result_value
;
361 result_value
= allocate_value (register_type (gdbarch
, regnum
));
362 VALUE_LVAL (result_value
) = lval_register
;
363 VALUE_REGNUM (result_value
) = regnum
;
364 buf
= value_contents_raw (result_value
);
366 if (i386_byte_regnum_p (gdbarch
, regnum
))
368 int gpnum
= regnum
- tdep
->al_regnum
;
370 /* Extract (always little endian). */
371 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
373 /* Special handling for AH, BH, CH, DH. */
374 status
= regcache_raw_read (regcache
,
375 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
377 if (status
== REG_VALID
)
378 memcpy (buf
, raw_buf
+ 1, 1);
380 mark_value_bytes_unavailable (result_value
, 0,
381 TYPE_LENGTH (value_type (result_value
)));
385 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
386 if (status
== REG_VALID
)
387 memcpy (buf
, raw_buf
, 1);
389 mark_value_bytes_unavailable (result_value
, 0,
390 TYPE_LENGTH (value_type (result_value
)));
393 else if (i386_dword_regnum_p (gdbarch
, regnum
))
395 int gpnum
= regnum
- tdep
->eax_regnum
;
396 /* Extract (always little endian). */
397 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
398 if (status
== REG_VALID
)
399 memcpy (buf
, raw_buf
, 4);
401 mark_value_bytes_unavailable (result_value
, 0,
402 TYPE_LENGTH (value_type (result_value
)));
405 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
412 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
417 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
419 if (i386_byte_regnum_p (gdbarch
, regnum
))
421 int gpnum
= regnum
- tdep
->al_regnum
;
423 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
425 /* Read ... AH, BH, CH, DH. */
426 regcache_raw_read (regcache
,
427 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf
+ 1, buf
, 1);
431 regcache_raw_write (regcache
,
432 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
437 regcache_raw_read (regcache
, gpnum
, raw_buf
);
438 /* ... Modify ... (always little endian). */
439 memcpy (raw_buf
, buf
, 1);
441 regcache_raw_write (regcache
, gpnum
, raw_buf
);
444 else if (i386_dword_regnum_p (gdbarch
, regnum
))
446 int gpnum
= regnum
- tdep
->eax_regnum
;
449 regcache_raw_read (regcache
, gpnum
, raw_buf
);
450 /* ... Modify ... (always little endian). */
451 memcpy (raw_buf
, buf
, 4);
453 regcache_raw_write (regcache
, gpnum
, raw_buf
);
456 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
461 /* Register classes as defined in the psABI. */
475 /* Return the union class of CLASS1 and CLASS2. See the psABI for
478 static enum amd64_reg_class
479 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
481 /* Rule (a): If both classes are equal, this is the resulting class. */
482 if (class1
== class2
)
485 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
486 is the other class. */
487 if (class1
== AMD64_NO_CLASS
)
489 if (class2
== AMD64_NO_CLASS
)
492 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
493 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
496 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
497 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
498 return AMD64_INTEGER
;
500 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
501 MEMORY is used as class. */
502 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
503 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
504 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
507 /* Rule (f): Otherwise class SSE is used. */
511 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
513 /* Return non-zero if TYPE is a non-POD structure or union type. */
516 amd64_non_pod_p (struct type
*type
)
518 /* ??? A class with a base class certainly isn't POD, but does this
519 catch all non-POD structure types? */
520 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
526 /* Classify TYPE according to the rules for aggregate (structures and
527 arrays) and union types, and store the result in CLASS. */
530 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
532 /* 1. If the size of an object is larger than two eightbytes, or in
533 C++, is a non-POD structure or union type, or contains
534 unaligned fields, it has class memory. */
535 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
537 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
541 /* 2. Both eightbytes get initialized to class NO_CLASS. */
542 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
544 /* 3. Each field of an object is classified recursively so that
545 always two fields are considered. The resulting class is
546 calculated according to the classes of the fields in the
549 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
551 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
553 /* All fields in an array have the same type. */
554 amd64_classify (subtype
, theclass
);
555 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
556 theclass
[1] = theclass
[0];
562 /* Structure or union. */
563 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
564 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
566 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
568 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
569 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
570 enum amd64_reg_class subclass
[2];
571 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
575 bitsize
= TYPE_LENGTH (subtype
) * 8;
576 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
578 /* Ignore static fields. */
579 if (field_is_static (&TYPE_FIELD (type
, i
)))
582 gdb_assert (pos
== 0 || pos
== 1);
584 amd64_classify (subtype
, subclass
);
585 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
586 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
587 /* This is a bit of an odd case: We have a field that would
588 normally fit in one of the two eightbytes, except that
589 it is placed in a way that this field straddles them.
590 This has been seen with a structure containing an array.
592 The ABI is a bit unclear in this case, but we assume that
593 this field's class (stored in subclass[0]) must also be merged
594 into class[1]. In other words, our field has a piece stored
595 in the second eight-byte, and thus its class applies to
596 the second eight-byte as well.
598 In the case where the field length exceeds 8 bytes,
599 it should not be necessary to merge the field class
600 into class[1]. As LEN > 8, subclass[1] is necessarily
601 different from AMD64_NO_CLASS. If subclass[1] is equal
602 to subclass[0], then the normal class[1]/subclass[1]
603 merging will take care of everything. For subclass[1]
604 to be different from subclass[0], I can only see the case
605 where we have a SSE/SSEUP or X87/X87UP pair, which both
606 use up all 16 bytes of the aggregate, and are already
607 handled just fine (because each portion sits on its own
609 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
611 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
615 /* 4. Then a post merger cleanup is done: */
617 /* Rule (a): If one of the classes is MEMORY, the whole argument is
619 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
620 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
622 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
624 if (theclass
[0] == AMD64_SSEUP
)
625 theclass
[0] = AMD64_SSE
;
626 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
627 theclass
[1] = AMD64_SSE
;
630 /* Classify TYPE, and store the result in CLASS. */
633 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
635 enum type_code code
= TYPE_CODE (type
);
636 int len
= TYPE_LENGTH (type
);
638 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
640 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
641 long, long long, and pointers are in the INTEGER class. Similarly,
642 range types, used by languages such as Ada, are also in the INTEGER
644 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
645 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
646 || code
== TYPE_CODE_CHAR
647 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
648 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
649 theclass
[0] = AMD64_INTEGER
;
651 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
653 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
654 && (len
== 4 || len
== 8))
656 theclass
[0] = AMD64_SSE
;
658 /* Arguments of types __float128, _Decimal128 and __m128 are split into
659 two halves. The least significant ones belong to class SSE, the most
660 significant one to class SSEUP. */
661 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
662 /* FIXME: __float128, __m128. */
663 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
665 /* The 64-bit mantissa of arguments of type long double belongs to
666 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
668 else if (code
== TYPE_CODE_FLT
&& len
== 16)
669 /* Class X87 and X87UP. */
670 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
672 /* Arguments of complex T where T is one of the types float or
673 double get treated as if they are implemented as:
681 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
682 theclass
[0] = AMD64_SSE
;
683 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
684 theclass
[0] = theclass
[1] = AMD64_SSE
;
686 /* A variable of type complex long double is classified as type
688 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
689 theclass
[0] = AMD64_COMPLEX_X87
;
692 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
693 || code
== TYPE_CODE_UNION
)
694 amd64_classify_aggregate (type
, theclass
);
697 static enum return_value_convention
698 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
699 struct type
*type
, struct regcache
*regcache
,
700 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
702 enum amd64_reg_class theclass
[2];
703 int len
= TYPE_LENGTH (type
);
704 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
705 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
710 gdb_assert (!(readbuf
&& writebuf
));
712 /* 1. Classify the return type with the classification algorithm. */
713 amd64_classify (type
, theclass
);
715 /* 2. If the type has class MEMORY, then the caller provides space
716 for the return value and passes the address of this storage in
717 %rdi as if it were the first argument to the function. In effect,
718 this address becomes a hidden first argument.
720 On return %rax will contain the address that has been passed in
721 by the caller in %rdi. */
722 if (theclass
[0] == AMD64_MEMORY
)
724 /* As indicated by the comment above, the ABI guarantees that we
725 can always find the return value just after the function has
732 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
733 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
736 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
739 /* 8. If the class is COMPLEX_X87, the real part of the value is
740 returned in %st0 and the imaginary part in %st1. */
741 if (theclass
[0] == AMD64_COMPLEX_X87
)
745 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
746 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
751 i387_return_value (gdbarch
, regcache
);
752 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
753 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
755 /* Fix up the tag word such that both %st(0) and %st(1) are
757 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
760 return RETURN_VALUE_REGISTER_CONVENTION
;
763 gdb_assert (theclass
[1] != AMD64_MEMORY
);
764 gdb_assert (len
<= 16);
766 for (i
= 0; len
> 0; i
++, len
-= 8)
774 /* 3. If the class is INTEGER, the next available register
775 of the sequence %rax, %rdx is used. */
776 regnum
= integer_regnum
[integer_reg
++];
780 /* 4. If the class is SSE, the next available SSE register
781 of the sequence %xmm0, %xmm1 is used. */
782 regnum
= sse_regnum
[sse_reg
++];
786 /* 5. If the class is SSEUP, the eightbyte is passed in the
787 upper half of the last used SSE register. */
788 gdb_assert (sse_reg
> 0);
789 regnum
= sse_regnum
[sse_reg
- 1];
794 /* 6. If the class is X87, the value is returned on the X87
795 stack in %st0 as 80-bit x87 number. */
796 regnum
= AMD64_ST0_REGNUM
;
798 i387_return_value (gdbarch
, regcache
);
802 /* 7. If the class is X87UP, the value is returned together
803 with the previous X87 value in %st0. */
804 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
805 regnum
= AMD64_ST0_REGNUM
;
814 gdb_assert (!"Unexpected register class.");
817 gdb_assert (regnum
!= -1);
820 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
823 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
827 return RETURN_VALUE_REGISTER_CONVENTION
;
832 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
833 struct value
**args
, CORE_ADDR sp
, int struct_return
)
835 static int integer_regnum
[] =
837 AMD64_RDI_REGNUM
, /* %rdi */
838 AMD64_RSI_REGNUM
, /* %rsi */
839 AMD64_RDX_REGNUM
, /* %rdx */
840 AMD64_RCX_REGNUM
, /* %rcx */
841 AMD64_R8_REGNUM
, /* %r8 */
842 AMD64_R9_REGNUM
/* %r9 */
844 static int sse_regnum
[] =
846 /* %xmm0 ... %xmm7 */
847 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
848 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
849 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
850 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
852 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
853 int num_stack_args
= 0;
854 int num_elements
= 0;
860 /* Reserve a register for the "hidden" argument. */
864 for (i
= 0; i
< nargs
; i
++)
866 struct type
*type
= value_type (args
[i
]);
867 int len
= TYPE_LENGTH (type
);
868 enum amd64_reg_class theclass
[2];
869 int needed_integer_regs
= 0;
870 int needed_sse_regs
= 0;
873 /* Classify argument. */
874 amd64_classify (type
, theclass
);
876 /* Calculate the number of integer and SSE registers needed for
878 for (j
= 0; j
< 2; j
++)
880 if (theclass
[j
] == AMD64_INTEGER
)
881 needed_integer_regs
++;
882 else if (theclass
[j
] == AMD64_SSE
)
886 /* Check whether enough registers are available, and if the
887 argument should be passed in registers at all. */
888 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
889 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
890 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
892 /* The argument will be passed on the stack. */
893 num_elements
+= ((len
+ 7) / 8);
894 stack_args
[num_stack_args
++] = args
[i
];
898 /* The argument will be passed in registers. */
899 const gdb_byte
*valbuf
= value_contents (args
[i
]);
902 gdb_assert (len
<= 16);
904 for (j
= 0; len
> 0; j
++, len
-= 8)
912 regnum
= integer_regnum
[integer_reg
++];
916 regnum
= sse_regnum
[sse_reg
++];
920 gdb_assert (sse_reg
> 0);
921 regnum
= sse_regnum
[sse_reg
- 1];
926 gdb_assert (!"Unexpected register class.");
929 gdb_assert (regnum
!= -1);
930 memset (buf
, 0, sizeof buf
);
931 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
932 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
937 /* Allocate space for the arguments on the stack. */
938 sp
-= num_elements
* 8;
940 /* The psABI says that "The end of the input argument area shall be
941 aligned on a 16 byte boundary." */
944 /* Write out the arguments to the stack. */
945 for (i
= 0; i
< num_stack_args
; i
++)
947 struct type
*type
= value_type (stack_args
[i
]);
948 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
949 int len
= TYPE_LENGTH (type
);
951 write_memory (sp
+ element
* 8, valbuf
, len
);
952 element
+= ((len
+ 7) / 8);
955 /* The psABI says that "For calls that may call functions that use
956 varargs or stdargs (prototype-less calls or calls to functions
957 containing ellipsis (...) in the declaration) %al is used as
958 hidden argument to specify the number of SSE registers used. */
959 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
964 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
965 struct regcache
*regcache
, CORE_ADDR bp_addr
,
966 int nargs
, struct value
**args
, CORE_ADDR sp
,
967 int struct_return
, CORE_ADDR struct_addr
)
969 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
972 /* Pass arguments. */
973 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
975 /* Pass "hidden" argument". */
978 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
979 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
982 /* Store return address. */
984 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
985 write_memory (sp
, buf
, 8);
987 /* Finally, update the stack pointer... */
988 store_unsigned_integer (buf
, 8, byte_order
, sp
);
989 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
991 /* ...and fake a frame pointer. */
992 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
997 /* Displaced instruction handling. */
999 /* A partially decoded instruction.
1000 This contains enough details for displaced stepping purposes. */
1004 /* The number of opcode bytes. */
1006 /* The offset of the rex prefix or -1 if not present. */
1008 /* The offset to the first opcode byte. */
1010 /* The offset to the modrm byte or -1 if not present. */
1013 /* The raw instruction. */
1017 struct displaced_step_closure
1019 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1024 /* Details of the instruction. */
1025 struct amd64_insn insn_details
;
1027 /* Amount of space allocated to insn_buf. */
1030 /* The possibly modified insn.
1031 This is a variable-length field. */
1032 gdb_byte insn_buf
[1];
1035 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1036 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1037 at which point delete these in favor of libopcodes' versions). */
1039 static const unsigned char onebyte_has_modrm
[256] = {
1040 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1041 /* ------------------------------- */
1042 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1043 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1044 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1045 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1046 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1047 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1048 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1049 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1050 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1051 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1052 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1053 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1054 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1055 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1056 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1057 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1058 /* ------------------------------- */
1059 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1062 static const unsigned char twobyte_has_modrm
[256] = {
1063 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1064 /* ------------------------------- */
1065 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1066 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1067 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1068 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1069 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1070 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1071 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1072 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1073 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1074 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1075 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1076 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1077 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1078 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1079 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1080 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1081 /* ------------------------------- */
1082 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1085 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1088 rex_prefix_p (gdb_byte pfx
)
1090 return REX_PREFIX_P (pfx
);
1093 /* Skip the legacy instruction prefixes in INSN.
1094 We assume INSN is properly sentineled so we don't have to worry
1095 about falling off the end of the buffer. */
1098 amd64_skip_prefixes (gdb_byte
*insn
)
1104 case DATA_PREFIX_OPCODE
:
1105 case ADDR_PREFIX_OPCODE
:
1106 case CS_PREFIX_OPCODE
:
1107 case DS_PREFIX_OPCODE
:
1108 case ES_PREFIX_OPCODE
:
1109 case FS_PREFIX_OPCODE
:
1110 case GS_PREFIX_OPCODE
:
1111 case SS_PREFIX_OPCODE
:
1112 case LOCK_PREFIX_OPCODE
:
1113 case REPE_PREFIX_OPCODE
:
1114 case REPNE_PREFIX_OPCODE
:
1126 /* Return an integer register (other than RSP) that is unused as an input
1128 In order to not require adding a rex prefix if the insn doesn't already
1129 have one, the result is restricted to RAX ... RDI, sans RSP.
1130 The register numbering of the result follows architecture ordering,
1134 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1136 /* 1 bit for each reg */
1137 int used_regs_mask
= 0;
1139 /* There can be at most 3 int regs used as inputs in an insn, and we have
1140 7 to choose from (RAX ... RDI, sans RSP).
1141 This allows us to take a conservative approach and keep things simple.
1142 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1143 that implicitly specify RAX. */
1146 used_regs_mask
|= 1 << EAX_REG_NUM
;
1147 /* Similarily avoid RDX, implicit operand in divides. */
1148 used_regs_mask
|= 1 << EDX_REG_NUM
;
1150 used_regs_mask
|= 1 << ESP_REG_NUM
;
1152 /* If the opcode is one byte long and there's no ModRM byte,
1153 assume the opcode specifies a register. */
1154 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1155 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1157 /* Mark used regs in the modrm/sib bytes. */
1158 if (details
->modrm_offset
!= -1)
1160 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1161 int mod
= MODRM_MOD_FIELD (modrm
);
1162 int reg
= MODRM_REG_FIELD (modrm
);
1163 int rm
= MODRM_RM_FIELD (modrm
);
1164 int have_sib
= mod
!= 3 && rm
== 4;
1166 /* Assume the reg field of the modrm byte specifies a register. */
1167 used_regs_mask
|= 1 << reg
;
1171 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1172 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1173 used_regs_mask
|= 1 << base
;
1174 used_regs_mask
|= 1 << idx
;
1178 used_regs_mask
|= 1 << rm
;
1182 gdb_assert (used_regs_mask
< 256);
1183 gdb_assert (used_regs_mask
!= 255);
1185 /* Finally, find a free reg. */
1189 for (i
= 0; i
< 8; ++i
)
1191 if (! (used_regs_mask
& (1 << i
)))
1195 /* We shouldn't get here. */
1196 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1200 /* Extract the details of INSN that we need. */
1203 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1205 gdb_byte
*start
= insn
;
1208 details
->raw_insn
= insn
;
1210 details
->opcode_len
= -1;
1211 details
->rex_offset
= -1;
1212 details
->opcode_offset
= -1;
1213 details
->modrm_offset
= -1;
1215 /* Skip legacy instruction prefixes. */
1216 insn
= amd64_skip_prefixes (insn
);
1218 /* Skip REX instruction prefix. */
1219 if (rex_prefix_p (*insn
))
1221 details
->rex_offset
= insn
- start
;
1225 details
->opcode_offset
= insn
- start
;
1227 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1229 /* Two or three-byte opcode. */
1231 need_modrm
= twobyte_has_modrm
[*insn
];
1233 /* Check for three-byte opcode. */
1243 details
->opcode_len
= 3;
1246 details
->opcode_len
= 2;
1252 /* One-byte opcode. */
1253 need_modrm
= onebyte_has_modrm
[*insn
];
1254 details
->opcode_len
= 1;
1260 details
->modrm_offset
= insn
- start
;
1264 /* Update %rip-relative addressing in INSN.
1266 %rip-relative addressing only uses a 32-bit displacement.
1267 32 bits is not enough to be guaranteed to cover the distance between where
1268 the real instruction is and where its copy is.
1269 Convert the insn to use base+disp addressing.
1270 We set base = pc + insn_length so we can leave disp unchanged. */
1273 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1274 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1276 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1277 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1278 int modrm_offset
= insn_details
->modrm_offset
;
1279 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1283 int arch_tmp_regno
, tmp_regno
;
1284 ULONGEST orig_value
;
1286 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1289 /* Compute the rip-relative address. */
1290 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1291 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1292 dsc
->max_len
, from
);
1293 rip_base
= from
+ insn_length
;
1295 /* We need a register to hold the address.
1296 Pick one not used in the insn.
1297 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1298 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1299 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1301 /* REX.B should be unset as we were using rip-relative addressing,
1302 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1303 if (insn_details
->rex_offset
!= -1)
1304 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1306 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1307 dsc
->tmp_regno
= tmp_regno
;
1308 dsc
->tmp_save
= orig_value
;
1311 /* Convert the ModRM field to be base+disp. */
1312 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1313 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1315 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1317 if (debug_displaced
)
1318 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1319 "displaced: using temp reg %d, old value %s, new value %s\n",
1320 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1321 paddress (gdbarch
, rip_base
));
1325 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1326 struct displaced_step_closure
*dsc
,
1327 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1329 const struct amd64_insn
*details
= &dsc
->insn_details
;
1331 if (details
->modrm_offset
!= -1)
1333 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1335 if ((modrm
& 0xc7) == 0x05)
1337 /* The insn uses rip-relative addressing.
1339 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1344 struct displaced_step_closure
*
1345 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1346 CORE_ADDR from
, CORE_ADDR to
,
1347 struct regcache
*regs
)
1349 int len
= gdbarch_max_insn_length (gdbarch
);
1350 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1351 continually watch for running off the end of the buffer. */
1352 int fixup_sentinel_space
= len
;
1353 struct displaced_step_closure
*dsc
=
1354 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1355 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1356 struct amd64_insn
*details
= &dsc
->insn_details
;
1359 dsc
->max_len
= len
+ fixup_sentinel_space
;
1361 read_memory (from
, buf
, len
);
1363 /* Set up the sentinel space so we don't have to worry about running
1364 off the end of the buffer. An excessive number of leading prefixes
1365 could otherwise cause this. */
1366 memset (buf
+ len
, 0, fixup_sentinel_space
);
1368 amd64_get_insn_details (buf
, details
);
1370 /* GDB may get control back after the insn after the syscall.
1371 Presumably this is a kernel bug.
1372 If this is a syscall, make sure there's a nop afterwards. */
1376 if (amd64_syscall_p (details
, &syscall_length
))
1377 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1380 /* Modify the insn to cope with the address where it will be executed from.
1381 In particular, handle any rip-relative addressing. */
1382 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1384 write_memory (to
, buf
, len
);
1386 if (debug_displaced
)
1388 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1389 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1390 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1397 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1399 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1401 if (insn
[0] == 0xff)
1403 /* jump near, absolute indirect (/4) */
1404 if ((insn
[1] & 0x38) == 0x20)
1407 /* jump far, absolute indirect (/5) */
1408 if ((insn
[1] & 0x38) == 0x28)
1415 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1418 amd64_jmp_p (const struct amd64_insn
*details
)
1420 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1422 /* jump short, relative. */
1423 if (insn
[0] == 0xeb)
1426 /* jump near, relative. */
1427 if (insn
[0] == 0xe9)
1430 return amd64_absolute_jmp_p (details
);
1434 amd64_absolute_call_p (const struct amd64_insn
*details
)
1436 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1438 if (insn
[0] == 0xff)
1440 /* Call near, absolute indirect (/2) */
1441 if ((insn
[1] & 0x38) == 0x10)
1444 /* Call far, absolute indirect (/3) */
1445 if ((insn
[1] & 0x38) == 0x18)
1453 amd64_ret_p (const struct amd64_insn
*details
)
1455 /* NOTE: gcc can emit "repz ; ret". */
1456 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1460 case 0xc2: /* ret near, pop N bytes */
1461 case 0xc3: /* ret near */
1462 case 0xca: /* ret far, pop N bytes */
1463 case 0xcb: /* ret far */
1464 case 0xcf: /* iret */
1473 amd64_call_p (const struct amd64_insn
*details
)
1475 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1477 if (amd64_absolute_call_p (details
))
1480 /* call near, relative */
1481 if (insn
[0] == 0xe8)
1487 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1488 length in bytes. Otherwise, return zero. */
1491 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1493 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1495 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1504 /* Classify the instruction at ADDR using PRED.
1505 Throw an error if the memory can't be read. */
1508 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1509 int (*pred
) (const struct amd64_insn
*))
1511 struct amd64_insn details
;
1513 int len
, classification
;
1515 len
= gdbarch_max_insn_length (gdbarch
);
1518 read_code (addr
, buf
, len
);
1519 amd64_get_insn_details (buf
, &details
);
1521 classification
= pred (&details
);
1523 return classification
;
1526 /* The gdbarch insn_is_call method. */
1529 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1531 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1534 /* The gdbarch insn_is_ret method. */
1537 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1539 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1542 /* The gdbarch insn_is_jump method. */
1545 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1547 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1550 /* Fix up the state of registers and memory after having single-stepped
1551 a displaced instruction. */
1554 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1555 struct displaced_step_closure
*dsc
,
1556 CORE_ADDR from
, CORE_ADDR to
,
1557 struct regcache
*regs
)
1559 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1560 /* The offset we applied to the instruction's address. */
1561 ULONGEST insn_offset
= to
- from
;
1562 gdb_byte
*insn
= dsc
->insn_buf
;
1563 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1565 if (debug_displaced
)
1566 fprintf_unfiltered (gdb_stdlog
,
1567 "displaced: fixup (%s, %s), "
1568 "insn = 0x%02x 0x%02x ...\n",
1569 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1572 /* If we used a tmp reg, restore it. */
1576 if (debug_displaced
)
1577 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1578 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1579 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1582 /* The list of issues to contend with here is taken from
1583 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1584 Yay for Free Software! */
1586 /* Relocate the %rip back to the program's instruction stream,
1589 /* Except in the case of absolute or indirect jump or call
1590 instructions, or a return instruction, the new rip is relative to
1591 the displaced instruction; make it relative to the original insn.
1592 Well, signal handler returns don't need relocation either, but we use the
1593 value of %rip to recognize those; see below. */
1594 if (! amd64_absolute_jmp_p (insn_details
)
1595 && ! amd64_absolute_call_p (insn_details
)
1596 && ! amd64_ret_p (insn_details
))
1601 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1603 /* A signal trampoline system call changes the %rip, resuming
1604 execution of the main program after the signal handler has
1605 returned. That makes them like 'return' instructions; we
1606 shouldn't relocate %rip.
1608 But most system calls don't, and we do need to relocate %rip.
1610 Our heuristic for distinguishing these cases: if stepping
1611 over the system call instruction left control directly after
1612 the instruction, the we relocate --- control almost certainly
1613 doesn't belong in the displaced copy. Otherwise, we assume
1614 the instruction has put control where it belongs, and leave
1615 it unrelocated. Goodness help us if there are PC-relative
1617 if (amd64_syscall_p (insn_details
, &insn_len
)
1618 && orig_rip
!= to
+ insn_len
1619 /* GDB can get control back after the insn after the syscall.
1620 Presumably this is a kernel bug.
1621 Fixup ensures its a nop, we add one to the length for it. */
1622 && orig_rip
!= to
+ insn_len
+ 1)
1624 if (debug_displaced
)
1625 fprintf_unfiltered (gdb_stdlog
,
1626 "displaced: syscall changed %%rip; "
1627 "not relocating\n");
1631 ULONGEST rip
= orig_rip
- insn_offset
;
1633 /* If we just stepped over a breakpoint insn, we don't backup
1634 the pc on purpose; this is to match behaviour without
1637 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1639 if (debug_displaced
)
1640 fprintf_unfiltered (gdb_stdlog
,
1642 "relocated %%rip from %s to %s\n",
1643 paddress (gdbarch
, orig_rip
),
1644 paddress (gdbarch
, rip
));
1648 /* If the instruction was PUSHFL, then the TF bit will be set in the
1649 pushed value, and should be cleared. We'll leave this for later,
1650 since GDB already messes up the TF flag when stepping over a
1653 /* If the instruction was a call, the return address now atop the
1654 stack is the address following the copied instruction. We need
1655 to make it the address following the original instruction. */
1656 if (amd64_call_p (insn_details
))
1660 const ULONGEST retaddr_len
= 8;
1662 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1663 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1664 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1665 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1667 if (debug_displaced
)
1668 fprintf_unfiltered (gdb_stdlog
,
1669 "displaced: relocated return addr at %s "
1671 paddress (gdbarch
, rsp
),
1672 paddress (gdbarch
, retaddr
));
1676 /* If the instruction INSN uses RIP-relative addressing, return the
1677 offset into the raw INSN where the displacement to be adjusted is
1678 found. Returns 0 if the instruction doesn't use RIP-relative
1682 rip_relative_offset (struct amd64_insn
*insn
)
1684 if (insn
->modrm_offset
!= -1)
1686 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1688 if ((modrm
& 0xc7) == 0x05)
1690 /* The displacement is found right after the ModRM byte. */
1691 return insn
->modrm_offset
+ 1;
1699 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1701 target_write_memory (*to
, buf
, len
);
1706 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1707 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1709 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1710 int len
= gdbarch_max_insn_length (gdbarch
);
1711 /* Extra space for sentinels. */
1712 int fixup_sentinel_space
= len
;
1713 gdb_byte
*buf
= xmalloc (len
+ fixup_sentinel_space
);
1714 struct amd64_insn insn_details
;
1716 LONGEST rel32
, newrel
;
1720 read_memory (oldloc
, buf
, len
);
1722 /* Set up the sentinel space so we don't have to worry about running
1723 off the end of the buffer. An excessive number of leading prefixes
1724 could otherwise cause this. */
1725 memset (buf
+ len
, 0, fixup_sentinel_space
);
1728 amd64_get_insn_details (insn
, &insn_details
);
1730 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1732 /* Skip legacy instruction prefixes. */
1733 insn
= amd64_skip_prefixes (insn
);
1735 /* Adjust calls with 32-bit relative addresses as push/jump, with
1736 the address pushed being the location where the original call in
1737 the user program would return to. */
1738 if (insn
[0] == 0xe8)
1740 gdb_byte push_buf
[16];
1741 unsigned int ret_addr
;
1743 /* Where "ret" in the original code will return to. */
1744 ret_addr
= oldloc
+ insn_length
;
1745 push_buf
[0] = 0x68; /* pushq $... */
1746 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1747 /* Push the push. */
1748 append_insns (to
, 5, push_buf
);
1750 /* Convert the relative call to a relative jump. */
1753 /* Adjust the destination offset. */
1754 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1755 newrel
= (oldloc
- *to
) + rel32
;
1756 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1758 if (debug_displaced
)
1759 fprintf_unfiltered (gdb_stdlog
,
1760 "Adjusted insn rel32=%s at %s to"
1761 " rel32=%s at %s\n",
1762 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1763 hex_string (newrel
), paddress (gdbarch
, *to
));
1765 /* Write the adjusted jump into its displaced location. */
1766 append_insns (to
, 5, insn
);
1770 offset
= rip_relative_offset (&insn_details
);
1773 /* Adjust jumps with 32-bit relative addresses. Calls are
1774 already handled above. */
1775 if (insn
[0] == 0xe9)
1777 /* Adjust conditional jumps. */
1778 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1784 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1785 newrel
= (oldloc
- *to
) + rel32
;
1786 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1787 if (debug_displaced
)
1788 fprintf_unfiltered (gdb_stdlog
,
1789 "Adjusted insn rel32=%s at %s to"
1790 " rel32=%s at %s\n",
1791 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1792 hex_string (newrel
), paddress (gdbarch
, *to
));
1795 /* Write the adjusted instruction into its displaced location. */
1796 append_insns (to
, insn_length
, buf
);
1800 /* The maximum number of saved registers. This should include %rip. */
1801 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1803 struct amd64_frame_cache
1808 CORE_ADDR sp_offset
;
1811 /* Saved registers. */
1812 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1816 /* Do we have a frame? */
1820 /* Initialize a frame cache. */
1823 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1830 cache
->sp_offset
= -8;
1833 /* Saved registers. We initialize these to -1 since zero is a valid
1834 offset (that's where %rbp is supposed to be stored).
1835 The values start out as being offsets, and are later converted to
1836 addresses (at which point -1 is interpreted as an address, still meaning
1838 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1839 cache
->saved_regs
[i
] = -1;
1840 cache
->saved_sp
= 0;
1841 cache
->saved_sp_reg
= -1;
1843 /* Frameless until proven otherwise. */
1844 cache
->frameless_p
= 1;
1847 /* Allocate and initialize a frame cache. */
1849 static struct amd64_frame_cache
*
1850 amd64_alloc_frame_cache (void)
1852 struct amd64_frame_cache
*cache
;
1854 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1855 amd64_init_frame_cache (cache
);
1859 /* GCC 4.4 and later, can put code in the prologue to realign the
1860 stack pointer. Check whether PC points to such code, and update
1861 CACHE accordingly. Return the first instruction after the code
1862 sequence or CURRENT_PC, whichever is smaller. If we don't
1863 recognize the code, return PC. */
1866 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1867 struct amd64_frame_cache
*cache
)
1869 /* There are 2 code sequences to re-align stack before the frame
1872 1. Use a caller-saved saved register:
1878 2. Use a callee-saved saved register:
1885 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1887 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1888 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1893 int offset
, offset_and
;
1895 if (target_read_code (pc
, buf
, sizeof buf
))
1898 /* Check caller-saved saved register. The first instruction has
1899 to be "leaq 8(%rsp), %reg". */
1900 if ((buf
[0] & 0xfb) == 0x48
1905 /* MOD must be binary 10 and R/M must be binary 100. */
1906 if ((buf
[2] & 0xc7) != 0x44)
1909 /* REG has register number. */
1910 reg
= (buf
[2] >> 3) & 7;
1912 /* Check the REX.R bit. */
1920 /* Check callee-saved saved register. The first instruction
1921 has to be "pushq %reg". */
1923 if ((buf
[0] & 0xf8) == 0x50)
1925 else if ((buf
[0] & 0xf6) == 0x40
1926 && (buf
[1] & 0xf8) == 0x50)
1928 /* Check the REX.B bit. */
1929 if ((buf
[0] & 1) != 0)
1938 reg
+= buf
[offset
] & 0x7;
1942 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1943 if ((buf
[offset
] & 0xfb) != 0x48
1944 || buf
[offset
+ 1] != 0x8d
1945 || buf
[offset
+ 3] != 0x24
1946 || buf
[offset
+ 4] != 0x10)
1949 /* MOD must be binary 10 and R/M must be binary 100. */
1950 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1953 /* REG has register number. */
1954 r
= (buf
[offset
+ 2] >> 3) & 7;
1956 /* Check the REX.R bit. */
1957 if (buf
[offset
] == 0x4c)
1960 /* Registers in pushq and leaq have to be the same. */
1967 /* Rigister can't be %rsp nor %rbp. */
1968 if (reg
== 4 || reg
== 5)
1971 /* The next instruction has to be "andq $-XXX, %rsp". */
1972 if (buf
[offset
] != 0x48
1973 || buf
[offset
+ 2] != 0xe4
1974 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1977 offset_and
= offset
;
1978 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1980 /* The next instruction has to be "pushq -8(%reg)". */
1982 if (buf
[offset
] == 0xff)
1984 else if ((buf
[offset
] & 0xf6) == 0x40
1985 && buf
[offset
+ 1] == 0xff)
1987 /* Check the REX.B bit. */
1988 if ((buf
[offset
] & 0x1) != 0)
1995 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1997 if (buf
[offset
+ 1] != 0xf8
1998 || (buf
[offset
] & 0xf8) != 0x70)
2001 /* R/M has register. */
2002 r
+= buf
[offset
] & 7;
2004 /* Registers in leaq and pushq have to be the same. */
2008 if (current_pc
> pc
+ offset_and
)
2009 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2011 return min (pc
+ offset
+ 2, current_pc
);
2014 /* Similar to amd64_analyze_stack_align for x32. */
2017 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2018 struct amd64_frame_cache
*cache
)
2020 /* There are 2 code sequences to re-align stack before the frame
2023 1. Use a caller-saved saved register:
2031 [addr32] leal 8(%rsp), %reg
2033 [addr32] pushq -8(%reg)
2035 2. Use a callee-saved saved register:
2045 [addr32] leal 16(%rsp), %reg
2047 [addr32] pushq -8(%reg)
2049 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2051 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2052 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2054 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2056 0x83 0xe4 0xf0 andl $-16, %esp
2057 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2062 int offset
, offset_and
;
2064 if (target_read_memory (pc
, buf
, sizeof buf
))
2067 /* Skip optional addr32 prefix. */
2068 offset
= buf
[0] == 0x67 ? 1 : 0;
2070 /* Check caller-saved saved register. The first instruction has
2071 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2072 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2073 && buf
[offset
+ 1] == 0x8d
2074 && buf
[offset
+ 3] == 0x24
2075 && buf
[offset
+ 4] == 0x8)
2077 /* MOD must be binary 10 and R/M must be binary 100. */
2078 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2081 /* REG has register number. */
2082 reg
= (buf
[offset
+ 2] >> 3) & 7;
2084 /* Check the REX.R bit. */
2085 if ((buf
[offset
] & 0x4) != 0)
2092 /* Check callee-saved saved register. The first instruction
2093 has to be "pushq %reg". */
2095 if ((buf
[offset
] & 0xf6) == 0x40
2096 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2098 /* Check the REX.B bit. */
2099 if ((buf
[offset
] & 1) != 0)
2104 else if ((buf
[offset
] & 0xf8) != 0x50)
2108 reg
+= buf
[offset
] & 0x7;
2112 /* Skip optional addr32 prefix. */
2113 if (buf
[offset
] == 0x67)
2116 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2117 "leal 16(%rsp), %reg". */
2118 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2119 || buf
[offset
+ 1] != 0x8d
2120 || buf
[offset
+ 3] != 0x24
2121 || buf
[offset
+ 4] != 0x10)
2124 /* MOD must be binary 10 and R/M must be binary 100. */
2125 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2128 /* REG has register number. */
2129 r
= (buf
[offset
+ 2] >> 3) & 7;
2131 /* Check the REX.R bit. */
2132 if ((buf
[offset
] & 0x4) != 0)
2135 /* Registers in pushq and leaq have to be the same. */
2142 /* Rigister can't be %rsp nor %rbp. */
2143 if (reg
== 4 || reg
== 5)
2146 /* The next instruction may be "andq $-XXX, %rsp" or
2147 "andl $-XXX, %esp". */
2148 if (buf
[offset
] != 0x48)
2151 if (buf
[offset
+ 2] != 0xe4
2152 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2155 offset_and
= offset
;
2156 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2158 /* Skip optional addr32 prefix. */
2159 if (buf
[offset
] == 0x67)
2162 /* The next instruction has to be "pushq -8(%reg)". */
2164 if (buf
[offset
] == 0xff)
2166 else if ((buf
[offset
] & 0xf6) == 0x40
2167 && buf
[offset
+ 1] == 0xff)
2169 /* Check the REX.B bit. */
2170 if ((buf
[offset
] & 0x1) != 0)
2177 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2179 if (buf
[offset
+ 1] != 0xf8
2180 || (buf
[offset
] & 0xf8) != 0x70)
2183 /* R/M has register. */
2184 r
+= buf
[offset
] & 7;
2186 /* Registers in leaq and pushq have to be the same. */
2190 if (current_pc
> pc
+ offset_and
)
2191 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2193 return min (pc
+ offset
+ 2, current_pc
);
2196 /* Do a limited analysis of the prologue at PC and update CACHE
2197 accordingly. Bail out early if CURRENT_PC is reached. Return the
2198 address where the analysis stopped.
2200 We will handle only functions beginning with:
2203 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2205 or (for the X32 ABI):
2208 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2210 Any function that doesn't start with one of these sequences will be
2211 assumed to have no prologue and thus no valid frame pointer in
2215 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2216 CORE_ADDR pc
, CORE_ADDR current_pc
,
2217 struct amd64_frame_cache
*cache
)
2219 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2220 /* There are two variations of movq %rsp, %rbp. */
2221 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2222 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2223 /* Ditto for movl %esp, %ebp. */
2224 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2225 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2230 if (current_pc
<= pc
)
2233 if (gdbarch_ptr_bit (gdbarch
) == 32)
2234 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2236 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2238 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2240 if (op
== 0x55) /* pushq %rbp */
2242 /* Take into account that we've executed the `pushq %rbp' that
2243 starts this instruction sequence. */
2244 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2245 cache
->sp_offset
+= 8;
2247 /* If that's all, return now. */
2248 if (current_pc
<= pc
+ 1)
2251 read_code (pc
+ 1, buf
, 3);
2253 /* Check for `movq %rsp, %rbp'. */
2254 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2255 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2257 /* OK, we actually have a frame. */
2258 cache
->frameless_p
= 0;
2262 /* For X32, also check for `movq %esp, %ebp'. */
2263 if (gdbarch_ptr_bit (gdbarch
) == 32)
2265 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2266 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2268 /* OK, we actually have a frame. */
2269 cache
->frameless_p
= 0;
2280 /* Work around false termination of prologue - GCC PR debug/48827.
2282 START_PC is the first instruction of a function, PC is its minimal already
2283 determined advanced address. Function returns PC if it has nothing to do.
2287 <-- here is 0 lines advance - the false prologue end marker.
2288 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2289 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2290 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2291 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2292 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2293 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2294 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2295 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2299 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2301 struct symtab_and_line start_pc_sal
, next_sal
;
2302 gdb_byte buf
[4 + 8 * 7];
2308 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2309 if (start_pc_sal
.symtab
== NULL
2310 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2311 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2312 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2315 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2316 if (next_sal
.line
!= start_pc_sal
.line
)
2319 /* START_PC can be from overlayed memory, ignored here. */
2320 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2324 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2331 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2333 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2334 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2335 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2339 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2341 /* 8-bit displacement. */
2345 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2347 /* 32-bit displacement. */
2355 if (offset
- 4 != buf
[3])
2358 return next_sal
.end
;
2361 /* Return PC of first real instruction. */
2364 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2366 struct amd64_frame_cache cache
;
2368 CORE_ADDR func_addr
;
2370 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2372 CORE_ADDR post_prologue_pc
2373 = skip_prologue_using_sal (gdbarch
, func_addr
);
2374 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2376 /* Clang always emits a line note before the prologue and another
2377 one after. We trust clang to emit usable line notes. */
2378 if (post_prologue_pc
2380 && COMPUNIT_PRODUCER (cust
) != NULL
2381 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2382 return max (start_pc
, post_prologue_pc
);
2385 amd64_init_frame_cache (&cache
);
2386 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2388 if (cache
.frameless_p
)
2391 return amd64_skip_xmm_prologue (pc
, start_pc
);
2395 /* Normal frames. */
2398 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2399 struct amd64_frame_cache
*cache
)
2401 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2402 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2406 cache
->pc
= get_frame_func (this_frame
);
2408 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2411 if (cache
->frameless_p
)
2413 /* We didn't find a valid frame. If we're at the start of a
2414 function, or somewhere half-way its prologue, the function's
2415 frame probably hasn't been fully setup yet. Try to
2416 reconstruct the base address for the stack frame by looking
2417 at the stack pointer. For truly "frameless" functions this
2420 if (cache
->saved_sp_reg
!= -1)
2422 /* Stack pointer has been saved. */
2423 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2424 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2426 /* We're halfway aligning the stack. */
2427 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2428 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2430 /* This will be added back below. */
2431 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2435 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2436 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2442 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2443 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2446 /* Now that we have the base address for the stack frame we can
2447 calculate the value of %rsp in the calling frame. */
2448 cache
->saved_sp
= cache
->base
+ 16;
2450 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2451 frame we find it at the same offset from the reconstructed base
2452 address. If we're halfway aligning the stack, %rip is handled
2453 differently (see above). */
2454 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2455 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2457 /* Adjust all the saved registers such that they contain addresses
2458 instead of offsets. */
2459 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2460 if (cache
->saved_regs
[i
] != -1)
2461 cache
->saved_regs
[i
] += cache
->base
;
2466 static struct amd64_frame_cache
*
2467 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2469 volatile struct gdb_exception ex
;
2470 struct amd64_frame_cache
*cache
;
2475 cache
= amd64_alloc_frame_cache ();
2476 *this_cache
= cache
;
2478 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2480 amd64_frame_cache_1 (this_frame
, cache
);
2482 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2483 throw_exception (ex
);
2488 static enum unwind_stop_reason
2489 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2492 struct amd64_frame_cache
*cache
=
2493 amd64_frame_cache (this_frame
, this_cache
);
2496 return UNWIND_UNAVAILABLE
;
2498 /* This marks the outermost frame. */
2499 if (cache
->base
== 0)
2500 return UNWIND_OUTERMOST
;
2502 return UNWIND_NO_REASON
;
2506 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2507 struct frame_id
*this_id
)
2509 struct amd64_frame_cache
*cache
=
2510 amd64_frame_cache (this_frame
, this_cache
);
2513 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2514 else if (cache
->base
== 0)
2516 /* This marks the outermost frame. */
2520 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2523 static struct value
*
2524 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2527 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2528 struct amd64_frame_cache
*cache
=
2529 amd64_frame_cache (this_frame
, this_cache
);
2531 gdb_assert (regnum
>= 0);
2533 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2534 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2536 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2537 return frame_unwind_got_memory (this_frame
, regnum
,
2538 cache
->saved_regs
[regnum
]);
2540 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2543 static const struct frame_unwind amd64_frame_unwind
=
2546 amd64_frame_unwind_stop_reason
,
2547 amd64_frame_this_id
,
2548 amd64_frame_prev_register
,
2550 default_frame_sniffer
2553 /* Generate a bytecode expression to get the value of the saved PC. */
2556 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2557 struct agent_expr
*ax
, struct axs_value
*value
,
2560 /* The following sequence assumes the traditional use of the base
2562 ax_reg (ax
, AMD64_RBP_REGNUM
);
2564 ax_simple (ax
, aop_add
);
2565 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2566 value
->kind
= axs_lvalue_memory
;
2570 /* Signal trampolines. */
2572 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2573 64-bit variants. This would require using identical frame caches
2574 on both platforms. */
2576 static struct amd64_frame_cache
*
2577 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2579 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2580 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2581 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2582 volatile struct gdb_exception ex
;
2583 struct amd64_frame_cache
*cache
;
2591 cache
= amd64_alloc_frame_cache ();
2593 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2595 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2596 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2598 addr
= tdep
->sigcontext_addr (this_frame
);
2599 gdb_assert (tdep
->sc_reg_offset
);
2600 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2601 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2602 if (tdep
->sc_reg_offset
[i
] != -1)
2603 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2607 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2608 throw_exception (ex
);
2610 *this_cache
= cache
;
2614 static enum unwind_stop_reason
2615 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2618 struct amd64_frame_cache
*cache
=
2619 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2622 return UNWIND_UNAVAILABLE
;
2624 return UNWIND_NO_REASON
;
2628 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2629 void **this_cache
, struct frame_id
*this_id
)
2631 struct amd64_frame_cache
*cache
=
2632 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2635 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2636 else if (cache
->base
== 0)
2638 /* This marks the outermost frame. */
2642 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2645 static struct value
*
2646 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2647 void **this_cache
, int regnum
)
2649 /* Make sure we've initialized the cache. */
2650 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2652 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2656 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2657 struct frame_info
*this_frame
,
2660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2662 /* We shouldn't even bother if we don't have a sigcontext_addr
2664 if (tdep
->sigcontext_addr
== NULL
)
2667 if (tdep
->sigtramp_p
!= NULL
)
2669 if (tdep
->sigtramp_p (this_frame
))
2673 if (tdep
->sigtramp_start
!= 0)
2675 CORE_ADDR pc
= get_frame_pc (this_frame
);
2677 gdb_assert (tdep
->sigtramp_end
!= 0);
2678 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2685 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2688 amd64_sigtramp_frame_unwind_stop_reason
,
2689 amd64_sigtramp_frame_this_id
,
2690 amd64_sigtramp_frame_prev_register
,
2692 amd64_sigtramp_frame_sniffer
2697 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2699 struct amd64_frame_cache
*cache
=
2700 amd64_frame_cache (this_frame
, this_cache
);
2705 static const struct frame_base amd64_frame_base
=
2707 &amd64_frame_unwind
,
2708 amd64_frame_base_address
,
2709 amd64_frame_base_address
,
2710 amd64_frame_base_address
2713 /* Normal frames, but in a function epilogue. */
2715 /* The epilogue is defined here as the 'ret' instruction, which will
2716 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2717 the function's stack frame. */
2720 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2723 struct compunit_symtab
*cust
;
2725 cust
= find_pc_compunit_symtab (pc
);
2726 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2729 if (target_read_memory (pc
, &insn
, 1))
2730 return 0; /* Can't read memory at pc. */
2732 if (insn
!= 0xc3) /* 'ret' instruction. */
2739 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2740 struct frame_info
*this_frame
,
2741 void **this_prologue_cache
)
2743 if (frame_relative_level (this_frame
) == 0)
2744 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
2745 get_frame_pc (this_frame
));
2750 static struct amd64_frame_cache
*
2751 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2753 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2754 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2755 volatile struct gdb_exception ex
;
2756 struct amd64_frame_cache
*cache
;
2762 cache
= amd64_alloc_frame_cache ();
2763 *this_cache
= cache
;
2765 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2767 /* Cache base will be %esp plus cache->sp_offset (-8). */
2768 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2769 cache
->base
= extract_unsigned_integer (buf
, 8,
2770 byte_order
) + cache
->sp_offset
;
2772 /* Cache pc will be the frame func. */
2773 cache
->pc
= get_frame_pc (this_frame
);
2775 /* The saved %esp will be at cache->base plus 16. */
2776 cache
->saved_sp
= cache
->base
+ 16;
2778 /* The saved %eip will be at cache->base plus 8. */
2779 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2783 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2784 throw_exception (ex
);
2789 static enum unwind_stop_reason
2790 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2793 struct amd64_frame_cache
*cache
2794 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2797 return UNWIND_UNAVAILABLE
;
2799 return UNWIND_NO_REASON
;
2803 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2805 struct frame_id
*this_id
)
2807 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2811 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2813 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2816 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2819 amd64_epilogue_frame_unwind_stop_reason
,
2820 amd64_epilogue_frame_this_id
,
2821 amd64_frame_prev_register
,
2823 amd64_epilogue_frame_sniffer
2826 static struct frame_id
2827 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2831 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2833 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2836 /* 16 byte align the SP per frame requirements. */
2839 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2841 return sp
& -(CORE_ADDR
)16;
2845 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2846 in the floating-point register set REGSET to register cache
2847 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2850 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2851 int regnum
, const void *fpregs
, size_t len
)
2853 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2854 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2856 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2857 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2860 /* Collect register REGNUM from the register cache REGCACHE and store
2861 it in the buffer specified by FPREGS and LEN as described by the
2862 floating-point register set REGSET. If REGNUM is -1, do this for
2863 all registers in REGSET. */
2866 amd64_collect_fpregset (const struct regset
*regset
,
2867 const struct regcache
*regcache
,
2868 int regnum
, void *fpregs
, size_t len
)
2870 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2871 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2873 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2874 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2877 const struct regset amd64_fpregset
=
2879 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2883 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2884 %rdi. We expect its value to be a pointer to the jmp_buf structure
2885 from which we extract the address that we will land at. This
2886 address is copied into PC. This routine returns non-zero on
2890 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2894 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2895 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2896 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2898 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2899 longjmp will land. */
2900 if (jb_pc_offset
== -1)
2903 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2904 jb_addr
= extract_typed_address
2905 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2906 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2909 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2914 static const int amd64_record_regmap
[] =
2916 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2917 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2918 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2919 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2920 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2921 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2925 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2927 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2928 const struct target_desc
*tdesc
= info
.target_desc
;
2929 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
2930 static const char *const stap_register_prefixes
[] = { "%", NULL
};
2931 static const char *const stap_register_indirection_prefixes
[] = { "(",
2933 static const char *const stap_register_indirection_suffixes
[] = { ")",
2936 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2937 floating-point registers. */
2938 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2939 tdep
->fpregset
= &amd64_fpregset
;
2941 if (! tdesc_has_registers (tdesc
))
2942 tdesc
= tdesc_amd64
;
2943 tdep
->tdesc
= tdesc
;
2945 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2946 tdep
->register_names
= amd64_register_names
;
2948 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
2950 tdep
->zmmh_register_names
= amd64_zmmh_names
;
2951 tdep
->k_register_names
= amd64_k_names
;
2952 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
2953 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
2955 tdep
->num_zmm_regs
= 32;
2956 tdep
->num_xmm_avx512_regs
= 16;
2957 tdep
->num_ymm_avx512_regs
= 16;
2959 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
2960 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
2961 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
2962 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
2965 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2967 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2968 tdep
->num_ymm_regs
= 16;
2969 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2972 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
2974 tdep
->mpx_register_names
= amd64_mpx_names
;
2975 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
2976 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
2979 tdep
->num_byte_regs
= 20;
2980 tdep
->num_word_regs
= 16;
2981 tdep
->num_dword_regs
= 16;
2982 /* Avoid wiring in the MMX registers for now. */
2983 tdep
->num_mmx_regs
= 0;
2985 set_gdbarch_pseudo_register_read_value (gdbarch
,
2986 amd64_pseudo_register_read_value
);
2987 set_gdbarch_pseudo_register_write (gdbarch
,
2988 amd64_pseudo_register_write
);
2990 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
2992 /* AMD64 has an FPU and 16 SSE registers. */
2993 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2994 tdep
->num_xmm_regs
= 16;
2996 /* This is what all the fuss is about. */
2997 set_gdbarch_long_bit (gdbarch
, 64);
2998 set_gdbarch_long_long_bit (gdbarch
, 64);
2999 set_gdbarch_ptr_bit (gdbarch
, 64);
3001 /* In contrast to the i386, on AMD64 a `long double' actually takes
3002 up 128 bits, even though it's still based on the i387 extended
3003 floating-point format which has only 80 significant bits. */
3004 set_gdbarch_long_double_bit (gdbarch
, 128);
3006 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3008 /* Register numbers of various important registers. */
3009 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3010 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3011 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3012 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3014 /* The "default" register numbering scheme for AMD64 is referred to
3015 as the "DWARF Register Number Mapping" in the System V psABI.
3016 The preferred debugging format for all known AMD64 targets is
3017 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3018 DWARF-1), but we provide the same mapping just in case. This
3019 mapping is also used for stabs, which GCC does support. */
3020 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3021 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3023 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3024 be in use on any of the supported AMD64 targets. */
3026 /* Call dummy code. */
3027 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3028 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3029 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3031 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3032 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3033 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3035 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3037 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3039 tdep
->record_regmap
= amd64_record_regmap
;
3041 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3043 /* Hook the function epilogue frame unwinder. This unwinder is
3044 appended to the list first, so that it supercedes the other
3045 unwinders in function epilogues. */
3046 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3048 /* Hook the prologue-based frame unwinders. */
3049 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3050 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3051 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3053 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3055 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3057 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3059 /* SystemTap variables and functions. */
3060 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3061 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3062 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3063 stap_register_indirection_prefixes
);
3064 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3065 stap_register_indirection_suffixes
);
3066 set_gdbarch_stap_is_single_operand (gdbarch
,
3067 i386_stap_is_single_operand
);
3068 set_gdbarch_stap_parse_special_token (gdbarch
,
3069 i386_stap_parse_special_token
);
3070 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3071 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3072 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3076 static struct type
*
3077 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3081 switch (regnum
- tdep
->eax_regnum
)
3083 case AMD64_RBP_REGNUM
: /* %ebp */
3084 case AMD64_RSP_REGNUM
: /* %esp */
3085 return builtin_type (gdbarch
)->builtin_data_ptr
;
3086 case AMD64_RIP_REGNUM
: /* %eip */
3087 return builtin_type (gdbarch
)->builtin_func_ptr
;
3090 return i386_pseudo_register_type (gdbarch
, regnum
);
3094 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3096 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3097 const struct target_desc
*tdesc
= info
.target_desc
;
3099 amd64_init_abi (info
, gdbarch
);
3101 if (! tdesc_has_registers (tdesc
))
3103 tdep
->tdesc
= tdesc
;
3105 tdep
->num_dword_regs
= 17;
3106 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3108 set_gdbarch_long_bit (gdbarch
, 32);
3109 set_gdbarch_ptr_bit (gdbarch
, 32);
3112 /* Provide a prototype to silence -Wmissing-prototypes. */
3113 void _initialize_amd64_tdep (void);
3116 _initialize_amd64_tdep (void)
3118 initialize_tdesc_amd64 ();
3119 initialize_tdesc_amd64_avx ();
3120 initialize_tdesc_amd64_mpx ();
3121 initialize_tdesc_amd64_avx512 ();
3123 initialize_tdesc_x32 ();
3124 initialize_tdesc_x32_avx ();
3125 initialize_tdesc_x32_avx512 ();
3129 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3130 sense that the instruction pointer and data pointer are simply
3131 64-bit offsets into the code segment and the data segment instead
3132 of a selector offset pair. The functions below store the upper 32
3133 bits of these pointers (instead of just the 16-bits of the segment
3136 /* Fill register REGNUM in REGCACHE with the appropriate
3137 floating-point or SSE register value from *FXSAVE. If REGNUM is
3138 -1, do this for all registers. This function masks off any of the
3139 reserved bits in *FXSAVE. */
3142 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3145 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3146 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3148 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3151 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3153 const gdb_byte
*regs
= fxsave
;
3155 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3156 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3157 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3158 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3162 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3165 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3168 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3169 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3171 i387_supply_xsave (regcache
, regnum
, xsave
);
3174 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3176 const gdb_byte
*regs
= xsave
;
3178 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3179 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3181 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3182 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3187 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3188 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3189 all registers. This function doesn't touch any of the reserved
3193 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3196 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3197 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3198 gdb_byte
*regs
= fxsave
;
3200 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3202 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3204 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3205 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3206 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3207 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3211 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3214 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3215 void *xsave
, int gcore
)
3217 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3219 gdb_byte
*regs
= xsave
;
3221 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3223 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3225 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3226 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3228 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3229 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),