1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2019 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "common/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "common/byte-vector.h"
53 /* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
55 returned by config.guess, and used as the name for the AMD64 port
56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
60 /* Register information. */
62 static const char *amd64_register_names
[] =
64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
66 /* %r8 is indeed register number 8. */
67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
70 /* %st0 is register number 24. */
71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
74 /* %xmm0 is register number 40. */
75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80 static const char *amd64_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
88 static const char *amd64_ymm_avx512_names
[] =
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
96 static const char *amd64_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
104 static const char *amd64_ymmh_avx512_names
[] =
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
112 static const char *amd64_mpx_names
[] =
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
117 static const char *amd64_k_names
[] =
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
123 static const char *amd64_zmmh_names
[] =
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
135 static const char *amd64_zmm_names
[] =
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
147 static const char *amd64_xmm_avx512_names
[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
154 static const char *amd64_pkeys_names
[] = {
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap
[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
165 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
166 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM
, /* %r8 */
176 AMD64_R9_REGNUM
, /* %r9 */
177 AMD64_R10_REGNUM
, /* %r10 */
178 AMD64_R11_REGNUM
, /* %r11 */
179 AMD64_R12_REGNUM
, /* %r12 */
180 AMD64_R13_REGNUM
, /* %r13 */
181 AMD64_R14_REGNUM
, /* %r14 */
182 AMD64_R15_REGNUM
, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
189 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
190 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
191 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
195 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
196 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
197 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
201 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
202 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
203 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len
=
241 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 int ymm0_regnum
= tdep
->ymm0_regnum
;
253 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
254 regnum
= amd64_dwarf_regmap
[reg
];
257 && i386_xmm_regnum_p (gdbarch
, regnum
))
258 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap
[16] =
267 AMD64_RAX_REGNUM
, /* %rax */
268 AMD64_RCX_REGNUM
, /* %rcx */
269 AMD64_RDX_REGNUM
, /* %rdx */
270 AMD64_RBX_REGNUM
, /* %rbx */
271 AMD64_RSP_REGNUM
, /* %rsp */
272 AMD64_RBP_REGNUM
, /* %rbp */
273 AMD64_RSI_REGNUM
, /* %rsi */
274 AMD64_RDI_REGNUM
, /* %rdi */
275 AMD64_R8_REGNUM
, /* %r8 */
276 AMD64_R9_REGNUM
, /* %r9 */
277 AMD64_R10_REGNUM
, /* %r10 */
278 AMD64_R11_REGNUM
, /* %r11 */
279 AMD64_R12_REGNUM
, /* %r12 */
280 AMD64_R13_REGNUM
, /* %r13 */
281 AMD64_R14_REGNUM
, /* %r14 */
282 AMD64_R15_REGNUM
/* %r15 */
285 static const int amd64_arch_regmap_len
=
286 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg
)
294 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
296 return amd64_arch_regmap
[reg
];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names
[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names
[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names
[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 if (i386_byte_regnum_p (gdbarch
, regnum
))
335 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
336 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
337 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
338 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
339 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
340 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
342 else if (i386_word_regnum_p (gdbarch
, regnum
))
343 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
344 else if (i386_dword_regnum_p (gdbarch
, regnum
))
345 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
347 return i386_pseudo_register_name (gdbarch
, regnum
);
350 static struct value
*
351 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
352 readable_regcache
*regcache
,
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
358 VALUE_LVAL (result_value
) = lval_register
;
359 VALUE_REGNUM (result_value
) = regnum
;
360 gdb_byte
*buf
= value_contents_raw (result_value
);
362 if (i386_byte_regnum_p (gdbarch
, regnum
))
364 int gpnum
= regnum
- tdep
->al_regnum
;
366 /* Extract (always little endian). */
367 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
369 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
370 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
372 /* Special handling for AH, BH, CH, DH. */
373 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
374 if (status
== REG_VALID
)
375 memcpy (buf
, raw_buf
+ 1, 1);
377 mark_value_bytes_unavailable (result_value
, 0,
378 TYPE_LENGTH (value_type (result_value
)));
382 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
383 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
384 if (status
== REG_VALID
)
385 memcpy (buf
, raw_buf
, 1);
387 mark_value_bytes_unavailable (result_value
, 0,
388 TYPE_LENGTH (value_type (result_value
)));
391 else if (i386_dword_regnum_p (gdbarch
, regnum
))
393 int gpnum
= regnum
- tdep
->eax_regnum
;
394 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
395 /* Extract (always little endian). */
396 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
397 if (status
== REG_VALID
)
398 memcpy (buf
, raw_buf
, 4);
400 mark_value_bytes_unavailable (result_value
, 0,
401 TYPE_LENGTH (value_type (result_value
)));
404 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
411 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
412 struct regcache
*regcache
,
413 int regnum
, const gdb_byte
*buf
)
415 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
417 if (i386_byte_regnum_p (gdbarch
, regnum
))
419 int gpnum
= regnum
- tdep
->al_regnum
;
421 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
423 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
424 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
426 /* Read ... AH, BH, CH, DH. */
427 regcache
->raw_read (gpnum
, raw_buf
);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf
+ 1, buf
, 1);
431 regcache
->raw_write (gpnum
, raw_buf
);
435 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
438 regcache
->raw_read (gpnum
, raw_buf
);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf
, buf
, 1);
442 regcache
->raw_write (gpnum
, raw_buf
);
445 else if (i386_dword_regnum_p (gdbarch
, regnum
))
447 int gpnum
= regnum
- tdep
->eax_regnum
;
448 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
451 regcache
->raw_read (gpnum
, raw_buf
);
452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf
, buf
, 4);
455 regcache
->raw_write (gpnum
, raw_buf
);
458 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
461 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
465 struct agent_expr
*ax
, int regnum
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 if (i386_byte_regnum_p (gdbarch
, regnum
))
471 int gpnum
= regnum
- tdep
->al_regnum
;
473 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
474 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
476 ax_reg_mask (ax
, gpnum
);
479 else if (i386_dword_regnum_p (gdbarch
, regnum
))
481 int gpnum
= regnum
- tdep
->eax_regnum
;
483 ax_reg_mask (ax
, gpnum
);
487 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
492 /* Register classes as defined in the psABI. */
506 /* Return the union class of CLASS1 and CLASS2. See the psABI for
509 static enum amd64_reg_class
510 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1
== class2
)
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1
== AMD64_NO_CLASS
)
520 if (class2
== AMD64_NO_CLASS
)
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
529 return AMD64_INTEGER
;
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
534 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
535 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
538 /* Rule (f): Otherwise class SSE is used. */
542 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
544 /* Return non-zero if TYPE is a non-POD structure or union type. */
547 amd64_non_pod_p (struct type
*type
)
549 /* ??? A class with a base class certainly isn't POD, but does this
550 catch all non-POD structure types? */
551 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
557 /* Classify TYPE according to the rules for aggregate (structures and
558 arrays) and union types, and store the result in CLASS. */
561 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
563 /* 1. If the size of an object is larger than two eightbytes, or in
564 C++, is a non-POD structure or union type, or contains
565 unaligned fields, it has class memory. */
566 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
568 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
572 /* 2. Both eightbytes get initialized to class NO_CLASS. */
573 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
575 /* 3. Each field of an object is classified recursively so that
576 always two fields are considered. The resulting class is
577 calculated according to the classes of the fields in the
580 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
582 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
584 /* All fields in an array have the same type. */
585 amd64_classify (subtype
, theclass
);
586 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
587 theclass
[1] = theclass
[0];
593 /* Structure or union. */
594 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
595 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
597 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
599 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
600 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
601 enum amd64_reg_class subclass
[2];
602 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
606 bitsize
= TYPE_LENGTH (subtype
) * 8;
607 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
609 /* Ignore static fields, or empty fields, for example nested
611 if (field_is_static (&TYPE_FIELD (type
, i
)) || bitsize
== 0)
614 gdb_assert (pos
== 0 || pos
== 1);
616 amd64_classify (subtype
, subclass
);
617 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
618 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
619 /* This is a bit of an odd case: We have a field that would
620 normally fit in one of the two eightbytes, except that
621 it is placed in a way that this field straddles them.
622 This has been seen with a structure containing an array.
624 The ABI is a bit unclear in this case, but we assume that
625 this field's class (stored in subclass[0]) must also be merged
626 into class[1]. In other words, our field has a piece stored
627 in the second eight-byte, and thus its class applies to
628 the second eight-byte as well.
630 In the case where the field length exceeds 8 bytes,
631 it should not be necessary to merge the field class
632 into class[1]. As LEN > 8, subclass[1] is necessarily
633 different from AMD64_NO_CLASS. If subclass[1] is equal
634 to subclass[0], then the normal class[1]/subclass[1]
635 merging will take care of everything. For subclass[1]
636 to be different from subclass[0], I can only see the case
637 where we have a SSE/SSEUP or X87/X87UP pair, which both
638 use up all 16 bytes of the aggregate, and are already
639 handled just fine (because each portion sits on its own
641 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
643 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
647 /* 4. Then a post merger cleanup is done: */
649 /* Rule (a): If one of the classes is MEMORY, the whole argument is
651 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
652 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
654 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
656 if (theclass
[0] == AMD64_SSEUP
)
657 theclass
[0] = AMD64_SSE
;
658 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
659 theclass
[1] = AMD64_SSE
;
662 /* Classify TYPE, and store the result in CLASS. */
665 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
667 enum type_code code
= TYPE_CODE (type
);
668 int len
= TYPE_LENGTH (type
);
670 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
672 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
673 long, long long, and pointers are in the INTEGER class. Similarly,
674 range types, used by languages such as Ada, are also in the INTEGER
676 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
677 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
678 || code
== TYPE_CODE_CHAR
679 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
680 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
681 theclass
[0] = AMD64_INTEGER
;
683 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
685 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
686 && (len
== 4 || len
== 8))
688 theclass
[0] = AMD64_SSE
;
690 /* Arguments of types __float128, _Decimal128 and __m128 are split into
691 two halves. The least significant ones belong to class SSE, the most
692 significant one to class SSEUP. */
693 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
694 /* FIXME: __float128, __m128. */
695 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
697 /* The 64-bit mantissa of arguments of type long double belongs to
698 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
700 else if (code
== TYPE_CODE_FLT
&& len
== 16)
701 /* Class X87 and X87UP. */
702 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
704 /* Arguments of complex T where T is one of the types float or
705 double get treated as if they are implemented as:
713 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
714 theclass
[0] = AMD64_SSE
;
715 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
716 theclass
[0] = theclass
[1] = AMD64_SSE
;
718 /* A variable of type complex long double is classified as type
720 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
721 theclass
[0] = AMD64_COMPLEX_X87
;
724 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
725 || code
== TYPE_CODE_UNION
)
726 amd64_classify_aggregate (type
, theclass
);
729 static enum return_value_convention
730 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
731 struct type
*type
, struct regcache
*regcache
,
732 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
734 enum amd64_reg_class theclass
[2];
735 int len
= TYPE_LENGTH (type
);
736 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
737 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
742 gdb_assert (!(readbuf
&& writebuf
));
744 /* 1. Classify the return type with the classification algorithm. */
745 amd64_classify (type
, theclass
);
747 /* 2. If the type has class MEMORY, then the caller provides space
748 for the return value and passes the address of this storage in
749 %rdi as if it were the first argument to the function. In effect,
750 this address becomes a hidden first argument.
752 On return %rax will contain the address that has been passed in
753 by the caller in %rdi. */
754 if (theclass
[0] == AMD64_MEMORY
)
756 /* As indicated by the comment above, the ABI guarantees that we
757 can always find the return value just after the function has
764 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
765 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
768 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
771 /* 8. If the class is COMPLEX_X87, the real part of the value is
772 returned in %st0 and the imaginary part in %st1. */
773 if (theclass
[0] == AMD64_COMPLEX_X87
)
777 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
778 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
783 i387_return_value (gdbarch
, regcache
);
784 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
785 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
787 /* Fix up the tag word such that both %st(0) and %st(1) are
789 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
792 return RETURN_VALUE_REGISTER_CONVENTION
;
795 gdb_assert (theclass
[1] != AMD64_MEMORY
);
796 gdb_assert (len
<= 16);
798 for (i
= 0; len
> 0; i
++, len
-= 8)
806 /* 3. If the class is INTEGER, the next available register
807 of the sequence %rax, %rdx is used. */
808 regnum
= integer_regnum
[integer_reg
++];
812 /* 4. If the class is SSE, the next available SSE register
813 of the sequence %xmm0, %xmm1 is used. */
814 regnum
= sse_regnum
[sse_reg
++];
818 /* 5. If the class is SSEUP, the eightbyte is passed in the
819 upper half of the last used SSE register. */
820 gdb_assert (sse_reg
> 0);
821 regnum
= sse_regnum
[sse_reg
- 1];
826 /* 6. If the class is X87, the value is returned on the X87
827 stack in %st0 as 80-bit x87 number. */
828 regnum
= AMD64_ST0_REGNUM
;
830 i387_return_value (gdbarch
, regcache
);
834 /* 7. If the class is X87UP, the value is returned together
835 with the previous X87 value in %st0. */
836 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
837 regnum
= AMD64_ST0_REGNUM
;
846 gdb_assert (!"Unexpected register class.");
849 gdb_assert (regnum
!= -1);
852 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
855 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
859 return RETURN_VALUE_REGISTER_CONVENTION
;
864 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
865 CORE_ADDR sp
, function_call_return_method return_method
)
867 static int integer_regnum
[] =
869 AMD64_RDI_REGNUM
, /* %rdi */
870 AMD64_RSI_REGNUM
, /* %rsi */
871 AMD64_RDX_REGNUM
, /* %rdx */
872 AMD64_RCX_REGNUM
, /* %rcx */
873 AMD64_R8_REGNUM
, /* %r8 */
874 AMD64_R9_REGNUM
/* %r9 */
876 static int sse_regnum
[] =
878 /* %xmm0 ... %xmm7 */
879 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
880 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
881 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
882 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
884 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
885 int num_stack_args
= 0;
886 int num_elements
= 0;
892 /* Reserve a register for the "hidden" argument. */
893 if (return_method
== return_method_struct
)
896 for (i
= 0; i
< nargs
; i
++)
898 struct type
*type
= value_type (args
[i
]);
899 int len
= TYPE_LENGTH (type
);
900 enum amd64_reg_class theclass
[2];
901 int needed_integer_regs
= 0;
902 int needed_sse_regs
= 0;
905 /* Classify argument. */
906 amd64_classify (type
, theclass
);
908 /* Calculate the number of integer and SSE registers needed for
910 for (j
= 0; j
< 2; j
++)
912 if (theclass
[j
] == AMD64_INTEGER
)
913 needed_integer_regs
++;
914 else if (theclass
[j
] == AMD64_SSE
)
918 /* Check whether enough registers are available, and if the
919 argument should be passed in registers at all. */
920 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
921 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
922 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
924 /* The argument will be passed on the stack. */
925 num_elements
+= ((len
+ 7) / 8);
926 stack_args
[num_stack_args
++] = args
[i
];
930 /* The argument will be passed in registers. */
931 const gdb_byte
*valbuf
= value_contents (args
[i
]);
934 gdb_assert (len
<= 16);
936 for (j
= 0; len
> 0; j
++, len
-= 8)
944 regnum
= integer_regnum
[integer_reg
++];
948 regnum
= sse_regnum
[sse_reg
++];
952 gdb_assert (sse_reg
> 0);
953 regnum
= sse_regnum
[sse_reg
- 1];
958 gdb_assert (!"Unexpected register class.");
961 gdb_assert (regnum
!= -1);
962 memset (buf
, 0, sizeof buf
);
963 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
964 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
969 /* Allocate space for the arguments on the stack. */
970 sp
-= num_elements
* 8;
972 /* The psABI says that "The end of the input argument area shall be
973 aligned on a 16 byte boundary." */
976 /* Write out the arguments to the stack. */
977 for (i
= 0; i
< num_stack_args
; i
++)
979 struct type
*type
= value_type (stack_args
[i
]);
980 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
981 int len
= TYPE_LENGTH (type
);
983 write_memory (sp
+ element
* 8, valbuf
, len
);
984 element
+= ((len
+ 7) / 8);
987 /* The psABI says that "For calls that may call functions that use
988 varargs or stdargs (prototype-less calls or calls to functions
989 containing ellipsis (...) in the declaration) %al is used as
990 hidden argument to specify the number of SSE registers used. */
991 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
996 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
997 struct regcache
*regcache
, CORE_ADDR bp_addr
,
998 int nargs
, struct value
**args
, CORE_ADDR sp
,
999 function_call_return_method return_method
,
1000 CORE_ADDR struct_addr
)
1002 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1005 /* BND registers can be in arbitrary values at the moment of the
1006 inferior call. This can cause boundary violations that are not
1007 due to a real bug or even desired by the user. The best to be done
1008 is set the BND registers to allow access to the whole memory, INIT
1009 state, before pushing the inferior call. */
1010 i387_reset_bnd_regs (gdbarch
, regcache
);
1012 /* Pass arguments. */
1013 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1015 /* Pass "hidden" argument". */
1016 if (return_method
== return_method_struct
)
1018 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1019 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1022 /* Store return address. */
1024 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1025 write_memory (sp
, buf
, 8);
1027 /* Finally, update the stack pointer... */
1028 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1029 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1031 /* ...and fake a frame pointer. */
1032 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1037 /* Displaced instruction handling. */
1039 /* A partially decoded instruction.
1040 This contains enough details for displaced stepping purposes. */
1044 /* The number of opcode bytes. */
1046 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1048 int enc_prefix_offset
;
1049 /* The offset to the first opcode byte. */
1051 /* The offset to the modrm byte or -1 if not present. */
1054 /* The raw instruction. */
1058 struct amd64_displaced_step_closure
: public displaced_step_closure
1060 amd64_displaced_step_closure (int insn_buf_len
)
1061 : insn_buf (insn_buf_len
, 0)
1064 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1069 /* Details of the instruction. */
1070 struct amd64_insn insn_details
;
1072 /* The possibly modified insn. */
1073 gdb::byte_vector insn_buf
;
1076 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1077 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1078 at which point delete these in favor of libopcodes' versions). */
1080 static const unsigned char onebyte_has_modrm
[256] = {
1081 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1082 /* ------------------------------- */
1083 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1084 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1085 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1086 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1087 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1088 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1089 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1090 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1091 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1092 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1093 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1094 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1095 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1096 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1097 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1098 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1099 /* ------------------------------- */
1100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1103 static const unsigned char twobyte_has_modrm
[256] = {
1104 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1105 /* ------------------------------- */
1106 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1107 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1108 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1109 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1110 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1111 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1112 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1113 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1114 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1115 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1116 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1117 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1118 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1119 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1120 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1121 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1122 /* ------------------------------- */
1123 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1126 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1129 rex_prefix_p (gdb_byte pfx
)
1131 return REX_PREFIX_P (pfx
);
1134 /* True if PFX is the start of the 2-byte VEX prefix. */
1137 vex2_prefix_p (gdb_byte pfx
)
1142 /* True if PFX is the start of the 3-byte VEX prefix. */
1145 vex3_prefix_p (gdb_byte pfx
)
1150 /* Skip the legacy instruction prefixes in INSN.
1151 We assume INSN is properly sentineled so we don't have to worry
1152 about falling off the end of the buffer. */
1155 amd64_skip_prefixes (gdb_byte
*insn
)
1161 case DATA_PREFIX_OPCODE
:
1162 case ADDR_PREFIX_OPCODE
:
1163 case CS_PREFIX_OPCODE
:
1164 case DS_PREFIX_OPCODE
:
1165 case ES_PREFIX_OPCODE
:
1166 case FS_PREFIX_OPCODE
:
1167 case GS_PREFIX_OPCODE
:
1168 case SS_PREFIX_OPCODE
:
1169 case LOCK_PREFIX_OPCODE
:
1170 case REPE_PREFIX_OPCODE
:
1171 case REPNE_PREFIX_OPCODE
:
1183 /* Return an integer register (other than RSP) that is unused as an input
1185 In order to not require adding a rex prefix if the insn doesn't already
1186 have one, the result is restricted to RAX ... RDI, sans RSP.
1187 The register numbering of the result follows architecture ordering,
1191 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1193 /* 1 bit for each reg */
1194 int used_regs_mask
= 0;
1196 /* There can be at most 3 int regs used as inputs in an insn, and we have
1197 7 to choose from (RAX ... RDI, sans RSP).
1198 This allows us to take a conservative approach and keep things simple.
1199 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1200 that implicitly specify RAX. */
1203 used_regs_mask
|= 1 << EAX_REG_NUM
;
1204 /* Similarily avoid RDX, implicit operand in divides. */
1205 used_regs_mask
|= 1 << EDX_REG_NUM
;
1207 used_regs_mask
|= 1 << ESP_REG_NUM
;
1209 /* If the opcode is one byte long and there's no ModRM byte,
1210 assume the opcode specifies a register. */
1211 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1212 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1214 /* Mark used regs in the modrm/sib bytes. */
1215 if (details
->modrm_offset
!= -1)
1217 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1218 int mod
= MODRM_MOD_FIELD (modrm
);
1219 int reg
= MODRM_REG_FIELD (modrm
);
1220 int rm
= MODRM_RM_FIELD (modrm
);
1221 int have_sib
= mod
!= 3 && rm
== 4;
1223 /* Assume the reg field of the modrm byte specifies a register. */
1224 used_regs_mask
|= 1 << reg
;
1228 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1229 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1230 used_regs_mask
|= 1 << base
;
1231 used_regs_mask
|= 1 << idx
;
1235 used_regs_mask
|= 1 << rm
;
1239 gdb_assert (used_regs_mask
< 256);
1240 gdb_assert (used_regs_mask
!= 255);
1242 /* Finally, find a free reg. */
1246 for (i
= 0; i
< 8; ++i
)
1248 if (! (used_regs_mask
& (1 << i
)))
1252 /* We shouldn't get here. */
1253 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1257 /* Extract the details of INSN that we need. */
1260 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1262 gdb_byte
*start
= insn
;
1265 details
->raw_insn
= insn
;
1267 details
->opcode_len
= -1;
1268 details
->enc_prefix_offset
= -1;
1269 details
->opcode_offset
= -1;
1270 details
->modrm_offset
= -1;
1272 /* Skip legacy instruction prefixes. */
1273 insn
= amd64_skip_prefixes (insn
);
1275 /* Skip REX/VEX instruction encoding prefixes. */
1276 if (rex_prefix_p (*insn
))
1278 details
->enc_prefix_offset
= insn
- start
;
1281 else if (vex2_prefix_p (*insn
))
1283 /* Don't record the offset in this case because this prefix has
1284 no REX.B equivalent. */
1287 else if (vex3_prefix_p (*insn
))
1289 details
->enc_prefix_offset
= insn
- start
;
1293 details
->opcode_offset
= insn
- start
;
1295 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1297 /* Two or three-byte opcode. */
1299 need_modrm
= twobyte_has_modrm
[*insn
];
1301 /* Check for three-byte opcode. */
1311 details
->opcode_len
= 3;
1314 details
->opcode_len
= 2;
1320 /* One-byte opcode. */
1321 need_modrm
= onebyte_has_modrm
[*insn
];
1322 details
->opcode_len
= 1;
1328 details
->modrm_offset
= insn
- start
;
1332 /* Update %rip-relative addressing in INSN.
1334 %rip-relative addressing only uses a 32-bit displacement.
1335 32 bits is not enough to be guaranteed to cover the distance between where
1336 the real instruction is and where its copy is.
1337 Convert the insn to use base+disp addressing.
1338 We set base = pc + insn_length so we can leave disp unchanged. */
1341 fixup_riprel (struct gdbarch
*gdbarch
, amd64_displaced_step_closure
*dsc
,
1342 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1344 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1345 int modrm_offset
= insn_details
->modrm_offset
;
1346 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1349 int arch_tmp_regno
, tmp_regno
;
1350 ULONGEST orig_value
;
1352 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1355 /* Compute the rip-relative address. */
1356 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1357 dsc
->insn_buf
.size (), from
);
1358 rip_base
= from
+ insn_length
;
1360 /* We need a register to hold the address.
1361 Pick one not used in the insn.
1362 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1363 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1364 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1366 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1367 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1369 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1370 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1372 if (insn_details
->enc_prefix_offset
!= -1)
1374 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1375 if (rex_prefix_p (pfx
[0]))
1377 else if (vex3_prefix_p (pfx
[0]))
1378 pfx
[1] |= VEX3_NOT_B
;
1380 gdb_assert_not_reached ("unhandled prefix");
1383 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1384 dsc
->tmp_regno
= tmp_regno
;
1385 dsc
->tmp_save
= orig_value
;
1388 /* Convert the ModRM field to be base+disp. */
1389 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1390 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1392 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1394 if (debug_displaced
)
1395 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1396 "displaced: using temp reg %d, old value %s, new value %s\n",
1397 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1398 paddress (gdbarch
, rip_base
));
1402 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1403 amd64_displaced_step_closure
*dsc
,
1404 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1406 const struct amd64_insn
*details
= &dsc
->insn_details
;
1408 if (details
->modrm_offset
!= -1)
1410 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1412 if ((modrm
& 0xc7) == 0x05)
1414 /* The insn uses rip-relative addressing.
1416 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1421 struct displaced_step_closure
*
1422 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1423 CORE_ADDR from
, CORE_ADDR to
,
1424 struct regcache
*regs
)
1426 int len
= gdbarch_max_insn_length (gdbarch
);
1427 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1428 continually watch for running off the end of the buffer. */
1429 int fixup_sentinel_space
= len
;
1430 amd64_displaced_step_closure
*dsc
1431 = new amd64_displaced_step_closure (len
+ fixup_sentinel_space
);
1432 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1433 struct amd64_insn
*details
= &dsc
->insn_details
;
1435 read_memory (from
, buf
, len
);
1437 /* Set up the sentinel space so we don't have to worry about running
1438 off the end of the buffer. An excessive number of leading prefixes
1439 could otherwise cause this. */
1440 memset (buf
+ len
, 0, fixup_sentinel_space
);
1442 amd64_get_insn_details (buf
, details
);
1444 /* GDB may get control back after the insn after the syscall.
1445 Presumably this is a kernel bug.
1446 If this is a syscall, make sure there's a nop afterwards. */
1450 if (amd64_syscall_p (details
, &syscall_length
))
1451 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1454 /* Modify the insn to cope with the address where it will be executed from.
1455 In particular, handle any rip-relative addressing. */
1456 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1458 write_memory (to
, buf
, len
);
1460 if (debug_displaced
)
1462 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1463 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1464 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1471 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1473 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1475 if (insn
[0] == 0xff)
1477 /* jump near, absolute indirect (/4) */
1478 if ((insn
[1] & 0x38) == 0x20)
1481 /* jump far, absolute indirect (/5) */
1482 if ((insn
[1] & 0x38) == 0x28)
1489 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1492 amd64_jmp_p (const struct amd64_insn
*details
)
1494 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1496 /* jump short, relative. */
1497 if (insn
[0] == 0xeb)
1500 /* jump near, relative. */
1501 if (insn
[0] == 0xe9)
1504 return amd64_absolute_jmp_p (details
);
1508 amd64_absolute_call_p (const struct amd64_insn
*details
)
1510 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1512 if (insn
[0] == 0xff)
1514 /* Call near, absolute indirect (/2) */
1515 if ((insn
[1] & 0x38) == 0x10)
1518 /* Call far, absolute indirect (/3) */
1519 if ((insn
[1] & 0x38) == 0x18)
1527 amd64_ret_p (const struct amd64_insn
*details
)
1529 /* NOTE: gcc can emit "repz ; ret". */
1530 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1534 case 0xc2: /* ret near, pop N bytes */
1535 case 0xc3: /* ret near */
1536 case 0xca: /* ret far, pop N bytes */
1537 case 0xcb: /* ret far */
1538 case 0xcf: /* iret */
1547 amd64_call_p (const struct amd64_insn
*details
)
1549 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1551 if (amd64_absolute_call_p (details
))
1554 /* call near, relative */
1555 if (insn
[0] == 0xe8)
1561 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1562 length in bytes. Otherwise, return zero. */
1565 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1567 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1569 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1578 /* Classify the instruction at ADDR using PRED.
1579 Throw an error if the memory can't be read. */
1582 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1583 int (*pred
) (const struct amd64_insn
*))
1585 struct amd64_insn details
;
1587 int len
, classification
;
1589 len
= gdbarch_max_insn_length (gdbarch
);
1590 buf
= (gdb_byte
*) alloca (len
);
1592 read_code (addr
, buf
, len
);
1593 amd64_get_insn_details (buf
, &details
);
1595 classification
= pred (&details
);
1597 return classification
;
1600 /* The gdbarch insn_is_call method. */
1603 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1605 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1608 /* The gdbarch insn_is_ret method. */
1611 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1613 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1616 /* The gdbarch insn_is_jump method. */
1619 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1621 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1624 /* Fix up the state of registers and memory after having single-stepped
1625 a displaced instruction. */
1628 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1629 struct displaced_step_closure
*dsc_
,
1630 CORE_ADDR from
, CORE_ADDR to
,
1631 struct regcache
*regs
)
1633 amd64_displaced_step_closure
*dsc
= (amd64_displaced_step_closure
*) dsc_
;
1634 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1635 /* The offset we applied to the instruction's address. */
1636 ULONGEST insn_offset
= to
- from
;
1637 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1638 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1640 if (debug_displaced
)
1641 fprintf_unfiltered (gdb_stdlog
,
1642 "displaced: fixup (%s, %s), "
1643 "insn = 0x%02x 0x%02x ...\n",
1644 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1647 /* If we used a tmp reg, restore it. */
1651 if (debug_displaced
)
1652 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1653 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1654 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1657 /* The list of issues to contend with here is taken from
1658 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1659 Yay for Free Software! */
1661 /* Relocate the %rip back to the program's instruction stream,
1664 /* Except in the case of absolute or indirect jump or call
1665 instructions, or a return instruction, the new rip is relative to
1666 the displaced instruction; make it relative to the original insn.
1667 Well, signal handler returns don't need relocation either, but we use the
1668 value of %rip to recognize those; see below. */
1669 if (! amd64_absolute_jmp_p (insn_details
)
1670 && ! amd64_absolute_call_p (insn_details
)
1671 && ! amd64_ret_p (insn_details
))
1676 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1678 /* A signal trampoline system call changes the %rip, resuming
1679 execution of the main program after the signal handler has
1680 returned. That makes them like 'return' instructions; we
1681 shouldn't relocate %rip.
1683 But most system calls don't, and we do need to relocate %rip.
1685 Our heuristic for distinguishing these cases: if stepping
1686 over the system call instruction left control directly after
1687 the instruction, the we relocate --- control almost certainly
1688 doesn't belong in the displaced copy. Otherwise, we assume
1689 the instruction has put control where it belongs, and leave
1690 it unrelocated. Goodness help us if there are PC-relative
1692 if (amd64_syscall_p (insn_details
, &insn_len
)
1693 && orig_rip
!= to
+ insn_len
1694 /* GDB can get control back after the insn after the syscall.
1695 Presumably this is a kernel bug.
1696 Fixup ensures its a nop, we add one to the length for it. */
1697 && orig_rip
!= to
+ insn_len
+ 1)
1699 if (debug_displaced
)
1700 fprintf_unfiltered (gdb_stdlog
,
1701 "displaced: syscall changed %%rip; "
1702 "not relocating\n");
1706 ULONGEST rip
= orig_rip
- insn_offset
;
1708 /* If we just stepped over a breakpoint insn, we don't backup
1709 the pc on purpose; this is to match behaviour without
1712 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1714 if (debug_displaced
)
1715 fprintf_unfiltered (gdb_stdlog
,
1717 "relocated %%rip from %s to %s\n",
1718 paddress (gdbarch
, orig_rip
),
1719 paddress (gdbarch
, rip
));
1723 /* If the instruction was PUSHFL, then the TF bit will be set in the
1724 pushed value, and should be cleared. We'll leave this for later,
1725 since GDB already messes up the TF flag when stepping over a
1728 /* If the instruction was a call, the return address now atop the
1729 stack is the address following the copied instruction. We need
1730 to make it the address following the original instruction. */
1731 if (amd64_call_p (insn_details
))
1735 const ULONGEST retaddr_len
= 8;
1737 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1738 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1739 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1740 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1742 if (debug_displaced
)
1743 fprintf_unfiltered (gdb_stdlog
,
1744 "displaced: relocated return addr at %s "
1746 paddress (gdbarch
, rsp
),
1747 paddress (gdbarch
, retaddr
));
1751 /* If the instruction INSN uses RIP-relative addressing, return the
1752 offset into the raw INSN where the displacement to be adjusted is
1753 found. Returns 0 if the instruction doesn't use RIP-relative
1757 rip_relative_offset (struct amd64_insn
*insn
)
1759 if (insn
->modrm_offset
!= -1)
1761 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1763 if ((modrm
& 0xc7) == 0x05)
1765 /* The displacement is found right after the ModRM byte. */
1766 return insn
->modrm_offset
+ 1;
1774 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1776 target_write_memory (*to
, buf
, len
);
1781 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1782 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1784 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1785 int len
= gdbarch_max_insn_length (gdbarch
);
1786 /* Extra space for sentinels. */
1787 int fixup_sentinel_space
= len
;
1788 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1789 struct amd64_insn insn_details
;
1791 LONGEST rel32
, newrel
;
1795 read_memory (oldloc
, buf
, len
);
1797 /* Set up the sentinel space so we don't have to worry about running
1798 off the end of the buffer. An excessive number of leading prefixes
1799 could otherwise cause this. */
1800 memset (buf
+ len
, 0, fixup_sentinel_space
);
1803 amd64_get_insn_details (insn
, &insn_details
);
1805 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1807 /* Skip legacy instruction prefixes. */
1808 insn
= amd64_skip_prefixes (insn
);
1810 /* Adjust calls with 32-bit relative addresses as push/jump, with
1811 the address pushed being the location where the original call in
1812 the user program would return to. */
1813 if (insn
[0] == 0xe8)
1815 gdb_byte push_buf
[32];
1819 /* Where "ret" in the original code will return to. */
1820 ret_addr
= oldloc
+ insn_length
;
1822 /* If pushing an address higher than or equal to 0x80000000,
1823 avoid 'pushq', as that sign extends its 32-bit operand, which
1824 would be incorrect. */
1825 if (ret_addr
<= 0x7fffffff)
1827 push_buf
[0] = 0x68; /* pushq $... */
1828 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1833 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1834 push_buf
[i
++] = 0x83;
1835 push_buf
[i
++] = 0xec;
1836 push_buf
[i
++] = 0x08;
1838 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1839 push_buf
[i
++] = 0x04;
1840 push_buf
[i
++] = 0x24;
1841 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1842 ret_addr
& 0xffffffff);
1845 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1846 push_buf
[i
++] = 0x44;
1847 push_buf
[i
++] = 0x24;
1848 push_buf
[i
++] = 0x04;
1849 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1853 gdb_assert (i
<= sizeof (push_buf
));
1854 /* Push the push. */
1855 append_insns (to
, i
, push_buf
);
1857 /* Convert the relative call to a relative jump. */
1860 /* Adjust the destination offset. */
1861 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1862 newrel
= (oldloc
- *to
) + rel32
;
1863 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1865 if (debug_displaced
)
1866 fprintf_unfiltered (gdb_stdlog
,
1867 "Adjusted insn rel32=%s at %s to"
1868 " rel32=%s at %s\n",
1869 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1870 hex_string (newrel
), paddress (gdbarch
, *to
));
1872 /* Write the adjusted jump into its displaced location. */
1873 append_insns (to
, 5, insn
);
1877 offset
= rip_relative_offset (&insn_details
);
1880 /* Adjust jumps with 32-bit relative addresses. Calls are
1881 already handled above. */
1882 if (insn
[0] == 0xe9)
1884 /* Adjust conditional jumps. */
1885 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1891 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1892 newrel
= (oldloc
- *to
) + rel32
;
1893 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1894 if (debug_displaced
)
1895 fprintf_unfiltered (gdb_stdlog
,
1896 "Adjusted insn rel32=%s at %s to"
1897 " rel32=%s at %s\n",
1898 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1899 hex_string (newrel
), paddress (gdbarch
, *to
));
1902 /* Write the adjusted instruction into its displaced location. */
1903 append_insns (to
, insn_length
, buf
);
1907 /* The maximum number of saved registers. This should include %rip. */
1908 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1910 struct amd64_frame_cache
1915 CORE_ADDR sp_offset
;
1918 /* Saved registers. */
1919 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1923 /* Do we have a frame? */
1927 /* Initialize a frame cache. */
1930 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1937 cache
->sp_offset
= -8;
1940 /* Saved registers. We initialize these to -1 since zero is a valid
1941 offset (that's where %rbp is supposed to be stored).
1942 The values start out as being offsets, and are later converted to
1943 addresses (at which point -1 is interpreted as an address, still meaning
1945 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1946 cache
->saved_regs
[i
] = -1;
1947 cache
->saved_sp
= 0;
1948 cache
->saved_sp_reg
= -1;
1950 /* Frameless until proven otherwise. */
1951 cache
->frameless_p
= 1;
1954 /* Allocate and initialize a frame cache. */
1956 static struct amd64_frame_cache
*
1957 amd64_alloc_frame_cache (void)
1959 struct amd64_frame_cache
*cache
;
1961 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1962 amd64_init_frame_cache (cache
);
1966 /* GCC 4.4 and later, can put code in the prologue to realign the
1967 stack pointer. Check whether PC points to such code, and update
1968 CACHE accordingly. Return the first instruction after the code
1969 sequence or CURRENT_PC, whichever is smaller. If we don't
1970 recognize the code, return PC. */
1973 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1974 struct amd64_frame_cache
*cache
)
1976 /* There are 2 code sequences to re-align stack before the frame
1979 1. Use a caller-saved saved register:
1985 2. Use a callee-saved saved register:
1992 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1994 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1995 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2000 int offset
, offset_and
;
2002 if (target_read_code (pc
, buf
, sizeof buf
))
2005 /* Check caller-saved saved register. The first instruction has
2006 to be "leaq 8(%rsp), %reg". */
2007 if ((buf
[0] & 0xfb) == 0x48
2012 /* MOD must be binary 10 and R/M must be binary 100. */
2013 if ((buf
[2] & 0xc7) != 0x44)
2016 /* REG has register number. */
2017 reg
= (buf
[2] >> 3) & 7;
2019 /* Check the REX.R bit. */
2027 /* Check callee-saved saved register. The first instruction
2028 has to be "pushq %reg". */
2030 if ((buf
[0] & 0xf8) == 0x50)
2032 else if ((buf
[0] & 0xf6) == 0x40
2033 && (buf
[1] & 0xf8) == 0x50)
2035 /* Check the REX.B bit. */
2036 if ((buf
[0] & 1) != 0)
2045 reg
+= buf
[offset
] & 0x7;
2049 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2050 if ((buf
[offset
] & 0xfb) != 0x48
2051 || buf
[offset
+ 1] != 0x8d
2052 || buf
[offset
+ 3] != 0x24
2053 || buf
[offset
+ 4] != 0x10)
2056 /* MOD must be binary 10 and R/M must be binary 100. */
2057 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2060 /* REG has register number. */
2061 r
= (buf
[offset
+ 2] >> 3) & 7;
2063 /* Check the REX.R bit. */
2064 if (buf
[offset
] == 0x4c)
2067 /* Registers in pushq and leaq have to be the same. */
2074 /* Rigister can't be %rsp nor %rbp. */
2075 if (reg
== 4 || reg
== 5)
2078 /* The next instruction has to be "andq $-XXX, %rsp". */
2079 if (buf
[offset
] != 0x48
2080 || buf
[offset
+ 2] != 0xe4
2081 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2084 offset_and
= offset
;
2085 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2087 /* The next instruction has to be "pushq -8(%reg)". */
2089 if (buf
[offset
] == 0xff)
2091 else if ((buf
[offset
] & 0xf6) == 0x40
2092 && buf
[offset
+ 1] == 0xff)
2094 /* Check the REX.B bit. */
2095 if ((buf
[offset
] & 0x1) != 0)
2102 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2104 if (buf
[offset
+ 1] != 0xf8
2105 || (buf
[offset
] & 0xf8) != 0x70)
2108 /* R/M has register. */
2109 r
+= buf
[offset
] & 7;
2111 /* Registers in leaq and pushq have to be the same. */
2115 if (current_pc
> pc
+ offset_and
)
2116 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2118 return std::min (pc
+ offset
+ 2, current_pc
);
2121 /* Similar to amd64_analyze_stack_align for x32. */
2124 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2125 struct amd64_frame_cache
*cache
)
2127 /* There are 2 code sequences to re-align stack before the frame
2130 1. Use a caller-saved saved register:
2138 [addr32] leal 8(%rsp), %reg
2140 [addr32] pushq -8(%reg)
2142 2. Use a callee-saved saved register:
2152 [addr32] leal 16(%rsp), %reg
2154 [addr32] pushq -8(%reg)
2156 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2158 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2159 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2161 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2163 0x83 0xe4 0xf0 andl $-16, %esp
2164 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2169 int offset
, offset_and
;
2171 if (target_read_memory (pc
, buf
, sizeof buf
))
2174 /* Skip optional addr32 prefix. */
2175 offset
= buf
[0] == 0x67 ? 1 : 0;
2177 /* Check caller-saved saved register. The first instruction has
2178 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2179 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2180 && buf
[offset
+ 1] == 0x8d
2181 && buf
[offset
+ 3] == 0x24
2182 && buf
[offset
+ 4] == 0x8)
2184 /* MOD must be binary 10 and R/M must be binary 100. */
2185 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2188 /* REG has register number. */
2189 reg
= (buf
[offset
+ 2] >> 3) & 7;
2191 /* Check the REX.R bit. */
2192 if ((buf
[offset
] & 0x4) != 0)
2199 /* Check callee-saved saved register. The first instruction
2200 has to be "pushq %reg". */
2202 if ((buf
[offset
] & 0xf6) == 0x40
2203 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2205 /* Check the REX.B bit. */
2206 if ((buf
[offset
] & 1) != 0)
2211 else if ((buf
[offset
] & 0xf8) != 0x50)
2215 reg
+= buf
[offset
] & 0x7;
2219 /* Skip optional addr32 prefix. */
2220 if (buf
[offset
] == 0x67)
2223 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2224 "leal 16(%rsp), %reg". */
2225 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2226 || buf
[offset
+ 1] != 0x8d
2227 || buf
[offset
+ 3] != 0x24
2228 || buf
[offset
+ 4] != 0x10)
2231 /* MOD must be binary 10 and R/M must be binary 100. */
2232 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2235 /* REG has register number. */
2236 r
= (buf
[offset
+ 2] >> 3) & 7;
2238 /* Check the REX.R bit. */
2239 if ((buf
[offset
] & 0x4) != 0)
2242 /* Registers in pushq and leaq have to be the same. */
2249 /* Rigister can't be %rsp nor %rbp. */
2250 if (reg
== 4 || reg
== 5)
2253 /* The next instruction may be "andq $-XXX, %rsp" or
2254 "andl $-XXX, %esp". */
2255 if (buf
[offset
] != 0x48)
2258 if (buf
[offset
+ 2] != 0xe4
2259 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2262 offset_and
= offset
;
2263 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2265 /* Skip optional addr32 prefix. */
2266 if (buf
[offset
] == 0x67)
2269 /* The next instruction has to be "pushq -8(%reg)". */
2271 if (buf
[offset
] == 0xff)
2273 else if ((buf
[offset
] & 0xf6) == 0x40
2274 && buf
[offset
+ 1] == 0xff)
2276 /* Check the REX.B bit. */
2277 if ((buf
[offset
] & 0x1) != 0)
2284 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2286 if (buf
[offset
+ 1] != 0xf8
2287 || (buf
[offset
] & 0xf8) != 0x70)
2290 /* R/M has register. */
2291 r
+= buf
[offset
] & 7;
2293 /* Registers in leaq and pushq have to be the same. */
2297 if (current_pc
> pc
+ offset_and
)
2298 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2300 return std::min (pc
+ offset
+ 2, current_pc
);
2303 /* Do a limited analysis of the prologue at PC and update CACHE
2304 accordingly. Bail out early if CURRENT_PC is reached. Return the
2305 address where the analysis stopped.
2307 We will handle only functions beginning with:
2310 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2312 or (for the X32 ABI):
2315 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2317 Any function that doesn't start with one of these sequences will be
2318 assumed to have no prologue and thus no valid frame pointer in
2322 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2323 CORE_ADDR pc
, CORE_ADDR current_pc
,
2324 struct amd64_frame_cache
*cache
)
2326 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2327 /* There are two variations of movq %rsp, %rbp. */
2328 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2329 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2330 /* Ditto for movl %esp, %ebp. */
2331 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2332 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2337 if (current_pc
<= pc
)
2340 if (gdbarch_ptr_bit (gdbarch
) == 32)
2341 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2343 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2345 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2347 if (op
== 0x55) /* pushq %rbp */
2349 /* Take into account that we've executed the `pushq %rbp' that
2350 starts this instruction sequence. */
2351 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2352 cache
->sp_offset
+= 8;
2354 /* If that's all, return now. */
2355 if (current_pc
<= pc
+ 1)
2358 read_code (pc
+ 1, buf
, 3);
2360 /* Check for `movq %rsp, %rbp'. */
2361 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2362 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2364 /* OK, we actually have a frame. */
2365 cache
->frameless_p
= 0;
2369 /* For X32, also check for `movq %esp, %ebp'. */
2370 if (gdbarch_ptr_bit (gdbarch
) == 32)
2372 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2373 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2375 /* OK, we actually have a frame. */
2376 cache
->frameless_p
= 0;
2387 /* Work around false termination of prologue - GCC PR debug/48827.
2389 START_PC is the first instruction of a function, PC is its minimal already
2390 determined advanced address. Function returns PC if it has nothing to do.
2394 <-- here is 0 lines advance - the false prologue end marker.
2395 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2396 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2397 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2398 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2399 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2400 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2401 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2402 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2406 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2408 struct symtab_and_line start_pc_sal
, next_sal
;
2409 gdb_byte buf
[4 + 8 * 7];
2415 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2416 if (start_pc_sal
.symtab
== NULL
2417 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2418 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2419 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2422 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2423 if (next_sal
.line
!= start_pc_sal
.line
)
2426 /* START_PC can be from overlayed memory, ignored here. */
2427 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2431 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2438 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2440 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2441 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2442 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2446 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2448 /* 8-bit displacement. */
2452 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2454 /* 32-bit displacement. */
2462 if (offset
- 4 != buf
[3])
2465 return next_sal
.end
;
2468 /* Return PC of first real instruction. */
2471 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2473 struct amd64_frame_cache cache
;
2475 CORE_ADDR func_addr
;
2477 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2479 CORE_ADDR post_prologue_pc
2480 = skip_prologue_using_sal (gdbarch
, func_addr
);
2481 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2483 /* Clang always emits a line note before the prologue and another
2484 one after. We trust clang to emit usable line notes. */
2485 if (post_prologue_pc
2487 && COMPUNIT_PRODUCER (cust
) != NULL
2488 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2489 return std::max (start_pc
, post_prologue_pc
);
2492 amd64_init_frame_cache (&cache
);
2493 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2495 if (cache
.frameless_p
)
2498 return amd64_skip_xmm_prologue (pc
, start_pc
);
2502 /* Normal frames. */
2505 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2506 struct amd64_frame_cache
*cache
)
2508 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2509 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2513 cache
->pc
= get_frame_func (this_frame
);
2515 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2518 if (cache
->frameless_p
)
2520 /* We didn't find a valid frame. If we're at the start of a
2521 function, or somewhere half-way its prologue, the function's
2522 frame probably hasn't been fully setup yet. Try to
2523 reconstruct the base address for the stack frame by looking
2524 at the stack pointer. For truly "frameless" functions this
2527 if (cache
->saved_sp_reg
!= -1)
2529 /* Stack pointer has been saved. */
2530 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2531 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2533 /* We're halfway aligning the stack. */
2534 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2535 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2537 /* This will be added back below. */
2538 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2542 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2543 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2549 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2550 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2553 /* Now that we have the base address for the stack frame we can
2554 calculate the value of %rsp in the calling frame. */
2555 cache
->saved_sp
= cache
->base
+ 16;
2557 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2558 frame we find it at the same offset from the reconstructed base
2559 address. If we're halfway aligning the stack, %rip is handled
2560 differently (see above). */
2561 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2562 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2564 /* Adjust all the saved registers such that they contain addresses
2565 instead of offsets. */
2566 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2567 if (cache
->saved_regs
[i
] != -1)
2568 cache
->saved_regs
[i
] += cache
->base
;
2573 static struct amd64_frame_cache
*
2574 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2576 struct amd64_frame_cache
*cache
;
2579 return (struct amd64_frame_cache
*) *this_cache
;
2581 cache
= amd64_alloc_frame_cache ();
2582 *this_cache
= cache
;
2586 amd64_frame_cache_1 (this_frame
, cache
);
2588 catch (const gdb_exception_RETURN_MASK_ERROR
&ex
)
2590 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2591 throw_exception (ex
);
2597 static enum unwind_stop_reason
2598 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2601 struct amd64_frame_cache
*cache
=
2602 amd64_frame_cache (this_frame
, this_cache
);
2605 return UNWIND_UNAVAILABLE
;
2607 /* This marks the outermost frame. */
2608 if (cache
->base
== 0)
2609 return UNWIND_OUTERMOST
;
2611 return UNWIND_NO_REASON
;
2615 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2616 struct frame_id
*this_id
)
2618 struct amd64_frame_cache
*cache
=
2619 amd64_frame_cache (this_frame
, this_cache
);
2622 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2623 else if (cache
->base
== 0)
2625 /* This marks the outermost frame. */
2629 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2632 static struct value
*
2633 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2636 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2637 struct amd64_frame_cache
*cache
=
2638 amd64_frame_cache (this_frame
, this_cache
);
2640 gdb_assert (regnum
>= 0);
2642 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2643 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2645 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2646 return frame_unwind_got_memory (this_frame
, regnum
,
2647 cache
->saved_regs
[regnum
]);
2649 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2652 static const struct frame_unwind amd64_frame_unwind
=
2655 amd64_frame_unwind_stop_reason
,
2656 amd64_frame_this_id
,
2657 amd64_frame_prev_register
,
2659 default_frame_sniffer
2662 /* Generate a bytecode expression to get the value of the saved PC. */
2665 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2666 struct agent_expr
*ax
, struct axs_value
*value
,
2669 /* The following sequence assumes the traditional use of the base
2671 ax_reg (ax
, AMD64_RBP_REGNUM
);
2673 ax_simple (ax
, aop_add
);
2674 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2675 value
->kind
= axs_lvalue_memory
;
2679 /* Signal trampolines. */
2681 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2682 64-bit variants. This would require using identical frame caches
2683 on both platforms. */
2685 static struct amd64_frame_cache
*
2686 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2688 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2689 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2690 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2691 struct amd64_frame_cache
*cache
;
2697 return (struct amd64_frame_cache
*) *this_cache
;
2699 cache
= amd64_alloc_frame_cache ();
2703 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2704 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2706 addr
= tdep
->sigcontext_addr (this_frame
);
2707 gdb_assert (tdep
->sc_reg_offset
);
2708 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2709 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2710 if (tdep
->sc_reg_offset
[i
] != -1)
2711 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2715 catch (const gdb_exception_RETURN_MASK_ERROR
&ex
)
2717 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2718 throw_exception (ex
);
2721 *this_cache
= cache
;
2725 static enum unwind_stop_reason
2726 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2729 struct amd64_frame_cache
*cache
=
2730 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2733 return UNWIND_UNAVAILABLE
;
2735 return UNWIND_NO_REASON
;
2739 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2740 void **this_cache
, struct frame_id
*this_id
)
2742 struct amd64_frame_cache
*cache
=
2743 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2746 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2747 else if (cache
->base
== 0)
2749 /* This marks the outermost frame. */
2753 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2756 static struct value
*
2757 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2758 void **this_cache
, int regnum
)
2760 /* Make sure we've initialized the cache. */
2761 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2763 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2767 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2768 struct frame_info
*this_frame
,
2771 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2773 /* We shouldn't even bother if we don't have a sigcontext_addr
2775 if (tdep
->sigcontext_addr
== NULL
)
2778 if (tdep
->sigtramp_p
!= NULL
)
2780 if (tdep
->sigtramp_p (this_frame
))
2784 if (tdep
->sigtramp_start
!= 0)
2786 CORE_ADDR pc
= get_frame_pc (this_frame
);
2788 gdb_assert (tdep
->sigtramp_end
!= 0);
2789 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2796 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2799 amd64_sigtramp_frame_unwind_stop_reason
,
2800 amd64_sigtramp_frame_this_id
,
2801 amd64_sigtramp_frame_prev_register
,
2803 amd64_sigtramp_frame_sniffer
2808 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2810 struct amd64_frame_cache
*cache
=
2811 amd64_frame_cache (this_frame
, this_cache
);
2816 static const struct frame_base amd64_frame_base
=
2818 &amd64_frame_unwind
,
2819 amd64_frame_base_address
,
2820 amd64_frame_base_address
,
2821 amd64_frame_base_address
2824 /* Normal frames, but in a function epilogue. */
2826 /* Implement the stack_frame_destroyed_p gdbarch method.
2828 The epilogue is defined here as the 'ret' instruction, which will
2829 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2830 the function's stack frame. */
2833 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2836 struct compunit_symtab
*cust
;
2838 cust
= find_pc_compunit_symtab (pc
);
2839 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2842 if (target_read_memory (pc
, &insn
, 1))
2843 return 0; /* Can't read memory at pc. */
2845 if (insn
!= 0xc3) /* 'ret' instruction. */
2852 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2853 struct frame_info
*this_frame
,
2854 void **this_prologue_cache
)
2856 if (frame_relative_level (this_frame
) == 0)
2857 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2858 get_frame_pc (this_frame
));
2863 static struct amd64_frame_cache
*
2864 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2866 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2868 struct amd64_frame_cache
*cache
;
2872 return (struct amd64_frame_cache
*) *this_cache
;
2874 cache
= amd64_alloc_frame_cache ();
2875 *this_cache
= cache
;
2879 /* Cache base will be %esp plus cache->sp_offset (-8). */
2880 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2881 cache
->base
= extract_unsigned_integer (buf
, 8,
2882 byte_order
) + cache
->sp_offset
;
2884 /* Cache pc will be the frame func. */
2885 cache
->pc
= get_frame_pc (this_frame
);
2887 /* The saved %esp will be at cache->base plus 16. */
2888 cache
->saved_sp
= cache
->base
+ 16;
2890 /* The saved %eip will be at cache->base plus 8. */
2891 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2895 catch (const gdb_exception_RETURN_MASK_ERROR
&ex
)
2897 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2898 throw_exception (ex
);
2904 static enum unwind_stop_reason
2905 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2908 struct amd64_frame_cache
*cache
2909 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2912 return UNWIND_UNAVAILABLE
;
2914 return UNWIND_NO_REASON
;
2918 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2920 struct frame_id
*this_id
)
2922 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2926 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2928 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2931 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2934 amd64_epilogue_frame_unwind_stop_reason
,
2935 amd64_epilogue_frame_this_id
,
2936 amd64_frame_prev_register
,
2938 amd64_epilogue_frame_sniffer
2941 static struct frame_id
2942 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2946 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2948 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2951 /* 16 byte align the SP per frame requirements. */
2954 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2956 return sp
& -(CORE_ADDR
)16;
2960 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2961 in the floating-point register set REGSET to register cache
2962 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2965 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2966 int regnum
, const void *fpregs
, size_t len
)
2968 struct gdbarch
*gdbarch
= regcache
->arch ();
2969 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2971 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2972 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2975 /* Collect register REGNUM from the register cache REGCACHE and store
2976 it in the buffer specified by FPREGS and LEN as described by the
2977 floating-point register set REGSET. If REGNUM is -1, do this for
2978 all registers in REGSET. */
2981 amd64_collect_fpregset (const struct regset
*regset
,
2982 const struct regcache
*regcache
,
2983 int regnum
, void *fpregs
, size_t len
)
2985 struct gdbarch
*gdbarch
= regcache
->arch ();
2986 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2988 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2989 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2992 const struct regset amd64_fpregset
=
2994 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2998 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2999 %rdi. We expect its value to be a pointer to the jmp_buf structure
3000 from which we extract the address that we will land at. This
3001 address is copied into PC. This routine returns non-zero on
3005 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3009 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3010 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
3011 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3013 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3014 longjmp will land. */
3015 if (jb_pc_offset
== -1)
3018 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3019 jb_addr
= extract_typed_address
3020 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3021 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3024 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3029 static const int amd64_record_regmap
[] =
3031 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3032 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3033 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3034 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3035 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3036 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3039 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3042 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3044 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3050 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3051 const target_desc
*default_tdesc
)
3053 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3054 const struct target_desc
*tdesc
= info
.target_desc
;
3055 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3056 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3057 static const char *const stap_register_indirection_prefixes
[] = { "(",
3059 static const char *const stap_register_indirection_suffixes
[] = { ")",
3062 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3063 floating-point registers. */
3064 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3065 tdep
->fpregset
= &amd64_fpregset
;
3067 if (! tdesc_has_registers (tdesc
))
3068 tdesc
= default_tdesc
;
3069 tdep
->tdesc
= tdesc
;
3071 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3072 tdep
->register_names
= amd64_register_names
;
3074 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3076 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3077 tdep
->k_register_names
= amd64_k_names
;
3078 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3079 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3081 tdep
->num_zmm_regs
= 32;
3082 tdep
->num_xmm_avx512_regs
= 16;
3083 tdep
->num_ymm_avx512_regs
= 16;
3085 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3086 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3087 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3088 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3091 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3093 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3094 tdep
->num_ymm_regs
= 16;
3095 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3098 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3100 tdep
->mpx_register_names
= amd64_mpx_names
;
3101 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3102 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3105 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3107 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3110 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3112 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3113 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3114 tdep
->num_pkeys_regs
= 1;
3117 tdep
->num_byte_regs
= 20;
3118 tdep
->num_word_regs
= 16;
3119 tdep
->num_dword_regs
= 16;
3120 /* Avoid wiring in the MMX registers for now. */
3121 tdep
->num_mmx_regs
= 0;
3123 set_gdbarch_pseudo_register_read_value (gdbarch
,
3124 amd64_pseudo_register_read_value
);
3125 set_gdbarch_pseudo_register_write (gdbarch
,
3126 amd64_pseudo_register_write
);
3127 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3128 amd64_ax_pseudo_register_collect
);
3130 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3132 /* AMD64 has an FPU and 16 SSE registers. */
3133 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3134 tdep
->num_xmm_regs
= 16;
3136 /* This is what all the fuss is about. */
3137 set_gdbarch_long_bit (gdbarch
, 64);
3138 set_gdbarch_long_long_bit (gdbarch
, 64);
3139 set_gdbarch_ptr_bit (gdbarch
, 64);
3141 /* In contrast to the i386, on AMD64 a `long double' actually takes
3142 up 128 bits, even though it's still based on the i387 extended
3143 floating-point format which has only 80 significant bits. */
3144 set_gdbarch_long_double_bit (gdbarch
, 128);
3146 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3148 /* Register numbers of various important registers. */
3149 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3150 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3151 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3152 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3154 /* The "default" register numbering scheme for AMD64 is referred to
3155 as the "DWARF Register Number Mapping" in the System V psABI.
3156 The preferred debugging format for all known AMD64 targets is
3157 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3158 DWARF-1), but we provide the same mapping just in case. This
3159 mapping is also used for stabs, which GCC does support. */
3160 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3161 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3163 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3164 be in use on any of the supported AMD64 targets. */
3166 /* Call dummy code. */
3167 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3168 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3169 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3171 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3172 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3173 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3175 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3177 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3179 tdep
->record_regmap
= amd64_record_regmap
;
3181 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3183 /* Hook the function epilogue frame unwinder. This unwinder is
3184 appended to the list first, so that it supercedes the other
3185 unwinders in function epilogues. */
3186 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3188 /* Hook the prologue-based frame unwinders. */
3189 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3190 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3191 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3193 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3195 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3197 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3199 /* SystemTap variables and functions. */
3200 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3201 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3202 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3203 stap_register_indirection_prefixes
);
3204 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3205 stap_register_indirection_suffixes
);
3206 set_gdbarch_stap_is_single_operand (gdbarch
,
3207 i386_stap_is_single_operand
);
3208 set_gdbarch_stap_parse_special_token (gdbarch
,
3209 i386_stap_parse_special_token
);
3210 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3211 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3212 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3214 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3215 amd64_in_indirect_branch_thunk
);
3218 /* Initialize ARCH for x86-64, no osabi. */
3221 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3223 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3227 static struct type
*
3228 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3232 switch (regnum
- tdep
->eax_regnum
)
3234 case AMD64_RBP_REGNUM
: /* %ebp */
3235 case AMD64_RSP_REGNUM
: /* %esp */
3236 return builtin_type (gdbarch
)->builtin_data_ptr
;
3237 case AMD64_RIP_REGNUM
: /* %eip */
3238 return builtin_type (gdbarch
)->builtin_func_ptr
;
3241 return i386_pseudo_register_type (gdbarch
, regnum
);
3245 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3246 const target_desc
*default_tdesc
)
3248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3250 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3252 tdep
->num_dword_regs
= 17;
3253 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3255 set_gdbarch_long_bit (gdbarch
, 32);
3256 set_gdbarch_ptr_bit (gdbarch
, 32);
3259 /* Initialize ARCH for x64-32, no osabi. */
3262 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3264 amd64_x32_init_abi (info
, arch
,
3265 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3268 /* Return the target description for a specified XSAVE feature mask. */
3270 const struct target_desc
*
3271 amd64_target_description (uint64_t xcr0
, bool segments
)
3273 static target_desc
*amd64_tdescs \
3274 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3275 target_desc
**tdesc
;
3277 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3278 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3279 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3280 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3284 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3291 _initialize_amd64_tdep (void)
3293 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3294 amd64_none_init_abi
);
3295 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3296 amd64_x32_none_init_abi
);
3304 { "i386/amd64.xml", X86_XSTATE_SSE_MASK
},
3305 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK
},
3306 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK
},
3307 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK
},
3308 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK
},
3309 { "i386/amd64-avx-mpx-avx512-pku.xml",
3310 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
},
3313 for (auto &a
: xml_masks
)
3315 auto tdesc
= amd64_target_description (a
.mask
, true);
3317 selftests::record_xml_tdesc (a
.xml
, tdesc
);
3319 #endif /* GDB_SELF_TEST */
3323 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3324 sense that the instruction pointer and data pointer are simply
3325 64-bit offsets into the code segment and the data segment instead
3326 of a selector offset pair. The functions below store the upper 32
3327 bits of these pointers (instead of just the 16-bits of the segment
3330 /* Fill register REGNUM in REGCACHE with the appropriate
3331 floating-point or SSE register value from *FXSAVE. If REGNUM is
3332 -1, do this for all registers. This function masks off any of the
3333 reserved bits in *FXSAVE. */
3336 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3339 struct gdbarch
*gdbarch
= regcache
->arch ();
3340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3342 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3345 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3347 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3349 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3350 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3351 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3352 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3356 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3359 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3362 struct gdbarch
*gdbarch
= regcache
->arch ();
3363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3365 i387_supply_xsave (regcache
, regnum
, xsave
);
3368 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3370 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3373 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3375 /* If the FISEG and FOSEG registers have not been initialised yet
3376 (their CLEAR_BV bit is set) then their default values of zero will
3377 have already been setup by I387_SUPPLY_XSAVE. */
3378 if (!(clear_bv
& X86_XSTATE_X87
))
3380 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3381 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3382 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3383 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3388 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3389 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3390 all registers. This function doesn't touch any of the reserved
3394 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3397 struct gdbarch
*gdbarch
= regcache
->arch ();
3398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3399 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3401 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3403 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3405 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3406 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3407 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3408 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3412 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3415 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3416 void *xsave
, int gcore
)
3418 struct gdbarch
*gdbarch
= regcache
->arch ();
3419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3420 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3422 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3424 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3426 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3427 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3429 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3430 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),