1 /* Target dependent code for ARC architecture, for GDB.
3 Copyright 2005-2021 Free Software Foundation, Inc.
4 Contributed by Synopsys Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* GDB header files. */
23 #include "arch-utils.h"
26 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
33 #include "prologue-value.h"
34 #include "target-descriptions.h"
35 #include "trad-frame.h"
37 /* ARC header files. */
38 #include "opcode/arc.h"
39 #include "opcodes/arc-dis.h"
43 /* Standard headers. */
47 /* The frame unwind cache for ARC. */
49 struct arc_frame_cache
51 /* The stack pointer at the time this frame was created; i.e. the caller's
52 stack pointer when this function was called. It is used to identify this
56 /* Register that is a base for this frame - FP for normal frame, SP for
60 /* Offset from the previous SP to the current frame base. If GCC uses
61 `SUB SP,SP,offset` to allocate space for local variables, then it will be
62 done after setting up a frame pointer, but it still will be considered
63 part of prologue, therefore SP will be lesser than FP at the end of the
64 prologue analysis. In this case that would be an offset from old SP to a
65 new FP. But in case of non-FP frames, frame base is an SP and thus that
66 would be an offset from old SP to new SP. What is important is that this
67 is an offset from old SP to a known register, so it can be used to find
70 Using FP is preferable, when possible, because SP can change in function
71 body after prologue due to alloca, variadic arguments or other shenanigans.
72 If that is the case in the caller frame, then PREV_SP will point to SP at
73 the moment of function call, but it will be different from SP value at the
74 end of the caller prologue. As a result it will not be possible to
75 reconstruct caller's frame and go past it in the backtrace. Those things
76 are unlikely to happen to FP - FP value at the moment of function call (as
77 stored on stack in callee prologue) is also an FP value at the end of the
80 LONGEST frame_base_offset
;
82 /* Store addresses for registers saved in prologue. During prologue analysis
83 GDB stores offsets relatively to "old SP", then after old SP is evaluated,
84 offsets are replaced with absolute addresses. */
85 trad_frame_saved_reg
*saved_regs
;
88 /* Global debug flag. */
92 /* List of "maintenance print arc" commands. */
94 static struct cmd_list_element
*maintenance_print_arc_list
= NULL
;
96 /* A set of registers that we expect to find in a tdesc_feature. These
97 are used in ARC_TDESC_INIT when processing the target description. */
99 struct arc_register_feature
101 /* Information for a single register. */
104 /* The GDB register number for this register. */
107 /* List of names for this register. The first name in this list is the
108 preferred name, the name GDB will use when describing this register. */
109 std::vector
<const char *> names
;
111 /* When true, this register must be present in this feature set. */
115 /* The name for this feature. This is the name used to find this feature
116 within the target description. */
119 /* List of all the registers that we expect to encounter in this register
121 std::vector
<struct register_info
> registers
;
124 /* Obsolete feature names for backward compatibility. */
125 static const char *ARC_CORE_V1_OBSOLETE_FEATURE_NAME
126 = "org.gnu.gdb.arc.core.arcompact";
127 static const char *ARC_CORE_V2_OBSOLETE_FEATURE_NAME
128 = "org.gnu.gdb.arc.core.v2";
129 static const char *ARC_CORE_V2_REDUCED_OBSOLETE_FEATURE_NAME
130 = "org.gnu.gdb.arc.core-reduced.v2";
131 static const char *ARC_AUX_OBSOLETE_FEATURE_NAME
132 = "org.gnu.gdb.arc.aux-minimal";
133 /* Modern feature names. */
134 static const char *ARC_CORE_FEATURE_NAME
= "org.gnu.gdb.arc.core";
135 static const char *ARC_AUX_FEATURE_NAME
= "org.gnu.gdb.arc.aux";
137 /* ARCv1 (ARC600, ARC601, ARC700) general core registers feature set.
138 See also arc_update_acc_reg_names() for "accl/acch" names. */
140 static struct arc_register_feature arc_v1_core_reg_feature
=
142 ARC_CORE_FEATURE_NAME
,
144 { ARC_R0_REGNUM
+ 0, { "r0" }, true },
145 { ARC_R0_REGNUM
+ 1, { "r1" }, true },
146 { ARC_R0_REGNUM
+ 2, { "r2" }, true },
147 { ARC_R0_REGNUM
+ 3, { "r3" }, true },
148 { ARC_R0_REGNUM
+ 4, { "r4" }, false },
149 { ARC_R0_REGNUM
+ 5, { "r5" }, false },
150 { ARC_R0_REGNUM
+ 6, { "r6" }, false },
151 { ARC_R0_REGNUM
+ 7, { "r7" }, false },
152 { ARC_R0_REGNUM
+ 8, { "r8" }, false },
153 { ARC_R0_REGNUM
+ 9, { "r9" }, false },
154 { ARC_R0_REGNUM
+ 10, { "r10" }, true },
155 { ARC_R0_REGNUM
+ 11, { "r11" }, true },
156 { ARC_R0_REGNUM
+ 12, { "r12" }, true },
157 { ARC_R0_REGNUM
+ 13, { "r13" }, true },
158 { ARC_R0_REGNUM
+ 14, { "r14" }, true },
159 { ARC_R0_REGNUM
+ 15, { "r15" }, true },
160 { ARC_R0_REGNUM
+ 16, { "r16" }, false },
161 { ARC_R0_REGNUM
+ 17, { "r17" }, false },
162 { ARC_R0_REGNUM
+ 18, { "r18" }, false },
163 { ARC_R0_REGNUM
+ 19, { "r19" }, false },
164 { ARC_R0_REGNUM
+ 20, { "r20" }, false },
165 { ARC_R0_REGNUM
+ 21, { "r21" }, false },
166 { ARC_R0_REGNUM
+ 22, { "r22" }, false },
167 { ARC_R0_REGNUM
+ 23, { "r23" }, false },
168 { ARC_R0_REGNUM
+ 24, { "r24" }, false },
169 { ARC_R0_REGNUM
+ 25, { "r25" }, false },
170 { ARC_R0_REGNUM
+ 26, { "gp" }, true },
171 { ARC_R0_REGNUM
+ 27, { "fp" }, true },
172 { ARC_R0_REGNUM
+ 28, { "sp" }, true },
173 { ARC_R0_REGNUM
+ 29, { "ilink1" }, false },
174 { ARC_R0_REGNUM
+ 30, { "ilink2" }, false },
175 { ARC_R0_REGNUM
+ 31, { "blink" }, true },
176 { ARC_R0_REGNUM
+ 32, { "r32" }, false },
177 { ARC_R0_REGNUM
+ 33, { "r33" }, false },
178 { ARC_R0_REGNUM
+ 34, { "r34" }, false },
179 { ARC_R0_REGNUM
+ 35, { "r35" }, false },
180 { ARC_R0_REGNUM
+ 36, { "r36" }, false },
181 { ARC_R0_REGNUM
+ 37, { "r37" }, false },
182 { ARC_R0_REGNUM
+ 38, { "r38" }, false },
183 { ARC_R0_REGNUM
+ 39, { "r39" }, false },
184 { ARC_R0_REGNUM
+ 40, { "r40" }, false },
185 { ARC_R0_REGNUM
+ 41, { "r41" }, false },
186 { ARC_R0_REGNUM
+ 42, { "r42" }, false },
187 { ARC_R0_REGNUM
+ 43, { "r43" }, false },
188 { ARC_R0_REGNUM
+ 44, { "r44" }, false },
189 { ARC_R0_REGNUM
+ 45, { "r45" }, false },
190 { ARC_R0_REGNUM
+ 46, { "r46" }, false },
191 { ARC_R0_REGNUM
+ 47, { "r47" }, false },
192 { ARC_R0_REGNUM
+ 48, { "r48" }, false },
193 { ARC_R0_REGNUM
+ 49, { "r49" }, false },
194 { ARC_R0_REGNUM
+ 50, { "r50" }, false },
195 { ARC_R0_REGNUM
+ 51, { "r51" }, false },
196 { ARC_R0_REGNUM
+ 52, { "r52" }, false },
197 { ARC_R0_REGNUM
+ 53, { "r53" }, false },
198 { ARC_R0_REGNUM
+ 54, { "r54" }, false },
199 { ARC_R0_REGNUM
+ 55, { "r55" }, false },
200 { ARC_R0_REGNUM
+ 56, { "r56" }, false },
201 { ARC_R0_REGNUM
+ 57, { "r57" }, false },
202 { ARC_R0_REGNUM
+ 58, { "r58", "accl" }, false },
203 { ARC_R0_REGNUM
+ 59, { "r59", "acch" }, false },
204 { ARC_R0_REGNUM
+ 60, { "lp_count" }, false },
205 { ARC_R0_REGNUM
+ 61, { "reserved" }, false },
206 { ARC_R0_REGNUM
+ 62, { "limm" }, false },
207 { ARC_R0_REGNUM
+ 63, { "pcl" }, true }
211 /* ARCv2 (ARCHS) general core registers feature set. See also
212 arc_update_acc_reg_names() for "accl/acch" names. */
214 static struct arc_register_feature arc_v2_core_reg_feature
=
216 ARC_CORE_FEATURE_NAME
,
218 { ARC_R0_REGNUM
+ 0, { "r0" }, true },
219 { ARC_R0_REGNUM
+ 1, { "r1" }, true },
220 { ARC_R0_REGNUM
+ 2, { "r2" }, true },
221 { ARC_R0_REGNUM
+ 3, { "r3" }, true },
222 { ARC_R0_REGNUM
+ 4, { "r4" }, false },
223 { ARC_R0_REGNUM
+ 5, { "r5" }, false },
224 { ARC_R0_REGNUM
+ 6, { "r6" }, false },
225 { ARC_R0_REGNUM
+ 7, { "r7" }, false },
226 { ARC_R0_REGNUM
+ 8, { "r8" }, false },
227 { ARC_R0_REGNUM
+ 9, { "r9" }, false },
228 { ARC_R0_REGNUM
+ 10, { "r10" }, true },
229 { ARC_R0_REGNUM
+ 11, { "r11" }, true },
230 { ARC_R0_REGNUM
+ 12, { "r12" }, true },
231 { ARC_R0_REGNUM
+ 13, { "r13" }, true },
232 { ARC_R0_REGNUM
+ 14, { "r14" }, true },
233 { ARC_R0_REGNUM
+ 15, { "r15" }, true },
234 { ARC_R0_REGNUM
+ 16, { "r16" }, false },
235 { ARC_R0_REGNUM
+ 17, { "r17" }, false },
236 { ARC_R0_REGNUM
+ 18, { "r18" }, false },
237 { ARC_R0_REGNUM
+ 19, { "r19" }, false },
238 { ARC_R0_REGNUM
+ 20, { "r20" }, false },
239 { ARC_R0_REGNUM
+ 21, { "r21" }, false },
240 { ARC_R0_REGNUM
+ 22, { "r22" }, false },
241 { ARC_R0_REGNUM
+ 23, { "r23" }, false },
242 { ARC_R0_REGNUM
+ 24, { "r24" }, false },
243 { ARC_R0_REGNUM
+ 25, { "r25" }, false },
244 { ARC_R0_REGNUM
+ 26, { "gp" }, true },
245 { ARC_R0_REGNUM
+ 27, { "fp" }, true },
246 { ARC_R0_REGNUM
+ 28, { "sp" }, true },
247 { ARC_R0_REGNUM
+ 29, { "ilink" }, false },
248 { ARC_R0_REGNUM
+ 30, { "r30" }, true },
249 { ARC_R0_REGNUM
+ 31, { "blink" }, true },
250 { ARC_R0_REGNUM
+ 32, { "r32" }, false },
251 { ARC_R0_REGNUM
+ 33, { "r33" }, false },
252 { ARC_R0_REGNUM
+ 34, { "r34" }, false },
253 { ARC_R0_REGNUM
+ 35, { "r35" }, false },
254 { ARC_R0_REGNUM
+ 36, { "r36" }, false },
255 { ARC_R0_REGNUM
+ 37, { "r37" }, false },
256 { ARC_R0_REGNUM
+ 38, { "r38" }, false },
257 { ARC_R0_REGNUM
+ 39, { "r39" }, false },
258 { ARC_R0_REGNUM
+ 40, { "r40" }, false },
259 { ARC_R0_REGNUM
+ 41, { "r41" }, false },
260 { ARC_R0_REGNUM
+ 42, { "r42" }, false },
261 { ARC_R0_REGNUM
+ 43, { "r43" }, false },
262 { ARC_R0_REGNUM
+ 44, { "r44" }, false },
263 { ARC_R0_REGNUM
+ 45, { "r45" }, false },
264 { ARC_R0_REGNUM
+ 46, { "r46" }, false },
265 { ARC_R0_REGNUM
+ 47, { "r47" }, false },
266 { ARC_R0_REGNUM
+ 48, { "r48" }, false },
267 { ARC_R0_REGNUM
+ 49, { "r49" }, false },
268 { ARC_R0_REGNUM
+ 50, { "r50" }, false },
269 { ARC_R0_REGNUM
+ 51, { "r51" }, false },
270 { ARC_R0_REGNUM
+ 52, { "r52" }, false },
271 { ARC_R0_REGNUM
+ 53, { "r53" }, false },
272 { ARC_R0_REGNUM
+ 54, { "r54" }, false },
273 { ARC_R0_REGNUM
+ 55, { "r55" }, false },
274 { ARC_R0_REGNUM
+ 56, { "r56" }, false },
275 { ARC_R0_REGNUM
+ 57, { "r57" }, false },
276 { ARC_R0_REGNUM
+ 58, { "r58", "accl" }, false },
277 { ARC_R0_REGNUM
+ 59, { "r59", "acch" }, false },
278 { ARC_R0_REGNUM
+ 60, { "lp_count" }, false },
279 { ARC_R0_REGNUM
+ 61, { "reserved" }, false },
280 { ARC_R0_REGNUM
+ 62, { "limm" }, false },
281 { ARC_R0_REGNUM
+ 63, { "pcl" }, true }
285 /* The common auxiliary registers feature set. The REGNUM field
286 must match the ARC_REGNUM enum in arc-tdep.h. */
288 static const struct arc_register_feature arc_common_aux_reg_feature
=
290 ARC_AUX_FEATURE_NAME
,
292 { ARC_FIRST_AUX_REGNUM
+ 0, { "pc" }, true },
293 { ARC_FIRST_AUX_REGNUM
+ 1, { "status32" }, true },
294 { ARC_FIRST_AUX_REGNUM
+ 2, { "lp_start" }, false },
295 { ARC_FIRST_AUX_REGNUM
+ 3, { "lp_end" }, false },
296 { ARC_FIRST_AUX_REGNUM
+ 4, { "bta" }, false }
300 static char *arc_disassembler_options
= NULL
;
302 /* Functions are sorted in the order as they are used in the
303 _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static
304 functions are defined before the first invocation. */
306 /* Returns an unsigned value of OPERAND_NUM in instruction INSN.
307 For relative branch instructions returned value is an offset, not an actual
311 arc_insn_get_operand_value (const struct arc_instruction
&insn
,
312 unsigned int operand_num
)
314 switch (insn
.operands
[operand_num
].kind
)
316 case ARC_OPERAND_KIND_LIMM
:
317 gdb_assert (insn
.limm_p
);
318 return insn
.limm_value
;
319 case ARC_OPERAND_KIND_SHIMM
:
320 return insn
.operands
[operand_num
].value
;
322 /* Value in instruction is a register number. */
323 struct regcache
*regcache
= get_current_regcache ();
325 regcache_cooked_read_unsigned (regcache
,
326 insn
.operands
[operand_num
].value
,
332 /* Like arc_insn_get_operand_value, but returns a signed value. */
335 arc_insn_get_operand_value_signed (const struct arc_instruction
&insn
,
336 unsigned int operand_num
)
338 switch (insn
.operands
[operand_num
].kind
)
340 case ARC_OPERAND_KIND_LIMM
:
341 gdb_assert (insn
.limm_p
);
342 /* Convert unsigned raw value to signed one. This assumes 2's
343 complement arithmetic, but so is the LONG_MIN value from generic
344 defs.h and that assumption is true for ARC. */
345 gdb_static_assert (sizeof (insn
.limm_value
) == sizeof (int));
346 return (((LONGEST
) insn
.limm_value
) ^ INT_MIN
) - INT_MIN
;
347 case ARC_OPERAND_KIND_SHIMM
:
348 /* Sign conversion has been done by binutils. */
349 return insn
.operands
[operand_num
].value
;
351 /* Value in instruction is a register number. */
352 struct regcache
*regcache
= get_current_regcache ();
354 regcache_cooked_read_signed (regcache
,
355 insn
.operands
[operand_num
].value
,
361 /* Get register with base address of memory operation. */
364 arc_insn_get_memory_base_reg (const struct arc_instruction
&insn
)
366 /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */
367 if (insn
.insn_class
== PUSH
|| insn
.insn_class
== POP
)
368 return ARC_SP_REGNUM
;
370 gdb_assert (insn
.insn_class
== LOAD
|| insn
.insn_class
== STORE
);
372 /* Other instructions all have at least two operands: operand 0 is data,
373 operand 1 is address. Operand 2 is offset from address. However, see
374 comment to arc_instruction.operands - in some cases, third operand may be
375 missing, namely if it is 0. */
376 gdb_assert (insn
.operands_count
>= 2);
377 return insn
.operands
[1].value
;
380 /* Get offset of a memory operation INSN. */
383 arc_insn_get_memory_offset (const struct arc_instruction
&insn
)
385 /* POP_S and PUSH_S have offset as an implicit argument in a
387 if (insn
.insn_class
== POP
)
389 else if (insn
.insn_class
== PUSH
)
392 gdb_assert (insn
.insn_class
== LOAD
|| insn
.insn_class
== STORE
);
394 /* Other instructions all have at least two operands: operand 0 is data,
395 operand 1 is address. Operand 2 is offset from address. However, see
396 comment to arc_instruction.operands - in some cases, third operand may be
397 missing, namely if it is 0. */
398 if (insn
.operands_count
< 3)
401 CORE_ADDR value
= arc_insn_get_operand_value (insn
, 2);
402 /* Handle scaling. */
403 if (insn
.writeback_mode
== ARC_WRITEBACK_AS
)
405 /* Byte data size is not valid for AS. Halfword means shift by 1 bit.
406 Word and double word means shift by 2 bits. */
407 gdb_assert (insn
.data_size_mode
!= ARC_SCALING_B
);
408 if (insn
.data_size_mode
== ARC_SCALING_H
)
417 arc_insn_get_branch_target (const struct arc_instruction
&insn
)
419 gdb_assert (insn
.is_control_flow
);
421 /* BI [c]: PC = nextPC + (c << 2). */
422 if (insn
.insn_class
== BI
)
424 ULONGEST reg_value
= arc_insn_get_operand_value (insn
, 0);
425 return arc_insn_get_linear_next_pc (insn
) + (reg_value
<< 2);
427 /* BIH [c]: PC = nextPC + (c << 1). */
428 else if (insn
.insn_class
== BIH
)
430 ULONGEST reg_value
= arc_insn_get_operand_value (insn
, 0);
431 return arc_insn_get_linear_next_pc (insn
) + (reg_value
<< 1);
434 /* JLI and EI depend on optional AUX registers. Not supported right now. */
435 else if (insn
.insn_class
== JLI
)
437 fprintf_unfiltered (gdb_stderr
,
438 "JLI_S instruction is not supported by the GDB.");
441 else if (insn
.insn_class
== EI
)
443 fprintf_unfiltered (gdb_stderr
,
444 "EI_S instruction is not supported by the GDB.");
447 /* LEAVE_S: PC = BLINK. */
448 else if (insn
.insn_class
== LEAVE
)
450 struct regcache
*regcache
= get_current_regcache ();
452 regcache_cooked_read_unsigned (regcache
, ARC_BLINK_REGNUM
, &value
);
455 /* BBIT0/1, BRcc: PC = currentPC + operand. */
456 else if (insn
.insn_class
== BBIT0
|| insn
.insn_class
== BBIT1
457 || insn
.insn_class
== BRCC
)
459 /* Most instructions has branch target as their sole argument. However
460 conditional brcc/bbit has it as a third operand. */
461 CORE_ADDR pcrel_addr
= arc_insn_get_operand_value (insn
, 2);
463 /* Offset is relative to the 4-byte aligned address of the current
464 instruction, hence last two bits should be truncated. */
465 return pcrel_addr
+ align_down (insn
.address
, 4);
467 /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */
468 else if (insn
.insn_class
== BRANCH
|| insn
.insn_class
== LOOP
)
470 CORE_ADDR pcrel_addr
= arc_insn_get_operand_value (insn
, 0);
472 /* Offset is relative to the 4-byte aligned address of the current
473 instruction, hence last two bits should be truncated. */
474 return pcrel_addr
+ align_down (insn
.address
, 4);
476 /* J, Jcc, JL, JLcc: PC = operand. */
477 else if (insn
.insn_class
== JUMP
)
479 /* All jumps are single-operand. */
480 return arc_insn_get_operand_value (insn
, 0);
483 /* This is some new and unknown instruction. */
484 gdb_assert_not_reached ("Unknown branch instruction.");
487 /* Dump INSN into gdb_stdlog. */
490 arc_insn_dump (const struct arc_instruction
&insn
)
492 struct gdbarch
*gdbarch
= target_gdbarch ();
494 arc_print ("Dumping arc_instruction at %s\n",
495 paddress (gdbarch
, insn
.address
));
496 arc_print ("\tlength = %u\n", insn
.length
);
500 arc_print ("\tThis is not a valid ARC instruction.\n");
504 arc_print ("\tlength_with_limm = %u\n", insn
.length
+ (insn
.limm_p
? 4 : 0));
505 arc_print ("\tcc = 0x%x\n", insn
.condition_code
);
506 arc_print ("\tinsn_class = %u\n", insn
.insn_class
);
507 arc_print ("\tis_control_flow = %i\n", insn
.is_control_flow
);
508 arc_print ("\thas_delay_slot = %i\n", insn
.has_delay_slot
);
510 CORE_ADDR next_pc
= arc_insn_get_linear_next_pc (insn
);
511 arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch
, next_pc
));
513 if (insn
.is_control_flow
)
515 CORE_ADDR t
= arc_insn_get_branch_target (insn
);
516 arc_print ("\tbranch_target = %s\n", paddress (gdbarch
, t
));
519 arc_print ("\tlimm_p = %i\n", insn
.limm_p
);
521 arc_print ("\tlimm_value = 0x%08x\n", insn
.limm_value
);
523 if (insn
.insn_class
== STORE
|| insn
.insn_class
== LOAD
524 || insn
.insn_class
== PUSH
|| insn
.insn_class
== POP
)
526 arc_print ("\twriteback_mode = %u\n", insn
.writeback_mode
);
527 arc_print ("\tdata_size_mode = %u\n", insn
.data_size_mode
);
528 arc_print ("\tmemory_base_register = %s\n",
529 gdbarch_register_name (gdbarch
,
530 arc_insn_get_memory_base_reg (insn
)));
531 /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a
532 LONGEST for a nicer representation. */
533 arc_print ("\taddr_offset = %s\n",
534 plongest (arc_insn_get_memory_offset (insn
)));
537 arc_print ("\toperands_count = %u\n", insn
.operands_count
);
538 for (unsigned int i
= 0; i
< insn
.operands_count
; ++i
)
540 int is_reg
= (insn
.operands
[i
].kind
== ARC_OPERAND_KIND_REG
);
542 arc_print ("\toperand[%u] = {\n", i
);
543 arc_print ("\t\tis_reg = %i\n", is_reg
);
545 arc_print ("\t\tregister = %s\n",
546 gdbarch_register_name (gdbarch
, insn
.operands
[i
].value
));
547 /* Don't know if this value is signed or not, so print both
548 representations. This tends to look quite ugly, especially for big
550 arc_print ("\t\tunsigned value = %s\n",
551 pulongest (arc_insn_get_operand_value (insn
, i
)));
552 arc_print ("\t\tsigned value = %s\n",
553 plongest (arc_insn_get_operand_value_signed (insn
, i
)));
559 arc_insn_get_linear_next_pc (const struct arc_instruction
&insn
)
561 /* In ARC long immediate is always 4 bytes. */
562 return (insn
.address
+ insn
.length
+ (insn
.limm_p
? 4 : 0));
565 /* Implement the "write_pc" gdbarch method.
567 In ARC PC register is a normal register so in most cases setting PC value
568 is a straightforward process: debugger just writes PC value. However it
569 gets trickier in case when current instruction is an instruction in delay
570 slot. In this case CPU will execute instruction at current PC value, then
571 will set PC to the current value of BTA register; also current instruction
572 cannot be branch/jump and some of the other instruction types. Thus if
573 debugger would try to just change PC value in this case, this instruction
574 will get executed, but then core will "jump" to the original branch target.
576 Whether current instruction is a delay-slot instruction or not is indicated
577 by DE bit in STATUS32 register indicates if current instruction is a delay
578 slot instruction. This bit is writable by debug host, which allows debug
579 host to prevent core from jumping after the delay slot instruction. It
580 also works in another direction: setting this bit will make core to treat
581 any current instructions as a delay slot instruction and to set PC to the
582 current value of BTA register.
584 To workaround issues with changing PC register while in delay slot
585 instruction, debugger should check for the STATUS32.DE bit and reset it if
586 it is set. No other change is required in this function. Most common
587 case, where this function might be required is calling inferior functions
588 from debugger. Generic GDB logic handles this pretty well: current values
589 of registers are stored, value of PC is changed (that is the job of this
590 function), and after inferior function is executed, GDB restores all
591 registers, include BTA and STATUS32, which also means that core is returned
592 to its original state of being halted on delay slot instructions.
594 This method is useless for ARC 600, because it doesn't have externally
595 exposed BTA register. In the case of ARC 600 it is impossible to restore
596 core to its state in all occasions thus core should never be halted (from
597 the perspective of debugger host) in the delay slot. */
600 arc_write_pc (struct regcache
*regcache
, CORE_ADDR new_pc
)
602 struct gdbarch
*gdbarch
= regcache
->arch ();
604 arc_debug_printf ("Writing PC, new value=%s",
605 paddress (gdbarch
, new_pc
));
607 regcache_cooked_write_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
),
611 regcache_cooked_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
),
614 if ((status32
& ARC_STATUS32_DE_MASK
) != 0)
616 arc_debug_printf ("Changing PC while in delay slot. Will "
617 "reset STATUS32.DE bit to zero. Value of STATUS32 "
619 phex (status32
, ARC_REGISTER_SIZE
));
621 /* Reset bit and write to the cache. */
623 regcache_cooked_write_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
),
628 /* Implement the "virtual_frame_pointer" gdbarch method.
630 According to ABI the FP (r27) is used to point to the middle of the current
631 stack frame, just below the saved FP and before local variables, register
632 spill area and outgoing args. However for optimization levels above O2 and
633 in any case in leaf functions, the frame pointer is usually not set at all.
634 The exception being when handling nested functions.
636 We use this function to return a "virtual" frame pointer, marking the start
637 of the current stack frame as a register-offset pair. If the FP is not
638 being used, then it should return SP, with an offset of the frame size.
640 The current implementation doesn't actually know the frame size, nor
641 whether the FP is actually being used, so for now we just return SP and an
642 offset of zero. This is no worse than other architectures, but is needed
643 to avoid assertion failures.
645 TODO: Can we determine the frame size to get a correct offset?
647 PC is a program counter where we need the virtual FP. REG_PTR is the base
648 register used for the virtual FP. OFFSET_PTR is the offset used for the
652 arc_virtual_frame_pointer (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
653 int *reg_ptr
, LONGEST
*offset_ptr
)
655 *reg_ptr
= gdbarch_sp_regnum (gdbarch
);
659 /* Implement the "push_dummy_call" gdbarch method.
663 This shows the layout of the stack frame for the general case of a
664 function call; a given function might not have a variable number of
665 arguments or local variables, or might not save any registers, so it would
666 not have the corresponding frame areas. Additionally, a leaf function
667 (i.e. one which calls no other functions) does not need to save the
668 contents of the BLINK register (which holds its return address), and a
669 function might not have a frame pointer.
671 The stack grows downward, so SP points below FP in memory; SP always
672 points to the last used word on the stack, not the first one.
675 | arg word N | | caller's
679 old SP ---> +-----------------------+ --+
683 | including fp, blink | |
685 new FP ---> +-----------------------+ | frame
695 new SP ---> +-----------------------+ --+
704 The list of arguments to be passed to a function is considered to be a
705 sequence of _N_ words (as though all the parameters were stored in order in
706 memory with each parameter occupying an integral number of words). Words
707 1..8 are passed in registers 0..7; if the function has more than 8 words of
708 arguments then words 9..@em N are passed on the stack in the caller's frame.
710 If the function has a variable number of arguments, e.g. it has a form such
711 as `function (p1, p2, ...);' and _P_ words are required to hold the values
712 of the named parameters (which are passed in registers 0..@em P -1), then
713 the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the
714 top of the frame so that the anonymous parameter words occupy a continuous
717 Any arguments are already in target byte order. We just need to store
720 BP_ADDR is the return address where breakpoint must be placed. NARGS is
721 the number of arguments to the function. ARGS is the arguments values (in
722 target byte order). SP is the Current value of SP register. STRUCT_RETURN
723 is TRUE if structures are returned by the function. STRUCT_ADDR is the
724 hidden address for returning a struct. Returns SP of a new frame. */
727 arc_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
728 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
729 struct value
**args
, CORE_ADDR sp
,
730 function_call_return_method return_method
,
731 CORE_ADDR struct_addr
)
733 arc_debug_printf ("nargs = %d", nargs
);
735 int arg_reg
= ARC_FIRST_ARG_REGNUM
;
737 /* Push the return address. */
738 regcache_cooked_write_unsigned (regcache
, ARC_BLINK_REGNUM
, bp_addr
);
740 /* Are we returning a value using a structure return instead of a normal
741 value return? If so, struct_addr is the address of the reserved space for
742 the return structure to be written on the stack, and that address is
743 passed to that function as a hidden first argument. */
744 if (return_method
== return_method_struct
)
746 /* Pass the return address in the first argument register. */
747 regcache_cooked_write_unsigned (regcache
, arg_reg
, struct_addr
);
749 arc_debug_printf ("struct return address %s passed in R%d",
750 print_core_address (gdbarch
, struct_addr
), arg_reg
);
757 unsigned int total_space
= 0;
759 /* How much space do the arguments occupy in total? Must round each
760 argument's size up to an integral number of words. */
761 for (int i
= 0; i
< nargs
; i
++)
763 unsigned int len
= TYPE_LENGTH (value_type (args
[i
]));
764 unsigned int space
= align_up (len
, 4);
766 total_space
+= space
;
768 arc_debug_printf ("arg %d: %u bytes -> %u", i
, len
, space
);
771 /* Allocate a buffer to hold a memory image of the arguments. */
772 gdb_byte
*memory_image
= XCNEWVEC (gdb_byte
, total_space
);
774 /* Now copy all of the arguments into the buffer, correctly aligned. */
775 gdb_byte
*data
= memory_image
;
776 for (int i
= 0; i
< nargs
; i
++)
778 unsigned int len
= TYPE_LENGTH (value_type (args
[i
]));
779 unsigned int space
= align_up (len
, 4);
781 memcpy (data
, value_contents (args
[i
]), (size_t) len
);
782 arc_debug_printf ("copying arg %d, val 0x%08x, len %d to mem",
783 i
, *((int *) value_contents (args
[i
])), len
);
788 /* Now load as much as possible of the memory image into registers. */
790 while (arg_reg
<= ARC_LAST_ARG_REGNUM
)
792 arc_debug_printf ("passing 0x%02x%02x%02x%02x in register R%d",
793 data
[0], data
[1], data
[2], data
[3], arg_reg
);
795 /* Note we don't use write_unsigned here, since that would convert
796 the byte order, but we are already in the correct byte order. */
797 regcache
->cooked_write (arg_reg
, data
);
799 data
+= ARC_REGISTER_SIZE
;
800 total_space
-= ARC_REGISTER_SIZE
;
802 /* All the data is now in registers. */
803 if (total_space
== 0)
809 /* If there is any data left, push it onto the stack (in a single write
813 arc_debug_printf ("passing %d bytes on stack\n", total_space
);
816 write_memory (sp
, data
, (int) total_space
);
819 xfree (memory_image
);
822 /* Finally, update the SP register. */
823 regcache_cooked_write_unsigned (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
828 /* Implement the "push_dummy_code" gdbarch method.
830 We don't actually push any code. We just identify where a breakpoint can
831 be inserted to which we are can return and the resume address where we
834 ARC does not necessarily have an executable stack, so we can't put the
835 return breakpoint there. Instead we put it at the entry point of the
836 function. This means the SP is unchanged.
838 SP is a current stack pointer FUNADDR is an address of the function to be
839 called. ARGS is arguments to pass. NARGS is a number of args to pass.
840 VALUE_TYPE is a type of value returned. REAL_PC is a resume address when
841 the function is called. BP_ADDR is an address where breakpoint should be
842 set. Returns the updated stack pointer. */
845 arc_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
846 struct value
**args
, int nargs
, struct type
*value_type
,
847 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
848 struct regcache
*regcache
)
851 *bp_addr
= entry_point_address ();
855 /* Implement the "cannot_fetch_register" gdbarch method. */
858 arc_cannot_fetch_register (struct gdbarch
*gdbarch
, int regnum
)
860 /* Assume that register is readable if it is unknown. LIMM and RESERVED are
861 not real registers, but specific register numbers. They are available as
862 regnums to align architectural register numbers with GDB internal regnums,
863 but they shouldn't appear in target descriptions generated by
867 case ARC_RESERVED_REGNUM
:
868 case ARC_LIMM_REGNUM
:
875 /* Implement the "cannot_store_register" gdbarch method. */
878 arc_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
880 /* Assume that register is writable if it is unknown. See comment in
881 arc_cannot_fetch_register about LIMM and RESERVED. */
884 case ARC_RESERVED_REGNUM
:
885 case ARC_LIMM_REGNUM
:
893 /* Get the return value of a function from the registers/memory used to
894 return it, according to the convention used by the ABI - 4-bytes values are
895 in the R0, while 8-byte values are in the R0-R1.
897 TODO: This implementation ignores the case of "complex double", where
898 according to ABI, value is returned in the R0-R3 registers.
900 TYPE is a returned value's type. VALBUF is a buffer for the returned
904 arc_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
905 struct regcache
*regcache
, gdb_byte
*valbuf
)
907 unsigned int len
= TYPE_LENGTH (type
);
909 arc_debug_printf ("called");
911 if (len
<= ARC_REGISTER_SIZE
)
915 /* Get the return value from one register. */
916 regcache_cooked_read_unsigned (regcache
, ARC_R0_REGNUM
, &val
);
917 store_unsigned_integer (valbuf
, (int) len
,
918 gdbarch_byte_order (gdbarch
), val
);
920 arc_debug_printf ("returning 0x%s", phex (val
, ARC_REGISTER_SIZE
));
922 else if (len
<= ARC_REGISTER_SIZE
* 2)
926 /* Get the return value from two registers. */
927 regcache_cooked_read_unsigned (regcache
, ARC_R0_REGNUM
, &low
);
928 regcache_cooked_read_unsigned (regcache
, ARC_R1_REGNUM
, &high
);
930 store_unsigned_integer (valbuf
, ARC_REGISTER_SIZE
,
931 gdbarch_byte_order (gdbarch
), low
);
932 store_unsigned_integer (valbuf
+ ARC_REGISTER_SIZE
,
933 (int) len
- ARC_REGISTER_SIZE
,
934 gdbarch_byte_order (gdbarch
), high
);
936 arc_debug_printf ("returning 0x%s%s",
937 phex (high
, ARC_REGISTER_SIZE
),
938 phex (low
, ARC_REGISTER_SIZE
));
941 error (_("arc: extract_return_value: type length %u too large"), len
);
945 /* Store the return value of a function into the registers/memory used to
946 return it, according to the convention used by the ABI.
948 TODO: This implementation ignores the case of "complex double", where
949 according to ABI, value is returned in the R0-R3 registers.
951 TYPE is a returned value's type. VALBUF is a buffer with the value to
955 arc_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
956 struct regcache
*regcache
, const gdb_byte
*valbuf
)
958 unsigned int len
= TYPE_LENGTH (type
);
960 arc_debug_printf ("called");
962 if (len
<= ARC_REGISTER_SIZE
)
966 /* Put the return value into one register. */
967 val
= extract_unsigned_integer (valbuf
, (int) len
,
968 gdbarch_byte_order (gdbarch
));
969 regcache_cooked_write_unsigned (regcache
, ARC_R0_REGNUM
, val
);
971 arc_debug_printf ("storing 0x%s", phex (val
, ARC_REGISTER_SIZE
));
973 else if (len
<= ARC_REGISTER_SIZE
* 2)
977 /* Put the return value into two registers. */
978 low
= extract_unsigned_integer (valbuf
, ARC_REGISTER_SIZE
,
979 gdbarch_byte_order (gdbarch
));
980 high
= extract_unsigned_integer (valbuf
+ ARC_REGISTER_SIZE
,
981 (int) len
- ARC_REGISTER_SIZE
,
982 gdbarch_byte_order (gdbarch
));
984 regcache_cooked_write_unsigned (regcache
, ARC_R0_REGNUM
, low
);
985 regcache_cooked_write_unsigned (regcache
, ARC_R1_REGNUM
, high
);
987 arc_debug_printf ("storing 0x%s%s",
988 phex (high
, ARC_REGISTER_SIZE
),
989 phex (low
, ARC_REGISTER_SIZE
));
992 error (_("arc_store_return_value: type length too large."));
995 /* Implement the "get_longjmp_target" gdbarch method. */
998 arc_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1000 arc_debug_printf ("called");
1002 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1003 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1004 int pc_offset
= tdep
->jb_pc
* ARC_REGISTER_SIZE
;
1005 gdb_byte buf
[ARC_REGISTER_SIZE
];
1006 CORE_ADDR jb_addr
= get_frame_register_unsigned (frame
, ARC_FIRST_ARG_REGNUM
);
1008 if (target_read_memory (jb_addr
+ pc_offset
, buf
, ARC_REGISTER_SIZE
))
1009 return 0; /* Failed to read from memory. */
1011 *pc
= extract_unsigned_integer (buf
, ARC_REGISTER_SIZE
,
1012 gdbarch_byte_order (gdbarch
));
1016 /* Implement the "return_value" gdbarch method. */
1018 static enum return_value_convention
1019 arc_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1020 struct type
*valtype
, struct regcache
*regcache
,
1021 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1023 /* If the return type is a struct, or a union, or would occupy more than two
1024 registers, the ABI uses the "struct return convention": the calling
1025 function passes a hidden first parameter to the callee (in R0). That
1026 parameter is the address at which the value being returned should be
1027 stored. Otherwise, the result is returned in registers. */
1028 int is_struct_return
= (valtype
->code () == TYPE_CODE_STRUCT
1029 || valtype
->code () == TYPE_CODE_UNION
1030 || TYPE_LENGTH (valtype
) > 2 * ARC_REGISTER_SIZE
);
1032 arc_debug_printf ("readbuf = %s, writebuf = %s",
1033 host_address_to_string (readbuf
),
1034 host_address_to_string (writebuf
));
1036 if (writebuf
!= NULL
)
1038 /* Case 1. GDB should not ask us to set a struct return value: it
1039 should know the struct return location and write the value there
1041 gdb_assert (!is_struct_return
);
1042 arc_store_return_value (gdbarch
, valtype
, regcache
, writebuf
);
1044 else if (readbuf
!= NULL
)
1046 /* Case 2. GDB should not ask us to get a struct return value: it
1047 should know the struct return location and read the value from there
1049 gdb_assert (!is_struct_return
);
1050 arc_extract_return_value (gdbarch
, valtype
, regcache
, readbuf
);
1053 return (is_struct_return
1054 ? RETURN_VALUE_STRUCT_CONVENTION
1055 : RETURN_VALUE_REGISTER_CONVENTION
);
1058 /* Return the base address of the frame. For ARC, the base address is the
1062 arc_frame_base_address (struct frame_info
*this_frame
, void **prologue_cache
)
1064 return (CORE_ADDR
) get_frame_register_unsigned (this_frame
, ARC_FP_REGNUM
);
1067 /* Helper function that returns valid pv_t for an instruction operand:
1068 either a register or a constant. */
1071 arc_pv_get_operand (pv_t
*regs
, const struct arc_instruction
&insn
, int operand
)
1073 if (insn
.operands
[operand
].kind
== ARC_OPERAND_KIND_REG
)
1074 return regs
[insn
.operands
[operand
].value
];
1076 return pv_constant (arc_insn_get_operand_value (insn
, operand
));
1079 /* Determine whether the given disassembled instruction may be part of a
1080 function prologue. If it is, the information in the frame unwind cache will
1084 arc_is_in_prologue (struct gdbarch
*gdbarch
, const struct arc_instruction
&insn
,
1085 pv_t
*regs
, struct pv_area
*stack
)
1087 /* It might be that currently analyzed address doesn't contain an
1088 instruction, hence INSN is not valid. It likely means that address points
1089 to a data, non-initialized memory, or middle of a 32-bit instruction. In
1090 practice this may happen if GDB connects to a remote target that has
1091 non-zeroed memory. GDB would read PC value and would try to analyze
1092 prologue, but there is no guarantee that memory contents at the address
1093 specified in PC is address is a valid instruction. There is not much that
1094 that can be done about that. */
1098 /* Branch/jump or a predicated instruction. */
1099 if (insn
.is_control_flow
|| insn
.condition_code
!= ARC_CC_AL
)
1102 /* Store of some register. May or may not update base address register. */
1103 if (insn
.insn_class
== STORE
|| insn
.insn_class
== PUSH
)
1105 /* There is definitely at least one operand - register/value being
1107 gdb_assert (insn
.operands_count
> 0);
1109 /* Store at some constant address. */
1110 if (insn
.operands_count
> 1
1111 && insn
.operands
[1].kind
!= ARC_OPERAND_KIND_REG
)
1115 Mode Address used Writeback value
1116 --------------------------------------------------
1118 A/AW reg + offset reg + offset
1120 AS reg + (offset << scaling) no
1122 "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However
1123 16-bit PUSH_S is a distinct instruction encoding, where offset and
1124 base register are implied through opcode. */
1126 /* Register with base memory address. */
1127 int base_reg
= arc_insn_get_memory_base_reg (insn
);
1129 /* Address where to write. arc_insn_get_memory_offset returns scaled
1130 value for ARC_WRITEBACK_AS. */
1132 if (insn
.writeback_mode
== ARC_WRITEBACK_AB
)
1133 addr
= regs
[base_reg
];
1135 addr
= pv_add_constant (regs
[base_reg
],
1136 arc_insn_get_memory_offset (insn
));
1138 if (stack
->store_would_trash (addr
))
1141 if (insn
.data_size_mode
!= ARC_SCALING_D
)
1143 /* Find the value being stored. */
1144 pv_t store_value
= arc_pv_get_operand (regs
, insn
, 0);
1146 /* What is the size of a the stored value? */
1148 if (insn
.data_size_mode
== ARC_SCALING_B
)
1150 else if (insn
.data_size_mode
== ARC_SCALING_H
)
1153 size
= ARC_REGISTER_SIZE
;
1155 stack
->store (addr
, size
, store_value
);
1159 if (insn
.operands
[0].kind
== ARC_OPERAND_KIND_REG
)
1161 /* If this is a double store, than write N+1 register as well. */
1162 pv_t store_value1
= regs
[insn
.operands
[0].value
];
1163 pv_t store_value2
= regs
[insn
.operands
[0].value
+ 1];
1164 stack
->store (addr
, ARC_REGISTER_SIZE
, store_value1
);
1165 stack
->store (pv_add_constant (addr
, ARC_REGISTER_SIZE
),
1166 ARC_REGISTER_SIZE
, store_value2
);
1171 = pv_constant (arc_insn_get_operand_value (insn
, 0));
1172 stack
->store (addr
, ARC_REGISTER_SIZE
* 2, store_value
);
1176 /* Is base register updated? */
1177 if (insn
.writeback_mode
== ARC_WRITEBACK_A
1178 || insn
.writeback_mode
== ARC_WRITEBACK_AB
)
1179 regs
[base_reg
] = pv_add_constant (regs
[base_reg
],
1180 arc_insn_get_memory_offset (insn
));
1184 else if (insn
.insn_class
== MOVE
)
1186 gdb_assert (insn
.operands_count
== 2);
1188 /* Destination argument can be "0", so nothing will happen. */
1189 if (insn
.operands
[0].kind
== ARC_OPERAND_KIND_REG
)
1191 int dst_regnum
= insn
.operands
[0].value
;
1192 regs
[dst_regnum
] = arc_pv_get_operand (regs
, insn
, 1);
1196 else if (insn
.insn_class
== SUB
)
1198 gdb_assert (insn
.operands_count
== 3);
1201 if (insn
.operands
[0].kind
!= ARC_OPERAND_KIND_REG
)
1204 int dst_regnum
= insn
.operands
[0].value
;
1205 regs
[dst_regnum
] = pv_subtract (arc_pv_get_operand (regs
, insn
, 1),
1206 arc_pv_get_operand (regs
, insn
, 2));
1209 else if (insn
.insn_class
== ENTER
)
1211 /* ENTER_S is a prologue-in-instruction - it saves all callee-saved
1212 registers according to given arguments thus greatly reducing code
1213 size. Which registers will be actually saved depends on arguments.
1215 ENTER_S {R13-...,FP,BLINK} stores registers in following order:
1226 There are up to three arguments for this opcode, as presented by ARC
1228 1) amount of general-purpose registers to be saved - this argument is
1229 always present even when it is 0;
1230 2) FP register number (27) if FP has to be stored, otherwise argument
1232 3) BLINK register number (31) if BLINK has to be stored, otherwise
1233 argument is not present. If both FP and BLINK are stored, then FP
1234 is present before BLINK in argument list. */
1235 gdb_assert (insn
.operands_count
> 0);
1237 int regs_saved
= arc_insn_get_operand_value (insn
, 0);
1240 if (insn
.operands_count
> 1)
1241 is_fp_saved
= (insn
.operands
[1].value
== ARC_FP_REGNUM
);
1243 is_fp_saved
= false;
1245 bool is_blink_saved
;
1246 if (insn
.operands_count
> 1)
1247 is_blink_saved
= (insn
.operands
[insn
.operands_count
- 1].value
1248 == ARC_BLINK_REGNUM
);
1250 is_blink_saved
= false;
1252 /* Amount of bytes to be allocated to store specified registers. */
1253 CORE_ADDR st_size
= ((regs_saved
+ is_fp_saved
+ is_blink_saved
)
1254 * ARC_REGISTER_SIZE
);
1255 pv_t new_sp
= pv_add_constant (regs
[ARC_SP_REGNUM
], -st_size
);
1257 /* Assume that if the last register (closest to new SP) can be written,
1258 then it is possible to write all of them. */
1259 if (stack
->store_would_trash (new_sp
))
1262 /* Current store address. */
1263 pv_t addr
= regs
[ARC_SP_REGNUM
];
1267 addr
= pv_add_constant (addr
, -ARC_REGISTER_SIZE
);
1268 stack
->store (addr
, ARC_REGISTER_SIZE
, regs
[ARC_FP_REGNUM
]);
1271 /* Registers are stored in backward order: from GP (R26) to R13. */
1272 for (int i
= ARC_R13_REGNUM
+ regs_saved
- 1; i
>= ARC_R13_REGNUM
; i
--)
1274 addr
= pv_add_constant (addr
, -ARC_REGISTER_SIZE
);
1275 stack
->store (addr
, ARC_REGISTER_SIZE
, regs
[i
]);
1280 addr
= pv_add_constant (addr
, -ARC_REGISTER_SIZE
);
1281 stack
->store (addr
, ARC_REGISTER_SIZE
,
1282 regs
[ARC_BLINK_REGNUM
]);
1285 gdb_assert (pv_is_identical (addr
, new_sp
));
1287 regs
[ARC_SP_REGNUM
] = new_sp
;
1290 regs
[ARC_FP_REGNUM
] = regs
[ARC_SP_REGNUM
];
1295 /* Some other architectures, like nds32 or arm, try to continue as far as
1296 possible when building a prologue cache (as opposed to when skipping
1297 prologue), so that cache will be as full as possible. However current
1298 code for ARC doesn't recognize some instructions that may modify SP, like
1299 ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't
1300 clobbered by the skipped instruction. Potential existence of extension
1301 instruction, which may do anything they want makes this even more complex,
1302 so it is just better to halt on a first unrecognized instruction. */
1307 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */
1309 static int ATTRIBUTE_PRINTF (2, 3)
1310 arc_fprintf_disasm (void *stream
, const char *format
, ...)
1315 struct disassemble_info
1316 arc_disassemble_info (struct gdbarch
*gdbarch
)
1318 struct disassemble_info di
;
1319 init_disassemble_info (&di
, &null_stream
, arc_fprintf_disasm
);
1320 di
.arch
= gdbarch_bfd_arch_info (gdbarch
)->arch
;
1321 di
.mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
1322 di
.endian
= gdbarch_byte_order (gdbarch
);
1323 di
.read_memory_func
= [](bfd_vma memaddr
, gdb_byte
*myaddr
,
1324 unsigned int len
, struct disassemble_info
*info
)
1326 return target_read_code (memaddr
, myaddr
, len
);
1331 /* Analyze the prologue and update the corresponding frame cache for the frame
1332 unwinder for unwinding frames that doesn't have debug info. In such
1333 situation GDB attempts to parse instructions in the prologue to understand
1334 where each register is saved.
1336 If CACHE is not NULL, then it will be filled with information about saved
1339 There are several variations of prologue which GDB may encounter. "Full"
1340 prologue looks like this:
1342 sub sp,sp,<imm> ; Space for variadic arguments.
1343 push blink ; Store return address.
1344 push r13 ; Store callee saved registers (up to R26/GP).
1346 push fp ; Store frame pointer.
1347 mov fp,sp ; Update frame pointer.
1348 sub sp,sp,<imm> ; Create space for local vars on the stack.
1350 Depending on compiler options lots of things may change:
1352 1) BLINK is not saved in leaf functions.
1353 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used.
1354 3) 16-bit versions of those instructions may be used.
1355 4) Instead of a sequence of several push'es, compiler may instead prefer to
1356 do one subtract on stack pointer and then store registers using normal
1357 store, that doesn't update SP. Like this:
1360 sub sp,sp,8 ; Create space for callee-saved registers.
1361 st r13,[sp,4] ; Store callee saved registers (up to R26/GP).
1364 5) ENTER_S instruction can encode most of prologue sequence in one
1365 instruction (except for those subtracts for variadic arguments and local
1367 6) GCC may use "millicode" functions from libgcc to store callee-saved
1368 registers with minimal code-size requirements. This function currently
1369 doesn't support this.
1371 ENTRYPOINT is a function entry point where prologue starts.
1373 LIMIT_PC is a maximum possible end address of prologue (meaning address
1374 of first instruction after the prologue). It might also point to the middle
1375 of prologue if execution has been stopped by the breakpoint at this address
1376 - in this case debugger should analyze prologue only up to this address,
1377 because further instructions haven't been executed yet.
1379 Returns address of the first instruction after the prologue. */
1382 arc_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR entrypoint
,
1383 const CORE_ADDR limit_pc
, struct arc_frame_cache
*cache
)
1385 arc_debug_printf ("entrypoint=%s, limit_pc=%s",
1386 paddress (gdbarch
, entrypoint
),
1387 paddress (gdbarch
, limit_pc
));
1389 /* Prologue values. Only core registers can be stored. */
1390 pv_t regs
[ARC_LAST_CORE_REGNUM
+ 1];
1391 for (int i
= 0; i
<= ARC_LAST_CORE_REGNUM
; i
++)
1392 regs
[i
] = pv_register (i
, 0);
1393 pv_area
stack (ARC_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1395 CORE_ADDR current_prologue_end
= entrypoint
;
1397 /* Look at each instruction in the prologue. */
1398 while (current_prologue_end
< limit_pc
)
1400 struct arc_instruction insn
;
1401 struct disassemble_info di
= arc_disassemble_info (gdbarch
);
1402 arc_insn_decode (current_prologue_end
, &di
, arc_delayed_print_insn
,
1406 arc_insn_dump (insn
);
1408 /* If this instruction is in the prologue, fields in the cache will be
1409 updated, and the saved registers mask may be updated. */
1410 if (!arc_is_in_prologue (gdbarch
, insn
, regs
, &stack
))
1412 /* Found an instruction that is not in the prologue. */
1413 arc_debug_printf ("End of prologue reached at address %s",
1414 paddress (gdbarch
, insn
.address
));
1418 current_prologue_end
= arc_insn_get_linear_next_pc (insn
);
1423 /* Figure out if it is a frame pointer or just a stack pointer. */
1424 if (pv_is_register (regs
[ARC_FP_REGNUM
], ARC_SP_REGNUM
))
1426 cache
->frame_base_reg
= ARC_FP_REGNUM
;
1427 cache
->frame_base_offset
= -regs
[ARC_FP_REGNUM
].k
;
1431 cache
->frame_base_reg
= ARC_SP_REGNUM
;
1432 cache
->frame_base_offset
= -regs
[ARC_SP_REGNUM
].k
;
1435 /* Assign offset from old SP to all saved registers. */
1436 for (int i
= 0; i
<= ARC_LAST_CORE_REGNUM
; i
++)
1439 if (stack
.find_reg (gdbarch
, i
, &offset
))
1440 cache
->saved_regs
[i
].set_addr (offset
);
1444 return current_prologue_end
;
1447 /* Estimated maximum prologue length in bytes. This should include:
1448 1) Store instruction for each callee-saved register (R25 - R13 + 1)
1449 2) Two instructions for FP
1451 4) Three substract instructions for SP (for variadic args, for
1452 callee saved regs and for local vars) and assuming that those SUB use
1453 long-immediate (hence double length).
1454 5) Stores of arguments registers are considered part of prologue too
1456 This is quite an extreme case, because even with -O0 GCC will collapse first
1457 two SUBs into one and long immediate values are quite unlikely to appear in
1458 this case, but still better to overshoot a bit - prologue analysis will
1459 anyway stop at the first instruction that doesn't fit prologue, so this
1460 limit will be rarely reached. */
1462 const static int MAX_PROLOGUE_LENGTH
1463 = 4 * (ARC_R25_REGNUM
- ARC_R13_REGNUM
+ 1 + 2 + 1 + 6
1464 + ARC_LAST_ARG_REGNUM
- ARC_FIRST_ARG_REGNUM
+ 1);
1466 /* Implement the "skip_prologue" gdbarch method.
1468 Skip the prologue for the function at PC. This is done by checking from
1469 the line information read from the DWARF, if possible; otherwise, we scan
1470 the function prologue to find its end. */
1473 arc_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1475 arc_debug_printf ("called");
1477 CORE_ADDR func_addr
;
1478 const char *func_name
;
1480 /* See what the symbol table says. */
1481 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, NULL
))
1483 /* Found a function. */
1484 CORE_ADDR postprologue_pc
1485 = skip_prologue_using_sal (gdbarch
, func_addr
);
1487 if (postprologue_pc
!= 0)
1488 return std::max (pc
, postprologue_pc
);
1491 /* No prologue info in symbol table, have to analyze prologue. */
1493 /* Find an upper limit on the function prologue using the debug
1494 information. If there is no debug information about prologue end, then
1495 skip_prologue_using_sal will return 0. */
1496 CORE_ADDR limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1498 /* If there is no debug information at all, it is required to give some
1499 semi-arbitrary hard limit on amount of bytes to scan during prologue
1502 limit_pc
= pc
+ MAX_PROLOGUE_LENGTH
;
1504 /* Find the address of the first instruction after the prologue by scanning
1505 through it - no other information is needed, so pass NULL as a cache. */
1506 return arc_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1509 /* Implement the "print_insn" gdbarch method.
1511 arc_get_disassembler () may return different functions depending on bfd
1512 type, so it is not possible to pass print_insn directly to
1513 set_gdbarch_print_insn (). Instead this wrapper function is used. It also
1514 may be used by other functions to get disassemble_info for address. It is
1515 important to note, that those print_insn from opcodes always print
1516 instruction to the stream specified in the INFO. If this is not desired,
1517 then either `print_insn` function in INFO should be set to some function
1518 that will not print, or `stream` should be different from standard
1522 arc_delayed_print_insn (bfd_vma addr
, struct disassemble_info
*info
)
1524 /* Standard BFD "machine number" field allows libopcodes disassembler to
1525 distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM
1526 and HS, which have some difference between. There are two ways to specify
1527 what is the target core:
1528 1) via the disassemble_info->disassembler_options;
1529 2) otherwise libopcodes will use private (architecture-specific) ELF
1532 Using disassembler_options is preferable, because it comes directly from
1533 GDBserver which scanned an actual ARC core identification info. However,
1534 not all GDBservers report core architecture, so as a fallback GDB still
1535 should support analysis of ELF header. The libopcodes disassembly code
1536 uses the section to find the BFD and the BFD to find the ELF header,
1537 therefore this function should set disassemble_info->section properly.
1539 disassembler_options was already set by non-target specific code with
1540 proper options obtained via gdbarch_disassembler_options ().
1542 This function might be called multiple times in a sequence, reusing same
1543 disassemble_info. */
1544 if ((info
->disassembler_options
== NULL
) && (info
->section
== NULL
))
1546 struct obj_section
*s
= find_pc_section (addr
);
1548 info
->section
= s
->the_bfd_section
;
1551 return default_print_insn (addr
, info
);
1554 /* Baremetal breakpoint instructions.
1556 ARC supports both big- and little-endian. However, instructions for
1557 little-endian processors are encoded in the middle-endian: half-words are
1558 in big-endian, while bytes inside the half-words are in little-endian; data
1559 is represented in the "normal" little-endian. Big-endian processors treat
1560 data and code identically.
1562 Assuming the number 0x01020304, it will be presented this way:
1564 Address : N N+1 N+2 N+3
1565 little-endian : 0x04 0x03 0x02 0x01
1566 big-endian : 0x01 0x02 0x03 0x04
1567 ARC middle-endian : 0x02 0x01 0x04 0x03
1570 static const gdb_byte arc_brk_s_be
[] = { 0x7f, 0xff };
1571 static const gdb_byte arc_brk_s_le
[] = { 0xff, 0x7f };
1572 static const gdb_byte arc_brk_be
[] = { 0x25, 0x6f, 0x00, 0x3f };
1573 static const gdb_byte arc_brk_le
[] = { 0x6f, 0x25, 0x3f, 0x00 };
1575 /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff
1576 (little endian) or 0xff7f (big endian). We used to insert BRK_S even
1577 instead of 32-bit instructions, which works mostly ok, unless breakpoint is
1578 inserted into delay slot instruction. In this case if branch is taken
1579 BLINK value will be set to address of instruction after delay slot, however
1580 if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S,
1581 then BLINK value will have an invalid value - it will point to the address
1582 after the BRK_S (which was there at the moment of branch execution) while
1583 it should point to the address after the 32-bit long instruction. To avoid
1584 such issues this function disassembles instruction at target location and
1587 ARC 600 supports only 16-bit BRK_S.
1589 NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S]
1590 is much better because it doesn't commit unlike TRAP_S, so it can be set in
1591 delay slots; however it cannot be used in user-mode, hence usage of TRAP_S
1592 in GDB for user-space. */
1594 /* Implement the "breakpoint_kind_from_pc" gdbarch method. */
1597 arc_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1599 size_t length_with_limm
= gdb_insn_length (gdbarch
, *pcptr
);
1601 /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with
1602 BRK. LIMM is part of instruction length, so it can be either 4 or 8
1603 bytes for 32-bit instructions. */
1604 if ((length_with_limm
== 4 || length_with_limm
== 8)
1605 && !arc_mach_is_arc600 (gdbarch
))
1606 return sizeof (arc_brk_le
);
1608 return sizeof (arc_brk_s_le
);
1611 /* Implement the "sw_breakpoint_from_kind" gdbarch method. */
1613 static const gdb_byte
*
1614 arc_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1616 gdb_assert (kind
== 2 || kind
== 4);
1619 if (kind
== sizeof (arc_brk_le
))
1621 return ((gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1627 return ((gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1633 /* Implement the "frame_align" gdbarch method. */
1636 arc_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1638 return align_down (sp
, 4);
1641 /* Dump the frame info. Used for internal debugging only. */
1644 arc_print_frame_cache (struct gdbarch
*gdbarch
, const char *message
,
1645 struct arc_frame_cache
*cache
, int addresses_known
)
1647 arc_debug_printf ("frame_info %s", message
);
1648 arc_debug_printf ("prev_sp = %s", paddress (gdbarch
, cache
->prev_sp
));
1649 arc_debug_printf ("frame_base_reg = %i", cache
->frame_base_reg
);
1650 arc_debug_printf ("frame_base_offset = %s",
1651 plongest (cache
->frame_base_offset
));
1653 for (int i
= 0; i
<= ARC_BLINK_REGNUM
; i
++)
1655 if (cache
->saved_regs
[i
].is_addr ())
1656 arc_debug_printf ("saved register %s at %s %s",
1657 gdbarch_register_name (gdbarch
, i
),
1658 (addresses_known
) ? "address" : "offset",
1659 paddress (gdbarch
, cache
->saved_regs
[i
].addr ()));
1663 /* Frame unwinder for normal frames. */
1665 static struct arc_frame_cache
*
1666 arc_make_frame_cache (struct frame_info
*this_frame
)
1668 arc_debug_printf ("called");
1670 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1672 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1673 CORE_ADDR entrypoint
, prologue_end
;
1674 if (find_pc_partial_function (block_addr
, NULL
, &entrypoint
, &prologue_end
))
1676 struct symtab_and_line sal
= find_pc_line (entrypoint
, 0);
1677 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1679 /* No line info so use current PC. */
1680 prologue_end
= prev_pc
;
1681 else if (sal
.end
< prologue_end
)
1682 /* The next line begins after the function end. */
1683 prologue_end
= sal
.end
;
1685 prologue_end
= std::min (prologue_end
, prev_pc
);
1689 /* If find_pc_partial_function returned nothing then there is no symbol
1690 information at all for this PC. Currently it is assumed in this case
1691 that current PC is entrypoint to function and try to construct the
1692 frame from that. This is, probably, suboptimal, for example ARM
1693 assumes in this case that program is inside the normal frame (with
1694 frame pointer). ARC, perhaps, should try to do the same. */
1695 entrypoint
= get_frame_register_unsigned (this_frame
,
1696 gdbarch_pc_regnum (gdbarch
));
1697 prologue_end
= entrypoint
+ MAX_PROLOGUE_LENGTH
;
1700 /* Allocate new frame cache instance and space for saved register info.
1701 FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */
1702 struct arc_frame_cache
*cache
1703 = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache
);
1704 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1706 arc_analyze_prologue (gdbarch
, entrypoint
, prologue_end
, cache
);
1709 arc_print_frame_cache (gdbarch
, "after prologue", cache
, false);
1711 CORE_ADDR unwound_fb
= get_frame_register_unsigned (this_frame
,
1712 cache
->frame_base_reg
);
1713 if (unwound_fb
== 0)
1715 cache
->prev_sp
= unwound_fb
+ cache
->frame_base_offset
;
1717 for (int i
= 0; i
<= ARC_LAST_CORE_REGNUM
; i
++)
1719 if (cache
->saved_regs
[i
].is_addr ())
1720 cache
->saved_regs
[i
].set_addr (cache
->saved_regs
[i
].addr ()
1725 arc_print_frame_cache (gdbarch
, "after previous SP found", cache
, true);
1730 /* Implement the "this_id" frame_unwind method. */
1733 arc_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1734 struct frame_id
*this_id
)
1736 arc_debug_printf ("called");
1738 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1740 if (*this_cache
== NULL
)
1741 *this_cache
= arc_make_frame_cache (this_frame
);
1742 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) (*this_cache
);
1744 CORE_ADDR stack_addr
= cache
->prev_sp
;
1746 /* There are 4 possible situation which decide how frame_id->code_addr is
1749 1) Function is compiled with option -g. Then frame_id will be created
1750 in dwarf_* function and not in this function. NB: even if target
1751 binary is compiled with -g, some std functions like __start and _init
1752 are not, so they still will follow one of the following choices.
1754 2) Function is compiled without -g and binary hasn't been stripped in
1755 any way. In this case GDB still has enough information to evaluate
1756 frame code_addr properly. This case is covered by call to
1759 3) Binary has been striped with option -g (strip debug symbols). In
1760 this case there is still enough symbols for get_frame_func () to work
1761 properly, so this case is also covered by it.
1763 4) Binary has been striped with option -s (strip all symbols). In this
1764 case GDB cannot get function start address properly, so we return current
1767 CORE_ADDR code_addr
= get_frame_func (this_frame
);
1769 code_addr
= get_frame_register_unsigned (this_frame
,
1770 gdbarch_pc_regnum (gdbarch
));
1772 *this_id
= frame_id_build (stack_addr
, code_addr
);
1775 /* Implement the "prev_register" frame_unwind method. */
1777 static struct value
*
1778 arc_frame_prev_register (struct frame_info
*this_frame
,
1779 void **this_cache
, int regnum
)
1781 if (*this_cache
== NULL
)
1782 *this_cache
= arc_make_frame_cache (this_frame
);
1783 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) (*this_cache
);
1785 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1787 /* If we are asked to unwind the PC, then we need to return BLINK instead:
1788 the saved value of PC points into this frame's function's prologue, not
1789 the next frame's function's resume location. */
1790 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1791 regnum
= ARC_BLINK_REGNUM
;
1793 /* SP is a special case - we should return prev_sp, because
1794 trad_frame_get_prev_register will return _current_ SP value.
1795 Alternatively we could have stored cache->prev_sp in the cache->saved
1796 regs, but here we follow the lead of AArch64, ARM and Xtensa and will
1797 leave that logic in this function, instead of prologue analyzers. That I
1798 think is a bit more clear as `saved_regs` should contain saved regs, not
1801 Because value has been computed, "got_constant" should be used, so that
1802 returned value will be a "not_lval" - immutable. */
1804 if (regnum
== gdbarch_sp_regnum (gdbarch
))
1805 return frame_unwind_got_constant (this_frame
, regnum
, cache
->prev_sp
);
1807 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
, regnum
);
1810 /* Implement the "init_reg" dwarf2_frame method. */
1813 arc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1814 struct dwarf2_frame_state_reg
*reg
,
1815 struct frame_info
*info
)
1817 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1818 /* The return address column. */
1819 reg
->how
= DWARF2_FRAME_REG_RA
;
1820 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1821 /* The call frame address. */
1822 reg
->how
= DWARF2_FRAME_REG_CFA
;
1825 /* Signal trampoline frame unwinder. Allows frame unwinding to happen
1826 from within signal handlers. */
1828 static struct arc_frame_cache
*
1829 arc_make_sigtramp_frame_cache (struct frame_info
*this_frame
)
1831 arc_debug_printf ("called");
1833 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1835 /* Allocate new frame cache instance and space for saved register info. */
1836 struct arc_frame_cache
*cache
= FRAME_OBSTACK_ZALLOC (struct arc_frame_cache
);
1837 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1839 /* Get the stack pointer and use it as the frame base. */
1840 cache
->prev_sp
= arc_frame_base_address (this_frame
, NULL
);
1842 /* If the ARC-private target-dependent info doesn't have a table of
1843 offsets of saved register contents within an OS signal context
1844 structure, then there is nothing to analyze. */
1845 if (tdep
->sc_reg_offset
== NULL
)
1848 /* Find the address of the sigcontext structure. */
1849 CORE_ADDR addr
= tdep
->sigcontext_addr (this_frame
);
1851 /* For each register, if its contents have been saved within the
1852 sigcontext structure, determine the address of those contents. */
1853 gdb_assert (tdep
->sc_num_regs
<= (ARC_LAST_REGNUM
+ 1));
1854 for (int i
= 0; i
< tdep
->sc_num_regs
; i
++)
1856 if (tdep
->sc_reg_offset
[i
] != ARC_OFFSET_NO_REGISTER
)
1857 cache
->saved_regs
[i
].set_addr (addr
+ tdep
->sc_reg_offset
[i
]);
1863 /* Implement the "this_id" frame_unwind method for signal trampoline
1867 arc_sigtramp_frame_this_id (struct frame_info
*this_frame
,
1868 void **this_cache
, struct frame_id
*this_id
)
1870 arc_debug_printf ("called");
1872 if (*this_cache
== NULL
)
1873 *this_cache
= arc_make_sigtramp_frame_cache (this_frame
);
1875 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1876 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) *this_cache
;
1877 CORE_ADDR stack_addr
= cache
->prev_sp
;
1879 = get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1880 *this_id
= frame_id_build (stack_addr
, code_addr
);
1883 /* Get a register from a signal handler frame. */
1885 static struct value
*
1886 arc_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1887 void **this_cache
, int regnum
)
1889 arc_debug_printf ("regnum = %d", regnum
);
1891 /* Make sure we've initialized the cache. */
1892 if (*this_cache
== NULL
)
1893 *this_cache
= arc_make_sigtramp_frame_cache (this_frame
);
1895 struct arc_frame_cache
*cache
= (struct arc_frame_cache
*) *this_cache
;
1896 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
, regnum
);
1899 /* Frame sniffer for signal handler frame. Only recognize a frame if we
1900 have a sigcontext_addr handler in the target dependency. */
1903 arc_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1904 struct frame_info
*this_frame
,
1907 struct gdbarch_tdep
*tdep
;
1909 arc_debug_printf ("called");
1911 tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1913 /* If we have a sigcontext_addr handler, then just return 1 (same as the
1914 "default_frame_sniffer ()"). */
1915 return (tdep
->sigcontext_addr
!= NULL
&& tdep
->is_sigtramp
!= NULL
1916 && tdep
->is_sigtramp (this_frame
));
1919 /* Structure defining the ARC ordinary frame unwind functions. Since we are
1920 the fallback unwinder, we use the default frame sniffer, which always
1921 accepts the frame. */
1923 static const struct frame_unwind arc_frame_unwind
= {
1925 default_frame_unwind_stop_reason
,
1927 arc_frame_prev_register
,
1929 default_frame_sniffer
,
1934 /* Structure defining the ARC signal frame unwind functions. Custom
1935 sniffer is used, because this frame must be accepted only in the right
1938 static const struct frame_unwind arc_sigtramp_frame_unwind
= {
1940 default_frame_unwind_stop_reason
,
1941 arc_sigtramp_frame_this_id
,
1942 arc_sigtramp_frame_prev_register
,
1944 arc_sigtramp_frame_sniffer
,
1950 static const struct frame_base arc_normal_base
= {
1952 arc_frame_base_address
,
1953 arc_frame_base_address
,
1954 arc_frame_base_address
1958 mach_type_to_arc_isa (const unsigned long mach
)
1962 case bfd_mach_arc_arc600
:
1963 case bfd_mach_arc_arc601
:
1964 case bfd_mach_arc_arc700
:
1965 return ARC_ISA_ARCV1
;
1966 case bfd_mach_arc_arcv2
:
1967 return ARC_ISA_ARCV2
;
1969 internal_error (__FILE__
, __LINE__
,
1970 _("unknown machine id %lu"), mach
);
1974 /* See arc-tdep.h. */
1977 arc_arch_features_create (const bfd
*abfd
, const unsigned long mach
)
1979 /* Use 4 as a fallback value. */
1982 /* Try to guess the features parameters by looking at the binary to be
1983 executed. If the user is providing a binary that does not match the
1984 target, then tough luck. This is the last effort to makes sense of
1986 if (abfd
!= nullptr && bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
1988 unsigned char eclass
= elf_elfheader (abfd
)->e_ident
[EI_CLASS
];
1990 if (eclass
== ELFCLASS32
)
1992 else if (eclass
== ELFCLASS64
)
1995 internal_error (__FILE__
, __LINE__
,
1996 _("unknown ELF header class %d"), eclass
);
1999 /* MACH from a bfd_arch_info struct is used here. It should be a safe
2000 bet, as it looks like the struct is always initialized even when we
2001 don't pass any elf file to GDB at all (it uses default arch in that
2003 arc_isa isa
= mach_type_to_arc_isa (mach
);
2005 return arc_arch_features (reg_size
, isa
);
2008 /* Look for obsolete core feature names in TDESC. */
2010 static const struct tdesc_feature
*
2011 find_obsolete_core_names (const struct target_desc
*tdesc
)
2013 const struct tdesc_feature
*feat
= nullptr;
2015 feat
= tdesc_find_feature (tdesc
, ARC_CORE_V1_OBSOLETE_FEATURE_NAME
);
2017 if (feat
== nullptr)
2018 feat
= tdesc_find_feature (tdesc
, ARC_CORE_V2_OBSOLETE_FEATURE_NAME
);
2020 if (feat
== nullptr)
2021 feat
= tdesc_find_feature
2022 (tdesc
, ARC_CORE_V2_REDUCED_OBSOLETE_FEATURE_NAME
);
2027 /* Look for obsolete aux feature names in TDESC. */
2029 static const struct tdesc_feature
*
2030 find_obsolete_aux_names (const struct target_desc
*tdesc
)
2032 return tdesc_find_feature (tdesc
, ARC_AUX_OBSOLETE_FEATURE_NAME
);
2035 /* Based on the MACH value, determines which core register features set
2038 static arc_register_feature
*
2039 determine_core_reg_feature_set (const unsigned long mach
)
2041 switch (mach_type_to_arc_isa (mach
))
2044 return &arc_v1_core_reg_feature
;
2046 return &arc_v2_core_reg_feature
;
2048 gdb_assert_not_reached
2049 ("Unknown machine type to determine the core feature set.");
2053 /* At the moment, there is only 1 auxiliary register features set.
2054 This is a place holder for future extendability. */
2056 static const arc_register_feature
*
2057 determine_aux_reg_feature_set ()
2059 return &arc_common_aux_reg_feature
;
2062 /* Update accumulator register names (ACCH/ACCL) for r58 and r59 in the
2063 register sets. The endianness determines the assignment:
2067 ,----|------+------|
2070 `----^------^------' */
2073 arc_update_acc_reg_names (const int byte_order
)
2075 const char *r58_alias
2076 = byte_order
== BFD_ENDIAN_LITTLE
? "accl" : "acch";
2077 const char *r59_alias
2078 = byte_order
== BFD_ENDIAN_LITTLE
? "acch" : "accl";
2080 /* Subscript 1 must be OK because those registers have 2 names. */
2081 arc_v1_core_reg_feature
.registers
[ARC_R58_REGNUM
].names
[1] = r58_alias
;
2082 arc_v1_core_reg_feature
.registers
[ARC_R59_REGNUM
].names
[1] = r59_alias
;
2083 arc_v2_core_reg_feature
.registers
[ARC_R58_REGNUM
].names
[1] = r58_alias
;
2084 arc_v2_core_reg_feature
.registers
[ARC_R59_REGNUM
].names
[1] = r59_alias
;
2087 /* Go through all the registers in REG_SET and check if they exist
2088 in FEATURE. The TDESC_DATA is updated with the register number
2089 in REG_SET if it is found in the feature. If a required register
2090 is not found, this function returns false. */
2093 arc_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
2094 const struct tdesc_feature
*feature
,
2095 const struct arc_register_feature
*reg_set
)
2097 for (const auto ®
: reg_set
->registers
)
2101 for (const char *name
: reg
.names
)
2104 = tdesc_numbered_register (feature
, tdesc_data
, reg
.regnum
, name
);
2110 if (!found
&& reg
.required_p
)
2112 std::ostringstream reg_names
;
2113 for (std::size_t i
= 0; i
< reg
.names
.size(); ++i
)
2116 reg_names
<< "'" << reg
.names
[0] << "'";
2118 reg_names
<< " or '" << reg
.names
[0] << "'";
2120 arc_print (_("Error: Cannot find required register(s) %s "
2121 "in feature '%s'.\n"), reg_names
.str ().c_str (),
2122 feature
->name
.c_str ());
2130 /* Check for the existance of "lp_start" and "lp_end" in target description.
2131 If both are present, assume there is hardware loop support in the target.
2132 This can be improved by looking into "lpc_size" field of "isa_config"
2133 auxiliary register. */
2136 arc_check_for_hw_loops (const struct target_desc
*tdesc
,
2137 struct tdesc_arch_data
*data
)
2139 const auto feature_aux
= tdesc_find_feature (tdesc
, ARC_AUX_FEATURE_NAME
);
2140 const auto aux_regset
= determine_aux_reg_feature_set ();
2142 if (feature_aux
== nullptr)
2145 bool hw_loop_p
= false;
2146 const auto lp_start_name
=
2147 aux_regset
->registers
[ARC_LP_START_REGNUM
- ARC_FIRST_AUX_REGNUM
].names
[0];
2148 const auto lp_end_name
=
2149 aux_regset
->registers
[ARC_LP_END_REGNUM
- ARC_FIRST_AUX_REGNUM
].names
[0];
2151 hw_loop_p
= tdesc_numbered_register (feature_aux
, data
,
2152 ARC_LP_START_REGNUM
, lp_start_name
);
2153 hw_loop_p
&= tdesc_numbered_register (feature_aux
, data
,
2154 ARC_LP_END_REGNUM
, lp_end_name
);
2159 /* Initialize target description for the ARC.
2161 Returns true if input TDESC was valid and in this case it will assign TDESC
2162 and TDESC_DATA output parameters. */
2165 arc_tdesc_init (struct gdbarch_info info
, const struct target_desc
**tdesc
,
2166 tdesc_arch_data_up
*tdesc_data
)
2168 const struct target_desc
*tdesc_loc
= info
.target_desc
;
2169 arc_debug_printf ("Target description initialization.");
2171 /* If target doesn't provide a description, use the default ones. */
2172 if (!tdesc_has_registers (tdesc_loc
))
2174 arc_arch_features features
2175 = arc_arch_features_create (info
.abfd
,
2176 info
.bfd_arch_info
->mach
);
2177 tdesc_loc
= arc_lookup_target_description (features
);
2179 gdb_assert (tdesc_loc
!= nullptr);
2181 arc_debug_printf ("Have got a target description");
2183 const struct tdesc_feature
*feature_core
2184 = tdesc_find_feature (tdesc_loc
, ARC_CORE_FEATURE_NAME
);
2185 const struct tdesc_feature
*feature_aux
2186 = tdesc_find_feature (tdesc_loc
, ARC_AUX_FEATURE_NAME
);
2188 /* Maybe there still is a chance to salvage the input. */
2189 if (feature_core
== nullptr)
2190 feature_core
= find_obsolete_core_names (tdesc_loc
);
2191 if (feature_aux
== nullptr)
2192 feature_aux
= find_obsolete_aux_names (tdesc_loc
);
2194 if (feature_core
== nullptr)
2196 arc_print (_("Error: Cannot find required feature '%s' in supplied "
2197 "target description.\n"), ARC_CORE_FEATURE_NAME
);
2201 if (feature_aux
== nullptr)
2203 arc_print (_("Error: Cannot find required feature '%s' in supplied "
2204 "target description.\n"), ARC_AUX_FEATURE_NAME
);
2208 const arc_register_feature
*arc_core_reg_feature
2209 = determine_core_reg_feature_set (info
.bfd_arch_info
->mach
);
2210 const arc_register_feature
*arc_aux_reg_feature
2211 = determine_aux_reg_feature_set ();
2213 tdesc_arch_data_up tdesc_data_loc
= tdesc_data_alloc ();
2215 arc_update_acc_reg_names (info
.byte_order
);
2217 bool valid_p
= arc_check_tdesc_feature (tdesc_data_loc
.get (),
2219 arc_core_reg_feature
);
2221 valid_p
&= arc_check_tdesc_feature (tdesc_data_loc
.get (),
2223 arc_aux_reg_feature
);
2227 arc_debug_printf ("Target description is not valid");
2232 *tdesc_data
= std::move (tdesc_data_loc
);
2237 /* Implement the type_align gdbarch function. */
2240 arc_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
2242 switch (type
->code ())
2245 case TYPE_CODE_FUNC
:
2246 case TYPE_CODE_FLAGS
:
2248 case TYPE_CODE_RANGE
:
2250 case TYPE_CODE_ENUM
:
2252 case TYPE_CODE_RVALUE_REF
:
2253 case TYPE_CODE_CHAR
:
2254 case TYPE_CODE_BOOL
:
2255 case TYPE_CODE_DECFLOAT
:
2256 case TYPE_CODE_METHODPTR
:
2257 case TYPE_CODE_MEMBERPTR
:
2258 type
= check_typedef (type
);
2259 return std::min
<ULONGEST
> (4, TYPE_LENGTH (type
));
2265 /* Implement the "init" gdbarch method. */
2267 static struct gdbarch
*
2268 arc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2270 const struct target_desc
*tdesc
;
2271 tdesc_arch_data_up tdesc_data
;
2273 arc_debug_printf ("Architecture initialization.");
2275 if (!arc_tdesc_init (info
, &tdesc
, &tdesc_data
))
2278 /* Allocate the ARC-private target-dependent information structure, and the
2279 GDB target-independent information structure. */
2280 gdb::unique_xmalloc_ptr
<struct gdbarch_tdep
> tdep
2281 (XCNEW (struct gdbarch_tdep
));
2282 tdep
->jb_pc
= -1; /* No longjmp support by default. */
2283 tdep
->has_hw_loops
= arc_check_for_hw_loops (tdesc
, tdesc_data
.get ());
2284 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
.release ());
2287 set_gdbarch_short_bit (gdbarch
, 16);
2288 set_gdbarch_int_bit (gdbarch
, 32);
2289 set_gdbarch_long_bit (gdbarch
, 32);
2290 set_gdbarch_long_long_bit (gdbarch
, 64);
2291 set_gdbarch_type_align (gdbarch
, arc_type_align
);
2292 set_gdbarch_float_bit (gdbarch
, 32);
2293 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2294 set_gdbarch_double_bit (gdbarch
, 64);
2295 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2296 set_gdbarch_ptr_bit (gdbarch
, 32);
2297 set_gdbarch_addr_bit (gdbarch
, 32);
2298 set_gdbarch_char_signed (gdbarch
, 0);
2300 set_gdbarch_write_pc (gdbarch
, arc_write_pc
);
2302 set_gdbarch_virtual_frame_pointer (gdbarch
, arc_virtual_frame_pointer
);
2304 /* tdesc_use_registers expects gdbarch_num_regs to return number of registers
2305 parsed by gdbarch_init, and then it will add all of the remaining
2306 registers and will increase number of registers. */
2307 set_gdbarch_num_regs (gdbarch
, ARC_LAST_REGNUM
+ 1);
2308 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2309 set_gdbarch_sp_regnum (gdbarch
, ARC_SP_REGNUM
);
2310 set_gdbarch_pc_regnum (gdbarch
, ARC_PC_REGNUM
);
2311 set_gdbarch_ps_regnum (gdbarch
, ARC_STATUS32_REGNUM
);
2312 set_gdbarch_fp0_regnum (gdbarch
, -1); /* No FPU registers. */
2314 set_gdbarch_push_dummy_call (gdbarch
, arc_push_dummy_call
);
2315 set_gdbarch_push_dummy_code (gdbarch
, arc_push_dummy_code
);
2317 set_gdbarch_cannot_fetch_register (gdbarch
, arc_cannot_fetch_register
);
2318 set_gdbarch_cannot_store_register (gdbarch
, arc_cannot_store_register
);
2320 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2322 set_gdbarch_return_value (gdbarch
, arc_return_value
);
2324 set_gdbarch_skip_prologue (gdbarch
, arc_skip_prologue
);
2325 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2327 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arc_breakpoint_kind_from_pc
);
2328 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arc_sw_breakpoint_from_kind
);
2330 /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */
2331 if (!arc_mach_is_arc600 (gdbarch
))
2332 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2334 set_gdbarch_decr_pc_after_break (gdbarch
, 2);
2336 set_gdbarch_frame_align (gdbarch
, arc_frame_align
);
2338 set_gdbarch_print_insn (gdbarch
, arc_delayed_print_insn
);
2340 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
2342 /* "nonsteppable" watchpoint means that watchpoint triggers before
2343 instruction is committed, therefore it is required to remove watchpoint
2344 to step though instruction that triggers it. ARC watchpoints trigger
2345 only after instruction is committed, thus there is no need to remove
2346 them. In fact on ARC watchpoint for memory writes may trigger with more
2347 significant delay, like one or two instructions, depending on type of
2348 memory where write is performed (CCM or external) and next instruction
2349 after the memory write. */
2350 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 0);
2352 /* This doesn't include possible long-immediate value. */
2353 set_gdbarch_max_insn_length (gdbarch
, 4);
2355 /* Frame unwinders and sniffers. */
2356 dwarf2_frame_set_init_reg (gdbarch
, arc_dwarf2_frame_init_reg
);
2357 dwarf2_append_unwinders (gdbarch
);
2358 frame_unwind_append_unwinder (gdbarch
, &arc_sigtramp_frame_unwind
);
2359 frame_unwind_append_unwinder (gdbarch
, &arc_frame_unwind
);
2360 frame_base_set_default (gdbarch
, &arc_normal_base
);
2362 /* Setup stuff specific to a particular environment (baremetal or Linux).
2363 It can override functions set earlier. */
2364 gdbarch_init_osabi (info
, gdbarch
);
2366 if (gdbarch_tdep (gdbarch
)->jb_pc
>= 0)
2367 set_gdbarch_get_longjmp_target (gdbarch
, arc_get_longjmp_target
);
2369 /* Disassembler options. Enforce CPU if it was specified in XML target
2370 description, otherwise use default method of determining CPU (ELF private
2372 if (info
.target_desc
!= NULL
)
2374 const struct bfd_arch_info
*tdesc_arch
2375 = tdesc_architecture (info
.target_desc
);
2376 if (tdesc_arch
!= NULL
)
2378 xfree (arc_disassembler_options
);
2379 /* FIXME: It is not really good to change disassembler options
2380 behind the scene, because that might override options
2381 specified by the user. However as of now ARC doesn't support
2382 `set disassembler-options' hence this code is the only place
2383 where options are changed. It also changes options for all
2384 existing gdbarches, which also can be problematic, if
2385 arc_gdbarch_init will start reusing existing gdbarch
2387 /* Target description specifies a BFD architecture, which is
2388 different from ARC cpu, as accepted by disassembler (and most
2389 other ARC tools), because cpu values are much more fine grained -
2390 there can be multiple cpu values per single BFD architecture. As
2391 a result this code should translate architecture to some cpu
2392 value. Since there is no info on exact cpu configuration, it is
2393 best to use the most feature-rich CPU, so that disassembler will
2394 recognize all instructions available to the specified
2396 switch (tdesc_arch
->mach
)
2398 case bfd_mach_arc_arc601
:
2399 arc_disassembler_options
= xstrdup ("cpu=arc601");
2401 case bfd_mach_arc_arc600
:
2402 arc_disassembler_options
= xstrdup ("cpu=arc600");
2404 case bfd_mach_arc_arc700
:
2405 arc_disassembler_options
= xstrdup ("cpu=arc700");
2407 case bfd_mach_arc_arcv2
:
2408 /* Machine arcv2 has three arches: ARCv2, EM and HS; where ARCv2
2409 is treated as EM. */
2410 if (arc_arch_is_hs (tdesc_arch
))
2411 arc_disassembler_options
= xstrdup ("cpu=hs38_linux");
2413 arc_disassembler_options
= xstrdup ("cpu=em4_fpuda");
2416 arc_disassembler_options
= NULL
;
2419 set_gdbarch_disassembler_options (gdbarch
,
2420 &arc_disassembler_options
);
2424 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
2429 /* Implement the "dump_tdep" gdbarch method. */
2432 arc_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
2434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2436 fprintf_unfiltered (file
, "arc_dump_tdep: jb_pc = %i\n", tdep
->jb_pc
);
2438 fprintf_unfiltered (file
, "arc_dump_tdep: is_sigtramp = <%s>\n",
2439 host_address_to_string (tdep
->is_sigtramp
));
2440 fprintf_unfiltered (file
, "arc_dump_tdep: sigcontext_addr = <%s>\n",
2441 host_address_to_string (tdep
->sigcontext_addr
));
2442 fprintf_unfiltered (file
, "arc_dump_tdep: sc_reg_offset = <%s>\n",
2443 host_address_to_string (tdep
->sc_reg_offset
));
2444 fprintf_unfiltered (file
, "arc_dump_tdep: sc_num_regs = %d\n",
2448 /* This command accepts single argument - address of instruction to
2452 dump_arc_instruction_command (const char *args
, int from_tty
)
2455 if (args
!= NULL
&& strlen (args
) > 0)
2456 val
= evaluate_expression (parse_expression (args
).get ());
2458 val
= access_value_history (0);
2459 record_latest_value (val
);
2461 CORE_ADDR address
= value_as_address (val
);
2462 struct arc_instruction insn
;
2463 struct disassemble_info di
= arc_disassemble_info (target_gdbarch ());
2464 arc_insn_decode (address
, &di
, arc_delayed_print_insn
, &insn
);
2465 arc_insn_dump (insn
);
2468 void _initialize_arc_tdep ();
2470 _initialize_arc_tdep ()
2472 gdbarch_register (bfd_arch_arc
, arc_gdbarch_init
, arc_dump_tdep
);
2474 /* Register ARC-specific commands with gdb. */
2476 /* Add root prefix command for "maintenance print arc" commands. */
2477 add_show_prefix_cmd ("arc", class_maintenance
,
2478 _("ARC-specific maintenance commands for printing GDB "
2480 &maintenance_print_arc_list
, "maintenance print arc ",
2481 0, &maintenanceprintlist
);
2483 add_cmd ("arc-instruction", class_maintenance
,
2484 dump_arc_instruction_command
,
2485 _("Dump arc_instruction structure for specified address."),
2486 &maintenance_print_arc_list
);
2488 /* Debug internals for ARC GDB. */
2489 add_setshow_boolean_cmd ("arc", class_maintenance
,
2491 _("Set ARC specific debugging."),
2492 _("Show ARC specific debugging."),
2493 _("When set, ARC specific debugging is enabled."),
2494 NULL
, NULL
, &setdebuglist
, &showdebuglist
);