gdb/arc-tdep.h

   1 /* Target dependent code for ARC architecture, for GDB.
   2
   3    Copyright 2005-2020 Free Software Foundation, Inc.
   4    Contributed by Synopsys Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef ARC_TDEP_H
  22 #define ARC_TDEP_H
  23
  24 /* Need disassemble_info.  */
  25 #include "dis-asm.h"
  26 #include "arch/arc.h"
  27
  28 /* To simplify GDB code this enum assumes that internal regnums should be same
  29    as architectural register numbers, i.e. PCL regnum is 63.  This allows to
  30    use internal GDB regnums as architectural numbers when dealing with
  31    instruction encodings, for example when analyzing what are the registers
  32    saved in function prologue.  */
  33
  34 enum arc_regnum
  35   {
  36     /* Core registers.  */
  37     ARC_R0_REGNUM = 0,
  38     ARC_R1_REGNUM = 1,
  39     ARC_R4_REGNUM = 4,
  40     ARC_R7_REGNUM = 7,
  41     ARC_R9_REGNUM = 9,
  42     ARC_R13_REGNUM = 13,
  43     ARC_R16_REGNUM = 16,
  44     ARC_R25_REGNUM = 25,
  45     /* Global data pointer.  */
  46     ARC_GP_REGNUM,
  47     /* Frame pointer.  */
  48     ARC_FP_REGNUM,
  49     /* Stack pointer.  */
  50     ARC_SP_REGNUM,
  51     /* Return address from interrupt.  */
  52     ARC_ILINK_REGNUM,
  53     ARC_R30_REGNUM,
  54     /* Return address from function.  */
  55     ARC_BLINK_REGNUM,
  56     /* Accumulator registers.  */
  57     ARC_R58_REGNUM = 58,
  58     ARC_R59_REGNUM,
  59     /* Zero-delay loop counter.  */
  60     ARC_LP_COUNT_REGNUM = 60,
  61     /* Reserved register number.  There should never be a register with such
  62        number, this name is needed only for a sanity check in
  63       arc_cannot_(fetch|store)_register.  */
  64     ARC_RESERVED_REGNUM,
  65     /* Long-immediate value.  This is not a physical register - if instruction
  66        has register 62 as an operand, then this operand is a literal value
  67        stored in the instruction memory right after the instruction itself.
  68        This value is required in this enumeration as an architectural number
  69        for instruction analysis.  */
  70     ARC_LIMM_REGNUM,
  71     /* Program counter, aligned to 4-bytes, read-only.  */
  72     ARC_PCL_REGNUM,
  73     ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
  74
  75     /* AUX registers.  */
  76     /* Actual program counter.  */
  77     ARC_PC_REGNUM,
  78     ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM,
  79     /* Status register.  */
  80     ARC_STATUS32_REGNUM,
  81     /* Zero-delay loop start instruction.  */
  82     ARC_LP_START_REGNUM,
  83     /* Zero-delay loop next-after-last instruction.  */
  84     ARC_LP_END_REGNUM,
  85     /* Branch target address.  */
  86     ARC_BTA_REGNUM,
  87     ARC_LAST_AUX_REGNUM = ARC_BTA_REGNUM,
  88     ARC_LAST_REGNUM = ARC_LAST_AUX_REGNUM,
  89
  90     /* Additional ABI constants.  */
  91     ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM,
  92     ARC_LAST_ARG_REGNUM = ARC_R7_REGNUM,
  93     ARC_FIRST_CALLEE_SAVED_REGNUM = ARC_R13_REGNUM,
  94     ARC_LAST_CALLEE_SAVED_REGNUM = ARC_R25_REGNUM,
  95   };
  96
  97 /* Number of bytes in ARC register.  All ARC registers are considered 32-bit.
  98    Those registers, which are actually shorter has zero-on-read for extra bits.
  99    Longer registers are represented as pairs of 32-bit registers.  */
 100 #define ARC_REGISTER_SIZE  4
 101
 102 #define arc_print(fmt, args...) fprintf_unfiltered (gdb_stdlog, fmt, ##args)
 103
 104 extern int arc_debug;
 105
 106 /* Target-dependent information.  */
 107
 108 struct gdbarch_tdep
 109 {
 110   /* Offset to PC value in jump buffer.  If this is negative, longjmp
 111      support will be disabled.  */
 112   int jb_pc;
 113 };
 114
 115 /* Utility functions used by other ARC-specific modules.  */
 116
 117 static inline int
 118 arc_mach_is_arc600 (struct gdbarch *gdbarch)
 119 {
 120   return (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc600
 121           || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc601);
 122 }
 123
 124 static inline int
 125 arc_mach_is_arc700 (struct gdbarch *gdbarch)
 126 {
 127   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc700;
 128 }
 129
 130 static inline int
 131 arc_mach_is_arcv2 (struct gdbarch *gdbarch)
 132 {
 133   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
 134 }
 135
 136 /* ARC EM and ARC HS are unique BFD arches, however they share the same machine
 137    number as "ARCv2".  */
 138
 139 static inline bool
 140 arc_arch_is_hs (const struct bfd_arch_info* arch)
 141 {
 142   return startswith (arch->printable_name, "HS");
 143 }
 144
 145 static inline bool
 146 arc_arch_is_em (const struct bfd_arch_info* arch)
 147 {
 148   return startswith (arch->printable_name, "EM");
 149 }
 150
 151 /* Function to access ARC disassembler.  Underlying opcodes disassembler will
 152    print an instruction into stream specified in the INFO, so if it is
 153    undesired, then this stream should be set to some invisible stream, but it
 154    can't be set to an actual NULL value - that would cause a crash.  */
 155 int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
 156
 157 /* Return properly initialized disassemble_info for ARC disassembler - it will
 158    not print disassembled instructions to stderr.  */
 159
 160 struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch);
 161
 162 /* Get branch/jump target address for the INSN.  Note that this function
 163    returns branch target and doesn't evaluate if this branch is taken or not.
 164    For the indirect jumps value depends in register state, hence can change.
 165    It is an error to call this function for a non-branch instruction.  */
 166
 167 CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
 168
 169 /* Get address of next instruction after INSN, assuming linear execution (no
 170    taken branches).  If instruction has a delay slot, then returned value will
 171    point at the instruction in delay slot.  That is - "address of instruction +
 172    instruction length with LIMM".  */
 173
 174 CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
 175
 176 #endif /* ARC_TDEP_H */