1 /* Target dependent code for ARC architecture, for GDB.
3 Copyright 2005-2021 Free Software Foundation, Inc.
4 Contributed by Synopsys Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* Need disassemble_info. */
29 /* To simplify GDB code this enum assumes that internal regnums should be same
30 as architectural register numbers, i.e. PCL regnum is 63. This allows to
31 use internal GDB regnums as architectural numbers when dealing with
32 instruction encodings, for example when analyzing what are the registers
33 saved in function prologue. */
46 /* Global data pointer. */
52 /* Return address from interrupt. */
55 /* Return address from function. */
57 /* Accumulator registers. */
60 /* Zero-delay loop counter. */
61 ARC_LP_COUNT_REGNUM
= 60,
62 /* Reserved register number. There should never be a register with such
63 number, this name is needed only for a sanity check in
64 arc_cannot_(fetch|store)_register. */
66 /* Long-immediate value. This is not a physical register - if instruction
67 has register 62 as an operand, then this operand is a literal value
68 stored in the instruction memory right after the instruction itself.
69 This value is required in this enumeration as an architectural number
70 for instruction analysis. */
72 /* Program counter, aligned to 4-bytes, read-only. */
74 ARC_LAST_CORE_REGNUM
= ARC_PCL_REGNUM
,
77 /* Actual program counter. */
79 ARC_FIRST_AUX_REGNUM
= ARC_PC_REGNUM
,
80 /* Status register. */
82 /* Zero-delay loop start instruction. */
84 /* Zero-delay loop next-after-last instruction. */
86 /* Branch target address. */
88 /* Exception return address. */
90 ARC_LAST_AUX_REGNUM
= ARC_ERET_REGNUM
,
91 ARC_LAST_REGNUM
= ARC_LAST_AUX_REGNUM
,
93 /* Additional ABI constants. */
94 ARC_FIRST_ARG_REGNUM
= ARC_R0_REGNUM
,
95 ARC_LAST_ARG_REGNUM
= ARC_R7_REGNUM
,
96 ARC_FIRST_CALLEE_SAVED_REGNUM
= ARC_R13_REGNUM
,
97 ARC_LAST_CALLEE_SAVED_REGNUM
= ARC_R25_REGNUM
,
100 /* Number of bytes in ARC register. All ARC registers are considered 32-bit.
101 Those registers, which are actually shorter has zero-on-read for extra bits.
102 Longer registers are represented as pairs of 32-bit registers. */
103 #define ARC_REGISTER_SIZE 4
105 /* STATUS32 register: hardware loops disabled bit. */
106 #define ARC_STATUS32_L_MASK (1 << 12)
107 /* STATUS32 register: current instruction is a delay slot. */
108 #define ARC_STATUS32_DE_MASK (1 << 6)
110 /* Special value for register offset arrays. */
111 #define ARC_OFFSET_NO_REGISTER (-1)
113 #define arc_print(fmt, args...) fprintf_unfiltered (gdb_stdlog, fmt, ##args)
115 extern bool arc_debug
;
117 /* Target-dependent information. */
121 /* Offset to PC value in jump buffer. If this is negative, longjmp
122 support will be disabled. */
125 /* Whether target has hardware (aka zero-delay) loops. */
128 /* Detect sigtramp. */
129 bool (*is_sigtramp
) (struct frame_info
*);
131 /* Get address of sigcontext for sigtramp. */
132 CORE_ADDR (*sigcontext_addr
) (struct frame_info
*);
134 /* Offset of registers in `struct sigcontext'. */
135 const int *sc_reg_offset
;
137 /* Number of registers in sc_reg_offsets. Most likely a ARC_LAST_REGNUM,
138 but in theory it could be less, so it is kept separate. */
142 /* Utility functions used by other ARC-specific modules. */
145 arc_mach_is_arc600 (struct gdbarch
*gdbarch
)
147 return (gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_arc_arc600
148 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_arc_arc601
);
152 arc_mach_is_arc700 (struct gdbarch
*gdbarch
)
154 return gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_arc_arc700
;
158 arc_mach_is_arcv2 (struct gdbarch
*gdbarch
)
160 return gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_arc_arcv2
;
163 /* ARC EM and ARC HS are unique BFD arches, however they share the same machine
164 number as "ARCv2". */
167 arc_arch_is_hs (const struct bfd_arch_info
* arch
)
169 return startswith (arch
->printable_name
, "HS");
173 arc_arch_is_em (const struct bfd_arch_info
* arch
)
175 return startswith (arch
->printable_name
, "EM");
178 /* Function to access ARC disassembler. Underlying opcodes disassembler will
179 print an instruction into stream specified in the INFO, so if it is
180 undesired, then this stream should be set to some invisible stream, but it
181 can't be set to an actual NULL value - that would cause a crash. */
182 int arc_delayed_print_insn (bfd_vma addr
, struct disassemble_info
*info
);
184 /* Return properly initialized disassemble_info for ARC disassembler - it will
185 not print disassembled instructions to stderr. */
187 struct disassemble_info
arc_disassemble_info (struct gdbarch
*gdbarch
);
189 /* Get branch/jump target address for the INSN. Note that this function
190 returns branch target and doesn't evaluate if this branch is taken or not.
191 For the indirect jumps value depends in register state, hence can change.
192 It is an error to call this function for a non-branch instruction. */
194 CORE_ADDR
arc_insn_get_branch_target (const struct arc_instruction
&insn
);
196 /* Get address of next instruction after INSN, assuming linear execution (no
197 taken branches). If instruction has a delay slot, then returned value will
198 point at the instruction in delay slot. That is - "address of instruction +
199 instruction length with LIMM". */
201 CORE_ADDR
arc_insn_get_linear_next_pc (const struct arc_instruction
&insn
);
203 /* Create an arc_arch_features instance from the provided data. */
205 arc_arch_features
arc_arch_features_create (const bfd
*abfd
,
206 const unsigned long mach
);
208 #endif /* ARC_TDEP_H */