1 /* Common target-dependent functionality for AArch64.
3 Copyright (C) 2017-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #ifndef ARCH_AARCH64_H
21 #define ARCH_AARCH64_H
23 #include "gdbsupport/tdesc.h"
25 /* Holds information on what architectural features are available. This is
26 used to select register sets. */
27 struct aarch64_features
29 /* A non zero VQ value indicates both the presence of SVE and the
30 Vector Quotient - the number of 128-bit chunks in an SVE Z
33 The maximum value for VQ is 16 (5 bits). */
38 /* A positive TLS value indicates the number of TLS registers available. */
40 /* The allowed values for SVQ are the following:
42 0 - SME is not supported/available.
43 1 - SME is available, SVL is 16 bytes / 128-bit.
44 2 - SME is available, SVL is 32 bytes / 256-bit.
45 4 - SME is available, SVL is 64 bytes / 512-bit.
46 8 - SME is available, SVL is 128 bytes / 1024-bit.
47 16 - SME is available, SVL is 256 bytes / 2048-bit.
49 These use at most 5 bits to represent. */
52 /* Whether SME2 is supported. */
56 inline bool operator==(const aarch64_features
&lhs
, const aarch64_features
&rhs
)
58 return lhs
.vq
== rhs
.vq
59 && lhs
.pauth
== rhs
.pauth
63 && lhs
.sme2
== rhs
.sme2
;
69 struct hash
<aarch64_features
>
71 std::size_t operator()(const aarch64_features
&features
) const noexcept
76 h
= h
<< 1 | features
.pauth
;
77 h
= h
<< 1 | features
.mte
;
78 /* Shift by two bits for now. We may need to increase this in the future
79 if more TLS registers get added. */
80 h
= h
<< 2 | features
.tls
;
82 /* Make sure the SVQ values are within the limits. */
83 gdb_assert (features
.svq
>= 0);
84 gdb_assert (features
.svq
<= 16);
85 h
= h
<< 5 | (features
.svq
& 0x5);
88 h
= h
<< 1 | features
.sme2
;
94 /* Create the aarch64 target description. */
97 aarch64_create_target_description (const aarch64_features
&features
);
99 /* Given a pointer value POINTER and a MASK of non-address bits, remove the
100 non-address bits from the pointer and sign-extend the result if required.
101 The sign-extension is required so we can handle kernel addresses
103 CORE_ADDR
aarch64_remove_top_bits (CORE_ADDR pointer
, CORE_ADDR mask
);
105 /* Given CMASK and DMASK the two PAC mask registers, return the correct PAC
106 mask to use for removing non-address bits from a pointer. */
108 aarch64_mask_from_pac_registers (const CORE_ADDR cmask
, const CORE_ADDR dmask
);
110 /* Register numbers of various important registers.
111 Note that on SVE, the Z registers reuse the V register numbers and the V
112 registers become pseudo registers. */
115 AARCH64_X0_REGNUM
, /* First integer register. */
116 AARCH64_FP_REGNUM
= AARCH64_X0_REGNUM
+ 29, /* Frame register, if used. */
117 AARCH64_LR_REGNUM
= AARCH64_X0_REGNUM
+ 30, /* Return address. */
118 AARCH64_SP_REGNUM
, /* Stack pointer. */
119 AARCH64_PC_REGNUM
, /* Program counter. */
120 AARCH64_CPSR_REGNUM
, /* Current Program Status Register. */
121 AARCH64_V0_REGNUM
, /* First fp/vec register. */
122 AARCH64_V31_REGNUM
= AARCH64_V0_REGNUM
+ 31, /* Last fp/vec register. */
123 AARCH64_SVE_Z0_REGNUM
= AARCH64_V0_REGNUM
, /* First SVE Z register. */
124 AARCH64_SVE_Z31_REGNUM
= AARCH64_V31_REGNUM
, /* Last SVE Z register. */
125 AARCH64_FPSR_REGNUM
, /* Floating Point Status Register. */
126 AARCH64_FPCR_REGNUM
, /* Floating Point Control Register. */
127 AARCH64_SVE_P0_REGNUM
, /* First SVE predicate register. */
128 AARCH64_SVE_P15_REGNUM
= AARCH64_SVE_P0_REGNUM
+ 15, /* Last SVE predicate
130 AARCH64_SVE_FFR_REGNUM
, /* SVE First Fault Register. */
131 AARCH64_SVE_VG_REGNUM
, /* SVE Vector Granule. */
133 /* Other useful registers. */
134 AARCH64_LAST_X_ARG_REGNUM
= AARCH64_X0_REGNUM
+ 7,
135 AARCH64_STRUCT_RETURN_REGNUM
= AARCH64_X0_REGNUM
+ 8,
136 AARCH64_LAST_V_ARG_REGNUM
= AARCH64_V0_REGNUM
+ 7
139 /* Sizes of various AArch64 registers. */
140 #define AARCH64_TLS_REGISTER_SIZE 8
141 #define V_REGISTER_SIZE 16
143 /* PAC-related constants. */
144 /* Bit 55 is used to select between a kernel-space and user-space address. */
145 #define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL
146 /* Mask with 1's in bits 55~63, used to remove the top byte of pointers
147 (Top Byte Ignore). */
148 #define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL
150 /* Pseudo register base numbers. */
151 #define AARCH64_Q0_REGNUM 0
152 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
153 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
154 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
155 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
156 #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
158 #define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base)
159 #define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1)
160 /* The high versions of these masks are used for bare metal/kernel-mode pointer
161 authentication support. */
162 #define AARCH64_PAUTH_DMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 2)
163 #define AARCH64_PAUTH_CMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 3)
165 /* This size is only meant for Linux, not bare metal. QEMU exposes 4 masks. */
166 #define AARCH64_PAUTH_REGS_SIZE (16)
168 #define AARCH64_X_REGS_NUM 31
169 #define AARCH64_V_REGS_NUM 32
170 #define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM
171 #define AARCH64_SVE_P_REGS_NUM 16
172 #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
173 #define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
175 /* There are a number of ways of expressing the current SVE vector size:
178 The number of bytes in an SVE Z register.
179 VQ : Vector Quotient.
180 The number of 128bit chunks in an SVE Z register.
182 The number of 64bit chunks in an SVE Z register. */
184 #define sve_vg_from_vl(vl) ((vl) / 8)
185 #define sve_vl_from_vg(vg) ((vg) * 8)
186 #ifndef sve_vq_from_vl
187 #define sve_vq_from_vl(vl) ((vl) / 0x10)
189 #ifndef sve_vl_from_vq
190 #define sve_vl_from_vq(vq) ((vq) * 0x10)
192 #define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg)))
193 #define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq)))
196 /* Maximum supported VQ value. Increase if required. */
197 #define AARCH64_MAX_SVE_VQ 16
201 Some of these definitions are not found in the Architecture Reference
202 Manual, but we use them so we can keep a similar standard compared to the
203 SVE definitions that the Linux Kernel uses. Otherwise it can get
206 SVL : Streaming Vector Length.
207 Although the documentation handles SVL in bits, we do it in
208 bytes to match what we do for SVE.
210 The streaming vector length dictates the size of the ZA register and
211 the size of the SVE registers when in streaming mode.
213 SVQ : Streaming Vector Quotient.
214 The number of 128-bit chunks in an SVE Z register or the size of
215 each dimension of the SME ZA matrix.
217 SVG : Streaming Vector Granule.
218 The number of 64-bit chunks in an SVE Z register or the size of
219 half a SME ZA matrix dimension. The SVG definition was added so
220 we keep a familiar definition when dealing with SVE registers in
223 /* The total number of tiles. This is always fixed regardless of the
224 streaming vector length (svl). */
225 #define AARCH64_ZA_TILES_NUM 31
226 /* svl limits for SME. */
227 #define AARCH64_SME_MIN_SVL 128
228 #define AARCH64_SME_MAX_SVL 2048
230 /* Size of the SME2 ZT0 register in bytes. */
231 #define AARCH64_SME2_ZT0_SIZE 64
233 #endif /* ARCH_AARCH64_H */