gdb/arch/arm.c

   1 /* Common target dependent code for GDB on ARM systems.
   2
   3    Copyright (C) 1988-2022 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "gdbsupport/common-defs.h"
  21 #include "gdbsupport/common-regcache.h"
  22 #include "arm.h"
  23
  24 #include "../features/arm/arm-core.c"
  25 #include "../features/arm/arm-vfpv2.c"
  26 #include "../features/arm/arm-vfpv3.c"
  27 #include "../features/arm/xscale-iwmmxt.c"
  28 #include "../features/arm/arm-m-profile.c"
  29 #include "../features/arm/arm-m-profile-with-fpa.c"
  30 #include "../features/arm/arm-m-profile-mve.c"
  31
  32 /* See arm.h.  */
  33
  34 int
  35 thumb_insn_size (unsigned short inst1)
  36 {
  37   if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
  38     return 4;
  39   else
  40     return 2;
  41 }
  42
  43 /* See arm.h.  */
  44
  45 int
  46 condition_true (unsigned long cond, unsigned long status_reg)
  47 {
  48   if (cond == INST_AL || cond == INST_NV)
  49     return 1;
  50
  51   switch (cond)
  52     {
  53     case INST_EQ:
  54       return ((status_reg & FLAG_Z) != 0);
  55     case INST_NE:
  56       return ((status_reg & FLAG_Z) == 0);
  57     case INST_CS:
  58       return ((status_reg & FLAG_C) != 0);
  59     case INST_CC:
  60       return ((status_reg & FLAG_C) == 0);
  61     case INST_MI:
  62       return ((status_reg & FLAG_N) != 0);
  63     case INST_PL:
  64       return ((status_reg & FLAG_N) == 0);
  65     case INST_VS:
  66       return ((status_reg & FLAG_V) != 0);
  67     case INST_VC:
  68       return ((status_reg & FLAG_V) == 0);
  69     case INST_HI:
  70       return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
  71     case INST_LS:
  72       return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
  73     case INST_GE:
  74       return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
  75     case INST_LT:
  76       return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
  77     case INST_GT:
  78       return (((status_reg & FLAG_Z) == 0)
  79               && (((status_reg & FLAG_N) == 0)
  80                   == ((status_reg & FLAG_V) == 0)));
  81     case INST_LE:
  82       return (((status_reg & FLAG_Z) != 0)
  83               || (((status_reg & FLAG_N) == 0)
  84                   != ((status_reg & FLAG_V) == 0)));
  85     }
  86   return 1;
  87 }
  88
  89
  90 /* See arm.h.  */
  91
  92 int
  93 thumb_advance_itstate (unsigned int itstate)
  94 {
  95   /* Preserve IT[7:5], the first three bits of the condition.  Shift
  96      the upcoming condition flags left by one bit.  */
  97   itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
  98
  99   /* If we have finished the IT block, clear the state.  */
 100   if ((itstate & 0x0f) == 0)
 101     itstate = 0;
 102
 103   return itstate;
 104 }
 105
 106 /* See arm.h.  */
 107
 108 int
 109 arm_instruction_changes_pc (uint32_t this_instr)
 110 {
 111   if (bits (this_instr, 28, 31) == INST_NV)
 112     /* Unconditional instructions.  */
 113     switch (bits (this_instr, 24, 27))
 114       {
 115       case 0xa:
 116       case 0xb:
 117         /* Branch with Link and change to Thumb.  */
 118         return 1;
 119       case 0xc:
 120       case 0xd:
 121       case 0xe:
 122         /* Coprocessor register transfer.  */
 123         if (bits (this_instr, 12, 15) == 15)
 124           error (_("Invalid update to pc in instruction"));
 125         return 0;
 126       default:
 127         return 0;
 128       }
 129   else
 130     switch (bits (this_instr, 25, 27))
 131       {
 132       case 0x0:
 133         if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
 134           {
 135             /* Multiplies and extra load/stores.  */
 136             if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
 137               /* Neither multiplies nor extension load/stores are allowed
 138                  to modify PC.  */
 139               return 0;
 140
 141             /* Otherwise, miscellaneous instructions.  */
 142
 143             /* BX <reg>, BXJ <reg>, BLX <reg> */
 144             if (bits (this_instr, 4, 27) == 0x12fff1
 145                 || bits (this_instr, 4, 27) == 0x12fff2
 146                 || bits (this_instr, 4, 27) == 0x12fff3)
 147               return 1;
 148
 149             /* Other miscellaneous instructions are unpredictable if they
 150                modify PC.  */
 151             return 0;
 152           }
 153         /* Data processing instruction.  */
 154         /* Fall through.  */
 155
 156       case 0x1:
 157         if (bits (this_instr, 12, 15) == 15)
 158           return 1;
 159         else
 160           return 0;
 161
 162       case 0x2:
 163       case 0x3:
 164         /* Media instructions and architecturally undefined instructions.  */
 165         if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
 166           return 0;
 167
 168         /* Stores.  */
 169         if (bit (this_instr, 20) == 0)
 170           return 0;
 171
 172         /* Loads.  */
 173         if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
 174           return 1;
 175         else
 176           return 0;
 177
 178       case 0x4:
 179         /* Load/store multiple.  */
 180         if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
 181           return 1;
 182         else
 183           return 0;
 184
 185       case 0x5:
 186         /* Branch and branch with link.  */
 187         return 1;
 188
 189       case 0x6:
 190       case 0x7:
 191         /* Coprocessor transfers or SWIs can not affect PC.  */
 192         return 0;
 193
 194       default:
 195         internal_error (__FILE__, __LINE__, _("bad value in switch"));
 196       }
 197 }
 198
 199 /* See arm.h.  */
 200
 201 int
 202 thumb_instruction_changes_pc (unsigned short inst)
 203 {
 204   if ((inst & 0xff00) == 0xbd00)        /* pop {rlist, pc} */
 205     return 1;
 206
 207   if ((inst & 0xf000) == 0xd000)        /* conditional branch */
 208     return 1;
 209
 210   if ((inst & 0xf800) == 0xe000)        /* unconditional branch */
 211     return 1;
 212
 213   if ((inst & 0xff00) == 0x4700)        /* bx REG, blx REG */
 214     return 1;
 215
 216   if ((inst & 0xff87) == 0x4687)        /* mov pc, REG */
 217     return 1;
 218
 219   if ((inst & 0xf500) == 0xb100)        /* CBNZ or CBZ.  */
 220     return 1;
 221
 222   return 0;
 223 }
 224
 225
 226 /* See arm.h.  */
 227
 228 int
 229 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
 230 {
 231   if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
 232     {
 233       /* Branches and miscellaneous control instructions.  */
 234
 235       if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
 236         {
 237           /* B, BL, BLX.  */
 238           return 1;
 239         }
 240       else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
 241         {
 242           /* SUBS PC, LR, #imm8.  */
 243           return 1;
 244         }
 245       else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
 246         {
 247           /* Conditional branch.  */
 248           return 1;
 249         }
 250
 251       return 0;
 252     }
 253
 254   if ((inst1 & 0xfe50) == 0xe810)
 255     {
 256       /* Load multiple or RFE.  */
 257
 258       if (bit (inst1, 7) && !bit (inst1, 8))
 259         {
 260           /* LDMIA or POP */
 261           if (bit (inst2, 15))
 262             return 1;
 263         }
 264       else if (!bit (inst1, 7) && bit (inst1, 8))
 265         {
 266           /* LDMDB */
 267           if (bit (inst2, 15))
 268             return 1;
 269         }
 270       else if (bit (inst1, 7) && bit (inst1, 8))
 271         {
 272           /* RFEIA */
 273           return 1;
 274         }
 275       else if (!bit (inst1, 7) && !bit (inst1, 8))
 276         {
 277           /* RFEDB */
 278           return 1;
 279         }
 280
 281       return 0;
 282     }
 283
 284   if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
 285     {
 286       /* MOV PC or MOVS PC.  */
 287       return 1;
 288     }
 289
 290   if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
 291     {
 292       /* LDR PC.  */
 293       if (bits (inst1, 0, 3) == 15)
 294         return 1;
 295       if (bit (inst1, 7))
 296         return 1;
 297       if (bit (inst2, 11))
 298         return 1;
 299       if ((inst2 & 0x0fc0) == 0x0000)
 300         return 1;
 301
 302       return 0;
 303     }
 304
 305   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
 306     {
 307       /* TBB.  */
 308       return 1;
 309     }
 310
 311   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
 312     {
 313       /* TBH.  */
 314       return 1;
 315     }
 316
 317   return 0;
 318 }
 319
 320 /* See arm.h.  */
 321
 322 unsigned long
 323 shifted_reg_val (struct regcache *regcache, unsigned long inst,
 324                  int carry, unsigned long pc_val, unsigned long status_reg)
 325 {
 326   unsigned long res, shift;
 327   int rm = bits (inst, 0, 3);
 328   unsigned long shifttype = bits (inst, 5, 6);
 329
 330   if (bit (inst, 4))
 331     {
 332       int rs = bits (inst, 8, 11);
 333       shift = (rs == 15
 334                ? pc_val + 8
 335                : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
 336     }
 337   else
 338     shift = bits (inst, 7, 11);
 339
 340   res = (rm == ARM_PC_REGNUM
 341          ? (pc_val + (bit (inst, 4) ? 12 : 8))
 342          : regcache_raw_get_unsigned (regcache, rm));
 343
 344   switch (shifttype)
 345     {
 346     case 0:                     /* LSL */
 347       res = shift >= 32 ? 0 : res << shift;
 348       break;
 349
 350     case 1:                     /* LSR */
 351       res = shift >= 32 ? 0 : res >> shift;
 352       break;
 353
 354     case 2:                     /* ASR */
 355       if (shift >= 32)
 356         shift = 31;
 357       res = ((res & 0x80000000L)
 358              ? ~((~res) >> shift) : res >> shift);
 359       break;
 360
 361     case 3:                     /* ROR/RRX */
 362       shift &= 31;
 363       if (shift == 0)
 364         res = (res >> 1) | (carry ? 0x80000000L : 0);
 365       else
 366         res = (res >> shift) | (res << (32 - shift));
 367       break;
 368     }
 369
 370   return res & 0xffffffff;
 371 }
 372
 373 /* See arch/arm.h.  */
 374
 375 target_desc *
 376 arm_create_target_description (arm_fp_type fp_type)
 377 {
 378   target_desc_up tdesc = allocate_target_description ();
 379
 380 #ifndef IN_PROCESS_AGENT
 381   if (fp_type == ARM_FP_TYPE_IWMMXT)
 382     set_tdesc_architecture (tdesc.get (), "iwmmxt");
 383   else
 384     set_tdesc_architecture (tdesc.get (), "arm");
 385 #endif
 386
 387   long regnum = 0;
 388
 389   regnum = create_feature_arm_arm_core (tdesc.get (), regnum);
 390
 391   switch (fp_type)
 392     {
 393     case ARM_FP_TYPE_NONE:
 394       break;
 395
 396     case ARM_FP_TYPE_VFPV2:
 397       regnum = create_feature_arm_arm_vfpv2 (tdesc.get (), regnum);
 398       break;
 399
 400     case ARM_FP_TYPE_VFPV3:
 401       regnum = create_feature_arm_arm_vfpv3 (tdesc.get (), regnum);
 402       break;
 403
 404     case ARM_FP_TYPE_IWMMXT:
 405       regnum = create_feature_arm_xscale_iwmmxt (tdesc.get (), regnum);
 406       break;
 407
 408     default:
 409       error (_("Invalid Arm FP type: %d"), fp_type);
 410     }
 411
 412   return tdesc.release ();
 413 }
 414
 415 /* See arch/arm.h.  */
 416
 417 target_desc *
 418 arm_create_mprofile_target_description (arm_m_profile_type m_type)
 419 {
 420   target_desc *tdesc = allocate_target_description ().release ();
 421
 422 #ifndef IN_PROCESS_AGENT
 423   set_tdesc_architecture (tdesc, "arm");
 424 #endif
 425
 426   long regnum = 0;
 427
 428   switch (m_type)
 429     {
 430     case ARM_M_TYPE_M_PROFILE:
 431       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 432       break;
 433
 434     case ARM_M_TYPE_VFP_D16:
 435       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 436       regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
 437       break;
 438
 439     case ARM_M_TYPE_WITH_FPA:
 440       regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum);
 441       break;
 442
 443     case ARM_M_TYPE_MVE:
 444       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 445       regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
 446       regnum = create_feature_arm_arm_m_profile_mve (tdesc, regnum);
 447       break;
 448
 449     default:
 450       error (_("Invalid Arm M type: %d"), m_type);
 451     }
 452
 453   return tdesc;
 454 }