1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "gdbsupport/common-defs.h"
21 #include "gdbsupport/common-regcache.h"
24 #include "../features/arm/arm-core.c"
25 #include "../features/arm/arm-vfpv2.c"
26 #include "../features/arm/arm-vfpv3.c"
27 #include "../features/arm/xscale-iwmmxt.c"
28 #include "../features/arm/arm-m-profile.c"
29 #include "../features/arm/arm-m-profile-with-fpa.c"
30 #include "../features/arm/arm-m-profile-mve.c"
35 thumb_insn_size (unsigned short inst1
)
37 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
46 condition_true (unsigned long cond
, unsigned long status_reg
)
48 if (cond
== INST_AL
|| cond
== INST_NV
)
54 return ((status_reg
& FLAG_Z
) != 0);
56 return ((status_reg
& FLAG_Z
) == 0);
58 return ((status_reg
& FLAG_C
) != 0);
60 return ((status_reg
& FLAG_C
) == 0);
62 return ((status_reg
& FLAG_N
) != 0);
64 return ((status_reg
& FLAG_N
) == 0);
66 return ((status_reg
& FLAG_V
) != 0);
68 return ((status_reg
& FLAG_V
) == 0);
70 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
72 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
74 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
76 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
78 return (((status_reg
& FLAG_Z
) == 0)
79 && (((status_reg
& FLAG_N
) == 0)
80 == ((status_reg
& FLAG_V
) == 0)));
82 return (((status_reg
& FLAG_Z
) != 0)
83 || (((status_reg
& FLAG_N
) == 0)
84 != ((status_reg
& FLAG_V
) == 0)));
93 thumb_advance_itstate (unsigned int itstate
)
95 /* Preserve IT[7:5], the first three bits of the condition. Shift
96 the upcoming condition flags left by one bit. */
97 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
99 /* If we have finished the IT block, clear the state. */
100 if ((itstate
& 0x0f) == 0)
109 arm_instruction_changes_pc (uint32_t this_instr
)
111 if (bits (this_instr
, 28, 31) == INST_NV
)
112 /* Unconditional instructions. */
113 switch (bits (this_instr
, 24, 27))
117 /* Branch with Link and change to Thumb. */
122 /* Coprocessor register transfer. */
123 if (bits (this_instr
, 12, 15) == 15)
124 error (_("Invalid update to pc in instruction"));
130 switch (bits (this_instr
, 25, 27))
133 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
135 /* Multiplies and extra load/stores. */
136 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
137 /* Neither multiplies nor extension load/stores are allowed
141 /* Otherwise, miscellaneous instructions. */
143 /* BX <reg>, BXJ <reg>, BLX <reg> */
144 if (bits (this_instr
, 4, 27) == 0x12fff1
145 || bits (this_instr
, 4, 27) == 0x12fff2
146 || bits (this_instr
, 4, 27) == 0x12fff3)
149 /* Other miscellaneous instructions are unpredictable if they
153 /* Data processing instruction. */
157 if (bits (this_instr
, 12, 15) == 15)
164 /* Media instructions and architecturally undefined instructions. */
165 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
169 if (bit (this_instr
, 20) == 0)
173 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
179 /* Load/store multiple. */
180 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
186 /* Branch and branch with link. */
191 /* Coprocessor transfers or SWIs can not affect PC. */
195 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
202 thumb_instruction_changes_pc (unsigned short inst
)
204 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
207 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
210 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
213 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
216 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
219 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
229 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
231 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
233 /* Branches and miscellaneous control instructions. */
235 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
240 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
242 /* SUBS PC, LR, #imm8. */
245 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
247 /* Conditional branch. */
254 if ((inst1
& 0xfe50) == 0xe810)
256 /* Load multiple or RFE. */
258 if (bit (inst1
, 7) && !bit (inst1
, 8))
264 else if (!bit (inst1
, 7) && bit (inst1
, 8))
270 else if (bit (inst1
, 7) && bit (inst1
, 8))
275 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
284 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
286 /* MOV PC or MOVS PC. */
290 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
293 if (bits (inst1
, 0, 3) == 15)
299 if ((inst2
& 0x0fc0) == 0x0000)
305 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
311 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
323 shifted_reg_val (struct regcache
*regcache
, unsigned long inst
,
324 int carry
, unsigned long pc_val
, unsigned long status_reg
)
326 unsigned long res
, shift
;
327 int rm
= bits (inst
, 0, 3);
328 unsigned long shifttype
= bits (inst
, 5, 6);
332 int rs
= bits (inst
, 8, 11);
335 : regcache_raw_get_unsigned (regcache
, rs
)) & 0xFF;
338 shift
= bits (inst
, 7, 11);
340 res
= (rm
== ARM_PC_REGNUM
341 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
342 : regcache_raw_get_unsigned (regcache
, rm
));
347 res
= shift
>= 32 ? 0 : res
<< shift
;
351 res
= shift
>= 32 ? 0 : res
>> shift
;
357 res
= ((res
& 0x80000000L
)
358 ? ~((~res
) >> shift
) : res
>> shift
);
361 case 3: /* ROR/RRX */
364 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
366 res
= (res
>> shift
) | (res
<< (32 - shift
));
370 return res
& 0xffffffff;
373 /* See arch/arm.h. */
376 arm_create_target_description (arm_fp_type fp_type
)
378 target_desc_up tdesc
= allocate_target_description ();
380 #ifndef IN_PROCESS_AGENT
381 if (fp_type
== ARM_FP_TYPE_IWMMXT
)
382 set_tdesc_architecture (tdesc
.get (), "iwmmxt");
384 set_tdesc_architecture (tdesc
.get (), "arm");
389 regnum
= create_feature_arm_arm_core (tdesc
.get (), regnum
);
393 case ARM_FP_TYPE_NONE
:
396 case ARM_FP_TYPE_VFPV2
:
397 regnum
= create_feature_arm_arm_vfpv2 (tdesc
.get (), regnum
);
400 case ARM_FP_TYPE_VFPV3
:
401 regnum
= create_feature_arm_arm_vfpv3 (tdesc
.get (), regnum
);
404 case ARM_FP_TYPE_IWMMXT
:
405 regnum
= create_feature_arm_xscale_iwmmxt (tdesc
.get (), regnum
);
409 error (_("Invalid Arm FP type: %d"), fp_type
);
412 return tdesc
.release ();
415 /* See arch/arm.h. */
418 arm_create_mprofile_target_description (arm_m_profile_type m_type
)
420 target_desc
*tdesc
= allocate_target_description ().release ();
422 #ifndef IN_PROCESS_AGENT
423 set_tdesc_architecture (tdesc
, "arm");
430 case ARM_M_TYPE_M_PROFILE
:
431 regnum
= create_feature_arm_arm_m_profile (tdesc
, regnum
);
434 case ARM_M_TYPE_VFP_D16
:
435 regnum
= create_feature_arm_arm_m_profile (tdesc
, regnum
);
436 regnum
= create_feature_arm_arm_vfpv2 (tdesc
, regnum
);
439 case ARM_M_TYPE_WITH_FPA
:
440 regnum
= create_feature_arm_arm_m_profile_with_fpa (tdesc
, regnum
);
444 regnum
= create_feature_arm_arm_m_profile (tdesc
, regnum
);
445 regnum
= create_feature_arm_arm_vfpv2 (tdesc
, regnum
);
446 regnum
= create_feature_arm_arm_m_profile_mve (tdesc
, regnum
);
450 error (_("Invalid Arm M type: %d"), m_type
);