1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
33 #include "target-float.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "dwarf2/frame.h"
44 #include "prologue-value.h"
46 #include "target-descriptions.h"
47 #include "user-regs.h"
48 #include "observable.h"
49 #include "count-one-bits.h"
52 #include "arch/arm-get-next-pcs.h"
54 #include "gdb/sim-arm.h"
57 #include "coff/internal.h"
61 #include "record-full.h"
67 #include "gdbsupport/selftest.h"
70 static bool arm_debug
;
72 /* Print an "arm" debug statement. */
74 #define arm_debug_printf(fmt, ...) \
75 debug_prefixed_printf_cond (arm_debug, "arm", fmt, ##__VA_ARGS__)
77 /* Macros for setting and testing a bit in a minimal symbol that marks
78 it as Thumb function. The MSB of the minimal symbol's "info" field
79 is used for this purpose.
81 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
82 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
84 #define MSYMBOL_SET_SPECIAL(msym) \
85 (msym)->set_target_flag_1 (true)
87 #define MSYMBOL_IS_SPECIAL(msym) \
88 (msym)->target_flag_1 ()
90 struct arm_mapping_symbol
95 bool operator< (const arm_mapping_symbol
&other
) const
96 { return this->value
< other
.value
; }
99 typedef std::vector
<arm_mapping_symbol
> arm_mapping_symbol_vec
;
103 explicit arm_per_bfd (size_t num_sections
)
104 : section_maps (new arm_mapping_symbol_vec
[num_sections
]),
105 section_maps_sorted (new bool[num_sections
] ())
108 DISABLE_COPY_AND_ASSIGN (arm_per_bfd
);
110 /* Information about mapping symbols ($a, $d, $t) in the objfile.
112 The format is an array of vectors of arm_mapping_symbols, there is one
113 vector for each section of the objfile (the array is index by BFD section
116 For each section, the vector of arm_mapping_symbol is sorted by
117 symbol value (address). */
118 std::unique_ptr
<arm_mapping_symbol_vec
[]> section_maps
;
120 /* For each corresponding element of section_maps above, is this vector
122 std::unique_ptr
<bool[]> section_maps_sorted
;
125 /* Per-bfd data used for mapping symbols. */
126 static bfd_key
<arm_per_bfd
> arm_bfd_data_key
;
128 /* The list of available "set arm ..." and "show arm ..." commands. */
129 static struct cmd_list_element
*setarmcmdlist
= NULL
;
130 static struct cmd_list_element
*showarmcmdlist
= NULL
;
132 /* The type of floating-point to use. Keep this in sync with enum
133 arm_float_model, and the help string in _initialize_arm_tdep. */
134 static const char *const fp_model_strings
[] =
144 /* A variable that can be configured by the user. */
145 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
146 static const char *current_fp_model
= "auto";
148 /* The ABI to use. Keep this in sync with arm_abi_kind. */
149 static const char *const arm_abi_strings
[] =
157 /* A variable that can be configured by the user. */
158 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
159 static const char *arm_abi_string
= "auto";
161 /* The execution mode to assume. */
162 static const char *const arm_mode_strings
[] =
170 static const char *arm_fallback_mode_string
= "auto";
171 static const char *arm_force_mode_string
= "auto";
173 /* The standard register names, and all the valid aliases for them. Note
174 that `fp', `sp' and `pc' are not added in this alias list, because they
175 have been added as builtin user registers in
176 std-regs.c:_initialize_frame_reg. */
181 } arm_register_aliases
[] = {
182 /* Basic register numbers. */
199 /* Synonyms (argument and variable registers). */
212 /* Other platform-specific names for r9. */
218 /* Names used by GCC (not listed in the ARM EABI). */
220 /* A special name from the older ATPCS. */
224 static const char *const arm_register_names
[] =
225 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
226 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
227 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
228 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
229 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
230 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
231 "fps", "cpsr" }; /* 24 25 */
233 /* Holds the current set of options to be passed to the disassembler. */
234 static char *arm_disassembler_options
;
236 /* Valid register name styles. */
237 static const char **valid_disassembly_styles
;
239 /* Disassembly style to use. Default to "std" register names. */
240 static const char *disassembly_style
;
242 /* All possible arm target descriptors. */
243 static struct target_desc
*tdesc_arm_list
[ARM_FP_TYPE_INVALID
];
244 static struct target_desc
*tdesc_arm_mprofile_list
[ARM_M_TYPE_INVALID
];
246 /* This is used to keep the bfd arch_info in sync with the disassembly
248 static void set_disassembly_style_sfunc (const char *, int,
249 struct cmd_list_element
*);
250 static void show_disassembly_style_sfunc (struct ui_file
*, int,
251 struct cmd_list_element
*,
254 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
255 readable_regcache
*regcache
,
256 int regnum
, gdb_byte
*buf
);
257 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
258 struct regcache
*regcache
,
259 int regnum
, const gdb_byte
*buf
);
262 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
265 /* get_next_pcs operations. */
266 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
267 arm_get_next_pcs_read_memory_unsigned_integer
,
268 arm_get_next_pcs_syscall_next_pc
,
269 arm_get_next_pcs_addr_bits_remove
,
270 arm_get_next_pcs_is_thumb
,
274 struct arm_prologue_cache
276 /* The stack pointer at the time this frame was created; i.e. the
277 caller's stack pointer when this function was called. It is used
278 to identify this frame. */
281 /* Additional stack pointers used by M-profile with Security extension. */
282 /* Use msp_s / psp_s to hold the values of msp / psp when there is
283 no Security extension. */
289 /* Active stack pointer. */
290 int active_sp_regnum
;
292 /* The frame base for this frame is just prev_sp - frame size.
293 FRAMESIZE is the distance from the frame pointer to the
294 initial stack pointer. */
298 /* The register used to hold the frame pointer for this frame. */
301 /* True if the return address is signed, false otherwise. */
302 gdb::optional
<bool> ra_signed_state
;
304 /* Saved register offsets. */
305 trad_frame_saved_reg
*saved_regs
;
307 arm_prologue_cache() = default;
310 /* Initialize stack pointers, and flag the active one. */
313 arm_cache_init_sp (int regnum
, CORE_ADDR
* member
,
314 struct arm_prologue_cache
*cache
,
315 struct frame_info
*frame
)
317 CORE_ADDR val
= get_frame_register_unsigned (frame
, regnum
);
318 if (val
== cache
->sp
)
319 cache
->active_sp_regnum
= regnum
;
324 /* Initialize CACHE fields for which zero is not adequate (CACHE is
325 expected to have been ZALLOC'ed before calling this function). */
328 arm_cache_init (struct arm_prologue_cache
*cache
, struct gdbarch
*gdbarch
)
330 cache
->active_sp_regnum
= ARM_SP_REGNUM
;
332 cache
->saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
335 /* Similar to the previous function, but extracts GDBARCH from FRAME. */
338 arm_cache_init (struct arm_prologue_cache
*cache
, struct frame_info
*frame
)
340 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
341 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
343 arm_cache_init (cache
, gdbarch
);
345 if (tdep
->have_sec_ext
)
347 arm_cache_init_sp (tdep
->m_profile_msp_s_regnum
, &cache
->msp_s
, cache
, frame
);
348 arm_cache_init_sp (tdep
->m_profile_psp_s_regnum
, &cache
->psp_s
, cache
, frame
);
349 arm_cache_init_sp (tdep
->m_profile_msp_ns_regnum
, &cache
->msp_ns
, cache
, frame
);
350 arm_cache_init_sp (tdep
->m_profile_psp_ns_regnum
, &cache
->psp_ns
, cache
, frame
);
352 /* Use MSP_S as default stack pointer. */
353 if (cache
->active_sp_regnum
== ARM_SP_REGNUM
)
354 cache
->active_sp_regnum
= tdep
->m_profile_msp_s_regnum
;
358 arm_cache_init_sp (tdep
->m_profile_msp_regnum
, &cache
->msp_s
, cache
, frame
);
359 arm_cache_init_sp (tdep
->m_profile_psp_regnum
, &cache
->psp_s
, cache
, frame
);
362 arm_cache_init_sp (ARM_SP_REGNUM
, &cache
->msp_s
, cache
, frame
);
365 /* Return the requested stack pointer value (in REGNUM), taking into
366 account whether we have a Security extension or an M-profile
370 arm_cache_get_sp_register (struct arm_prologue_cache
*cache
,
371 arm_gdbarch_tdep
*tdep
, int regnum
)
373 if (regnum
== ARM_SP_REGNUM
)
376 if (tdep
->have_sec_ext
)
378 if (regnum
== tdep
->m_profile_msp_s_regnum
)
380 if (regnum
== tdep
->m_profile_msp_ns_regnum
)
381 return cache
->msp_ns
;
382 if (regnum
== tdep
->m_profile_psp_s_regnum
)
384 if (regnum
== tdep
->m_profile_psp_ns_regnum
)
385 return cache
->psp_ns
;
389 if (regnum
== tdep
->m_profile_msp_regnum
)
391 if (regnum
== tdep
->m_profile_psp_regnum
)
395 gdb_assert_not_reached ("Invalid SP selection");
398 /* Return the previous stack address, depending on which SP register
402 arm_cache_get_prev_sp_value (struct arm_prologue_cache
*cache
, arm_gdbarch_tdep
*tdep
)
404 CORE_ADDR val
= arm_cache_get_sp_register (cache
, tdep
, cache
->active_sp_regnum
);
408 /* Set the active stack pointer to VAL. */
411 arm_cache_set_active_sp_value (struct arm_prologue_cache
*cache
,
412 arm_gdbarch_tdep
*tdep
, CORE_ADDR val
)
414 if (cache
->active_sp_regnum
== ARM_SP_REGNUM
)
420 if (tdep
->have_sec_ext
)
422 if (cache
->active_sp_regnum
== tdep
->m_profile_msp_s_regnum
)
424 else if (cache
->active_sp_regnum
== tdep
->m_profile_msp_ns_regnum
)
426 else if (cache
->active_sp_regnum
== tdep
->m_profile_psp_s_regnum
)
428 else if (cache
->active_sp_regnum
== tdep
->m_profile_psp_ns_regnum
)
435 if (cache
->active_sp_regnum
== tdep
->m_profile_msp_regnum
)
437 else if (cache
->active_sp_regnum
== tdep
->m_profile_psp_regnum
)
443 gdb_assert_not_reached ("Invalid SP selection");
446 /* Return true if REGNUM is one of the stack pointers. */
449 arm_cache_is_sp_register (struct arm_prologue_cache
*cache
,
450 arm_gdbarch_tdep
*tdep
, int regnum
)
452 if ((regnum
== ARM_SP_REGNUM
)
453 || (regnum
== tdep
->m_profile_msp_regnum
)
454 || (regnum
== tdep
->m_profile_msp_s_regnum
)
455 || (regnum
== tdep
->m_profile_msp_ns_regnum
)
456 || (regnum
== tdep
->m_profile_psp_regnum
)
457 || (regnum
== tdep
->m_profile_psp_s_regnum
)
458 || (regnum
== tdep
->m_profile_psp_ns_regnum
))
464 /* Set the active stack pointer to SP_REGNUM. */
467 arm_cache_switch_prev_sp (struct arm_prologue_cache
*cache
,
468 arm_gdbarch_tdep
*tdep
, int sp_regnum
)
470 gdb_assert (sp_regnum
!= ARM_SP_REGNUM
);
471 gdb_assert (arm_cache_is_sp_register (cache
, tdep
, sp_regnum
));
473 if (tdep
->have_sec_ext
)
474 gdb_assert (sp_regnum
!= tdep
->m_profile_msp_regnum
475 && sp_regnum
!= tdep
->m_profile_psp_regnum
);
477 cache
->active_sp_regnum
= sp_regnum
;
482 /* Abstract class to read ARM instructions from memory. */
484 class arm_instruction_reader
487 /* Read a 4 bytes instruction from memory using the BYTE_ORDER endianness. */
488 virtual uint32_t read (CORE_ADDR memaddr
, bfd_endian byte_order
) const = 0;
491 /* Read instructions from target memory. */
493 class target_arm_instruction_reader
: public arm_instruction_reader
496 uint32_t read (CORE_ADDR memaddr
, bfd_endian byte_order
) const override
498 return read_code_unsigned_integer (memaddr
, 4, byte_order
);
504 static CORE_ADDR arm_analyze_prologue
505 (struct gdbarch
*gdbarch
, CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
506 struct arm_prologue_cache
*cache
, const arm_instruction_reader
&insn_reader
);
508 /* Architecture version for displaced stepping. This effects the behaviour of
509 certain instructions, and really should not be hard-wired. */
511 #define DISPLACED_STEPPING_ARCH_VERSION 5
513 /* See arm-tdep.h. */
515 bool arm_apcs_32
= true;
516 bool arm_unwind_secure_frames
= true;
518 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
521 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
523 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
531 /* Determine if the processor is currently executing in Thumb mode. */
534 arm_is_thumb (struct regcache
*regcache
)
537 ULONGEST t_bit
= arm_psr_thumb_bit (regcache
->arch ());
539 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
541 return (cpsr
& t_bit
) != 0;
544 /* Determine if FRAME is executing in Thumb mode. */
547 arm_frame_is_thumb (struct frame_info
*frame
)
550 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
552 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
553 directly (from a signal frame or dummy frame) or by interpreting
554 the saved LR (from a prologue or DWARF frame). So consult it and
555 trust the unwinders. */
556 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
558 return (cpsr
& t_bit
) != 0;
561 /* Search for the mapping symbol covering MEMADDR. If one is found,
562 return its type. Otherwise, return 0. If START is non-NULL,
563 set *START to the location of the mapping symbol. */
566 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
568 struct obj_section
*sec
;
570 /* If there are mapping symbols, consult them. */
571 sec
= find_pc_section (memaddr
);
574 arm_per_bfd
*data
= arm_bfd_data_key
.get (sec
->objfile
->obfd
);
577 unsigned int section_idx
= sec
->the_bfd_section
->index
;
578 arm_mapping_symbol_vec
&map
579 = data
->section_maps
[section_idx
];
581 /* Sort the vector on first use. */
582 if (!data
->section_maps_sorted
[section_idx
])
584 std::sort (map
.begin (), map
.end ());
585 data
->section_maps_sorted
[section_idx
] = true;
588 arm_mapping_symbol map_key
= { memaddr
- sec
->addr (), 0 };
589 arm_mapping_symbol_vec::const_iterator it
590 = std::lower_bound (map
.begin (), map
.end (), map_key
);
592 /* std::lower_bound finds the earliest ordered insertion
593 point. If the symbol at this position starts at this exact
594 address, we use that; otherwise, the preceding
595 mapping symbol covers this address. */
598 if (it
->value
== map_key
.value
)
601 *start
= it
->value
+ sec
->addr ();
606 if (it
> map
.begin ())
608 arm_mapping_symbol_vec::const_iterator prev_it
612 *start
= prev_it
->value
+ sec
->addr ();
613 return prev_it
->type
;
621 /* Determine if the program counter specified in MEMADDR is in a Thumb
622 function. This function should be called for addresses unrelated to
623 any executing frame; otherwise, prefer arm_frame_is_thumb. */
626 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
628 struct bound_minimal_symbol sym
;
630 arm_displaced_step_copy_insn_closure
*dsc
= nullptr;
631 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
633 if (gdbarch_displaced_step_copy_insn_closure_by_addr_p (gdbarch
))
634 dsc
= ((arm_displaced_step_copy_insn_closure
* )
635 gdbarch_displaced_step_copy_insn_closure_by_addr
636 (gdbarch
, current_inferior (), memaddr
));
638 /* If checking the mode of displaced instruction in copy area, the mode
639 should be determined by instruction on the original address. */
642 displaced_debug_printf ("check mode of %.8lx instead of %.8lx",
643 (unsigned long) dsc
->insn_addr
,
644 (unsigned long) memaddr
);
645 memaddr
= dsc
->insn_addr
;
648 /* If bit 0 of the address is set, assume this is a Thumb address. */
649 if (IS_THUMB_ADDR (memaddr
))
652 /* If the user wants to override the symbol table, let him. */
653 if (strcmp (arm_force_mode_string
, "arm") == 0)
655 if (strcmp (arm_force_mode_string
, "thumb") == 0)
658 /* ARM v6-M and v7-M are always in Thumb mode. */
662 /* If there are mapping symbols, consult them. */
663 type
= arm_find_mapping_symbol (memaddr
, NULL
);
667 /* Thumb functions have a "special" bit set in minimal symbols. */
668 sym
= lookup_minimal_symbol_by_pc (memaddr
);
670 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
672 /* If the user wants to override the fallback mode, let them. */
673 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
675 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
678 /* If we couldn't find any symbol, but we're talking to a running
679 target, then trust the current value of $cpsr. This lets
680 "display/i $pc" always show the correct mode (though if there is
681 a symbol table we will not reach here, so it still may not be
682 displayed in the mode it will be executed). */
683 if (target_has_registers ())
684 return arm_frame_is_thumb (get_current_frame ());
686 /* Otherwise we're out of luck; we assume ARM. */
690 /* Determine if the address specified equals any of these magic return
691 values, called EXC_RETURN, defined by the ARM v6-M, v7-M and v8-M
694 From ARMv6-M Reference Manual B1.5.8
695 Table B1-5 Exception return behavior
697 EXC_RETURN Return To Return Stack
698 0xFFFFFFF1 Handler mode Main
699 0xFFFFFFF9 Thread mode Main
700 0xFFFFFFFD Thread mode Process
702 From ARMv7-M Reference Manual B1.5.8
703 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
705 EXC_RETURN Return To Return Stack
706 0xFFFFFFF1 Handler mode Main
707 0xFFFFFFF9 Thread mode Main
708 0xFFFFFFFD Thread mode Process
710 Table B1-9 EXC_RETURN definition of exception return behavior, with
713 EXC_RETURN Return To Return Stack Frame Type
714 0xFFFFFFE1 Handler mode Main Extended
715 0xFFFFFFE9 Thread mode Main Extended
716 0xFFFFFFED Thread mode Process Extended
717 0xFFFFFFF1 Handler mode Main Basic
718 0xFFFFFFF9 Thread mode Main Basic
719 0xFFFFFFFD Thread mode Process Basic
721 For more details see "B1.5.8 Exception return behavior"
722 in both ARMv6-M and ARMv7-M Architecture Reference Manuals.
724 In the ARMv8-M Architecture Technical Reference also adds
725 for implementations without the Security Extension:
728 0xFFFFFFB0 Return to Handler mode.
729 0xFFFFFFB8 Return to Thread mode using the main stack.
730 0xFFFFFFBC Return to Thread mode using the process stack. */
733 arm_m_addr_is_magic (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
735 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
736 if (tdep
->have_sec_ext
)
738 switch ((addr
& 0xff000000))
740 case 0xff000000: /* EXC_RETURN pattern. */
741 case 0xfe000000: /* FNC_RETURN pattern. */
751 /* Values from ARMv8-M Architecture Technical Reference. */
755 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
756 the exception return behavior. */
763 /* Address is magic. */
767 /* Address is not magic. */
773 /* Remove useless bits from addresses in a running program. */
775 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
777 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
779 /* On M-profile devices, do not strip the low bit from EXC_RETURN
780 (the magic exception return address). */
781 if (tdep
->is_m
&& arm_m_addr_is_magic (gdbarch
, val
))
785 return UNMAKE_THUMB_ADDR (val
);
787 return (val
& 0x03fffffc);
790 /* Return 1 if PC is the start of a compiler helper function which
791 can be safely ignored during prologue skipping. IS_THUMB is true
792 if the function is known to be a Thumb function due to the way it
795 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
797 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
798 struct bound_minimal_symbol msym
;
800 msym
= lookup_minimal_symbol_by_pc (pc
);
801 if (msym
.minsym
!= NULL
802 && msym
.value_address () == pc
803 && msym
.minsym
->linkage_name () != NULL
)
805 const char *name
= msym
.minsym
->linkage_name ();
807 /* The GNU linker's Thumb call stub to foo is named
809 if (strstr (name
, "_from_thumb") != NULL
)
812 /* On soft-float targets, __truncdfsf2 is called to convert promoted
813 arguments to their argument types in non-prototyped
815 if (startswith (name
, "__truncdfsf2"))
817 if (startswith (name
, "__aeabi_d2f"))
820 /* Internal functions related to thread-local storage. */
821 if (startswith (name
, "__tls_get_addr"))
823 if (startswith (name
, "__aeabi_read_tp"))
828 /* If we run against a stripped glibc, we may be unable to identify
829 special functions by name. Check for one important case,
830 __aeabi_read_tp, by comparing the *code* against the default
831 implementation (this is hand-written ARM assembler in glibc). */
834 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
835 == 0xe3e00a0f /* mov r0, #0xffff0fff */
836 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
837 == 0xe240f01f) /* sub pc, r0, #31 */
844 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
845 the first 16-bit of instruction, and INSN2 is the second 16-bit of
847 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
848 ((bits ((insn1), 0, 3) << 12) \
849 | (bits ((insn1), 10, 10) << 11) \
850 | (bits ((insn2), 12, 14) << 8) \
851 | bits ((insn2), 0, 7))
853 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
854 the 32-bit instruction. */
855 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
856 ((bits ((insn), 16, 19) << 12) \
857 | bits ((insn), 0, 11))
859 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
862 thumb_expand_immediate (unsigned int imm
)
864 unsigned int count
= imm
>> 7;
872 return (imm
& 0xff) | ((imm
& 0xff) << 16);
874 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
876 return (imm
& 0xff) | ((imm
& 0xff) << 8)
877 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
880 return (0x80 | (imm
& 0x7f)) << (32 - count
);
883 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
884 epilogue, 0 otherwise. */
887 thumb_instruction_restores_sp (unsigned short insn
)
889 return (insn
== 0x46bd /* mov sp, r7 */
890 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
891 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
894 /* Analyze a Thumb prologue, looking for a recognizable stack frame
895 and frame pointer. Scan until we encounter a store that could
896 clobber the stack frame unexpectedly, or an unknown instruction.
897 Return the last address which is definitely safe to skip for an
898 initial breakpoint. */
901 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
902 CORE_ADDR start
, CORE_ADDR limit
,
903 struct arm_prologue_cache
*cache
)
905 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
906 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
910 CORE_ADDR unrecognized_pc
= 0;
912 for (i
= 0; i
< 16; i
++)
913 regs
[i
] = pv_register (i
, 0);
914 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
916 while (start
< limit
)
919 gdb::optional
<bool> ra_signed_state
;
921 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
923 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
928 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
931 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
932 whether to save LR (R14). */
933 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
935 /* Calculate offsets of saved R0-R7 and LR. */
936 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
937 if (mask
& (1 << regno
))
939 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
941 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
944 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
946 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
947 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
950 else if (thumb_instruction_restores_sp (insn
))
952 /* Don't scan past the epilogue. */
955 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
956 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
958 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
959 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
960 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
962 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
963 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
964 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
966 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
967 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
968 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
969 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
970 regs
[bits (insn
, 6, 8)]);
971 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
972 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
974 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
975 int rm
= bits (insn
, 3, 6);
976 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
978 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
980 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
981 int src_reg
= (insn
& 0x78) >> 3;
982 regs
[dst_reg
] = regs
[src_reg
];
984 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
986 /* Handle stores to the stack. Normally pushes are used,
987 but with GCC -mtpcs-frame, there may be other stores
988 in the prologue to create the frame. */
989 int regno
= (insn
>> 8) & 0x7;
992 offset
= (insn
& 0xff) << 2;
993 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
995 if (stack
.store_would_trash (addr
))
998 stack
.store (addr
, 4, regs
[regno
]);
1000 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
1002 int rd
= bits (insn
, 0, 2);
1003 int rn
= bits (insn
, 3, 5);
1006 offset
= bits (insn
, 6, 10) << 2;
1007 addr
= pv_add_constant (regs
[rn
], offset
);
1009 if (stack
.store_would_trash (addr
))
1012 stack
.store (addr
, 4, regs
[rd
]);
1014 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
1015 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
1016 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
1017 /* Ignore stores of argument registers to the stack. */
1019 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
1020 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
1021 /* Ignore block loads from the stack, potentially copying
1022 parameters from memory. */
1024 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
1025 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
1026 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
1027 /* Similarly ignore single loads from the stack. */
1029 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
1030 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
1031 /* Skip register copies, i.e. saves to another register
1032 instead of the stack. */
1034 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
1035 /* Recognize constant loads; even with small stacks these are necessary
1037 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
1038 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
1040 /* Constant pool loads, for the same reason. */
1041 unsigned int constant
;
1044 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
1045 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1046 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
1048 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
1050 unsigned short inst2
;
1052 inst2
= read_code_unsigned_integer (start
+ 2, 2,
1053 byte_order_for_code
);
1054 uint32_t whole_insn
= (insn
<< 16) | inst2
;
1056 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
1058 /* BL, BLX. Allow some special function calls when
1059 skipping the prologue; GCC generates these before
1060 storing arguments to the stack. */
1062 int j1
, j2
, imm1
, imm2
;
1064 imm1
= sbits (insn
, 0, 10);
1065 imm2
= bits (inst2
, 0, 10);
1066 j1
= bit (inst2
, 13);
1067 j2
= bit (inst2
, 11);
1069 offset
= ((imm1
<< 12) + (imm2
<< 1));
1070 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
1072 nextpc
= start
+ 4 + offset
;
1073 /* For BLX make sure to clear the low bits. */
1074 if (bit (inst2
, 12) == 0)
1075 nextpc
= nextpc
& 0xfffffffc;
1077 if (!skip_prologue_function (gdbarch
, nextpc
,
1078 bit (inst2
, 12) != 0))
1082 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
1084 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1086 pv_t addr
= regs
[bits (insn
, 0, 3)];
1089 if (stack
.store_would_trash (addr
))
1092 /* Calculate offsets of saved registers. */
1093 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
1094 if (inst2
& (1 << regno
))
1096 addr
= pv_add_constant (addr
, -4);
1097 stack
.store (addr
, 4, regs
[regno
]);
1101 regs
[bits (insn
, 0, 3)] = addr
;
1104 /* vstmdb Rn{!}, { D-registers } (aka vpush). */
1105 else if ((insn
& 0xff20) == 0xed20
1106 && (inst2
& 0x0f00) == 0x0b00
1107 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1109 /* Address SP points to. */
1110 pv_t addr
= regs
[bits (insn
, 0, 3)];
1112 /* Number of registers saved. */
1113 unsigned int number
= bits (inst2
, 0, 7) >> 1;
1115 /* First register to save. */
1116 int vd
= bits (inst2
, 12, 15) | (bits (insn
, 6, 6) << 4);
1118 if (stack
.store_would_trash (addr
))
1121 /* Calculate offsets of saved registers. */
1122 for (; number
> 0; number
--)
1124 addr
= pv_add_constant (addr
, -8);
1125 stack
.store (addr
, 8, pv_register (ARM_D0_REGNUM
1129 /* Writeback SP to account for the saved registers. */
1130 regs
[bits (insn
, 0, 3)] = addr
;
1133 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
1135 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1137 int regno1
= bits (inst2
, 12, 15);
1138 int regno2
= bits (inst2
, 8, 11);
1139 pv_t addr
= regs
[bits (insn
, 0, 3)];
1141 offset
= inst2
& 0xff;
1143 addr
= pv_add_constant (addr
, offset
);
1145 addr
= pv_add_constant (addr
, -offset
);
1147 if (stack
.store_would_trash (addr
))
1150 stack
.store (addr
, 4, regs
[regno1
]);
1151 stack
.store (pv_add_constant (addr
, 4),
1155 regs
[bits (insn
, 0, 3)] = addr
;
1158 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
1159 && (inst2
& 0x0c00) == 0x0c00
1160 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1162 int regno
= bits (inst2
, 12, 15);
1163 pv_t addr
= regs
[bits (insn
, 0, 3)];
1165 offset
= inst2
& 0xff;
1167 addr
= pv_add_constant (addr
, offset
);
1169 addr
= pv_add_constant (addr
, -offset
);
1171 if (stack
.store_would_trash (addr
))
1174 stack
.store (addr
, 4, regs
[regno
]);
1177 regs
[bits (insn
, 0, 3)] = addr
;
1180 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
1181 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1183 int regno
= bits (inst2
, 12, 15);
1186 offset
= inst2
& 0xfff;
1187 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
1189 if (stack
.store_would_trash (addr
))
1192 stack
.store (addr
, 4, regs
[regno
]);
1195 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
1196 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1197 /* Ignore stores of argument registers to the stack. */
1200 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
1201 && (inst2
& 0x0d00) == 0x0c00
1202 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1203 /* Ignore stores of argument registers to the stack. */
1206 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
1208 && (inst2
& 0x8000) == 0x0000
1209 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1210 /* Ignore block loads from the stack, potentially copying
1211 parameters from memory. */
1214 else if ((insn
& 0xff70) == 0xe950 /* ldrd Rt, Rt2,
1216 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1217 /* Similarly ignore dual loads from the stack. */
1220 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
1221 && (inst2
& 0x0d00) == 0x0c00
1222 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1223 /* Similarly ignore single loads from the stack. */
1226 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1227 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1228 /* Similarly ignore single loads from the stack. */
1231 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1232 && (inst2
& 0x8000) == 0x0000)
1234 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1235 | (bits (inst2
, 12, 14) << 8)
1236 | bits (inst2
, 0, 7));
1238 regs
[bits (inst2
, 8, 11)]
1239 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1240 thumb_expand_immediate (imm
));
1243 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1244 && (inst2
& 0x8000) == 0x0000)
1246 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1247 | (bits (inst2
, 12, 14) << 8)
1248 | bits (inst2
, 0, 7));
1250 regs
[bits (inst2
, 8, 11)]
1251 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1254 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1255 && (inst2
& 0x8000) == 0x0000)
1257 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1258 | (bits (inst2
, 12, 14) << 8)
1259 | bits (inst2
, 0, 7));
1261 regs
[bits (inst2
, 8, 11)]
1262 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1263 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1266 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1267 && (inst2
& 0x8000) == 0x0000)
1269 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1270 | (bits (inst2
, 12, 14) << 8)
1271 | bits (inst2
, 0, 7));
1273 regs
[bits (inst2
, 8, 11)]
1274 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1277 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1279 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1280 | (bits (inst2
, 12, 14) << 8)
1281 | bits (inst2
, 0, 7));
1283 regs
[bits (inst2
, 8, 11)]
1284 = pv_constant (thumb_expand_immediate (imm
));
1287 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1290 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1292 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1295 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1296 && (inst2
& 0xf0f0) == 0)
1298 int dst_reg
= (inst2
& 0x0f00) >> 8;
1299 int src_reg
= inst2
& 0xf;
1300 regs
[dst_reg
] = regs
[src_reg
];
1303 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1305 /* Constant pool loads. */
1306 unsigned int constant
;
1309 offset
= bits (inst2
, 0, 11);
1311 loc
= start
+ 4 + offset
;
1313 loc
= start
+ 4 - offset
;
1315 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1316 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1319 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1321 /* Constant pool loads. */
1322 unsigned int constant
;
1325 offset
= bits (inst2
, 0, 7) << 2;
1327 loc
= start
+ 4 + offset
;
1329 loc
= start
+ 4 - offset
;
1331 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1332 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1334 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1335 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1337 /* Start of ARMv8.1-m PACBTI extension instructions. */
1338 else if (IS_PAC (whole_insn
))
1340 /* LR and SP are input registers. PAC is in R12. LR is
1341 signed from this point onwards. NOP space. */
1342 ra_signed_state
= true;
1344 else if (IS_PACBTI (whole_insn
))
1346 /* LR and SP are input registers. PAC is in R12 and PC is a
1347 valid BTI landing pad. LR is signed from this point onwards.
1349 ra_signed_state
= true;
1351 else if (IS_BTI (whole_insn
))
1353 /* Valid BTI landing pad. NOP space. */
1355 else if (IS_PACG (whole_insn
))
1357 /* Sign Rn using Rm and store the PAC in Rd. Rd is signed from
1358 this point onwards. */
1359 ra_signed_state
= true;
1361 else if (IS_AUT (whole_insn
) || IS_AUTG (whole_insn
))
1363 /* These instructions appear close to the epilogue, when signed
1364 pointers are getting authenticated. */
1365 ra_signed_state
= false;
1367 /* End of ARMv8.1-m PACBTI extension instructions */
1368 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1370 /* Don't scan past anything that might change control flow. */
1375 /* The optimizer might shove anything into the prologue,
1376 so we just skip what we don't recognize. */
1377 unrecognized_pc
= start
;
1380 arm_gdbarch_tdep
*tdep
1381 = (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1383 /* Make sure we are dealing with a target that supports ARMv8.1-m
1385 if (cache
!= nullptr && tdep
->have_pacbti
1386 && ra_signed_state
.has_value ())
1388 arm_debug_printf ("Found pacbti instruction at %s",
1389 paddress (gdbarch
, start
));
1390 arm_debug_printf ("RA is %s",
1391 *ra_signed_state
? "signed" : "not signed");
1392 cache
->ra_signed_state
= ra_signed_state
;
1397 else if (thumb_instruction_changes_pc (insn
))
1399 /* Don't scan past anything that might change control flow. */
1404 /* The optimizer might shove anything into the prologue,
1405 so we just skip what we don't recognize. */
1406 unrecognized_pc
= start
;
1412 arm_debug_printf ("Prologue scan stopped at %s",
1413 paddress (gdbarch
, start
));
1415 if (unrecognized_pc
== 0)
1416 unrecognized_pc
= start
;
1419 return unrecognized_pc
;
1421 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1423 /* Frame pointer is fp. Frame size is constant. */
1424 cache
->framereg
= ARM_FP_REGNUM
;
1425 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1427 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1429 /* Frame pointer is r7. Frame size is constant. */
1430 cache
->framereg
= THUMB_FP_REGNUM
;
1431 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1435 /* Try the stack pointer... this is a bit desperate. */
1436 cache
->framereg
= ARM_SP_REGNUM
;
1437 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1440 for (i
= 0; i
< 16; i
++)
1441 if (stack
.find_reg (gdbarch
, i
, &offset
))
1442 cache
->saved_regs
[i
].set_addr (offset
);
1444 return unrecognized_pc
;
1448 /* Try to analyze the instructions starting from PC, which load symbol
1449 __stack_chk_guard. Return the address of instruction after loading this
1450 symbol, set the dest register number to *BASEREG, and set the size of
1451 instructions for loading symbol in OFFSET. Return 0 if instructions are
1455 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1456 unsigned int *destreg
, int *offset
)
1458 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1459 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1460 unsigned int low
, high
, address
;
1465 unsigned short insn1
1466 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1468 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1470 *destreg
= bits (insn1
, 8, 10);
1472 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1473 address
= read_memory_unsigned_integer (address
, 4,
1474 byte_order_for_code
);
1476 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1478 unsigned short insn2
1479 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1481 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1484 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1486 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1488 /* movt Rd, #const */
1489 if ((insn1
& 0xfbc0) == 0xf2c0)
1491 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1492 *destreg
= bits (insn2
, 8, 11);
1494 address
= (high
<< 16 | low
);
1501 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1503 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1505 address
= bits (insn
, 0, 11) + pc
+ 8;
1506 address
= read_memory_unsigned_integer (address
, 4,
1507 byte_order_for_code
);
1509 *destreg
= bits (insn
, 12, 15);
1512 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1514 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1517 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1519 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1521 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1522 *destreg
= bits (insn
, 12, 15);
1524 address
= (high
<< 16 | low
);
1532 /* Try to skip a sequence of instructions used for stack protector. If PC
1533 points to the first instruction of this sequence, return the address of
1534 first instruction after this sequence, otherwise, return original PC.
1536 On arm, this sequence of instructions is composed of mainly three steps,
1537 Step 1: load symbol __stack_chk_guard,
1538 Step 2: load from address of __stack_chk_guard,
1539 Step 3: store it to somewhere else.
1541 Usually, instructions on step 2 and step 3 are the same on various ARM
1542 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1543 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1544 instructions in step 1 vary from different ARM architectures. On ARMv7,
1547 movw Rn, #:lower16:__stack_chk_guard
1548 movt Rn, #:upper16:__stack_chk_guard
1555 .word __stack_chk_guard
1557 Since ldr/str is a very popular instruction, we can't use them as
1558 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1559 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1560 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1563 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1565 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1566 unsigned int basereg
;
1567 struct bound_minimal_symbol stack_chk_guard
;
1569 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1572 /* Try to parse the instructions in Step 1. */
1573 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1578 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1579 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1580 Otherwise, this sequence cannot be for stack protector. */
1581 if (stack_chk_guard
.minsym
== NULL
1582 || !startswith (stack_chk_guard
.minsym
->linkage_name (), "__stack_chk_guard"))
1587 unsigned int destreg
;
1589 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1591 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1592 if ((insn
& 0xf800) != 0x6800)
1594 if (bits (insn
, 3, 5) != basereg
)
1596 destreg
= bits (insn
, 0, 2);
1598 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1599 byte_order_for_code
);
1600 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1601 if ((insn
& 0xf800) != 0x6000)
1603 if (destreg
!= bits (insn
, 0, 2))
1608 unsigned int destreg
;
1610 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1612 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1613 if ((insn
& 0x0e500000) != 0x04100000)
1615 if (bits (insn
, 16, 19) != basereg
)
1617 destreg
= bits (insn
, 12, 15);
1618 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1619 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1620 4, byte_order_for_code
);
1621 if ((insn
& 0x0e500000) != 0x04000000)
1623 if (bits (insn
, 12, 15) != destreg
)
1626 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1629 return pc
+ offset
+ 4;
1631 return pc
+ offset
+ 8;
1634 /* Advance the PC across any function entry prologue instructions to
1635 reach some "real" code.
1637 The APCS (ARM Procedure Call Standard) defines the following
1641 [stmfd sp!, {a1,a2,a3,a4}]
1642 stmfd sp!, {...,fp,ip,lr,pc}
1643 [stfe f7, [sp, #-12]!]
1644 [stfe f6, [sp, #-12]!]
1645 [stfe f5, [sp, #-12]!]
1646 [stfe f4, [sp, #-12]!]
1647 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1650 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1652 CORE_ADDR func_addr
, limit_pc
;
1654 /* See if we can determine the end of the prologue via the symbol table.
1655 If so, then return either PC, or the PC after the prologue, whichever
1657 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1659 CORE_ADDR post_prologue_pc
1660 = skip_prologue_using_sal (gdbarch
, func_addr
);
1661 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1663 if (post_prologue_pc
)
1665 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1668 /* GCC always emits a line note before the prologue and another
1669 one after, even if the two are at the same address or on the
1670 same line. Take advantage of this so that we do not need to
1671 know every instruction that might appear in the prologue. We
1672 will have producer information for most binaries; if it is
1673 missing (e.g. for -gstabs), assuming the GNU tools. */
1674 if (post_prologue_pc
1676 || cust
->producer () == NULL
1677 || startswith (cust
->producer (), "GNU ")
1678 || producer_is_llvm (cust
->producer ())))
1679 return post_prologue_pc
;
1681 if (post_prologue_pc
!= 0)
1683 CORE_ADDR analyzed_limit
;
1685 /* For non-GCC compilers, make sure the entire line is an
1686 acceptable prologue; GDB will round this function's
1687 return value up to the end of the following line so we
1688 can not skip just part of a line (and we do not want to).
1690 RealView does not treat the prologue specially, but does
1691 associate prologue code with the opening brace; so this
1692 lets us skip the first line if we think it is the opening
1694 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1695 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1696 post_prologue_pc
, NULL
);
1699 = arm_analyze_prologue (gdbarch
, func_addr
, post_prologue_pc
,
1700 NULL
, target_arm_instruction_reader ());
1702 if (analyzed_limit
!= post_prologue_pc
)
1705 return post_prologue_pc
;
1709 /* Can't determine prologue from the symbol table, need to examine
1712 /* Find an upper limit on the function prologue using the debug
1713 information. If the debug information could not be used to provide
1714 that bound, then use an arbitrary large number as the upper bound. */
1715 /* Like arm_scan_prologue, stop no later than pc + 64. */
1716 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1718 limit_pc
= pc
+ 64; /* Magic. */
1721 /* Check if this is Thumb code. */
1722 if (arm_pc_is_thumb (gdbarch
, pc
))
1723 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1725 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
,
1726 target_arm_instruction_reader ());
1730 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1731 This function decodes a Thumb function prologue to determine:
1732 1) the size of the stack frame
1733 2) which registers are saved on it
1734 3) the offsets of saved regs
1735 4) the offset from the stack pointer to the frame pointer
1737 A typical Thumb function prologue would create this stack frame
1738 (offsets relative to FP)
1739 old SP -> 24 stack parameters
1742 R7 -> 0 local variables (16 bytes)
1743 SP -> -12 additional stack space (12 bytes)
1744 The frame size would thus be 36 bytes, and the frame offset would be
1745 12 bytes. The frame register is R7.
1747 The comments for thumb_skip_prolog() describe the algorithm we use
1748 to detect the end of the prolog. */
1752 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1753 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1755 CORE_ADDR prologue_start
;
1756 CORE_ADDR prologue_end
;
1758 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1761 /* See comment in arm_scan_prologue for an explanation of
1763 if (prologue_end
> prologue_start
+ 64)
1765 prologue_end
= prologue_start
+ 64;
1769 /* We're in the boondocks: we have no idea where the start of the
1773 prologue_end
= std::min (prologue_end
, prev_pc
);
1775 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1778 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1782 arm_instruction_restores_sp (unsigned int insn
)
1784 if (bits (insn
, 28, 31) != INST_NV
)
1786 if ((insn
& 0x0df0f000) == 0x0080d000
1787 /* ADD SP (register or immediate). */
1788 || (insn
& 0x0df0f000) == 0x0040d000
1789 /* SUB SP (register or immediate). */
1790 || (insn
& 0x0ffffff0) == 0x01a0d000
1792 || (insn
& 0x0fff0000) == 0x08bd0000
1794 || (insn
& 0x0fff0000) == 0x049d0000)
1795 /* POP of a single register. */
1802 /* Implement immediate value decoding, as described in section A5.2.4
1803 (Modified immediate constants in ARM instructions) of the ARM Architecture
1804 Reference Manual (ARMv7-A and ARMv7-R edition). */
1807 arm_expand_immediate (uint32_t imm
)
1809 /* Immediate values are 12 bits long. */
1810 gdb_assert ((imm
& 0xfffff000) == 0);
1812 uint32_t unrotated_value
= imm
& 0xff;
1813 uint32_t rotate_amount
= (imm
& 0xf00) >> 7;
1815 if (rotate_amount
== 0)
1816 return unrotated_value
;
1818 return ((unrotated_value
>> rotate_amount
)
1819 | (unrotated_value
<< (32 - rotate_amount
)));
1822 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1823 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1824 fill it in. Return the first address not recognized as a prologue
1827 We recognize all the instructions typically found in ARM prologues,
1828 plus harmless instructions which can be skipped (either for analysis
1829 purposes, or a more restrictive set that can be skipped when finding
1830 the end of the prologue). */
1833 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1834 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1835 struct arm_prologue_cache
*cache
,
1836 const arm_instruction_reader
&insn_reader
)
1838 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1840 CORE_ADDR offset
, current_pc
;
1841 pv_t regs
[ARM_FPS_REGNUM
];
1842 CORE_ADDR unrecognized_pc
= 0;
1843 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1845 /* Search the prologue looking for instructions that set up the
1846 frame pointer, adjust the stack pointer, and save registers.
1848 Be careful, however, and if it doesn't look like a prologue,
1849 don't try to scan it. If, for instance, a frameless function
1850 begins with stmfd sp!, then we will tell ourselves there is
1851 a frame, which will confuse stack traceback, as well as "finish"
1852 and other operations that rely on a knowledge of the stack
1855 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1856 regs
[regno
] = pv_register (regno
, 0);
1857 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1859 for (current_pc
= prologue_start
;
1860 current_pc
< prologue_end
;
1863 uint32_t insn
= insn_reader
.read (current_pc
, byte_order_for_code
);
1865 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1867 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1870 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1871 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1873 uint32_t imm
= arm_expand_immediate (insn
& 0xfff);
1874 int rd
= bits (insn
, 12, 15);
1875 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1878 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1879 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1881 uint32_t imm
= arm_expand_immediate (insn
& 0xfff);
1882 int rd
= bits (insn
, 12, 15);
1883 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1886 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1889 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1891 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1892 stack
.store (regs
[ARM_SP_REGNUM
], 4,
1893 regs
[bits (insn
, 12, 15)]);
1896 else if ((insn
& 0xffff0000) == 0xe92d0000)
1897 /* stmfd sp!, {..., fp, ip, lr, pc}
1899 stmfd sp!, {a1, a2, a3, a4} */
1901 int mask
= insn
& 0xffff;
1903 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1906 /* Calculate offsets of saved registers. */
1907 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1908 if (mask
& (1 << regno
))
1911 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1912 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1915 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1916 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1917 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1919 /* No need to add this to saved_regs -- it's just an arg reg. */
1922 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1923 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1924 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1926 /* No need to add this to saved_regs -- it's just an arg reg. */
1929 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1931 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1933 /* No need to add this to saved_regs -- it's just arg regs. */
1936 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1938 uint32_t imm
= arm_expand_immediate (insn
& 0xfff);
1939 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1941 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1943 uint32_t imm
= arm_expand_immediate(insn
& 0xfff);
1944 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1946 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1948 && tdep
->have_fpa_registers
)
1950 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1953 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1954 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1955 stack
.store (regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1957 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1959 && tdep
->have_fpa_registers
)
1961 int n_saved_fp_regs
;
1962 unsigned int fp_start_reg
, fp_bound_reg
;
1964 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1967 if ((insn
& 0x800) == 0x800) /* N0 is set */
1969 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1970 n_saved_fp_regs
= 3;
1972 n_saved_fp_regs
= 1;
1976 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1977 n_saved_fp_regs
= 2;
1979 n_saved_fp_regs
= 4;
1982 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1983 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1984 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1986 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1987 stack
.store (regs
[ARM_SP_REGNUM
], 12,
1988 regs
[fp_start_reg
++]);
1991 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1993 /* Allow some special function calls when skipping the
1994 prologue; GCC generates these before storing arguments to
1996 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1998 if (skip_prologue_function (gdbarch
, dest
, 0))
2003 else if ((insn
& 0xf0000000) != 0xe0000000)
2004 break; /* Condition not true, exit early. */
2005 else if (arm_instruction_changes_pc (insn
))
2006 /* Don't scan past anything that might change control flow. */
2008 else if (arm_instruction_restores_sp (insn
))
2010 /* Don't scan past the epilogue. */
2013 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
2014 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
2015 /* Ignore block loads from the stack, potentially copying
2016 parameters from memory. */
2018 else if ((insn
& 0xfc500000) == 0xe4100000
2019 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
2020 /* Similarly ignore single loads from the stack. */
2022 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
2023 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
2024 register instead of the stack. */
2028 /* The optimizer might shove anything into the prologue, if
2029 we build up cache (cache != NULL) from scanning prologue,
2030 we just skip what we don't recognize and scan further to
2031 make cache as complete as possible. However, if we skip
2032 prologue, we'll stop immediately on unrecognized
2034 unrecognized_pc
= current_pc
;
2042 if (unrecognized_pc
== 0)
2043 unrecognized_pc
= current_pc
;
2047 int framereg
, framesize
;
2049 /* The frame size is just the distance from the frame register
2050 to the original stack pointer. */
2051 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
2053 /* Frame pointer is fp. */
2054 framereg
= ARM_FP_REGNUM
;
2055 framesize
= -regs
[ARM_FP_REGNUM
].k
;
2059 /* Try the stack pointer... this is a bit desperate. */
2060 framereg
= ARM_SP_REGNUM
;
2061 framesize
= -regs
[ARM_SP_REGNUM
].k
;
2064 cache
->framereg
= framereg
;
2065 cache
->framesize
= framesize
;
2067 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
2068 if (stack
.find_reg (gdbarch
, regno
, &offset
))
2069 cache
->saved_regs
[regno
].set_addr (offset
);
2072 arm_debug_printf ("Prologue scan stopped at %s",
2073 paddress (gdbarch
, unrecognized_pc
));
2075 return unrecognized_pc
;
2079 arm_scan_prologue (struct frame_info
*this_frame
,
2080 struct arm_prologue_cache
*cache
)
2082 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2083 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2084 CORE_ADDR prologue_start
, prologue_end
;
2085 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
2086 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
2087 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2089 /* Assume there is no frame until proven otherwise. */
2090 cache
->framereg
= ARM_SP_REGNUM
;
2091 cache
->framesize
= 0;
2093 /* Check for Thumb prologue. */
2094 if (arm_frame_is_thumb (this_frame
))
2096 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
2100 /* Find the function prologue. If we can't find the function in
2101 the symbol table, peek in the stack frame to find the PC. */
2102 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
2105 /* One way to find the end of the prologue (which works well
2106 for unoptimized code) is to do the following:
2108 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
2111 prologue_end = prev_pc;
2112 else if (sal.end < prologue_end)
2113 prologue_end = sal.end;
2115 This mechanism is very accurate so long as the optimizer
2116 doesn't move any instructions from the function body into the
2117 prologue. If this happens, sal.end will be the last
2118 instruction in the first hunk of prologue code just before
2119 the first instruction that the scheduler has moved from
2120 the body to the prologue.
2122 In order to make sure that we scan all of the prologue
2123 instructions, we use a slightly less accurate mechanism which
2124 may scan more than necessary. To help compensate for this
2125 lack of accuracy, the prologue scanning loop below contains
2126 several clauses which'll cause the loop to terminate early if
2127 an implausible prologue instruction is encountered.
2133 is a suitable endpoint since it accounts for the largest
2134 possible prologue plus up to five instructions inserted by
2137 if (prologue_end
> prologue_start
+ 64)
2139 prologue_end
= prologue_start
+ 64; /* See above. */
2144 /* We have no symbol information. Our only option is to assume this
2145 function has a standard stack frame and the normal frame register.
2146 Then, we can find the value of our frame pointer on entrance to
2147 the callee (or at the present moment if this is the innermost frame).
2148 The value stored there should be the address of the stmfd + 8. */
2149 CORE_ADDR frame_loc
;
2150 ULONGEST return_value
;
2152 /* AAPCS does not use a frame register, so we can abort here. */
2153 if (tdep
->arm_abi
== ARM_ABI_AAPCS
)
2156 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
2157 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
2162 prologue_start
= gdbarch_addr_bits_remove
2163 (gdbarch
, return_value
) - 8;
2164 prologue_end
= prologue_start
+ 64; /* See above. */
2168 if (prev_pc
< prologue_end
)
2169 prologue_end
= prev_pc
;
2171 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
,
2172 target_arm_instruction_reader ());
2175 static struct arm_prologue_cache
*
2176 arm_make_prologue_cache (struct frame_info
*this_frame
)
2179 struct arm_prologue_cache
*cache
;
2180 CORE_ADDR unwound_fp
;
2182 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2183 arm_cache_init (cache
, this_frame
);
2185 arm_scan_prologue (this_frame
, cache
);
2187 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2188 if (unwound_fp
== 0)
2191 arm_gdbarch_tdep
*tdep
=
2192 (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
2194 arm_cache_set_active_sp_value (cache
, tdep
, unwound_fp
+ cache
->framesize
);
2196 /* Calculate actual addresses of saved registers using offsets
2197 determined by arm_scan_prologue. */
2198 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2199 if (cache
->saved_regs
[reg
].is_addr ())
2200 cache
->saved_regs
[reg
].set_addr (cache
->saved_regs
[reg
].addr ()
2201 + arm_cache_get_prev_sp_value (cache
, tdep
));
2206 /* Implementation of the stop_reason hook for arm_prologue frames. */
2208 static enum unwind_stop_reason
2209 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
2212 struct arm_prologue_cache
*cache
;
2215 if (*this_cache
== NULL
)
2216 *this_cache
= arm_make_prologue_cache (this_frame
);
2217 cache
= (struct arm_prologue_cache
*) *this_cache
;
2219 /* This is meant to halt the backtrace at "_start". */
2220 pc
= get_frame_pc (this_frame
);
2221 gdbarch
*arch
= get_frame_arch (this_frame
);
2222 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (arch
);
2223 if (pc
<= tdep
->lowest_pc
)
2224 return UNWIND_OUTERMOST
;
2226 /* If we've hit a wall, stop. */
2227 if (arm_cache_get_prev_sp_value (cache
, tdep
) == 0)
2228 return UNWIND_OUTERMOST
;
2230 return UNWIND_NO_REASON
;
2233 /* Our frame ID for a normal frame is the current function's starting PC
2234 and the caller's SP when we were called. */
2237 arm_prologue_this_id (struct frame_info
*this_frame
,
2239 struct frame_id
*this_id
)
2241 struct arm_prologue_cache
*cache
;
2245 if (*this_cache
== NULL
)
2246 *this_cache
= arm_make_prologue_cache (this_frame
);
2247 cache
= (struct arm_prologue_cache
*) *this_cache
;
2249 arm_gdbarch_tdep
*tdep
2250 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
2252 /* Use function start address as part of the frame ID. If we cannot
2253 identify the start address (due to missing symbol information),
2254 fall back to just using the current PC. */
2255 pc
= get_frame_pc (this_frame
);
2256 func
= get_frame_func (this_frame
);
2260 id
= frame_id_build (arm_cache_get_prev_sp_value (cache
, tdep
), func
);
2264 static struct value
*
2265 arm_prologue_prev_register (struct frame_info
*this_frame
,
2269 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2270 struct arm_prologue_cache
*cache
;
2273 if (*this_cache
== NULL
)
2274 *this_cache
= arm_make_prologue_cache (this_frame
);
2275 cache
= (struct arm_prologue_cache
*) *this_cache
;
2277 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2279 /* If this frame has signed the return address, mark it as so. */
2280 if (tdep
->have_pacbti
&& cache
->ra_signed_state
.has_value ()
2281 && *cache
->ra_signed_state
)
2282 set_frame_previous_pc_masked (this_frame
);
2284 /* If we are asked to unwind the PC, then we need to return the LR
2285 instead. The prologue may save PC, but it will point into this
2286 frame's prologue, not the next frame's resume location. Also
2287 strip the saved T bit. A valid LR may have the low bit set, but
2288 a valid PC never does. */
2289 if (prev_regnum
== ARM_PC_REGNUM
)
2293 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2294 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2295 arm_addr_bits_remove (gdbarch
, lr
));
2298 /* SP is generally not saved to the stack, but this frame is
2299 identified by the next frame's stack pointer at the time of the call.
2300 The value was already reconstructed into PREV_SP. */
2301 if (prev_regnum
== ARM_SP_REGNUM
)
2302 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2303 arm_cache_get_prev_sp_value (cache
, tdep
));
2305 /* The value might be one of the alternative SP, if so, use the
2306 value already constructed. */
2307 if (arm_cache_is_sp_register (cache
, tdep
, prev_regnum
))
2309 sp_value
= arm_cache_get_sp_register (cache
, tdep
, prev_regnum
);
2310 return frame_unwind_got_constant (this_frame
, prev_regnum
, sp_value
);
2313 /* The CPSR may have been changed by the call instruction and by the
2314 called function. The only bit we can reconstruct is the T bit,
2315 by checking the low bit of LR as of the call. This is a reliable
2316 indicator of Thumb-ness except for some ARM v4T pre-interworking
2317 Thumb code, which could get away with a clear low bit as long as
2318 the called function did not use bx. Guess that all other
2319 bits are unchanged; the condition flags are presumably lost,
2320 but the processor status is likely valid. */
2321 if (prev_regnum
== ARM_PS_REGNUM
)
2324 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2326 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2327 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2328 if (IS_THUMB_ADDR (lr
))
2332 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2335 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2339 static frame_unwind arm_prologue_unwind
= {
2342 arm_prologue_unwind_stop_reason
,
2343 arm_prologue_this_id
,
2344 arm_prologue_prev_register
,
2346 default_frame_sniffer
2349 /* Maintain a list of ARM exception table entries per objfile, similar to the
2350 list of mapping symbols. We only cache entries for standard ARM-defined
2351 personality routines; the cache will contain only the frame unwinding
2352 instructions associated with the entry (not the descriptors). */
2354 struct arm_exidx_entry
2359 bool operator< (const arm_exidx_entry
&other
) const
2361 return addr
< other
.addr
;
2365 struct arm_exidx_data
2367 std::vector
<std::vector
<arm_exidx_entry
>> section_maps
;
2370 /* Per-BFD key to store exception handling information. */
2371 static const struct bfd_key
<arm_exidx_data
> arm_exidx_data_key
;
2373 static struct obj_section
*
2374 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2376 struct obj_section
*osect
;
2378 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2379 if (bfd_section_flags (osect
->the_bfd_section
) & SEC_ALLOC
)
2381 bfd_vma start
, size
;
2382 start
= bfd_section_vma (osect
->the_bfd_section
);
2383 size
= bfd_section_size (osect
->the_bfd_section
);
2385 if (start
<= vma
&& vma
< start
+ size
)
2392 /* Parse contents of exception table and exception index sections
2393 of OBJFILE, and fill in the exception table entry cache.
2395 For each entry that refers to a standard ARM-defined personality
2396 routine, extract the frame unwinding instructions (from either
2397 the index or the table section). The unwinding instructions
2399 - extracting them from the rest of the table data
2400 - converting to host endianness
2401 - appending the implicit 0xb0 ("Finish") code
2403 The extracted and normalized instructions are stored for later
2404 retrieval by the arm_find_exidx_entry routine. */
2407 arm_exidx_new_objfile (struct objfile
*objfile
)
2409 struct arm_exidx_data
*data
;
2410 asection
*exidx
, *extab
;
2411 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2414 /* If we've already touched this file, do nothing. */
2415 if (!objfile
|| arm_exidx_data_key
.get (objfile
->obfd
) != NULL
)
2418 /* Read contents of exception table and index. */
2419 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2420 gdb::byte_vector exidx_data
;
2423 exidx_vma
= bfd_section_vma (exidx
);
2424 exidx_data
.resize (bfd_section_size (exidx
));
2426 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2427 exidx_data
.data (), 0,
2428 exidx_data
.size ()))
2432 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2433 gdb::byte_vector extab_data
;
2436 extab_vma
= bfd_section_vma (extab
);
2437 extab_data
.resize (bfd_section_size (extab
));
2439 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2440 extab_data
.data (), 0,
2441 extab_data
.size ()))
2445 /* Allocate exception table data structure. */
2446 data
= arm_exidx_data_key
.emplace (objfile
->obfd
);
2447 data
->section_maps
.resize (objfile
->obfd
->section_count
);
2449 /* Fill in exception table. */
2450 for (i
= 0; i
< exidx_data
.size () / 8; i
++)
2452 struct arm_exidx_entry new_exidx_entry
;
2453 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
.data () + i
* 8);
2454 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
,
2455 exidx_data
.data () + i
* 8 + 4);
2456 bfd_vma addr
= 0, word
= 0;
2457 int n_bytes
= 0, n_words
= 0;
2458 struct obj_section
*sec
;
2459 gdb_byte
*entry
= NULL
;
2461 /* Extract address of start of function. */
2462 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2463 idx
+= exidx_vma
+ i
* 8;
2465 /* Find section containing function and compute section offset. */
2466 sec
= arm_obj_section_from_vma (objfile
, idx
);
2469 idx
-= bfd_section_vma (sec
->the_bfd_section
);
2471 /* Determine address of exception table entry. */
2474 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2476 else if ((val
& 0xff000000) == 0x80000000)
2478 /* Exception table entry embedded in .ARM.exidx
2479 -- must be short form. */
2483 else if (!(val
& 0x80000000))
2485 /* Exception table entry in .ARM.extab. */
2486 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2487 addr
+= exidx_vma
+ i
* 8 + 4;
2489 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_data
.size ())
2491 word
= bfd_h_get_32 (objfile
->obfd
,
2492 extab_data
.data () + addr
- extab_vma
);
2495 if ((word
& 0xff000000) == 0x80000000)
2500 else if ((word
& 0xff000000) == 0x81000000
2501 || (word
& 0xff000000) == 0x82000000)
2505 n_words
= ((word
>> 16) & 0xff);
2507 else if (!(word
& 0x80000000))
2510 struct obj_section
*pers_sec
;
2511 int gnu_personality
= 0;
2513 /* Custom personality routine. */
2514 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2515 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2517 /* Check whether we've got one of the variants of the
2518 GNU personality routines. */
2519 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2522 static const char *personality
[] =
2524 "__gcc_personality_v0",
2525 "__gxx_personality_v0",
2526 "__gcj_personality_v0",
2527 "__gnu_objc_personality_v0",
2531 CORE_ADDR pc
= pers
+ pers_sec
->offset ();
2534 for (k
= 0; personality
[k
]; k
++)
2535 if (lookup_minimal_symbol_by_pc_name
2536 (pc
, personality
[k
], objfile
))
2538 gnu_personality
= 1;
2543 /* If so, the next word contains a word count in the high
2544 byte, followed by the same unwind instructions as the
2545 pre-defined forms. */
2547 && addr
+ 4 <= extab_vma
+ extab_data
.size ())
2549 word
= bfd_h_get_32 (objfile
->obfd
,
2551 + addr
- extab_vma
));
2554 n_words
= ((word
>> 24) & 0xff);
2560 /* Sanity check address. */
2562 if (addr
< extab_vma
2563 || addr
+ 4 * n_words
> extab_vma
+ extab_data
.size ())
2564 n_words
= n_bytes
= 0;
2566 /* The unwind instructions reside in WORD (only the N_BYTES least
2567 significant bytes are valid), followed by N_WORDS words in the
2568 extab section starting at ADDR. */
2569 if (n_bytes
|| n_words
)
2572 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2573 n_bytes
+ n_words
* 4 + 1);
2576 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2580 word
= bfd_h_get_32 (objfile
->obfd
,
2581 extab_data
.data () + addr
- extab_vma
);
2584 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2585 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2586 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2587 *p
++ = (gdb_byte
) (word
& 0xff);
2590 /* Implied "Finish" to terminate the list. */
2594 /* Push entry onto vector. They are guaranteed to always
2595 appear in order of increasing addresses. */
2596 new_exidx_entry
.addr
= idx
;
2597 new_exidx_entry
.entry
= entry
;
2598 data
->section_maps
[sec
->the_bfd_section
->index
].push_back
2603 /* Search for the exception table entry covering MEMADDR. If one is found,
2604 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2605 set *START to the start of the region covered by this entry. */
2608 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2610 struct obj_section
*sec
;
2612 sec
= find_pc_section (memaddr
);
2615 struct arm_exidx_data
*data
;
2616 struct arm_exidx_entry map_key
= { memaddr
- sec
->addr (), 0 };
2618 data
= arm_exidx_data_key
.get (sec
->objfile
->obfd
);
2621 std::vector
<arm_exidx_entry
> &map
2622 = data
->section_maps
[sec
->the_bfd_section
->index
];
2625 auto idx
= std::lower_bound (map
.begin (), map
.end (), map_key
);
2627 /* std::lower_bound finds the earliest ordered insertion
2628 point. If the following symbol starts at this exact
2629 address, we use that; otherwise, the preceding
2630 exception table entry covers this address. */
2631 if (idx
< map
.end ())
2633 if (idx
->addr
== map_key
.addr
)
2636 *start
= idx
->addr
+ sec
->addr ();
2641 if (idx
> map
.begin ())
2645 *start
= idx
->addr
+ sec
->addr ();
2655 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2656 instruction list from the ARM exception table entry ENTRY, allocate and
2657 return a prologue cache structure describing how to unwind this frame.
2659 Return NULL if the unwinding instruction list contains a "spare",
2660 "reserved" or "refuse to unwind" instruction as defined in section
2661 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2662 for the ARM Architecture" document. */
2664 static struct arm_prologue_cache
*
2665 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2670 struct arm_prologue_cache
*cache
;
2671 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2672 arm_cache_init (cache
, this_frame
);
2678 /* Whenever we reload SP, we actually have to retrieve its
2679 actual value in the current frame. */
2682 if (cache
->saved_regs
[ARM_SP_REGNUM
].is_realreg ())
2684 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg ();
2685 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2689 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr ();
2690 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2696 /* Decode next unwind instruction. */
2699 if ((insn
& 0xc0) == 0)
2701 int offset
= insn
& 0x3f;
2702 vsp
+= (offset
<< 2) + 4;
2704 else if ((insn
& 0xc0) == 0x40)
2706 int offset
= insn
& 0x3f;
2707 vsp
-= (offset
<< 2) + 4;
2709 else if ((insn
& 0xf0) == 0x80)
2711 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2714 /* The special case of an all-zero mask identifies
2715 "Refuse to unwind". We return NULL to fall back
2716 to the prologue analyzer. */
2720 /* Pop registers r4..r15 under mask. */
2721 for (i
= 0; i
< 12; i
++)
2722 if (mask
& (1 << i
))
2724 cache
->saved_regs
[4 + i
].set_addr (vsp
);
2728 /* Special-case popping SP -- we need to reload vsp. */
2729 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2732 else if ((insn
& 0xf0) == 0x90)
2734 int reg
= insn
& 0xf;
2736 /* Reserved cases. */
2737 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2740 /* Set SP from another register and mark VSP for reload. */
2741 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2744 else if ((insn
& 0xf0) == 0xa0)
2746 int count
= insn
& 0x7;
2747 int pop_lr
= (insn
& 0x8) != 0;
2750 /* Pop r4..r[4+count]. */
2751 for (i
= 0; i
<= count
; i
++)
2753 cache
->saved_regs
[4 + i
].set_addr (vsp
);
2757 /* If indicated by flag, pop LR as well. */
2760 cache
->saved_regs
[ARM_LR_REGNUM
].set_addr (vsp
);
2764 else if (insn
== 0xb0)
2766 /* We could only have updated PC by popping into it; if so, it
2767 will show up as address. Otherwise, copy LR into PC. */
2768 if (!cache
->saved_regs
[ARM_PC_REGNUM
].is_addr ())
2769 cache
->saved_regs
[ARM_PC_REGNUM
]
2770 = cache
->saved_regs
[ARM_LR_REGNUM
];
2775 else if (insn
== 0xb1)
2777 int mask
= *entry
++;
2780 /* All-zero mask and mask >= 16 is "spare". */
2781 if (mask
== 0 || mask
>= 16)
2784 /* Pop r0..r3 under mask. */
2785 for (i
= 0; i
< 4; i
++)
2786 if (mask
& (1 << i
))
2788 cache
->saved_regs
[i
].set_addr (vsp
);
2792 else if (insn
== 0xb2)
2794 ULONGEST offset
= 0;
2799 offset
|= (*entry
& 0x7f) << shift
;
2802 while (*entry
++ & 0x80);
2804 vsp
+= 0x204 + (offset
<< 2);
2806 else if (insn
== 0xb3)
2808 int start
= *entry
>> 4;
2809 int count
= (*entry
++) & 0xf;
2812 /* Only registers D0..D15 are valid here. */
2813 if (start
+ count
>= 16)
2816 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2817 for (i
= 0; i
<= count
; i
++)
2819 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].set_addr (vsp
);
2823 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2826 else if ((insn
& 0xf8) == 0xb8)
2828 int count
= insn
& 0x7;
2831 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2832 for (i
= 0; i
<= count
; i
++)
2834 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].set_addr (vsp
);
2838 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2841 else if (insn
== 0xc6)
2843 int start
= *entry
>> 4;
2844 int count
= (*entry
++) & 0xf;
2847 /* Only registers WR0..WR15 are valid. */
2848 if (start
+ count
>= 16)
2851 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2852 for (i
= 0; i
<= count
; i
++)
2854 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].set_addr (vsp
);
2858 else if (insn
== 0xc7)
2860 int mask
= *entry
++;
2863 /* All-zero mask and mask >= 16 is "spare". */
2864 if (mask
== 0 || mask
>= 16)
2867 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2868 for (i
= 0; i
< 4; i
++)
2869 if (mask
& (1 << i
))
2871 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].set_addr (vsp
);
2875 else if ((insn
& 0xf8) == 0xc0)
2877 int count
= insn
& 0x7;
2880 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2881 for (i
= 0; i
<= count
; i
++)
2883 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].set_addr (vsp
);
2887 else if (insn
== 0xc8)
2889 int start
= *entry
>> 4;
2890 int count
= (*entry
++) & 0xf;
2893 /* Only registers D0..D31 are valid. */
2894 if (start
+ count
>= 16)
2897 /* Pop VFP double-precision registers
2898 D[16+start]..D[16+start+count]. */
2899 for (i
= 0; i
<= count
; i
++)
2901 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].set_addr (vsp
);
2905 else if (insn
== 0xc9)
2907 int start
= *entry
>> 4;
2908 int count
= (*entry
++) & 0xf;
2911 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2912 for (i
= 0; i
<= count
; i
++)
2914 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].set_addr (vsp
);
2918 else if ((insn
& 0xf8) == 0xd0)
2920 int count
= insn
& 0x7;
2923 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2924 for (i
= 0; i
<= count
; i
++)
2926 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].set_addr (vsp
);
2932 /* Everything else is "spare". */
2937 /* If we restore SP from a register, assume this was the frame register.
2938 Otherwise just fall back to SP as frame register. */
2939 if (cache
->saved_regs
[ARM_SP_REGNUM
].is_realreg ())
2940 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg ();
2942 cache
->framereg
= ARM_SP_REGNUM
;
2944 /* Determine offset to previous frame. */
2946 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2948 /* We already got the previous SP. */
2949 arm_gdbarch_tdep
*tdep
2950 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
2951 arm_cache_set_active_sp_value (cache
, tdep
, vsp
);
2956 /* Unwinding via ARM exception table entries. Note that the sniffer
2957 already computes a filled-in prologue cache, which is then used
2958 with the same arm_prologue_this_id and arm_prologue_prev_register
2959 routines also used for prologue-parsing based unwinding. */
2962 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2963 struct frame_info
*this_frame
,
2964 void **this_prologue_cache
)
2966 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2967 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2968 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2969 struct arm_prologue_cache
*cache
;
2972 /* See if we have an ARM exception table entry covering this address. */
2973 addr_in_block
= get_frame_address_in_block (this_frame
);
2974 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2978 /* The ARM exception table does not describe unwind information
2979 for arbitrary PC values, but is guaranteed to be correct only
2980 at call sites. We have to decide here whether we want to use
2981 ARM exception table information for this frame, or fall back
2982 to using prologue parsing. (Note that if we have DWARF CFI,
2983 this sniffer isn't even called -- CFI is always preferred.)
2985 Before we make this decision, however, we check whether we
2986 actually have *symbol* information for the current frame.
2987 If not, prologue parsing would not work anyway, so we might
2988 as well use the exception table and hope for the best. */
2989 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2993 /* If the next frame is "normal", we are at a call site in this
2994 frame, so exception information is guaranteed to be valid. */
2995 if (get_next_frame (this_frame
)
2996 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2999 /* We also assume exception information is valid if we're currently
3000 blocked in a system call. The system library is supposed to
3001 ensure this, so that e.g. pthread cancellation works. */
3002 if (arm_frame_is_thumb (this_frame
))
3006 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
3007 2, byte_order_for_code
, &insn
)
3008 && (insn
& 0xff00) == 0xdf00 /* svc */)
3015 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
3016 4, byte_order_for_code
, &insn
)
3017 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
3021 /* Bail out if we don't know that exception information is valid. */
3025 /* The ARM exception index does not mark the *end* of the region
3026 covered by the entry, and some functions will not have any entry.
3027 To correctly recognize the end of the covered region, the linker
3028 should have inserted dummy records with a CANTUNWIND marker.
3030 Unfortunately, current versions of GNU ld do not reliably do
3031 this, and thus we may have found an incorrect entry above.
3032 As a (temporary) sanity check, we only use the entry if it
3033 lies *within* the bounds of the function. Note that this check
3034 might reject perfectly valid entries that just happen to cover
3035 multiple functions; therefore this check ought to be removed
3036 once the linker is fixed. */
3037 if (func_start
> exidx_region
)
3041 /* Decode the list of unwinding instructions into a prologue cache.
3042 Note that this may fail due to e.g. a "refuse to unwind" code. */
3043 cache
= arm_exidx_fill_cache (this_frame
, entry
);
3047 *this_prologue_cache
= cache
;
3051 struct frame_unwind arm_exidx_unwind
= {
3054 default_frame_unwind_stop_reason
,
3055 arm_prologue_this_id
,
3056 arm_prologue_prev_register
,
3058 arm_exidx_unwind_sniffer
3061 static struct arm_prologue_cache
*
3062 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
3064 struct arm_prologue_cache
*cache
;
3067 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3068 arm_cache_init (cache
, this_frame
);
3070 /* Still rely on the offset calculated from prologue. */
3071 arm_scan_prologue (this_frame
, cache
);
3073 /* Since we are in epilogue, the SP has been restored. */
3074 arm_gdbarch_tdep
*tdep
3075 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3076 arm_cache_set_active_sp_value (cache
, tdep
,
3077 get_frame_register_unsigned (this_frame
,
3080 /* Calculate actual addresses of saved registers using offsets
3081 determined by arm_scan_prologue. */
3082 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
3083 if (cache
->saved_regs
[reg
].is_addr ())
3084 cache
->saved_regs
[reg
].set_addr (cache
->saved_regs
[reg
].addr ()
3085 + arm_cache_get_prev_sp_value (cache
, tdep
));
3090 /* Implementation of function hook 'this_id' in
3091 'struct frame_uwnind' for epilogue unwinder. */
3094 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
3096 struct frame_id
*this_id
)
3098 struct arm_prologue_cache
*cache
;
3101 if (*this_cache
== NULL
)
3102 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
3103 cache
= (struct arm_prologue_cache
*) *this_cache
;
3105 /* Use function start address as part of the frame ID. If we cannot
3106 identify the start address (due to missing symbol information),
3107 fall back to just using the current PC. */
3108 pc
= get_frame_pc (this_frame
);
3109 func
= get_frame_func (this_frame
);
3113 arm_gdbarch_tdep
*tdep
3114 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3115 *this_id
= frame_id_build (arm_cache_get_prev_sp_value (cache
, tdep
), pc
);
3118 /* Implementation of function hook 'prev_register' in
3119 'struct frame_uwnind' for epilogue unwinder. */
3121 static struct value
*
3122 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3123 void **this_cache
, int regnum
)
3125 if (*this_cache
== NULL
)
3126 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
3128 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
3131 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
3133 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
3136 /* Implementation of function hook 'sniffer' in
3137 'struct frame_uwnind' for epilogue unwinder. */
3140 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3141 struct frame_info
*this_frame
,
3142 void **this_prologue_cache
)
3144 if (frame_relative_level (this_frame
) == 0)
3146 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3147 CORE_ADDR pc
= get_frame_pc (this_frame
);
3149 if (arm_frame_is_thumb (this_frame
))
3150 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3152 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3158 /* Frame unwinder from epilogue. */
3160 static const struct frame_unwind arm_epilogue_frame_unwind
=
3164 default_frame_unwind_stop_reason
,
3165 arm_epilogue_frame_this_id
,
3166 arm_epilogue_frame_prev_register
,
3168 arm_epilogue_frame_sniffer
,
3171 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
3172 trampoline, return the target PC. Otherwise return 0.
3174 void call0a (char c, short s, int i, long l) {}
3178 (*pointer_to_call0a) (c, s, i, l);
3181 Instead of calling a stub library function _call_via_xx (xx is
3182 the register name), GCC may inline the trampoline in the object
3183 file as below (register r2 has the address of call0a).
3186 .type main, %function
3195 The trampoline 'bx r2' doesn't belong to main. */
3198 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
3200 /* The heuristics of recognizing such trampoline is that FRAME is
3201 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
3202 if (arm_frame_is_thumb (frame
))
3206 if (target_read_memory (pc
, buf
, 2) == 0)
3208 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3209 enum bfd_endian byte_order_for_code
3210 = gdbarch_byte_order_for_code (gdbarch
);
3212 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3214 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3217 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
3219 /* Clear the LSB so that gdb core sets step-resume
3220 breakpoint at the right address. */
3221 return UNMAKE_THUMB_ADDR (dest
);
3229 static struct arm_prologue_cache
*
3230 arm_make_stub_cache (struct frame_info
*this_frame
)
3232 struct arm_prologue_cache
*cache
;
3234 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3235 arm_cache_init (cache
, this_frame
);
3237 arm_gdbarch_tdep
*tdep
3238 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3239 arm_cache_set_active_sp_value (cache
, tdep
,
3240 get_frame_register_unsigned (this_frame
,
3246 /* Our frame ID for a stub frame is the current SP and LR. */
3249 arm_stub_this_id (struct frame_info
*this_frame
,
3251 struct frame_id
*this_id
)
3253 struct arm_prologue_cache
*cache
;
3255 if (*this_cache
== NULL
)
3256 *this_cache
= arm_make_stub_cache (this_frame
);
3257 cache
= (struct arm_prologue_cache
*) *this_cache
;
3259 arm_gdbarch_tdep
*tdep
3260 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3261 *this_id
= frame_id_build (arm_cache_get_prev_sp_value (cache
, tdep
),
3262 get_frame_pc (this_frame
));
3266 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
3267 struct frame_info
*this_frame
,
3268 void **this_prologue_cache
)
3270 CORE_ADDR addr_in_block
;
3272 CORE_ADDR pc
, start_addr
;
3275 addr_in_block
= get_frame_address_in_block (this_frame
);
3276 pc
= get_frame_pc (this_frame
);
3277 if (in_plt_section (addr_in_block
)
3278 /* We also use the stub winder if the target memory is unreadable
3279 to avoid having the prologue unwinder trying to read it. */
3280 || target_read_memory (pc
, dummy
, 4) != 0)
3283 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
3284 && arm_skip_bx_reg (this_frame
, pc
) != 0)
3290 struct frame_unwind arm_stub_unwind
= {
3293 default_frame_unwind_stop_reason
,
3295 arm_prologue_prev_register
,
3297 arm_stub_unwind_sniffer
3300 /* Put here the code to store, into CACHE->saved_regs, the addresses
3301 of the saved registers of frame described by THIS_FRAME. CACHE is
3304 static struct arm_prologue_cache
*
3305 arm_m_exception_cache (struct frame_info
*this_frame
)
3307 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3308 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3309 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3310 struct arm_prologue_cache
*cache
;
3313 CORE_ADDR unwound_sp
;
3314 uint32_t sp_r0_offset
= 0;
3316 uint32_t exc_return
;
3318 uint32_t extended_frame_used
;
3319 bool secure_stack_used
= false;
3320 bool default_callee_register_stacking
= false;
3321 bool exception_domain_is_secure
= false;
3323 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3324 arm_cache_init (cache
, this_frame
);
3326 /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior"
3327 describes which bits in LR that define which stack was used prior
3328 to the exception and if FPU is used (causing extended stack frame). */
3330 lr
= get_frame_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3331 sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3333 fnc_return
= ((lr
& 0xfffffffe) == 0xfefffffe);
3334 if (tdep
->have_sec_ext
&& fnc_return
)
3338 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_msp_ns_regnum
);
3339 arm_cache_set_active_sp_value (cache
, tdep
, sp
);
3341 actual_sp
= tdep
->m_profile_msp_s_regnum
;
3343 actual_sp
= tdep
->m_profile_msp_ns_regnum
;
3345 arm_cache_switch_prev_sp (cache
, tdep
, actual_sp
);
3346 sp
= get_frame_register_unsigned (this_frame
, actual_sp
);
3348 cache
->saved_regs
[ARM_LR_REGNUM
].set_addr (sp
);
3350 arm_cache_set_active_sp_value (cache
, tdep
, sp
+ 8);
3355 /* Check EXC_RETURN indicator bits (24-31). */
3356 exc_return
= (((lr
>> 24) & 0xff) == 0xff);
3359 /* Check EXC_RETURN bit SPSEL if Main or Thread (process) stack used. */
3360 bool process_stack_used
= ((lr
& (1 << 2)) != 0);
3362 if (tdep
->have_sec_ext
)
3364 secure_stack_used
= ((lr
& (1 << 6)) != 0);
3365 default_callee_register_stacking
= ((lr
& (1 << 5)) != 0);
3366 exception_domain_is_secure
= ((lr
& (1 << 0)) == 0);
3368 /* Unwinding from non-secure to secure can trip security
3369 measures. In order to avoid the debugger being
3370 intrusive, rely on the user to configure the requested
3372 if (secure_stack_used
&& !exception_domain_is_secure
3373 && !arm_unwind_secure_frames
)
3375 warning (_("Non-secure to secure stack unwinding disabled."));
3377 /* Terminate any further stack unwinding by referring to self. */
3378 arm_cache_set_active_sp_value (cache
, tdep
, sp
);
3382 if (process_stack_used
)
3384 if (secure_stack_used
)
3385 /* Secure thread (process) stack used, use PSP_S as SP. */
3386 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_psp_s_regnum
);
3388 /* Non-secure thread (process) stack used, use PSP_NS as SP. */
3389 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_psp_ns_regnum
);
3393 if (secure_stack_used
)
3394 /* Secure main stack used, use MSP_S as SP. */
3395 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_msp_s_regnum
);
3397 /* Non-secure main stack used, use MSP_NS as SP. */
3398 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_msp_ns_regnum
);
3403 if (process_stack_used
)
3404 /* Thread (process) stack used, use PSP as SP. */
3405 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_psp_regnum
);
3407 /* Main stack used, use MSP as SP. */
3408 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_msp_regnum
);
3413 /* Main stack used, use MSP as SP. */
3414 arm_cache_switch_prev_sp (cache
, tdep
, tdep
->m_profile_msp_regnum
);
3417 /* Fetch the SP to use for this frame. */
3418 unwound_sp
= arm_cache_get_prev_sp_value (cache
, tdep
);
3420 /* With the Security extension, the hardware saves R4..R11 too. */
3421 if (exc_return
&& tdep
->have_sec_ext
&& secure_stack_used
3422 && (!default_callee_register_stacking
|| exception_domain_is_secure
))
3424 /* Read R4..R11 from the integer callee registers. */
3425 cache
->saved_regs
[4].set_addr (unwound_sp
+ 0x08);
3426 cache
->saved_regs
[5].set_addr (unwound_sp
+ 0x0C);
3427 cache
->saved_regs
[6].set_addr (unwound_sp
+ 0x10);
3428 cache
->saved_regs
[7].set_addr (unwound_sp
+ 0x14);
3429 cache
->saved_regs
[8].set_addr (unwound_sp
+ 0x18);
3430 cache
->saved_regs
[9].set_addr (unwound_sp
+ 0x1C);
3431 cache
->saved_regs
[10].set_addr (unwound_sp
+ 0x20);
3432 cache
->saved_regs
[11].set_addr (unwound_sp
+ 0x24);
3433 sp_r0_offset
= 0x28;
3436 /* The hardware saves eight 32-bit words, comprising xPSR,
3437 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3438 "B1.5.6 Exception entry behavior" in
3439 "ARMv7-M Architecture Reference Manual". */
3440 cache
->saved_regs
[0].set_addr (unwound_sp
+ sp_r0_offset
);
3441 cache
->saved_regs
[1].set_addr (unwound_sp
+ sp_r0_offset
+ 4);
3442 cache
->saved_regs
[2].set_addr (unwound_sp
+ sp_r0_offset
+ 8);
3443 cache
->saved_regs
[3].set_addr (unwound_sp
+ sp_r0_offset
+ 12);
3444 cache
->saved_regs
[ARM_IP_REGNUM
].set_addr (unwound_sp
+ sp_r0_offset
+ 16);
3445 cache
->saved_regs
[ARM_LR_REGNUM
].set_addr (unwound_sp
+ sp_r0_offset
+ 20);
3446 cache
->saved_regs
[ARM_PC_REGNUM
].set_addr (unwound_sp
+ sp_r0_offset
+ 24);
3447 cache
->saved_regs
[ARM_PS_REGNUM
].set_addr (unwound_sp
+ sp_r0_offset
+ 28);
3449 /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored)
3451 extended_frame_used
= ((lr
& (1 << 4)) == 0);
3452 if (exc_return
&& extended_frame_used
)
3455 int fpu_regs_stack_offset
;
3457 /* This code does not take into account the lazy stacking, see "Lazy
3458 context save of FP state", in B1.5.7, also ARM AN298, supported
3459 by Cortex-M4F architecture.
3460 To fully handle this the FPCCR register (Floating-point Context
3461 Control Register) needs to be read out and the bits ASPEN and LSPEN
3462 could be checked to setup correct lazy stacked FP registers.
3463 This register is located at address 0xE000EF34. */
3465 /* Extended stack frame type used. */
3466 fpu_regs_stack_offset
= unwound_sp
+ sp_r0_offset
+ 0x20;
3467 for (i
= 0; i
< 16; i
++)
3469 cache
->saved_regs
[ARM_D0_REGNUM
+ i
].set_addr (fpu_regs_stack_offset
);
3470 fpu_regs_stack_offset
+= 4;
3472 cache
->saved_regs
[ARM_FPSCR_REGNUM
].set_addr (unwound_sp
+ sp_r0_offset
+ 0x60);
3473 fpu_regs_stack_offset
+= 4;
3475 if (tdep
->have_sec_ext
&& !default_callee_register_stacking
)
3477 /* Handle floating-point callee saved registers. */
3478 fpu_regs_stack_offset
= 0x90;
3479 for (i
= 16; i
< 32; i
++)
3481 cache
->saved_regs
[ARM_D0_REGNUM
+ i
].set_addr (fpu_regs_stack_offset
);
3482 fpu_regs_stack_offset
+= 4;
3485 arm_cache_set_active_sp_value (cache
, tdep
, unwound_sp
+ sp_r0_offset
+ 0xD0);
3489 /* Offset 0x64 is reserved. */
3490 arm_cache_set_active_sp_value (cache
, tdep
, unwound_sp
+ sp_r0_offset
+ 0x68);
3495 /* Standard stack frame type used. */
3496 arm_cache_set_active_sp_value (cache
, tdep
, unwound_sp
+ sp_r0_offset
+ 0x20);
3499 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3500 aligner between the top of the 32-byte stack frame and the
3501 previous context's stack pointer. */
3502 if (safe_read_memory_integer (unwound_sp
+ sp_r0_offset
+ 28, 4, byte_order
, &xpsr
)
3503 && (xpsr
& (1 << 9)) != 0)
3504 arm_cache_set_active_sp_value (cache
, tdep
,
3505 arm_cache_get_prev_sp_value (cache
, tdep
) + 4);
3510 /* Implementation of function hook 'this_id' in
3511 'struct frame_uwnind'. */
3514 arm_m_exception_this_id (struct frame_info
*this_frame
,
3516 struct frame_id
*this_id
)
3518 struct arm_prologue_cache
*cache
;
3520 if (*this_cache
== NULL
)
3521 *this_cache
= arm_m_exception_cache (this_frame
);
3522 cache
= (struct arm_prologue_cache
*) *this_cache
;
3524 /* Our frame ID for a stub frame is the current SP and LR. */
3525 arm_gdbarch_tdep
*tdep
3526 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3527 *this_id
= frame_id_build (arm_cache_get_prev_sp_value (cache
, tdep
),
3528 get_frame_pc (this_frame
));
3531 /* Implementation of function hook 'prev_register' in
3532 'struct frame_uwnind'. */
3534 static struct value
*
3535 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3539 struct arm_prologue_cache
*cache
;
3542 if (*this_cache
== NULL
)
3543 *this_cache
= arm_m_exception_cache (this_frame
);
3544 cache
= (struct arm_prologue_cache
*) *this_cache
;
3546 /* The value was already reconstructed into PREV_SP. */
3547 arm_gdbarch_tdep
*tdep
3548 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3549 if (prev_regnum
== ARM_SP_REGNUM
)
3550 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3551 arm_cache_get_prev_sp_value (cache
, tdep
));
3553 /* The value might be one of the alternative SP, if so, use the
3554 value already constructed. */
3555 if (arm_cache_is_sp_register (cache
, tdep
, prev_regnum
))
3557 sp_value
= arm_cache_get_sp_register (cache
, tdep
, prev_regnum
);
3558 return frame_unwind_got_constant (this_frame
, prev_regnum
, sp_value
);
3561 if (prev_regnum
== ARM_PC_REGNUM
)
3563 CORE_ADDR lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3564 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3566 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3567 arm_addr_bits_remove (gdbarch
, lr
));
3570 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3574 /* Implementation of function hook 'sniffer' in
3575 'struct frame_uwnind'. */
3578 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3579 struct frame_info
*this_frame
,
3580 void **this_prologue_cache
)
3582 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3583 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3585 /* No need to check is_m; this sniffer is only registered for
3586 M-profile architectures. */
3588 /* Check if exception frame returns to a magic PC value. */
3589 return arm_m_addr_is_magic (gdbarch
, this_pc
);
3592 /* Frame unwinder for M-profile exceptions. */
3594 struct frame_unwind arm_m_exception_unwind
=
3598 default_frame_unwind_stop_reason
,
3599 arm_m_exception_this_id
,
3600 arm_m_exception_prev_register
,
3602 arm_m_exception_unwind_sniffer
3606 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3608 struct arm_prologue_cache
*cache
;
3610 if (*this_cache
== NULL
)
3611 *this_cache
= arm_make_prologue_cache (this_frame
);
3612 cache
= (struct arm_prologue_cache
*) *this_cache
;
3614 arm_gdbarch_tdep
*tdep
3615 = (arm_gdbarch_tdep
*) gdbarch_tdep (get_frame_arch (this_frame
));
3616 return arm_cache_get_prev_sp_value (cache
, tdep
) - cache
->framesize
;
3619 struct frame_base arm_normal_base
= {
3620 &arm_prologue_unwind
,
3621 arm_normal_frame_base
,
3622 arm_normal_frame_base
,
3623 arm_normal_frame_base
3626 static struct value
*
3627 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3630 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3631 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3633 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3638 /* The PC is normally copied from the return column, which
3639 describes saves of LR. However, that version may have an
3640 extra bit set to indicate Thumb state. The bit is not
3643 /* Record in the frame whether the return address was signed. */
3644 if (tdep
->have_pacbti
)
3646 CORE_ADDR ra_auth_code
3647 = frame_unwind_register_unsigned (this_frame
,
3648 tdep
->pacbti_pseudo_base
);
3650 if (ra_auth_code
!= 0)
3651 set_frame_previous_pc_masked (this_frame
);
3654 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3655 return frame_unwind_got_constant (this_frame
, regnum
,
3656 arm_addr_bits_remove (gdbarch
, lr
));
3659 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3660 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3661 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3662 if (IS_THUMB_ADDR (lr
))
3666 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3669 internal_error (__FILE__
, __LINE__
,
3670 _("Unexpected register %d"), regnum
);
3674 /* Implement the stack_frame_destroyed_p gdbarch method. */
3677 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3679 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3680 unsigned int insn
, insn2
;
3681 int found_return
= 0, found_stack_adjust
= 0;
3682 CORE_ADDR func_start
, func_end
;
3686 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3689 /* The epilogue is a sequence of instructions along the following lines:
3691 - add stack frame size to SP or FP
3692 - [if frame pointer used] restore SP from FP
3693 - restore registers from SP [may include PC]
3694 - a return-type instruction [if PC wasn't already restored]
3696 In a first pass, we scan forward from the current PC and verify the
3697 instructions we find as compatible with this sequence, ending in a
3700 However, this is not sufficient to distinguish indirect function calls
3701 within a function from indirect tail calls in the epilogue in some cases.
3702 Therefore, if we didn't already find any SP-changing instruction during
3703 forward scan, we add a backward scanning heuristic to ensure we actually
3704 are in the epilogue. */
3707 while (scan_pc
< func_end
&& !found_return
)
3709 if (target_read_memory (scan_pc
, buf
, 2))
3713 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3715 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3717 else if (insn
== 0x46f7) /* mov pc, lr */
3719 else if (thumb_instruction_restores_sp (insn
))
3721 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3724 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3726 if (target_read_memory (scan_pc
, buf
, 2))
3730 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3732 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3734 if (insn2
& 0x8000) /* <registers> include PC. */
3737 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3738 && (insn2
& 0x0fff) == 0x0b04)
3740 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3743 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3744 && (insn2
& 0x0e00) == 0x0a00)
3756 /* Since any instruction in the epilogue sequence, with the possible
3757 exception of return itself, updates the stack pointer, we need to
3758 scan backwards for at most one instruction. Try either a 16-bit or
3759 a 32-bit instruction. This is just a heuristic, so we do not worry
3760 too much about false positives. */
3762 if (pc
- 4 < func_start
)
3764 if (target_read_memory (pc
- 4, buf
, 4))
3767 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3768 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3770 if (thumb_instruction_restores_sp (insn2
))
3771 found_stack_adjust
= 1;
3772 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3773 found_stack_adjust
= 1;
3774 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3775 && (insn2
& 0x0fff) == 0x0b04)
3776 found_stack_adjust
= 1;
3777 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3778 && (insn2
& 0x0e00) == 0x0a00)
3779 found_stack_adjust
= 1;
3781 return found_stack_adjust
;
3785 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3787 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3790 CORE_ADDR func_start
, func_end
;
3792 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3795 /* We are in the epilogue if the previous instruction was a stack
3796 adjustment and the next instruction is a possible return (bx, mov
3797 pc, or pop). We could have to scan backwards to find the stack
3798 adjustment, or forwards to find the return, but this is a decent
3799 approximation. First scan forwards. */
3802 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3803 if (bits (insn
, 28, 31) != INST_NV
)
3805 if ((insn
& 0x0ffffff0) == 0x012fff10)
3808 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3811 else if ((insn
& 0x0fff0000) == 0x08bd0000
3812 && (insn
& 0x0000c000) != 0)
3813 /* POP (LDMIA), including PC or LR. */
3820 /* Scan backwards. This is just a heuristic, so do not worry about
3821 false positives from mode changes. */
3823 if (pc
< func_start
+ 4)
3826 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3827 if (arm_instruction_restores_sp (insn
))
3833 /* Implement the stack_frame_destroyed_p gdbarch method. */
3836 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3838 if (arm_pc_is_thumb (gdbarch
, pc
))
3839 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3841 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3844 /* When arguments must be pushed onto the stack, they go on in reverse
3845 order. The code below implements a FILO (stack) to do this. */
3850 struct stack_item
*prev
;
3854 static struct stack_item
*
3855 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3857 struct stack_item
*si
;
3858 si
= XNEW (struct stack_item
);
3859 si
->data
= (gdb_byte
*) xmalloc (len
);
3862 memcpy (si
->data
, contents
, len
);
3866 static struct stack_item
*
3867 pop_stack_item (struct stack_item
*si
)
3869 struct stack_item
*dead
= si
;
3876 /* Implement the gdbarch type alignment method, overrides the generic
3877 alignment algorithm for anything that is arm specific. */
3880 arm_type_align (gdbarch
*gdbarch
, struct type
*t
)
3882 t
= check_typedef (t
);
3883 if (t
->code () == TYPE_CODE_ARRAY
&& t
->is_vector ())
3885 /* Use the natural alignment for vector types (the same for
3886 scalar type), but the maximum alignment is 64-bit. */
3887 if (TYPE_LENGTH (t
) > 8)
3890 return TYPE_LENGTH (t
);
3893 /* Allow the common code to calculate the alignment. */
3897 /* Possible base types for a candidate for passing and returning in
3900 enum arm_vfp_cprc_base_type
3909 /* The length of one element of base type B. */
3912 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3916 case VFP_CPRC_SINGLE
:
3918 case VFP_CPRC_DOUBLE
:
3920 case VFP_CPRC_VEC64
:
3922 case VFP_CPRC_VEC128
:
3925 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3930 /* The character ('s', 'd' or 'q') for the type of VFP register used
3931 for passing base type B. */
3934 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3938 case VFP_CPRC_SINGLE
:
3940 case VFP_CPRC_DOUBLE
:
3942 case VFP_CPRC_VEC64
:
3944 case VFP_CPRC_VEC128
:
3947 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3952 /* Determine whether T may be part of a candidate for passing and
3953 returning in VFP registers, ignoring the limit on the total number
3954 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3955 classification of the first valid component found; if it is not
3956 VFP_CPRC_UNKNOWN, all components must have the same classification
3957 as *BASE_TYPE. If it is found that T contains a type not permitted
3958 for passing and returning in VFP registers, a type differently
3959 classified from *BASE_TYPE, or two types differently classified
3960 from each other, return -1, otherwise return the total number of
3961 base-type elements found (possibly 0 in an empty structure or
3962 array). Vector types are not currently supported, matching the
3963 generic AAPCS support. */
3966 arm_vfp_cprc_sub_candidate (struct type
*t
,
3967 enum arm_vfp_cprc_base_type
*base_type
)
3969 t
= check_typedef (t
);
3973 switch (TYPE_LENGTH (t
))
3976 if (*base_type
== VFP_CPRC_UNKNOWN
)
3977 *base_type
= VFP_CPRC_SINGLE
;
3978 else if (*base_type
!= VFP_CPRC_SINGLE
)
3983 if (*base_type
== VFP_CPRC_UNKNOWN
)
3984 *base_type
= VFP_CPRC_DOUBLE
;
3985 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3994 case TYPE_CODE_COMPLEX
:
3995 /* Arguments of complex T where T is one of the types float or
3996 double get treated as if they are implemented as:
4005 switch (TYPE_LENGTH (t
))
4008 if (*base_type
== VFP_CPRC_UNKNOWN
)
4009 *base_type
= VFP_CPRC_SINGLE
;
4010 else if (*base_type
!= VFP_CPRC_SINGLE
)
4015 if (*base_type
== VFP_CPRC_UNKNOWN
)
4016 *base_type
= VFP_CPRC_DOUBLE
;
4017 else if (*base_type
!= VFP_CPRC_DOUBLE
)
4026 case TYPE_CODE_ARRAY
:
4028 if (t
->is_vector ())
4030 /* A 64-bit or 128-bit containerized vector type are VFP
4032 switch (TYPE_LENGTH (t
))
4035 if (*base_type
== VFP_CPRC_UNKNOWN
)
4036 *base_type
= VFP_CPRC_VEC64
;
4039 if (*base_type
== VFP_CPRC_UNKNOWN
)
4040 *base_type
= VFP_CPRC_VEC128
;
4051 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
4055 if (TYPE_LENGTH (t
) == 0)
4057 gdb_assert (count
== 0);
4060 else if (count
== 0)
4062 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
4063 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
4064 return TYPE_LENGTH (t
) / unitlen
;
4069 case TYPE_CODE_STRUCT
:
4074 for (i
= 0; i
< t
->num_fields (); i
++)
4078 if (!field_is_static (&t
->field (i
)))
4079 sub_count
= arm_vfp_cprc_sub_candidate (t
->field (i
).type (),
4081 if (sub_count
== -1)
4085 if (TYPE_LENGTH (t
) == 0)
4087 gdb_assert (count
== 0);
4090 else if (count
== 0)
4092 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
4093 if (TYPE_LENGTH (t
) != unitlen
* count
)
4098 case TYPE_CODE_UNION
:
4103 for (i
= 0; i
< t
->num_fields (); i
++)
4105 int sub_count
= arm_vfp_cprc_sub_candidate (t
->field (i
).type (),
4107 if (sub_count
== -1)
4109 count
= (count
> sub_count
? count
: sub_count
);
4111 if (TYPE_LENGTH (t
) == 0)
4113 gdb_assert (count
== 0);
4116 else if (count
== 0)
4118 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
4119 if (TYPE_LENGTH (t
) != unitlen
* count
)
4131 /* Determine whether T is a VFP co-processor register candidate (CPRC)
4132 if passed to or returned from a non-variadic function with the VFP
4133 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
4134 *BASE_TYPE to the base type for T and *COUNT to the number of
4135 elements of that base type before returning. */
4138 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
4141 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
4142 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
4143 if (c
<= 0 || c
> 4)
4150 /* Return 1 if the VFP ABI should be used for passing arguments to and
4151 returning values from a function of type FUNC_TYPE, 0
4155 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
4157 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4159 /* Variadic functions always use the base ABI. Assume that functions
4160 without debug info are not variadic. */
4161 if (func_type
&& check_typedef (func_type
)->has_varargs ())
4164 /* The VFP ABI is only supported as a variant of AAPCS. */
4165 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
4168 return tdep
->fp_model
== ARM_FLOAT_VFP
;
4171 /* We currently only support passing parameters in integer registers, which
4172 conforms with GCC's default model, and VFP argument passing following
4173 the VFP variant of AAPCS. Several other variants exist and
4174 we should probably support some of them based on the selected ABI. */
4177 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4178 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
4179 struct value
**args
, CORE_ADDR sp
,
4180 function_call_return_method return_method
,
4181 CORE_ADDR struct_addr
)
4183 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4187 struct stack_item
*si
= NULL
;
4190 unsigned vfp_regs_free
= (1 << 16) - 1;
4191 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4193 /* Determine the type of this function and whether the VFP ABI
4195 ftype
= check_typedef (value_type (function
));
4196 if (ftype
->code () == TYPE_CODE_PTR
)
4197 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
4198 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
4200 /* Set the return address. For the ARM, the return breakpoint is
4201 always at BP_ADDR. */
4202 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
4204 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
4206 /* Walk through the list of args and determine how large a temporary
4207 stack is required. Need to take care here as structs may be
4208 passed on the stack, and we have to push them. */
4211 argreg
= ARM_A1_REGNUM
;
4214 /* The struct_return pointer occupies the first parameter
4215 passing register. */
4216 if (return_method
== return_method_struct
)
4218 arm_debug_printf ("struct return in %s = %s",
4219 gdbarch_register_name (gdbarch
, argreg
),
4220 paddress (gdbarch
, struct_addr
));
4222 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
4226 for (argnum
= 0; argnum
< nargs
; argnum
++)
4229 struct type
*arg_type
;
4230 struct type
*target_type
;
4231 enum type_code typecode
;
4232 const bfd_byte
*val
;
4234 enum arm_vfp_cprc_base_type vfp_base_type
;
4236 int may_use_core_reg
= 1;
4238 arg_type
= check_typedef (value_type (args
[argnum
]));
4239 len
= TYPE_LENGTH (arg_type
);
4240 target_type
= TYPE_TARGET_TYPE (arg_type
);
4241 typecode
= arg_type
->code ();
4242 val
= value_contents (args
[argnum
]).data ();
4244 align
= type_align (arg_type
);
4245 /* Round alignment up to a whole number of words. */
4246 align
= (align
+ ARM_INT_REGISTER_SIZE
- 1)
4247 & ~(ARM_INT_REGISTER_SIZE
- 1);
4248 /* Different ABIs have different maximum alignments. */
4249 if (tdep
->arm_abi
== ARM_ABI_APCS
)
4251 /* The APCS ABI only requires word alignment. */
4252 align
= ARM_INT_REGISTER_SIZE
;
4256 /* The AAPCS requires at most doubleword alignment. */
4257 if (align
> ARM_INT_REGISTER_SIZE
* 2)
4258 align
= ARM_INT_REGISTER_SIZE
* 2;
4262 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
4270 /* Because this is a CPRC it cannot go in a core register or
4271 cause a core register to be skipped for alignment.
4272 Either it goes in VFP registers and the rest of this loop
4273 iteration is skipped for this argument, or it goes on the
4274 stack (and the stack alignment code is correct for this
4276 may_use_core_reg
= 0;
4278 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
4279 shift
= unit_length
/ 4;
4280 mask
= (1 << (shift
* vfp_base_count
)) - 1;
4281 for (regno
= 0; regno
< 16; regno
+= shift
)
4282 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
4291 vfp_regs_free
&= ~(mask
<< regno
);
4292 reg_scaled
= regno
/ shift
;
4293 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
4294 for (i
= 0; i
< vfp_base_count
; i
++)
4298 if (reg_char
== 'q')
4299 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
4300 val
+ i
* unit_length
);
4303 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
4304 reg_char
, reg_scaled
+ i
);
4305 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4307 regcache
->cooked_write (regnum
, val
+ i
* unit_length
);
4314 /* This CPRC could not go in VFP registers, so all VFP
4315 registers are now marked as used. */
4320 /* Push stack padding for doubleword alignment. */
4321 if (nstack
& (align
- 1))
4323 si
= push_stack_item (si
, val
, ARM_INT_REGISTER_SIZE
);
4324 nstack
+= ARM_INT_REGISTER_SIZE
;
4327 /* Doubleword aligned quantities must go in even register pairs. */
4328 if (may_use_core_reg
4329 && argreg
<= ARM_LAST_ARG_REGNUM
4330 && align
> ARM_INT_REGISTER_SIZE
4334 /* If the argument is a pointer to a function, and it is a
4335 Thumb function, create a LOCAL copy of the value and set
4336 the THUMB bit in it. */
4337 if (TYPE_CODE_PTR
== typecode
4338 && target_type
!= NULL
4339 && TYPE_CODE_FUNC
== check_typedef (target_type
)->code ())
4341 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
4342 if (arm_pc_is_thumb (gdbarch
, regval
))
4344 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
4345 store_unsigned_integer (copy
, len
, byte_order
,
4346 MAKE_THUMB_ADDR (regval
));
4351 /* Copy the argument to general registers or the stack in
4352 register-sized pieces. Large arguments are split between
4353 registers and stack. */
4356 int partial_len
= len
< ARM_INT_REGISTER_SIZE
4357 ? len
: ARM_INT_REGISTER_SIZE
;
4359 = extract_unsigned_integer (val
, partial_len
, byte_order
);
4361 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
4363 /* The argument is being passed in a general purpose
4365 if (byte_order
== BFD_ENDIAN_BIG
)
4366 regval
<<= (ARM_INT_REGISTER_SIZE
- partial_len
) * 8;
4368 arm_debug_printf ("arg %d in %s = 0x%s", argnum
,
4369 gdbarch_register_name (gdbarch
, argreg
),
4370 phex (regval
, ARM_INT_REGISTER_SIZE
));
4372 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4377 gdb_byte buf
[ARM_INT_REGISTER_SIZE
];
4379 memset (buf
, 0, sizeof (buf
));
4380 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
4382 /* Push the arguments onto the stack. */
4383 arm_debug_printf ("arg %d @ sp + %d", argnum
, nstack
);
4384 si
= push_stack_item (si
, buf
, ARM_INT_REGISTER_SIZE
);
4385 nstack
+= ARM_INT_REGISTER_SIZE
;
4392 /* If we have an odd number of words to push, then decrement the stack
4393 by one word now, so first stack argument will be dword aligned. */
4400 write_memory (sp
, si
->data
, si
->len
);
4401 si
= pop_stack_item (si
);
4404 /* Finally, update teh SP register. */
4405 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
4411 /* Always align the frame to an 8-byte boundary. This is required on
4412 some platforms and harmless on the rest. */
4415 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
4417 /* Align the stack to eight bytes. */
4418 return sp
& ~ (CORE_ADDR
) 7;
4422 print_fpu_flags (struct ui_file
*file
, int flags
)
4424 if (flags
& (1 << 0))
4425 gdb_puts ("IVO ", file
);
4426 if (flags
& (1 << 1))
4427 gdb_puts ("DVZ ", file
);
4428 if (flags
& (1 << 2))
4429 gdb_puts ("OFL ", file
);
4430 if (flags
& (1 << 3))
4431 gdb_puts ("UFL ", file
);
4432 if (flags
& (1 << 4))
4433 gdb_puts ("INX ", file
);
4434 gdb_putc ('\n', file
);
4437 /* Print interesting information about the floating point processor
4438 (if present) or emulator. */
4440 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4441 struct frame_info
*frame
, const char *args
)
4443 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
4446 type
= (status
>> 24) & 127;
4447 if (status
& (1 << 31))
4448 gdb_printf (file
, _("Hardware FPU type %d\n"), type
);
4450 gdb_printf (file
, _("Software FPU type %d\n"), type
);
4451 /* i18n: [floating point unit] mask */
4452 gdb_puts (_("mask: "), file
);
4453 print_fpu_flags (file
, status
>> 16);
4454 /* i18n: [floating point unit] flags */
4455 gdb_puts (_("flags: "), file
);
4456 print_fpu_flags (file
, status
);
4459 /* Construct the ARM extended floating point type. */
4460 static struct type
*
4461 arm_ext_type (struct gdbarch
*gdbarch
)
4463 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4465 if (!tdep
->arm_ext_type
)
4467 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4468 floatformats_arm_ext
);
4470 return tdep
->arm_ext_type
;
4473 static struct type
*
4474 arm_neon_double_type (struct gdbarch
*gdbarch
)
4476 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4478 if (tdep
->neon_double_type
== NULL
)
4480 struct type
*t
, *elem
;
4482 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4484 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4485 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4486 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4487 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4488 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4489 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4490 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4491 append_composite_type_field (t
, "u64", elem
);
4492 elem
= builtin_type (gdbarch
)->builtin_float
;
4493 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4494 elem
= builtin_type (gdbarch
)->builtin_double
;
4495 append_composite_type_field (t
, "f64", elem
);
4497 t
->set_is_vector (true);
4498 t
->set_name ("neon_d");
4499 tdep
->neon_double_type
= t
;
4502 return tdep
->neon_double_type
;
4505 /* FIXME: The vector types are not correctly ordered on big-endian
4506 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4507 bits of d0 - regardless of what unit size is being held in d0. So
4508 the offset of the first uint8 in d0 is 7, but the offset of the
4509 first float is 4. This code works as-is for little-endian
4512 static struct type
*
4513 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4515 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4517 if (tdep
->neon_quad_type
== NULL
)
4519 struct type
*t
, *elem
;
4521 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4523 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4524 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4525 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4526 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4527 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4528 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4529 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4530 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4531 elem
= builtin_type (gdbarch
)->builtin_float
;
4532 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4533 elem
= builtin_type (gdbarch
)->builtin_double
;
4534 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4536 t
->set_is_vector (true);
4537 t
->set_name ("neon_q");
4538 tdep
->neon_quad_type
= t
;
4541 return tdep
->neon_quad_type
;
4544 /* Return true if REGNUM is a Q pseudo register. Return false
4547 REGNUM is the raw register number and not a pseudo-relative register
4551 is_q_pseudo (struct gdbarch
*gdbarch
, int regnum
)
4553 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4555 /* Q pseudo registers are available for both NEON (Q0~Q15) and
4556 MVE (Q0~Q7) features. */
4557 if (tdep
->have_q_pseudos
4558 && regnum
>= tdep
->q_pseudo_base
4559 && regnum
< (tdep
->q_pseudo_base
+ tdep
->q_pseudo_count
))
4565 /* Return true if REGNUM is a VFP S pseudo register. Return false
4568 REGNUM is the raw register number and not a pseudo-relative register
4572 is_s_pseudo (struct gdbarch
*gdbarch
, int regnum
)
4574 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4576 if (tdep
->have_s_pseudos
4577 && regnum
>= tdep
->s_pseudo_base
4578 && regnum
< (tdep
->s_pseudo_base
+ tdep
->s_pseudo_count
))
4584 /* Return true if REGNUM is a MVE pseudo register (P0). Return false
4587 REGNUM is the raw register number and not a pseudo-relative register
4591 is_mve_pseudo (struct gdbarch
*gdbarch
, int regnum
)
4593 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4596 && regnum
>= tdep
->mve_pseudo_base
4597 && regnum
< tdep
->mve_pseudo_base
+ tdep
->mve_pseudo_count
)
4603 /* Return true if REGNUM is a PACBTI pseudo register (ra_auth_code). Return
4606 REGNUM is the raw register number and not a pseudo-relative register
4610 is_pacbti_pseudo (struct gdbarch
*gdbarch
, int regnum
)
4612 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4614 if (tdep
->have_pacbti
4615 && regnum
>= tdep
->pacbti_pseudo_base
4616 && regnum
< tdep
->pacbti_pseudo_base
+ tdep
->pacbti_pseudo_count
)
4622 /* Return the GDB type object for the "standard" data type of data in
4625 static struct type
*
4626 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4628 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4630 if (is_s_pseudo (gdbarch
, regnum
))
4631 return builtin_type (gdbarch
)->builtin_float
;
4633 if (is_q_pseudo (gdbarch
, regnum
))
4634 return arm_neon_quad_type (gdbarch
);
4636 if (is_mve_pseudo (gdbarch
, regnum
))
4637 return builtin_type (gdbarch
)->builtin_int16
;
4639 if (is_pacbti_pseudo (gdbarch
, regnum
))
4640 return builtin_type (gdbarch
)->builtin_uint32
;
4642 /* If the target description has register information, we are only
4643 in this function so that we can override the types of
4644 double-precision registers for NEON. */
4645 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4647 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4649 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4650 && t
->code () == TYPE_CODE_FLT
4652 return arm_neon_double_type (gdbarch
);
4657 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4659 if (!tdep
->have_fpa_registers
)
4660 return builtin_type (gdbarch
)->builtin_void
;
4662 return arm_ext_type (gdbarch
);
4664 else if (regnum
== ARM_SP_REGNUM
)
4665 return builtin_type (gdbarch
)->builtin_data_ptr
;
4666 else if (regnum
== ARM_PC_REGNUM
)
4667 return builtin_type (gdbarch
)->builtin_func_ptr
;
4668 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4669 /* These registers are only supported on targets which supply
4670 an XML description. */
4671 return builtin_type (gdbarch
)->builtin_int0
;
4673 return builtin_type (gdbarch
)->builtin_uint32
;
4676 /* Map a DWARF register REGNUM onto the appropriate GDB register
4680 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4682 /* Core integer regs. */
4683 if (reg
>= 0 && reg
<= 15)
4686 /* Legacy FPA encoding. These were once used in a way which
4687 overlapped with VFP register numbering, so their use is
4688 discouraged, but GDB doesn't support the ARM toolchain
4689 which used them for VFP. */
4690 if (reg
>= 16 && reg
<= 23)
4691 return ARM_F0_REGNUM
+ reg
- 16;
4693 /* New assignments for the FPA registers. */
4694 if (reg
>= 96 && reg
<= 103)
4695 return ARM_F0_REGNUM
+ reg
- 96;
4697 /* WMMX register assignments. */
4698 if (reg
>= 104 && reg
<= 111)
4699 return ARM_WCGR0_REGNUM
+ reg
- 104;
4701 if (reg
>= 112 && reg
<= 127)
4702 return ARM_WR0_REGNUM
+ reg
- 112;
4704 /* PACBTI register containing the Pointer Authentication Code. */
4705 if (reg
== ARM_DWARF_RA_AUTH_CODE
)
4707 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4709 if (tdep
->have_pacbti
)
4710 return tdep
->pacbti_pseudo_base
;
4715 if (reg
>= 192 && reg
<= 199)
4716 return ARM_WC0_REGNUM
+ reg
- 192;
4718 /* VFP v2 registers. A double precision value is actually
4719 in d1 rather than s2, but the ABI only defines numbering
4720 for the single precision registers. This will "just work"
4721 in GDB for little endian targets (we'll read eight bytes,
4722 starting in s0 and then progressing to s1), but will be
4723 reversed on big endian targets with VFP. This won't
4724 be a problem for the new Neon quad registers; you're supposed
4725 to use DW_OP_piece for those. */
4726 if (reg
>= 64 && reg
<= 95)
4730 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4731 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4735 /* VFP v3 / Neon registers. This range is also used for VFP v2
4736 registers, except that it now describes d0 instead of s0. */
4737 if (reg
>= 256 && reg
<= 287)
4741 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4742 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4749 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4751 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4754 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4756 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4757 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4759 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4760 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4762 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4763 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4765 if (reg
< NUM_GREGS
)
4766 return SIM_ARM_R0_REGNUM
+ reg
;
4769 if (reg
< NUM_FREGS
)
4770 return SIM_ARM_FP0_REGNUM
+ reg
;
4773 if (reg
< NUM_SREGS
)
4774 return SIM_ARM_FPS_REGNUM
+ reg
;
4777 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4780 static const unsigned char op_lit0
= DW_OP_lit0
;
4783 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
4784 struct dwarf2_frame_state_reg
*reg
,
4785 struct frame_info
*this_frame
)
4787 if (is_pacbti_pseudo (gdbarch
, regnum
))
4789 /* Initialize RA_AUTH_CODE to zero. */
4790 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
4791 reg
->loc
.exp
.start
= &op_lit0
;
4792 reg
->loc
.exp
.len
= 1;
4800 reg
->how
= DWARF2_FRAME_REG_FN
;
4801 reg
->loc
.fn
= arm_dwarf2_prev_register
;
4804 reg
->how
= DWARF2_FRAME_REG_CFA
;
4809 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4810 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4811 NULL if an error occurs. BUF is freed. */
4814 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4815 int old_len
, int new_len
)
4818 int bytes_to_read
= new_len
- old_len
;
4820 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4821 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4823 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4831 /* An IT block is at most the 2-byte IT instruction followed by
4832 four 4-byte instructions. The furthest back we must search to
4833 find an IT block that affects the current instruction is thus
4834 2 + 3 * 4 == 14 bytes. */
4835 #define MAX_IT_BLOCK_PREFIX 14
4837 /* Use a quick scan if there are more than this many bytes of
4839 #define IT_SCAN_THRESHOLD 32
4841 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4842 A breakpoint in an IT block may not be hit, depending on the
4845 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4849 CORE_ADDR boundary
, func_start
;
4851 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4852 int i
, any
, last_it
, last_it_count
;
4853 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4855 /* If we are using BKPT breakpoints, none of this is necessary. */
4856 if (tdep
->thumb2_breakpoint
== NULL
)
4859 /* ARM mode does not have this problem. */
4860 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4863 /* We are setting a breakpoint in Thumb code that could potentially
4864 contain an IT block. The first step is to find how much Thumb
4865 code there is; we do not need to read outside of known Thumb
4867 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4869 /* Thumb-2 code must have mapping symbols to have a chance. */
4872 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4874 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4875 && func_start
> boundary
)
4876 boundary
= func_start
;
4878 /* Search for a candidate IT instruction. We have to do some fancy
4879 footwork to distinguish a real IT instruction from the second
4880 half of a 32-bit instruction, but there is no need for that if
4881 there's no candidate. */
4882 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4884 /* No room for an IT instruction. */
4887 buf
= (gdb_byte
*) xmalloc (buf_len
);
4888 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4891 for (i
= 0; i
< buf_len
; i
+= 2)
4893 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4894 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4907 /* OK, the code bytes before this instruction contain at least one
4908 halfword which resembles an IT instruction. We know that it's
4909 Thumb code, but there are still two possibilities. Either the
4910 halfword really is an IT instruction, or it is the second half of
4911 a 32-bit Thumb instruction. The only way we can tell is to
4912 scan forwards from a known instruction boundary. */
4913 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4917 /* There's a lot of code before this instruction. Start with an
4918 optimistic search; it's easy to recognize halfwords that can
4919 not be the start of a 32-bit instruction, and use that to
4920 lock on to the instruction boundaries. */
4921 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4924 buf_len
= IT_SCAN_THRESHOLD
;
4927 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4929 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4930 if (thumb_insn_size (inst1
) == 2)
4937 /* At this point, if DEFINITE, BUF[I] is the first place we
4938 are sure that we know the instruction boundaries, and it is far
4939 enough from BPADDR that we could not miss an IT instruction
4940 affecting BPADDR. If ! DEFINITE, give up - start from a
4944 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4948 buf_len
= bpaddr
- boundary
;
4954 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4957 buf_len
= bpaddr
- boundary
;
4961 /* Scan forwards. Find the last IT instruction before BPADDR. */
4966 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4968 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4973 else if (inst1
& 0x0002)
4975 else if (inst1
& 0x0004)
4980 i
+= thumb_insn_size (inst1
);
4986 /* There wasn't really an IT instruction after all. */
4989 if (last_it_count
< 1)
4990 /* It was too far away. */
4993 /* This really is a trouble spot. Move the breakpoint to the IT
4995 return bpaddr
- buf_len
+ last_it
;
4998 /* ARM displaced stepping support.
5000 Generally ARM displaced stepping works as follows:
5002 1. When an instruction is to be single-stepped, it is first decoded by
5003 arm_process_displaced_insn. Depending on the type of instruction, it is
5004 then copied to a scratch location, possibly in a modified form. The
5005 copy_* set of functions performs such modification, as necessary. A
5006 breakpoint is placed after the modified instruction in the scratch space
5007 to return control to GDB. Note in particular that instructions which
5008 modify the PC will no longer do so after modification.
5010 2. The instruction is single-stepped, by setting the PC to the scratch
5011 location address, and resuming. Control returns to GDB when the
5014 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5015 function used for the current instruction. This function's job is to
5016 put the CPU/memory state back to what it would have been if the
5017 instruction had been executed unmodified in its original location. */
5019 /* NOP instruction (mov r0, r0). */
5020 #define ARM_NOP 0xe1a00000
5021 #define THUMB_NOP 0x4600
5023 /* Helper for register reads for displaced stepping. In particular, this
5024 returns the PC as it would be seen by the instruction at its original
5028 displaced_read_reg (regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
,
5032 CORE_ADDR from
= dsc
->insn_addr
;
5034 if (regno
== ARM_PC_REGNUM
)
5036 /* Compute pipeline offset:
5037 - When executing an ARM instruction, PC reads as the address of the
5038 current instruction plus 8.
5039 - When executing a Thumb instruction, PC reads as the address of the
5040 current instruction plus 4. */
5047 displaced_debug_printf ("read pc value %.8lx",
5048 (unsigned long) from
);
5049 return (ULONGEST
) from
;
5053 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5055 displaced_debug_printf ("read r%d value %.8lx",
5056 regno
, (unsigned long) ret
);
5063 displaced_in_arm_mode (struct regcache
*regs
)
5066 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
5068 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5070 return (ps
& t_bit
) == 0;
5073 /* Write to the PC as from a branch instruction. */
5076 branch_write_pc (regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
,
5080 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5081 architecture versions < 6. */
5082 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5083 val
& ~(ULONGEST
) 0x3);
5085 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5086 val
& ~(ULONGEST
) 0x1);
5089 /* Write to the PC as from a branch-exchange instruction. */
5092 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5095 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
5097 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5101 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5102 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5104 else if ((val
& 2) == 0)
5106 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5107 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5111 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5112 mode, align dest to 4 bytes). */
5113 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5114 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5115 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5119 /* Write to the PC as if from a load instruction. */
5122 load_write_pc (regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
,
5125 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5126 bx_write_pc (regs
, val
);
5128 branch_write_pc (regs
, dsc
, val
);
5131 /* Write to the PC as if from an ALU instruction. */
5134 alu_write_pc (regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
,
5137 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5138 bx_write_pc (regs
, val
);
5140 branch_write_pc (regs
, dsc
, val
);
5143 /* Helper for writing to registers for displaced stepping. Writing to the PC
5144 has a varying effects depending on the instruction which does the write:
5145 this is controlled by the WRITE_PC argument. */
5148 displaced_write_reg (regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
,
5149 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5151 if (regno
== ARM_PC_REGNUM
)
5153 displaced_debug_printf ("writing pc %.8lx", (unsigned long) val
);
5157 case BRANCH_WRITE_PC
:
5158 branch_write_pc (regs
, dsc
, val
);
5162 bx_write_pc (regs
, val
);
5166 load_write_pc (regs
, dsc
, val
);
5170 alu_write_pc (regs
, dsc
, val
);
5173 case CANNOT_WRITE_PC
:
5174 warning (_("Instruction wrote to PC in an unexpected way when "
5175 "single-stepping"));
5179 internal_error (__FILE__
, __LINE__
,
5180 _("Invalid argument to displaced_write_reg"));
5183 dsc
->wrote_to_pc
= 1;
5187 displaced_debug_printf ("writing r%d value %.8lx",
5188 regno
, (unsigned long) val
);
5189 regcache_cooked_write_unsigned (regs
, regno
, val
);
5193 /* This function is used to concisely determine if an instruction INSN
5194 references PC. Register fields of interest in INSN should have the
5195 corresponding fields of BITMASK set to 0b1111. The function
5196 returns return 1 if any of these fields in INSN reference the PC
5197 (also 0b1111, r15), else it returns 0. */
5200 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5202 uint32_t lowbit
= 1;
5204 while (bitmask
!= 0)
5208 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5214 mask
= lowbit
* 0xf;
5216 if ((insn
& mask
) == mask
)
5225 /* The simplest copy function. Many instructions have the same effect no
5226 matter what address they are executed at: in those cases, use this. */
5229 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
, const char *iname
,
5230 arm_displaced_step_copy_insn_closure
*dsc
)
5232 displaced_debug_printf ("copying insn %.8lx, opcode/class '%s' unmodified",
5233 (unsigned long) insn
, iname
);
5235 dsc
->modinsn
[0] = insn
;
5241 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5242 uint16_t insn2
, const char *iname
,
5243 arm_displaced_step_copy_insn_closure
*dsc
)
5245 displaced_debug_printf ("copying insn %.4x %.4x, opcode/class '%s' "
5246 "unmodified", insn1
, insn2
, iname
);
5248 dsc
->modinsn
[0] = insn1
;
5249 dsc
->modinsn
[1] = insn2
;
5255 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5258 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
5260 arm_displaced_step_copy_insn_closure
*dsc
)
5262 displaced_debug_printf ("copying insn %.4x, opcode/class '%s' unmodified",
5265 dsc
->modinsn
[0] = insn
;
5270 /* Preload instructions with immediate offset. */
5273 cleanup_preload (struct gdbarch
*gdbarch
, regcache
*regs
,
5274 arm_displaced_step_copy_insn_closure
*dsc
)
5276 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5277 if (!dsc
->u
.preload
.immed
)
5278 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5282 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5283 arm_displaced_step_copy_insn_closure
*dsc
, unsigned int rn
)
5286 /* Preload instructions:
5288 {pli/pld} [rn, #+/-imm]
5290 {pli/pld} [r0, #+/-imm]. */
5292 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5293 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5294 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5295 dsc
->u
.preload
.immed
= 1;
5297 dsc
->cleanup
= &cleanup_preload
;
5301 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5302 arm_displaced_step_copy_insn_closure
*dsc
)
5304 unsigned int rn
= bits (insn
, 16, 19);
5306 if (!insn_references_pc (insn
, 0x000f0000ul
))
5307 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5309 displaced_debug_printf ("copying preload insn %.8lx", (unsigned long) insn
);
5311 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5313 install_preload (gdbarch
, regs
, dsc
, rn
);
5319 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5320 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
5322 unsigned int rn
= bits (insn1
, 0, 3);
5323 unsigned int u_bit
= bit (insn1
, 7);
5324 int imm12
= bits (insn2
, 0, 11);
5327 if (rn
!= ARM_PC_REGNUM
)
5328 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5330 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5331 PLD (literal) Encoding T1. */
5332 displaced_debug_printf ("copying pld/pli pc (0x%x) %c imm12 %.4x",
5333 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5339 /* Rewrite instruction {pli/pld} PC imm12 into:
5340 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5344 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5346 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5347 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5349 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5351 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5352 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5353 dsc
->u
.preload
.immed
= 0;
5355 /* {pli/pld} [r0, r1] */
5356 dsc
->modinsn
[0] = insn1
& 0xfff0;
5357 dsc
->modinsn
[1] = 0xf001;
5360 dsc
->cleanup
= &cleanup_preload
;
5364 /* Preload instructions with register offset. */
5367 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5368 arm_displaced_step_copy_insn_closure
*dsc
, unsigned int rn
,
5371 ULONGEST rn_val
, rm_val
;
5373 /* Preload register-offset instructions:
5375 {pli/pld} [rn, rm {, shift}]
5377 {pli/pld} [r0, r1 {, shift}]. */
5379 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5380 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5381 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5382 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5383 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5384 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5385 dsc
->u
.preload
.immed
= 0;
5387 dsc
->cleanup
= &cleanup_preload
;
5391 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5392 struct regcache
*regs
,
5393 arm_displaced_step_copy_insn_closure
*dsc
)
5395 unsigned int rn
= bits (insn
, 16, 19);
5396 unsigned int rm
= bits (insn
, 0, 3);
5399 if (!insn_references_pc (insn
, 0x000f000ful
))
5400 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5402 displaced_debug_printf ("copying preload insn %.8lx",
5403 (unsigned long) insn
);
5405 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5407 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5411 /* Copy/cleanup coprocessor load and store instructions. */
5414 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5415 struct regcache
*regs
,
5416 arm_displaced_step_copy_insn_closure
*dsc
)
5418 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5420 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5422 if (dsc
->u
.ldst
.writeback
)
5423 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5427 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5428 arm_displaced_step_copy_insn_closure
*dsc
,
5429 int writeback
, unsigned int rn
)
5433 /* Coprocessor load/store instructions:
5435 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5437 {stc/stc2} [r0, #+/-imm].
5439 ldc/ldc2 are handled identically. */
5441 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5442 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5443 /* PC should be 4-byte aligned. */
5444 rn_val
= rn_val
& 0xfffffffc;
5445 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5447 dsc
->u
.ldst
.writeback
= writeback
;
5448 dsc
->u
.ldst
.rn
= rn
;
5450 dsc
->cleanup
= &cleanup_copro_load_store
;
5454 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5455 struct regcache
*regs
,
5456 arm_displaced_step_copy_insn_closure
*dsc
)
5458 unsigned int rn
= bits (insn
, 16, 19);
5460 if (!insn_references_pc (insn
, 0x000f0000ul
))
5461 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5463 displaced_debug_printf ("copying coprocessor load/store insn %.8lx",
5464 (unsigned long) insn
);
5466 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5468 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5474 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5475 uint16_t insn2
, struct regcache
*regs
,
5476 arm_displaced_step_copy_insn_closure
*dsc
)
5478 unsigned int rn
= bits (insn1
, 0, 3);
5480 if (rn
!= ARM_PC_REGNUM
)
5481 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5482 "copro load/store", dsc
);
5484 displaced_debug_printf ("copying coprocessor load/store insn %.4x%.4x",
5487 dsc
->modinsn
[0] = insn1
& 0xfff0;
5488 dsc
->modinsn
[1] = insn2
;
5491 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5492 doesn't support writeback, so pass 0. */
5493 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
5498 /* Clean up branch instructions (actually perform the branch, by setting
5502 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5503 arm_displaced_step_copy_insn_closure
*dsc
)
5505 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5506 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
5507 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
5508 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
5513 if (dsc
->u
.branch
.link
)
5515 /* The value of LR should be the next insn of current one. In order
5516 not to confuse logic handling later insn `bx lr', if current insn mode
5517 is Thumb, the bit 0 of LR value should be set to 1. */
5518 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
5521 next_insn_addr
|= 0x1;
5523 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
5527 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
5530 /* Copy B/BL/BLX instructions with immediate destinations. */
5533 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5534 arm_displaced_step_copy_insn_closure
*dsc
,
5535 unsigned int cond
, int exchange
, int link
, long offset
)
5537 /* Implement "BL<cond> <label>" as:
5539 Preparation: cond <- instruction condition
5540 Insn: mov r0, r0 (nop)
5541 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5543 B<cond> similar, but don't set r14 in cleanup. */
5545 dsc
->u
.branch
.cond
= cond
;
5546 dsc
->u
.branch
.link
= link
;
5547 dsc
->u
.branch
.exchange
= exchange
;
5549 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5550 if (link
&& exchange
)
5551 /* For BLX, offset is computed from the Align (PC, 4). */
5552 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5555 dsc
->u
.branch
.dest
+= 4 + offset
;
5557 dsc
->u
.branch
.dest
+= 8 + offset
;
5559 dsc
->cleanup
= &cleanup_branch
;
5562 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5563 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
5565 unsigned int cond
= bits (insn
, 28, 31);
5566 int exchange
= (cond
== 0xf);
5567 int link
= exchange
|| bit (insn
, 24);
5570 displaced_debug_printf ("copying %s immediate insn %.8lx",
5571 (exchange
) ? "blx" : (link
) ? "bl" : "b",
5572 (unsigned long) insn
);
5574 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5575 then arrange the switch into Thumb mode. */
5576 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5578 offset
= bits (insn
, 0, 23) << 2;
5580 if (bit (offset
, 25))
5581 offset
= offset
| ~0x3ffffff;
5583 dsc
->modinsn
[0] = ARM_NOP
;
5585 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5590 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5591 uint16_t insn2
, struct regcache
*regs
,
5592 arm_displaced_step_copy_insn_closure
*dsc
)
5594 int link
= bit (insn2
, 14);
5595 int exchange
= link
&& !bit (insn2
, 12);
5598 int j1
= bit (insn2
, 13);
5599 int j2
= bit (insn2
, 11);
5600 int s
= sbits (insn1
, 10, 10);
5601 int i1
= !(j1
^ bit (insn1
, 10));
5602 int i2
= !(j2
^ bit (insn1
, 10));
5604 if (!link
&& !exchange
) /* B */
5606 offset
= (bits (insn2
, 0, 10) << 1);
5607 if (bit (insn2
, 12)) /* Encoding T4 */
5609 offset
|= (bits (insn1
, 0, 9) << 12)
5615 else /* Encoding T3 */
5617 offset
|= (bits (insn1
, 0, 5) << 12)
5621 cond
= bits (insn1
, 6, 9);
5626 offset
= (bits (insn1
, 0, 9) << 12);
5627 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5628 offset
|= exchange
?
5629 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5632 displaced_debug_printf ("copying %s insn %.4x %.4x with offset %.8lx",
5633 link
? (exchange
) ? "blx" : "bl" : "b",
5634 insn1
, insn2
, offset
);
5636 dsc
->modinsn
[0] = THUMB_NOP
;
5638 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5642 /* Copy B Thumb instructions. */
5644 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5645 arm_displaced_step_copy_insn_closure
*dsc
)
5647 unsigned int cond
= 0;
5649 unsigned short bit_12_15
= bits (insn
, 12, 15);
5650 CORE_ADDR from
= dsc
->insn_addr
;
5652 if (bit_12_15
== 0xd)
5654 /* offset = SignExtend (imm8:0, 32) */
5655 offset
= sbits ((insn
<< 1), 0, 8);
5656 cond
= bits (insn
, 8, 11);
5658 else if (bit_12_15
== 0xe) /* Encoding T2 */
5660 offset
= sbits ((insn
<< 1), 0, 11);
5664 displaced_debug_printf ("copying b immediate insn %.4x with offset %d",
5667 dsc
->u
.branch
.cond
= cond
;
5668 dsc
->u
.branch
.link
= 0;
5669 dsc
->u
.branch
.exchange
= 0;
5670 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5672 dsc
->modinsn
[0] = THUMB_NOP
;
5674 dsc
->cleanup
= &cleanup_branch
;
5679 /* Copy BX/BLX with register-specified destinations. */
5682 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5683 arm_displaced_step_copy_insn_closure
*dsc
, int link
,
5684 unsigned int cond
, unsigned int rm
)
5686 /* Implement {BX,BLX}<cond> <reg>" as:
5688 Preparation: cond <- instruction condition
5689 Insn: mov r0, r0 (nop)
5690 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5692 Don't set r14 in cleanup for BX. */
5694 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5696 dsc
->u
.branch
.cond
= cond
;
5697 dsc
->u
.branch
.link
= link
;
5699 dsc
->u
.branch
.exchange
= 1;
5701 dsc
->cleanup
= &cleanup_branch
;
5705 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5706 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
5708 unsigned int cond
= bits (insn
, 28, 31);
5711 int link
= bit (insn
, 5);
5712 unsigned int rm
= bits (insn
, 0, 3);
5714 displaced_debug_printf ("copying insn %.8lx", (unsigned long) insn
);
5716 dsc
->modinsn
[0] = ARM_NOP
;
5718 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5723 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5724 struct regcache
*regs
,
5725 arm_displaced_step_copy_insn_closure
*dsc
)
5727 int link
= bit (insn
, 7);
5728 unsigned int rm
= bits (insn
, 3, 6);
5730 displaced_debug_printf ("copying insn %.4x", (unsigned short) insn
);
5732 dsc
->modinsn
[0] = THUMB_NOP
;
5734 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5740 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5743 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5744 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
5746 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5747 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5748 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5749 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5753 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5754 arm_displaced_step_copy_insn_closure
*dsc
)
5756 unsigned int rn
= bits (insn
, 16, 19);
5757 unsigned int rd
= bits (insn
, 12, 15);
5758 unsigned int op
= bits (insn
, 21, 24);
5759 int is_mov
= (op
== 0xd);
5760 ULONGEST rd_val
, rn_val
;
5762 if (!insn_references_pc (insn
, 0x000ff000ul
))
5763 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5765 displaced_debug_printf ("copying immediate %s insn %.8lx",
5766 is_mov
? "move" : "ALU",
5767 (unsigned long) insn
);
5769 /* Instruction is of form:
5771 <op><cond> rd, [rn,] #imm
5775 Preparation: tmp1, tmp2 <- r0, r1;
5777 Insn: <op><cond> r0, r1, #imm
5778 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5781 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5782 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5783 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5784 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5785 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5786 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5790 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5792 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5794 dsc
->cleanup
= &cleanup_alu_imm
;
5800 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5801 uint16_t insn2
, struct regcache
*regs
,
5802 arm_displaced_step_copy_insn_closure
*dsc
)
5804 unsigned int op
= bits (insn1
, 5, 8);
5805 unsigned int rn
, rm
, rd
;
5806 ULONGEST rd_val
, rn_val
;
5808 rn
= bits (insn1
, 0, 3); /* Rn */
5809 rm
= bits (insn2
, 0, 3); /* Rm */
5810 rd
= bits (insn2
, 8, 11); /* Rd */
5812 /* This routine is only called for instruction MOV. */
5813 gdb_assert (op
== 0x2 && rn
== 0xf);
5815 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5816 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5818 displaced_debug_printf ("copying reg %s insn %.4x%.4x", "ALU", insn1
, insn2
);
5820 /* Instruction is of form:
5822 <op><cond> rd, [rn,] #imm
5826 Preparation: tmp1, tmp2 <- r0, r1;
5828 Insn: <op><cond> r0, r1, #imm
5829 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5832 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5833 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5834 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5835 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5836 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5837 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5840 dsc
->modinsn
[0] = insn1
;
5841 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5844 dsc
->cleanup
= &cleanup_alu_imm
;
5849 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5852 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5853 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
5858 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5860 for (i
= 0; i
< 3; i
++)
5861 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5863 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5867 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5868 arm_displaced_step_copy_insn_closure
*dsc
,
5869 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5871 ULONGEST rd_val
, rn_val
, rm_val
;
5873 /* Instruction is of form:
5875 <op><cond> rd, [rn,] rm [, <shift>]
5879 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5880 r0, r1, r2 <- rd, rn, rm
5881 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5882 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5885 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5886 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5887 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5888 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5889 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5890 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5891 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5892 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5893 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5896 dsc
->cleanup
= &cleanup_alu_reg
;
5900 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5901 arm_displaced_step_copy_insn_closure
*dsc
)
5903 unsigned int op
= bits (insn
, 21, 24);
5904 int is_mov
= (op
== 0xd);
5906 if (!insn_references_pc (insn
, 0x000ff00ful
))
5907 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5909 displaced_debug_printf ("copying reg %s insn %.8lx",
5910 is_mov
? "move" : "ALU", (unsigned long) insn
);
5913 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5915 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5917 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5923 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5924 struct regcache
*regs
,
5925 arm_displaced_step_copy_insn_closure
*dsc
)
5929 rm
= bits (insn
, 3, 6);
5930 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5932 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5933 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5935 displaced_debug_printf ("copying ALU reg insn %.4x", (unsigned short) insn
);
5937 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5939 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5944 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5947 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5948 struct regcache
*regs
,
5949 arm_displaced_step_copy_insn_closure
*dsc
)
5951 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5954 for (i
= 0; i
< 4; i
++)
5955 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5957 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5961 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5962 arm_displaced_step_copy_insn_closure
*dsc
,
5963 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5967 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5969 /* Instruction is of form:
5971 <op><cond> rd, [rn,] rm, <shift> rs
5975 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5976 r0, r1, r2, r3 <- rd, rn, rm, rs
5977 Insn: <op><cond> r0, r1, r2, <shift> r3
5979 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5983 for (i
= 0; i
< 4; i
++)
5984 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5986 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5987 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5988 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5989 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5990 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5991 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5992 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5993 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5995 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5999 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6000 struct regcache
*regs
,
6001 arm_displaced_step_copy_insn_closure
*dsc
)
6003 unsigned int op
= bits (insn
, 21, 24);
6004 int is_mov
= (op
== 0xd);
6005 unsigned int rd
, rn
, rm
, rs
;
6007 if (!insn_references_pc (insn
, 0x000fff0ful
))
6008 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6010 displaced_debug_printf ("copying shifted reg %s insn %.8lx",
6011 is_mov
? "move" : "ALU",
6012 (unsigned long) insn
);
6014 rn
= bits (insn
, 16, 19);
6015 rm
= bits (insn
, 0, 3);
6016 rs
= bits (insn
, 8, 11);
6017 rd
= bits (insn
, 12, 15);
6020 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6022 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6024 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6029 /* Clean up load instructions. */
6032 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6033 arm_displaced_step_copy_insn_closure
*dsc
)
6035 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6037 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6038 if (dsc
->u
.ldst
.xfersize
== 8)
6039 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6040 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6042 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6043 if (dsc
->u
.ldst
.xfersize
> 4)
6044 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6045 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6046 if (!dsc
->u
.ldst
.immed
)
6047 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6049 /* Handle register writeback. */
6050 if (dsc
->u
.ldst
.writeback
)
6051 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6052 /* Put result in right place. */
6053 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6054 if (dsc
->u
.ldst
.xfersize
== 8)
6055 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6058 /* Clean up store instructions. */
6061 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6062 arm_displaced_step_copy_insn_closure
*dsc
)
6064 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6066 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6067 if (dsc
->u
.ldst
.xfersize
> 4)
6068 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6069 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6070 if (!dsc
->u
.ldst
.immed
)
6071 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6072 if (!dsc
->u
.ldst
.restore_r4
)
6073 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6076 if (dsc
->u
.ldst
.writeback
)
6077 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6080 /* Copy "extra" load/store instructions. These are halfword/doubleword
6081 transfers, which have a different encoding to byte/word transfers. */
6084 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
6085 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
6087 unsigned int op1
= bits (insn
, 20, 24);
6088 unsigned int op2
= bits (insn
, 5, 6);
6089 unsigned int rt
= bits (insn
, 12, 15);
6090 unsigned int rn
= bits (insn
, 16, 19);
6091 unsigned int rm
= bits (insn
, 0, 3);
6092 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6093 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6094 int immed
= (op1
& 0x4) != 0;
6096 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6098 if (!insn_references_pc (insn
, 0x000ff00ful
))
6099 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6101 displaced_debug_printf ("copying %sextra load/store insn %.8lx",
6102 unprivileged
? "unprivileged " : "",
6103 (unsigned long) insn
);
6105 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6108 internal_error (__FILE__
, __LINE__
,
6109 _("copy_extra_ld_st: instruction decode error"));
6111 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6112 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6113 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6115 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6117 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6118 if (bytesize
[opcode
] == 8)
6119 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6120 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6122 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6124 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6125 if (bytesize
[opcode
] == 8)
6126 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6127 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6129 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6132 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6133 dsc
->u
.ldst
.rn
= rn
;
6134 dsc
->u
.ldst
.immed
= immed
;
6135 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6136 dsc
->u
.ldst
.restore_r4
= 0;
6139 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6141 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6142 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6144 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6146 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6147 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6149 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6154 /* Copy byte/half word/word loads and stores. */
6157 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6158 arm_displaced_step_copy_insn_closure
*dsc
, int load
,
6159 int immed
, int writeback
, int size
, int usermode
,
6160 int rt
, int rm
, int rn
)
6162 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6164 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6165 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6167 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6169 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6171 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6172 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6174 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6176 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6177 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6179 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6181 dsc
->u
.ldst
.xfersize
= size
;
6182 dsc
->u
.ldst
.rn
= rn
;
6183 dsc
->u
.ldst
.immed
= immed
;
6184 dsc
->u
.ldst
.writeback
= writeback
;
6186 /* To write PC we can do:
6188 Before this sequence of instructions:
6189 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6190 r2 is the Rn value got from displaced_read_reg.
6192 Insn1: push {pc} Write address of STR instruction + offset on stack
6193 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6194 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6195 = addr(Insn1) + offset - addr(Insn3) - 8
6197 Insn4: add r4, r4, #8 r4 = offset - 8
6198 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6200 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6202 Otherwise we don't know what value to write for PC, since the offset is
6203 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6204 of this can be found in Section "Saving from r15" in
6205 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6207 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6212 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6213 uint16_t insn2
, struct regcache
*regs
,
6214 arm_displaced_step_copy_insn_closure
*dsc
, int size
)
6216 unsigned int u_bit
= bit (insn1
, 7);
6217 unsigned int rt
= bits (insn2
, 12, 15);
6218 int imm12
= bits (insn2
, 0, 11);
6221 displaced_debug_printf ("copying ldr pc (0x%x) R%d %c imm12 %.4x",
6222 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6228 /* Rewrite instruction LDR Rt imm12 into:
6230 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6234 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6237 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6238 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6239 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6241 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6243 pc_val
= pc_val
& 0xfffffffc;
6245 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6246 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6250 dsc
->u
.ldst
.xfersize
= size
;
6251 dsc
->u
.ldst
.immed
= 0;
6252 dsc
->u
.ldst
.writeback
= 0;
6253 dsc
->u
.ldst
.restore_r4
= 0;
6255 /* LDR R0, R2, R3 */
6256 dsc
->modinsn
[0] = 0xf852;
6257 dsc
->modinsn
[1] = 0x3;
6260 dsc
->cleanup
= &cleanup_load
;
6266 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6267 uint16_t insn2
, struct regcache
*regs
,
6268 arm_displaced_step_copy_insn_closure
*dsc
,
6269 int writeback
, int immed
)
6271 unsigned int rt
= bits (insn2
, 12, 15);
6272 unsigned int rn
= bits (insn1
, 0, 3);
6273 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6274 /* In LDR (register), there is also a register Rm, which is not allowed to
6275 be PC, so we don't have to check it. */
6277 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6278 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6281 displaced_debug_printf ("copying ldr r%d [r%d] insn %.4x%.4x",
6282 rt
, rn
, insn1
, insn2
);
6284 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6287 dsc
->u
.ldst
.restore_r4
= 0;
6290 /* ldr[b]<cond> rt, [rn, #imm], etc.
6292 ldr[b]<cond> r0, [r2, #imm]. */
6294 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6295 dsc
->modinsn
[1] = insn2
& 0x0fff;
6298 /* ldr[b]<cond> rt, [rn, rm], etc.
6300 ldr[b]<cond> r0, [r2, r3]. */
6302 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6303 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6313 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6314 struct regcache
*regs
,
6315 arm_displaced_step_copy_insn_closure
*dsc
,
6316 int load
, int size
, int usermode
)
6318 int immed
= !bit (insn
, 25);
6319 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6320 unsigned int rt
= bits (insn
, 12, 15);
6321 unsigned int rn
= bits (insn
, 16, 19);
6322 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6324 if (!insn_references_pc (insn
, 0x000ff00ful
))
6325 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6327 displaced_debug_printf ("copying %s%s r%d [r%d] insn %.8lx",
6328 load
? (size
== 1 ? "ldrb" : "ldr")
6329 : (size
== 1 ? "strb" : "str"),
6330 usermode
? "t" : "",
6332 (unsigned long) insn
);
6334 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6335 usermode
, rt
, rm
, rn
);
6337 if (load
|| rt
!= ARM_PC_REGNUM
)
6339 dsc
->u
.ldst
.restore_r4
= 0;
6342 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6344 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6345 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6347 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6349 {ldr,str}[b]<cond> r0, [r2, r3]. */
6350 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6354 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6355 dsc
->u
.ldst
.restore_r4
= 1;
6356 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6357 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6358 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6359 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6360 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6364 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6366 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6371 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6376 /* Cleanup LDM instructions with fully-populated register list. This is an
6377 unfortunate corner case: it's impossible to implement correctly by modifying
6378 the instruction. The issue is as follows: we have an instruction,
6382 which we must rewrite to avoid loading PC. A possible solution would be to
6383 do the load in two halves, something like (with suitable cleanup
6387 ldm[id][ab] r8!, {r0-r7}
6389 ldm[id][ab] r8, {r7-r14}
6392 but at present there's no suitable place for <temp>, since the scratch space
6393 is overwritten before the cleanup routine is called. For now, we simply
6394 emulate the instruction. */
6397 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6398 arm_displaced_step_copy_insn_closure
*dsc
)
6400 int inc
= dsc
->u
.block
.increment
;
6401 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6402 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6403 uint32_t regmask
= dsc
->u
.block
.regmask
;
6404 int regno
= inc
? 0 : 15;
6405 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6406 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6407 && (regmask
& 0x8000) != 0;
6408 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6409 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6410 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6415 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6416 sensible we can do here. Complain loudly. */
6417 if (exception_return
)
6418 error (_("Cannot single-step exception return"));
6420 /* We don't handle any stores here for now. */
6421 gdb_assert (dsc
->u
.block
.load
!= 0);
6423 displaced_debug_printf ("emulating block transfer: %s %s %s",
6424 dsc
->u
.block
.load
? "ldm" : "stm",
6425 dsc
->u
.block
.increment
? "inc" : "dec",
6426 dsc
->u
.block
.before
? "before" : "after");
6433 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6436 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6439 xfer_addr
+= bump_before
;
6441 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6442 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6444 xfer_addr
+= bump_after
;
6446 regmask
&= ~(1 << regno
);
6449 if (dsc
->u
.block
.writeback
)
6450 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6454 /* Clean up an STM which included the PC in the register list. */
6457 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6458 arm_displaced_step_copy_insn_closure
*dsc
)
6460 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6461 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6462 CORE_ADDR pc_stored_at
, transferred_regs
6463 = count_one_bits (dsc
->u
.block
.regmask
);
6464 CORE_ADDR stm_insn_addr
;
6467 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6469 /* If condition code fails, there's nothing else to do. */
6470 if (!store_executed
)
6473 if (dsc
->u
.block
.increment
)
6475 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6477 if (dsc
->u
.block
.before
)
6482 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
6484 if (dsc
->u
.block
.before
)
6488 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
6489 stm_insn_addr
= dsc
->scratch_base
;
6490 offset
= pc_val
- stm_insn_addr
;
6492 displaced_debug_printf ("detected PC offset %.8lx for STM instruction",
6495 /* Rewrite the stored PC to the proper value for the non-displaced original
6497 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
6498 dsc
->insn_addr
+ offset
);
6501 /* Clean up an LDM which includes the PC in the register list. We clumped all
6502 the registers in the transferred list into a contiguous range r0...rX (to
6503 avoid loading PC directly and losing control of the debugged program), so we
6504 must undo that here. */
6507 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6508 struct regcache
*regs
,
6509 arm_displaced_step_copy_insn_closure
*dsc
)
6511 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6512 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6513 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
6514 unsigned int regs_loaded
= count_one_bits (mask
);
6515 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6517 /* The method employed here will fail if the register list is fully populated
6518 (we need to avoid loading PC directly). */
6519 gdb_assert (num_to_shuffle
< 16);
6524 clobbered
= (1 << num_to_shuffle
) - 1;
6526 while (num_to_shuffle
> 0)
6528 if ((mask
& (1 << write_reg
)) != 0)
6530 unsigned int read_reg
= num_to_shuffle
- 1;
6532 if (read_reg
!= write_reg
)
6534 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6535 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6536 displaced_debug_printf ("LDM: move loaded register r%d to r%d",
6537 read_reg
, write_reg
);
6540 displaced_debug_printf ("LDM: register r%d already in the right "
6541 "place", write_reg
);
6543 clobbered
&= ~(1 << write_reg
);
6551 /* Restore any registers we scribbled over. */
6552 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6554 if ((clobbered
& (1 << write_reg
)) != 0)
6556 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6558 displaced_debug_printf ("LDM: restored clobbered register r%d",
6560 clobbered
&= ~(1 << write_reg
);
6564 /* Perform register writeback manually. */
6565 if (dsc
->u
.block
.writeback
)
6567 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6569 if (dsc
->u
.block
.increment
)
6570 new_rn_val
+= regs_loaded
* 4;
6572 new_rn_val
-= regs_loaded
* 4;
6574 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6579 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6580 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6583 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6584 struct regcache
*regs
,
6585 arm_displaced_step_copy_insn_closure
*dsc
)
6587 int load
= bit (insn
, 20);
6588 int user
= bit (insn
, 22);
6589 int increment
= bit (insn
, 23);
6590 int before
= bit (insn
, 24);
6591 int writeback
= bit (insn
, 21);
6592 int rn
= bits (insn
, 16, 19);
6594 /* Block transfers which don't mention PC can be run directly
6596 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6597 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6599 if (rn
== ARM_PC_REGNUM
)
6601 warning (_("displaced: Unpredictable LDM or STM with "
6602 "base register r15"));
6603 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6606 displaced_debug_printf ("copying block transfer insn %.8lx",
6607 (unsigned long) insn
);
6609 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6610 dsc
->u
.block
.rn
= rn
;
6612 dsc
->u
.block
.load
= load
;
6613 dsc
->u
.block
.user
= user
;
6614 dsc
->u
.block
.increment
= increment
;
6615 dsc
->u
.block
.before
= before
;
6616 dsc
->u
.block
.writeback
= writeback
;
6617 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6619 dsc
->u
.block
.regmask
= insn
& 0xffff;
6623 if ((insn
& 0xffff) == 0xffff)
6625 /* LDM with a fully-populated register list. This case is
6626 particularly tricky. Implement for now by fully emulating the
6627 instruction (which might not behave perfectly in all cases, but
6628 these instructions should be rare enough for that not to matter
6630 dsc
->modinsn
[0] = ARM_NOP
;
6632 dsc
->cleanup
= &cleanup_block_load_all
;
6636 /* LDM of a list of registers which includes PC. Implement by
6637 rewriting the list of registers to be transferred into a
6638 contiguous chunk r0...rX before doing the transfer, then shuffling
6639 registers into the correct places in the cleanup routine. */
6640 unsigned int regmask
= insn
& 0xffff;
6641 unsigned int num_in_list
= count_one_bits (regmask
), new_regmask
;
6644 for (i
= 0; i
< num_in_list
; i
++)
6645 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6647 /* Writeback makes things complicated. We need to avoid clobbering
6648 the base register with one of the registers in our modified
6649 register list, but just using a different register can't work in
6652 ldm r14!, {r0-r13,pc}
6654 which would need to be rewritten as:
6658 but that can't work, because there's no free register for N.
6660 Solve this by turning off the writeback bit, and emulating
6661 writeback manually in the cleanup routine. */
6666 new_regmask
= (1 << num_in_list
) - 1;
6668 displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list "
6669 "%.4x, modified list %.4x",
6670 rn
, writeback
? "!" : "",
6671 (int) insn
& 0xffff, new_regmask
);
6673 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6675 dsc
->cleanup
= &cleanup_block_load_pc
;
6680 /* STM of a list of registers which includes PC. Run the instruction
6681 as-is, but out of line: this will store the wrong value for the PC,
6682 so we must manually fix up the memory in the cleanup routine.
6683 Doing things this way has the advantage that we can auto-detect
6684 the offset of the PC write (which is architecture-dependent) in
6685 the cleanup routine. */
6686 dsc
->modinsn
[0] = insn
;
6688 dsc
->cleanup
= &cleanup_block_store_pc
;
6695 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6696 struct regcache
*regs
,
6697 arm_displaced_step_copy_insn_closure
*dsc
)
6699 int rn
= bits (insn1
, 0, 3);
6700 int load
= bit (insn1
, 4);
6701 int writeback
= bit (insn1
, 5);
6703 /* Block transfers which don't mention PC can be run directly
6705 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6706 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6708 if (rn
== ARM_PC_REGNUM
)
6710 warning (_("displaced: Unpredictable LDM or STM with "
6711 "base register r15"));
6712 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6713 "unpredictable ldm/stm", dsc
);
6716 displaced_debug_printf ("copying block transfer insn %.4x%.4x",
6719 /* Clear bit 13, since it should be always zero. */
6720 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6721 dsc
->u
.block
.rn
= rn
;
6723 dsc
->u
.block
.load
= load
;
6724 dsc
->u
.block
.user
= 0;
6725 dsc
->u
.block
.increment
= bit (insn1
, 7);
6726 dsc
->u
.block
.before
= bit (insn1
, 8);
6727 dsc
->u
.block
.writeback
= writeback
;
6728 dsc
->u
.block
.cond
= INST_AL
;
6729 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6733 if (dsc
->u
.block
.regmask
== 0xffff)
6735 /* This branch is impossible to happen. */
6740 unsigned int regmask
= dsc
->u
.block
.regmask
;
6741 unsigned int num_in_list
= count_one_bits (regmask
), new_regmask
;
6744 for (i
= 0; i
< num_in_list
; i
++)
6745 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6750 new_regmask
= (1 << num_in_list
) - 1;
6752 displaced_debug_printf ("LDM r%d%s, {..., pc}: original reg list "
6753 "%.4x, modified list %.4x",
6754 rn
, writeback
? "!" : "",
6755 (int) dsc
->u
.block
.regmask
, new_regmask
);
6757 dsc
->modinsn
[0] = insn1
;
6758 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6761 dsc
->cleanup
= &cleanup_block_load_pc
;
6766 dsc
->modinsn
[0] = insn1
;
6767 dsc
->modinsn
[1] = insn2
;
6769 dsc
->cleanup
= &cleanup_block_store_pc
;
6774 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6775 This is used to avoid a dependency on BFD's bfd_endian enum. */
6778 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6781 return read_memory_unsigned_integer (memaddr
, len
,
6782 (enum bfd_endian
) byte_order
);
6785 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6788 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6791 return gdbarch_addr_bits_remove (self
->regcache
->arch (), val
);
6794 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6797 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6802 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6805 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6807 return arm_is_thumb (self
->regcache
);
6810 /* single_step() is called just before we want to resume the inferior,
6811 if we want to single-step it but there is no hardware or kernel
6812 single-step support. We find the target of the coming instructions
6813 and breakpoint them. */
6815 std::vector
<CORE_ADDR
>
6816 arm_software_single_step (struct regcache
*regcache
)
6818 struct gdbarch
*gdbarch
= regcache
->arch ();
6819 struct arm_get_next_pcs next_pcs_ctx
;
6821 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6822 &arm_get_next_pcs_ops
,
6823 gdbarch_byte_order (gdbarch
),
6824 gdbarch_byte_order_for_code (gdbarch
),
6828 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6830 for (CORE_ADDR
&pc_ref
: next_pcs
)
6831 pc_ref
= gdbarch_addr_bits_remove (gdbarch
, pc_ref
);
6836 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6837 for Linux, where some SVC instructions must be treated specially. */
6840 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6841 arm_displaced_step_copy_insn_closure
*dsc
)
6843 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6845 displaced_debug_printf ("cleanup for svc, resume at %.8lx",
6846 (unsigned long) resume_addr
);
6848 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6852 /* Common copy routine for svc instruction. */
6855 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6856 arm_displaced_step_copy_insn_closure
*dsc
)
6858 /* Preparation: none.
6859 Insn: unmodified svc.
6860 Cleanup: pc <- insn_addr + insn_size. */
6862 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6864 dsc
->wrote_to_pc
= 1;
6866 /* Allow OS-specific code to override SVC handling. */
6867 if (dsc
->u
.svc
.copy_svc_os
)
6868 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6871 dsc
->cleanup
= &cleanup_svc
;
6877 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6878 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
6881 displaced_debug_printf ("copying svc insn %.8lx",
6882 (unsigned long) insn
);
6884 dsc
->modinsn
[0] = insn
;
6886 return install_svc (gdbarch
, regs
, dsc
);
6890 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6891 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
6894 displaced_debug_printf ("copying svc insn %.4x", insn
);
6896 dsc
->modinsn
[0] = insn
;
6898 return install_svc (gdbarch
, regs
, dsc
);
6901 /* Copy undefined instructions. */
6904 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6905 arm_displaced_step_copy_insn_closure
*dsc
)
6907 displaced_debug_printf ("copying undefined insn %.8lx",
6908 (unsigned long) insn
);
6910 dsc
->modinsn
[0] = insn
;
6916 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6917 arm_displaced_step_copy_insn_closure
*dsc
)
6920 displaced_debug_printf ("copying undefined insn %.4x %.4x",
6921 (unsigned short) insn1
, (unsigned short) insn2
);
6923 dsc
->modinsn
[0] = insn1
;
6924 dsc
->modinsn
[1] = insn2
;
6930 /* Copy unpredictable instructions. */
6933 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6934 arm_displaced_step_copy_insn_closure
*dsc
)
6936 displaced_debug_printf ("copying unpredictable insn %.8lx",
6937 (unsigned long) insn
);
6939 dsc
->modinsn
[0] = insn
;
6944 /* The decode_* functions are instruction decoding helpers. They mostly follow
6945 the presentation in the ARM ARM. */
6948 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6949 struct regcache
*regs
,
6950 arm_displaced_step_copy_insn_closure
*dsc
)
6952 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6953 unsigned int rn
= bits (insn
, 16, 19);
6955 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0x1) == 0x0)
6956 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6957 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0x1) == 0x1)
6958 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6959 else if ((op1
& 0x60) == 0x20)
6960 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6961 else if ((op1
& 0x71) == 0x40)
6962 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6964 else if ((op1
& 0x77) == 0x41)
6965 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6966 else if ((op1
& 0x77) == 0x45)
6967 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6968 else if ((op1
& 0x77) == 0x51)
6971 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6973 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6975 else if ((op1
& 0x77) == 0x55)
6976 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6977 else if (op1
== 0x57)
6980 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6981 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6982 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6983 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6984 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6986 else if ((op1
& 0x63) == 0x43)
6987 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6988 else if ((op2
& 0x1) == 0x0)
6989 switch (op1
& ~0x80)
6992 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6994 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6995 case 0x71: case 0x75:
6997 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6998 case 0x63: case 0x67: case 0x73: case 0x77:
6999 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7001 return arm_copy_undef (gdbarch
, insn
, dsc
);
7004 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7008 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7009 struct regcache
*regs
,
7010 arm_displaced_step_copy_insn_closure
*dsc
)
7012 if (bit (insn
, 27) == 0)
7013 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7014 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7015 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7018 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7021 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7023 case 0x4: case 0x5: case 0x6: case 0x7:
7024 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7027 switch ((insn
& 0xe00000) >> 21)
7029 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7031 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7034 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7037 return arm_copy_undef (gdbarch
, insn
, dsc
);
7042 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7043 switch ((insn
& 0xe00000) >> 21)
7046 /* ldc/ldc2 imm (undefined for rn == pc). */
7047 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7048 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7051 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7053 case 0x4: case 0x5: case 0x6: case 0x7:
7054 /* ldc/ldc2 lit (undefined for rn != pc). */
7055 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7056 : arm_copy_undef (gdbarch
, insn
, dsc
);
7059 return arm_copy_undef (gdbarch
, insn
, dsc
);
7064 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7067 if (bits (insn
, 16, 19) == 0xf)
7069 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7071 return arm_copy_undef (gdbarch
, insn
, dsc
);
7075 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7077 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7081 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7083 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7086 return arm_copy_undef (gdbarch
, insn
, dsc
);
7090 /* Decode miscellaneous instructions in dp/misc encoding space. */
7093 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7094 struct regcache
*regs
,
7095 arm_displaced_step_copy_insn_closure
*dsc
)
7097 unsigned int op2
= bits (insn
, 4, 6);
7098 unsigned int op
= bits (insn
, 21, 22);
7103 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7106 if (op
== 0x1) /* bx. */
7107 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7109 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7111 return arm_copy_undef (gdbarch
, insn
, dsc
);
7115 /* Not really supported. */
7116 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7118 return arm_copy_undef (gdbarch
, insn
, dsc
);
7122 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7123 regs
, dsc
); /* blx register. */
7125 return arm_copy_undef (gdbarch
, insn
, dsc
);
7128 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7132 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7134 /* Not really supported. */
7135 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7139 return arm_copy_undef (gdbarch
, insn
, dsc
);
7144 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7145 struct regcache
*regs
,
7146 arm_displaced_step_copy_insn_closure
*dsc
)
7149 switch (bits (insn
, 20, 24))
7152 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7155 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7157 case 0x12: case 0x16:
7158 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7161 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7165 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7167 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7168 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7169 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7170 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7171 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7172 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7173 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7174 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7175 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7176 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7177 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7178 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7179 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7180 /* 2nd arg means "unprivileged". */
7181 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7185 /* Should be unreachable. */
7190 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7191 struct regcache
*regs
,
7192 arm_displaced_step_copy_insn_closure
*dsc
)
7194 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7195 uint32_t op1
= bits (insn
, 20, 24);
7197 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7198 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7199 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7200 else if ((!a
&& (op1
& 0x17) == 0x02)
7201 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7202 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7203 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7204 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7205 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7206 else if ((!a
&& (op1
& 0x17) == 0x03)
7207 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7208 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7209 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7210 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7211 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7212 else if ((!a
&& (op1
& 0x17) == 0x06)
7213 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7214 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7215 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7216 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7217 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7218 else if ((!a
&& (op1
& 0x17) == 0x07)
7219 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7220 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7222 /* Should be unreachable. */
7227 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7228 arm_displaced_step_copy_insn_closure
*dsc
)
7230 switch (bits (insn
, 20, 24))
7232 case 0x00: case 0x01: case 0x02: case 0x03:
7233 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7235 case 0x04: case 0x05: case 0x06: case 0x07:
7236 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7238 case 0x08: case 0x09: case 0x0a: case 0x0b:
7239 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7240 return arm_copy_unmodified (gdbarch
, insn
,
7241 "decode/pack/unpack/saturate/reverse", dsc
);
7244 if (bits (insn
, 5, 7) == 0) /* op2. */
7246 if (bits (insn
, 12, 15) == 0xf)
7247 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7249 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7252 return arm_copy_undef (gdbarch
, insn
, dsc
);
7254 case 0x1a: case 0x1b:
7255 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7256 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7258 return arm_copy_undef (gdbarch
, insn
, dsc
);
7260 case 0x1c: case 0x1d:
7261 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7263 if (bits (insn
, 0, 3) == 0xf)
7264 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7266 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7269 return arm_copy_undef (gdbarch
, insn
, dsc
);
7271 case 0x1e: case 0x1f:
7272 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7273 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7275 return arm_copy_undef (gdbarch
, insn
, dsc
);
7278 /* Should be unreachable. */
7283 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
7284 struct regcache
*regs
,
7285 arm_displaced_step_copy_insn_closure
*dsc
)
7288 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7290 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7294 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7295 struct regcache
*regs
,
7296 arm_displaced_step_copy_insn_closure
*dsc
)
7298 unsigned int opcode
= bits (insn
, 20, 24);
7302 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7303 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7305 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7306 case 0x12: case 0x16:
7307 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7309 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7310 case 0x13: case 0x17:
7311 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7313 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7314 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7315 /* Note: no writeback for these instructions. Bit 25 will always be
7316 zero though (via caller), so the following works OK. */
7317 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7320 /* Should be unreachable. */
7324 /* Decode shifted register instructions. */
7327 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7328 uint16_t insn2
, struct regcache
*regs
,
7329 arm_displaced_step_copy_insn_closure
*dsc
)
7331 /* PC is only allowed to be used in instruction MOV. */
7333 unsigned int op
= bits (insn1
, 5, 8);
7334 unsigned int rn
= bits (insn1
, 0, 3);
7336 if (op
== 0x2 && rn
== 0xf) /* MOV */
7337 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7339 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7340 "dp (shift reg)", dsc
);
7344 /* Decode extension register load/store. Exactly the same as
7345 arm_decode_ext_reg_ld_st. */
7348 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7349 uint16_t insn2
, struct regcache
*regs
,
7350 arm_displaced_step_copy_insn_closure
*dsc
)
7352 unsigned int opcode
= bits (insn1
, 4, 8);
7356 case 0x04: case 0x05:
7357 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7358 "vfp/neon vmov", dsc
);
7360 case 0x08: case 0x0c: /* 01x00 */
7361 case 0x0a: case 0x0e: /* 01x10 */
7362 case 0x12: case 0x16: /* 10x10 */
7363 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7364 "vfp/neon vstm/vpush", dsc
);
7366 case 0x09: case 0x0d: /* 01x01 */
7367 case 0x0b: case 0x0f: /* 01x11 */
7368 case 0x13: case 0x17: /* 10x11 */
7369 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7370 "vfp/neon vldm/vpop", dsc
);
7372 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7373 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7375 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7376 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7379 /* Should be unreachable. */
7384 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
7385 regcache
*regs
, arm_displaced_step_copy_insn_closure
*dsc
)
7387 unsigned int op1
= bits (insn
, 20, 25);
7388 int op
= bit (insn
, 4);
7389 unsigned int coproc
= bits (insn
, 8, 11);
7391 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7392 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7393 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7394 && (coproc
& 0xe) != 0xa)
7396 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7397 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7398 && (coproc
& 0xe) != 0xa)
7399 /* ldc/ldc2 imm/lit. */
7400 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7401 else if ((op1
& 0x3e) == 0x00)
7402 return arm_copy_undef (gdbarch
, insn
, dsc
);
7403 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7404 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7405 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7406 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7407 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7408 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7409 else if ((op1
& 0x30) == 0x20 && !op
)
7411 if ((coproc
& 0xe) == 0xa)
7412 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7414 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7416 else if ((op1
& 0x30) == 0x20 && op
)
7417 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7418 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7419 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7420 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7421 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7422 else if ((op1
& 0x30) == 0x30)
7423 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7425 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7429 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7430 uint16_t insn2
, struct regcache
*regs
,
7431 arm_displaced_step_copy_insn_closure
*dsc
)
7433 unsigned int coproc
= bits (insn2
, 8, 11);
7434 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7435 unsigned int bit_9
= bit (insn1
, 9);
7436 unsigned int bit_4
= bit (insn1
, 4);
7441 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7442 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7444 else if (bit_5_8
== 0) /* UNDEFINED. */
7445 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7448 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7449 if ((coproc
& 0xe) == 0xa)
7450 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7452 else /* coproc is not 101x. */
7454 if (bit_4
== 0) /* STC/STC2. */
7455 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7457 else /* LDC/LDC2 {literal, immediate}. */
7458 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7464 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7470 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7471 arm_displaced_step_copy_insn_closure
*dsc
, int rd
)
7477 Preparation: Rd <- PC
7483 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7484 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7488 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7489 arm_displaced_step_copy_insn_closure
*dsc
,
7490 int rd
, unsigned int imm
)
7493 /* Encoding T2: ADDS Rd, #imm */
7494 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7496 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7502 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7503 struct regcache
*regs
,
7504 arm_displaced_step_copy_insn_closure
*dsc
)
7506 unsigned int rd
= bits (insn
, 8, 10);
7507 unsigned int imm8
= bits (insn
, 0, 7);
7509 displaced_debug_printf ("copying thumb adr r%d, #%d insn %.4x",
7512 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7516 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7517 uint16_t insn2
, struct regcache
*regs
,
7518 arm_displaced_step_copy_insn_closure
*dsc
)
7520 unsigned int rd
= bits (insn2
, 8, 11);
7521 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7522 extract raw immediate encoding rather than computing immediate. When
7523 generating ADD or SUB instruction, we can simply perform OR operation to
7524 set immediate into ADD. */
7525 unsigned int imm_3_8
= insn2
& 0x70ff;
7526 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7528 displaced_debug_printf ("copying thumb adr r%d, #%d:%d insn %.4x%.4x",
7529 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7531 if (bit (insn1
, 7)) /* Encoding T2 */
7533 /* Encoding T3: SUB Rd, Rd, #imm */
7534 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7535 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7537 else /* Encoding T3 */
7539 /* Encoding T3: ADD Rd, Rd, #imm */
7540 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7541 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7545 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7551 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7552 struct regcache
*regs
,
7553 arm_displaced_step_copy_insn_closure
*dsc
)
7555 unsigned int rt
= bits (insn1
, 8, 10);
7557 int imm8
= (bits (insn1
, 0, 7) << 2);
7563 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7565 Insn: LDR R0, [R2, R3];
7566 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7568 displaced_debug_printf ("copying thumb ldr r%d [pc #%d]", rt
, imm8
);
7570 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7571 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7572 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7573 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7574 /* The assembler calculates the required value of the offset from the
7575 Align(PC,4) value of this instruction to the label. */
7576 pc
= pc
& 0xfffffffc;
7578 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7579 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7582 dsc
->u
.ldst
.xfersize
= 4;
7584 dsc
->u
.ldst
.immed
= 0;
7585 dsc
->u
.ldst
.writeback
= 0;
7586 dsc
->u
.ldst
.restore_r4
= 0;
7588 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7590 dsc
->cleanup
= &cleanup_load
;
7595 /* Copy Thumb cbnz/cbz instruction. */
7598 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7599 struct regcache
*regs
,
7600 arm_displaced_step_copy_insn_closure
*dsc
)
7602 int non_zero
= bit (insn1
, 11);
7603 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7604 CORE_ADDR from
= dsc
->insn_addr
;
7605 int rn
= bits (insn1
, 0, 2);
7606 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7608 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7609 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7610 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7611 condition is false, let it be, cleanup_branch will do nothing. */
7612 if (dsc
->u
.branch
.cond
)
7614 dsc
->u
.branch
.cond
= INST_AL
;
7615 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7618 dsc
->u
.branch
.dest
= from
+ 2;
7620 dsc
->u
.branch
.link
= 0;
7621 dsc
->u
.branch
.exchange
= 0;
7623 displaced_debug_printf ("copying %s [r%d = 0x%x] insn %.4x to %.8lx",
7624 non_zero
? "cbnz" : "cbz",
7625 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7627 dsc
->modinsn
[0] = THUMB_NOP
;
7629 dsc
->cleanup
= &cleanup_branch
;
7633 /* Copy Table Branch Byte/Halfword */
7635 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7636 uint16_t insn2
, struct regcache
*regs
,
7637 arm_displaced_step_copy_insn_closure
*dsc
)
7639 ULONGEST rn_val
, rm_val
;
7640 int is_tbh
= bit (insn2
, 4);
7641 CORE_ADDR halfwords
= 0;
7642 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7644 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7645 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7651 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7652 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7658 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7659 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7662 displaced_debug_printf ("%s base 0x%x offset 0x%x offset 0x%x",
7663 is_tbh
? "tbh" : "tbb",
7664 (unsigned int) rn_val
, (unsigned int) rm_val
,
7665 (unsigned int) halfwords
);
7667 dsc
->u
.branch
.cond
= INST_AL
;
7668 dsc
->u
.branch
.link
= 0;
7669 dsc
->u
.branch
.exchange
= 0;
7670 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7672 dsc
->cleanup
= &cleanup_branch
;
7678 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7679 arm_displaced_step_copy_insn_closure
*dsc
)
7682 int val
= displaced_read_reg (regs
, dsc
, 7);
7683 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7686 val
= displaced_read_reg (regs
, dsc
, 8);
7687 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7690 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7695 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7696 struct regcache
*regs
,
7697 arm_displaced_step_copy_insn_closure
*dsc
)
7699 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7701 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7704 (1) register list is full, that is, r0-r7 are used.
7705 Prepare: tmp[0] <- r8
7707 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7708 MOV r8, r7; Move value of r7 to r8;
7709 POP {r7}; Store PC value into r7.
7711 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7713 (2) register list is not full, supposing there are N registers in
7714 register list (except PC, 0 <= N <= 7).
7715 Prepare: for each i, 0 - N, tmp[i] <- ri.
7717 POP {r0, r1, ...., rN};
7719 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7720 from tmp[] properly.
7722 displaced_debug_printf ("copying thumb pop {%.8x, pc} insn %.4x",
7723 dsc
->u
.block
.regmask
, insn1
);
7725 if (dsc
->u
.block
.regmask
== 0xff)
7727 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7729 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7730 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7731 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7734 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7738 unsigned int num_in_list
= count_one_bits (dsc
->u
.block
.regmask
);
7740 unsigned int new_regmask
;
7742 for (i
= 0; i
< num_in_list
+ 1; i
++)
7743 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7745 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7747 displaced_debug_printf ("POP {..., pc}: original reg list %.4x, "
7748 "modified list %.4x",
7749 (int) dsc
->u
.block
.regmask
, new_regmask
);
7751 dsc
->u
.block
.regmask
|= 0x8000;
7752 dsc
->u
.block
.writeback
= 0;
7753 dsc
->u
.block
.cond
= INST_AL
;
7755 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7757 dsc
->cleanup
= &cleanup_block_load_pc
;
7764 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7765 struct regcache
*regs
,
7766 arm_displaced_step_copy_insn_closure
*dsc
)
7768 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7769 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7772 /* 16-bit thumb instructions. */
7773 switch (op_bit_12_15
)
7775 /* Shift (imme), add, subtract, move and compare. */
7776 case 0: case 1: case 2: case 3:
7777 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7778 "shift/add/sub/mov/cmp",
7782 switch (op_bit_10_11
)
7784 case 0: /* Data-processing */
7785 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7789 case 1: /* Special data instructions and branch and exchange. */
7791 unsigned short op
= bits (insn1
, 7, 9);
7792 if (op
== 6 || op
== 7) /* BX or BLX */
7793 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7794 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7795 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7797 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7801 default: /* LDR (literal) */
7802 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7805 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7806 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7809 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7810 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7811 else /* Generate SP-relative address */
7812 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7814 case 11: /* Misc 16-bit instructions */
7816 switch (bits (insn1
, 8, 11))
7818 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7819 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7821 case 12: case 13: /* POP */
7822 if (bit (insn1
, 8)) /* PC is in register list. */
7823 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7825 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7827 case 15: /* If-Then, and hints */
7828 if (bits (insn1
, 0, 3))
7829 /* If-Then makes up to four following instructions conditional.
7830 IT instruction itself is not conditional, so handle it as a
7831 common unmodified instruction. */
7832 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7835 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7838 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7843 if (op_bit_10_11
< 2) /* Store multiple registers */
7844 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7845 else /* Load multiple registers */
7846 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7848 case 13: /* Conditional branch and supervisor call */
7849 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7850 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7852 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7854 case 14: /* Unconditional branch */
7855 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7862 internal_error (__FILE__
, __LINE__
,
7863 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7867 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7868 uint16_t insn1
, uint16_t insn2
,
7869 struct regcache
*regs
,
7870 arm_displaced_step_copy_insn_closure
*dsc
)
7872 int rt
= bits (insn2
, 12, 15);
7873 int rn
= bits (insn1
, 0, 3);
7874 int op1
= bits (insn1
, 7, 8);
7876 switch (bits (insn1
, 5, 6))
7878 case 0: /* Load byte and memory hints */
7879 if (rt
== 0xf) /* PLD/PLI */
7882 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7883 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7885 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7890 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7891 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7894 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7895 "ldrb{reg, immediate}/ldrbt",
7900 case 1: /* Load halfword and memory hints. */
7901 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7902 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7903 "pld/unalloc memhint", dsc
);
7907 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7910 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7914 case 2: /* Load word */
7916 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7919 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7920 else if (op1
== 0x1) /* Encoding T3 */
7921 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7923 else /* op1 == 0x0 */
7925 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7926 /* LDR (immediate) */
7927 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7928 dsc
, bit (insn2
, 8), 1);
7929 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7930 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7933 /* LDR (register) */
7934 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7940 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7947 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7948 uint16_t insn2
, struct regcache
*regs
,
7949 arm_displaced_step_copy_insn_closure
*dsc
)
7952 unsigned short op
= bit (insn2
, 15);
7953 unsigned int op1
= bits (insn1
, 11, 12);
7959 switch (bits (insn1
, 9, 10))
7964 /* Load/store {dual, exclusive}, table branch. */
7965 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7966 && bits (insn2
, 5, 7) == 0)
7967 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7970 /* PC is not allowed to use in load/store {dual, exclusive}
7972 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7973 "load/store dual/ex", dsc
);
7975 else /* load/store multiple */
7977 switch (bits (insn1
, 7, 8))
7979 case 0: case 3: /* SRS, RFE */
7980 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7983 case 1: case 2: /* LDM/STM/PUSH/POP */
7984 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7991 /* Data-processing (shift register). */
7992 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7995 default: /* Coprocessor instructions. */
7996 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8001 case 2: /* op1 = 2 */
8002 if (op
) /* Branch and misc control. */
8004 if (bit (insn2
, 14) /* BLX/BL */
8005 || bit (insn2
, 12) /* Unconditional branch */
8006 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8007 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8009 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8014 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8016 int dp_op
= bits (insn1
, 4, 8);
8017 int rn
= bits (insn1
, 0, 3);
8018 if ((dp_op
== 0 || dp_op
== 0xa) && rn
== 0xf)
8019 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8022 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8025 else /* Data processing (modified immediate) */
8026 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8030 case 3: /* op1 = 3 */
8031 switch (bits (insn1
, 9, 10))
8035 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8037 else /* NEON Load/Store and Store single data item */
8038 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8039 "neon elt/struct load/store",
8042 case 1: /* op1 = 3, bits (9, 10) == 1 */
8043 switch (bits (insn1
, 7, 8))
8045 case 0: case 1: /* Data processing (register) */
8046 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8049 case 2: /* Multiply and absolute difference */
8050 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8051 "mul/mua/diff", dsc
);
8053 case 3: /* Long multiply and divide */
8054 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8059 default: /* Coprocessor instructions */
8060 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8069 internal_error (__FILE__
, __LINE__
,
8070 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8075 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8076 struct regcache
*regs
,
8077 arm_displaced_step_copy_insn_closure
*dsc
)
8079 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8081 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8083 displaced_debug_printf ("process thumb insn %.4x at %.8lx",
8084 insn1
, (unsigned long) from
);
8087 dsc
->insn_size
= thumb_insn_size (insn1
);
8088 if (thumb_insn_size (insn1
) == 4)
8091 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8092 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8095 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8099 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8100 CORE_ADDR to
, struct regcache
*regs
,
8101 arm_displaced_step_copy_insn_closure
*dsc
)
8104 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8107 /* Most displaced instructions use a 1-instruction scratch space, so set this
8108 here and override below if/when necessary. */
8110 dsc
->insn_addr
= from
;
8111 dsc
->scratch_base
= to
;
8112 dsc
->cleanup
= NULL
;
8113 dsc
->wrote_to_pc
= 0;
8115 if (!displaced_in_arm_mode (regs
))
8116 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
8120 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8121 displaced_debug_printf ("stepping insn %.8lx at %.8lx",
8122 (unsigned long) insn
, (unsigned long) from
);
8124 if ((insn
& 0xf0000000) == 0xf0000000)
8125 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8126 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8128 case 0x0: case 0x1: case 0x2: case 0x3:
8129 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8132 case 0x4: case 0x5: case 0x6:
8133 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8137 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8140 case 0x8: case 0x9: case 0xa: case 0xb:
8141 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8144 case 0xc: case 0xd: case 0xe: case 0xf:
8145 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
8150 internal_error (__FILE__
, __LINE__
,
8151 _("arm_process_displaced_insn: Instruction decode error"));
8154 /* Actually set up the scratch space for a displaced instruction. */
8157 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8159 arm_displaced_step_copy_insn_closure
*dsc
)
8161 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8162 unsigned int i
, len
, offset
;
8163 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8164 int size
= dsc
->is_thumb
? 2 : 4;
8165 const gdb_byte
*bkp_insn
;
8168 /* Poke modified instruction(s). */
8169 for (i
= 0; i
< dsc
->numinsns
; i
++)
8172 displaced_debug_printf ("writing insn %.8lx at %.8lx",
8173 dsc
->modinsn
[i
], (unsigned long) to
+ offset
);
8175 displaced_debug_printf ("writing insn %.4x at %.8lx",
8176 (unsigned short) dsc
->modinsn
[i
],
8177 (unsigned long) to
+ offset
);
8179 write_memory_unsigned_integer (to
+ offset
, size
,
8180 byte_order_for_code
,
8185 /* Choose the correct breakpoint instruction. */
8188 bkp_insn
= tdep
->thumb_breakpoint
;
8189 len
= tdep
->thumb_breakpoint_size
;
8193 bkp_insn
= tdep
->arm_breakpoint
;
8194 len
= tdep
->arm_breakpoint_size
;
8197 /* Put breakpoint afterwards. */
8198 write_memory (to
+ offset
, bkp_insn
, len
);
8200 displaced_debug_printf ("copy %s->%s", paddress (gdbarch
, from
),
8201 paddress (gdbarch
, to
));
8204 /* Entry point for cleaning things up after a displaced instruction has been
8208 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8209 struct displaced_step_copy_insn_closure
*dsc_
,
8210 CORE_ADDR from
, CORE_ADDR to
,
8211 struct regcache
*regs
)
8213 arm_displaced_step_copy_insn_closure
*dsc
8214 = (arm_displaced_step_copy_insn_closure
*) dsc_
;
8217 dsc
->cleanup (gdbarch
, regs
, dsc
);
8219 if (!dsc
->wrote_to_pc
)
8220 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8221 dsc
->insn_addr
+ dsc
->insn_size
);
8225 #include "bfd-in2.h"
8226 #include "libcoff.h"
8229 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8231 gdb_disassembler
*di
8232 = static_cast<gdb_disassembler
*>(info
->application_data
);
8233 struct gdbarch
*gdbarch
= di
->arch ();
8235 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8237 static asymbol
*asym
;
8238 static combined_entry_type ce
;
8239 static struct coff_symbol_struct csym
;
8240 static struct bfd fake_bfd
;
8241 static bfd_target fake_target
;
8243 if (csym
.native
== NULL
)
8245 /* Create a fake symbol vector containing a Thumb symbol.
8246 This is solely so that the code in print_insn_little_arm()
8247 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8248 the presence of a Thumb symbol and switch to decoding
8249 Thumb instructions. */
8251 fake_target
.flavour
= bfd_target_coff_flavour
;
8252 fake_bfd
.xvec
= &fake_target
;
8253 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8255 csym
.symbol
.the_bfd
= &fake_bfd
;
8256 csym
.symbol
.name
= "fake";
8257 asym
= (asymbol
*) & csym
;
8260 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8261 info
->symbols
= &asym
;
8264 info
->symbols
= NULL
;
8266 /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
8267 accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
8268 opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
8269 the assert on the mismatch of info->mach and
8270 bfd_get_mach (current_program_space->exec_bfd ()) in
8271 default_print_insn. */
8272 if (current_program_space
->exec_bfd () != NULL
8273 && (current_program_space
->exec_bfd ()->arch_info
8274 == gdbarch_bfd_arch_info (gdbarch
)))
8275 info
->flags
|= USER_SPECIFIED_MACHINE_TYPE
;
8277 return default_print_insn (memaddr
, info
);
8280 /* The following define instruction sequences that will cause ARM
8281 cpu's to take an undefined instruction trap. These are used to
8282 signal a breakpoint to GDB.
8284 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8285 modes. A different instruction is required for each mode. The ARM
8286 cpu's can also be big or little endian. Thus four different
8287 instructions are needed to support all cases.
8289 Note: ARMv4 defines several new instructions that will take the
8290 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8291 not in fact add the new instructions. The new undefined
8292 instructions in ARMv4 are all instructions that had no defined
8293 behaviour in earlier chips. There is no guarantee that they will
8294 raise an exception, but may be treated as NOP's. In practice, it
8295 may only safe to rely on instructions matching:
8297 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8298 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8299 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8301 Even this may only true if the condition predicate is true. The
8302 following use a condition predicate of ALWAYS so it is always TRUE.
8304 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8305 and NetBSD all use a software interrupt rather than an undefined
8306 instruction to force a trap. This can be handled by by the
8307 abi-specific code during establishment of the gdbarch vector. */
8309 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8310 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8311 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8312 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8314 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8315 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8316 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8317 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8319 /* Implement the breakpoint_kind_from_pc gdbarch method. */
8322 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
8324 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8325 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8327 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8329 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8331 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8332 check whether we are replacing a 32-bit instruction. */
8333 if (tdep
->thumb2_breakpoint
!= NULL
)
8337 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8339 unsigned short inst1
;
8341 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8342 if (thumb_insn_size (inst1
) == 4)
8343 return ARM_BP_KIND_THUMB2
;
8347 return ARM_BP_KIND_THUMB
;
8350 return ARM_BP_KIND_ARM
;
8354 /* Implement the sw_breakpoint_from_kind gdbarch method. */
8356 static const gdb_byte
*
8357 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
8359 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8363 case ARM_BP_KIND_ARM
:
8364 *size
= tdep
->arm_breakpoint_size
;
8365 return tdep
->arm_breakpoint
;
8366 case ARM_BP_KIND_THUMB
:
8367 *size
= tdep
->thumb_breakpoint_size
;
8368 return tdep
->thumb_breakpoint
;
8369 case ARM_BP_KIND_THUMB2
:
8370 *size
= tdep
->thumb2_breakpoint_size
;
8371 return tdep
->thumb2_breakpoint
;
8373 gdb_assert_not_reached ("unexpected arm breakpoint kind");
8377 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
8380 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
8381 struct regcache
*regcache
,
8386 /* Check the memory pointed by PC is readable. */
8387 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
8389 struct arm_get_next_pcs next_pcs_ctx
;
8391 arm_get_next_pcs_ctor (&next_pcs_ctx
,
8392 &arm_get_next_pcs_ops
,
8393 gdbarch_byte_order (gdbarch
),
8394 gdbarch_byte_order_for_code (gdbarch
),
8398 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
8400 /* If MEMADDR is the next instruction of current pc, do the
8401 software single step computation, and get the thumb mode by
8402 the destination address. */
8403 for (CORE_ADDR pc
: next_pcs
)
8405 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
8407 if (IS_THUMB_ADDR (pc
))
8409 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
8410 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
8413 return ARM_BP_KIND_ARM
;
8418 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
8421 /* Extract from an array REGBUF containing the (raw) register state a
8422 function return value of type TYPE, and copy that, in virtual
8423 format, into VALBUF. */
8426 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8429 struct gdbarch
*gdbarch
= regs
->arch ();
8430 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8431 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8433 if (TYPE_CODE_FLT
== type
->code ())
8435 switch (tdep
->fp_model
)
8439 /* The value is in register F0 in internal format. We need to
8440 extract the raw value and then convert it to the desired
8442 bfd_byte tmpbuf
[ARM_FP_REGISTER_SIZE
];
8444 regs
->cooked_read (ARM_F0_REGNUM
, tmpbuf
);
8445 target_float_convert (tmpbuf
, arm_ext_type (gdbarch
),
8450 case ARM_FLOAT_SOFT_FPA
:
8451 case ARM_FLOAT_SOFT_VFP
:
8452 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8453 not using the VFP ABI code. */
8455 regs
->cooked_read (ARM_A1_REGNUM
, valbuf
);
8456 if (TYPE_LENGTH (type
) > 4)
8457 regs
->cooked_read (ARM_A1_REGNUM
+ 1,
8458 valbuf
+ ARM_INT_REGISTER_SIZE
);
8462 internal_error (__FILE__
, __LINE__
,
8463 _("arm_extract_return_value: "
8464 "Floating point model not supported"));
8468 else if (type
->code () == TYPE_CODE_INT
8469 || type
->code () == TYPE_CODE_CHAR
8470 || type
->code () == TYPE_CODE_BOOL
8471 || type
->code () == TYPE_CODE_PTR
8472 || TYPE_IS_REFERENCE (type
)
8473 || type
->code () == TYPE_CODE_ENUM
8474 || is_fixed_point_type (type
))
8476 /* If the type is a plain integer, then the access is
8477 straight-forward. Otherwise we have to play around a bit
8479 int len
= TYPE_LENGTH (type
);
8480 int regno
= ARM_A1_REGNUM
;
8485 /* By using store_unsigned_integer we avoid having to do
8486 anything special for small big-endian values. */
8487 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8488 store_unsigned_integer (valbuf
,
8489 (len
> ARM_INT_REGISTER_SIZE
8490 ? ARM_INT_REGISTER_SIZE
: len
),
8492 len
-= ARM_INT_REGISTER_SIZE
;
8493 valbuf
+= ARM_INT_REGISTER_SIZE
;
8498 /* For a structure or union the behaviour is as if the value had
8499 been stored to word-aligned memory and then loaded into
8500 registers with 32-bit load instruction(s). */
8501 int len
= TYPE_LENGTH (type
);
8502 int regno
= ARM_A1_REGNUM
;
8503 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
8507 regs
->cooked_read (regno
++, tmpbuf
);
8508 memcpy (valbuf
, tmpbuf
,
8509 len
> ARM_INT_REGISTER_SIZE
? ARM_INT_REGISTER_SIZE
: len
);
8510 len
-= ARM_INT_REGISTER_SIZE
;
8511 valbuf
+= ARM_INT_REGISTER_SIZE
;
8517 /* Will a function return an aggregate type in memory or in a
8518 register? Return 0 if an aggregate type can be returned in a
8519 register, 1 if it must be returned in memory. */
8522 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8524 enum type_code code
;
8526 type
= check_typedef (type
);
8528 /* Simple, non-aggregate types (ie not including vectors and
8529 complex) are always returned in a register (or registers). */
8530 code
= type
->code ();
8531 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8532 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8535 if (TYPE_CODE_ARRAY
== code
&& type
->is_vector ())
8537 /* Vector values should be returned using ARM registers if they
8538 are not over 16 bytes. */
8539 return (TYPE_LENGTH (type
) > 16);
8542 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8543 if (tdep
->arm_abi
!= ARM_ABI_APCS
)
8545 /* The AAPCS says all aggregates not larger than a word are returned
8547 if (TYPE_LENGTH (type
) <= ARM_INT_REGISTER_SIZE
8548 && language_pass_by_reference (type
).trivially_copyable
)
8557 /* All aggregate types that won't fit in a register must be returned
8559 if (TYPE_LENGTH (type
) > ARM_INT_REGISTER_SIZE
8560 || !language_pass_by_reference (type
).trivially_copyable
)
8563 /* In the ARM ABI, "integer" like aggregate types are returned in
8564 registers. For an aggregate type to be integer like, its size
8565 must be less than or equal to ARM_INT_REGISTER_SIZE and the
8566 offset of each addressable subfield must be zero. Note that bit
8567 fields are not addressable, and all addressable subfields of
8568 unions always start at offset zero.
8570 This function is based on the behaviour of GCC 2.95.1.
8571 See: gcc/arm.c: arm_return_in_memory() for details.
8573 Note: All versions of GCC before GCC 2.95.2 do not set up the
8574 parameters correctly for a function returning the following
8575 structure: struct { float f;}; This should be returned in memory,
8576 not a register. Richard Earnshaw sent me a patch, but I do not
8577 know of any way to detect if a function like the above has been
8578 compiled with the correct calling convention. */
8580 /* Assume all other aggregate types can be returned in a register.
8581 Run a check for structures, unions and arrays. */
8584 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8587 /* Need to check if this struct/union is "integer" like. For
8588 this to be true, its size must be less than or equal to
8589 ARM_INT_REGISTER_SIZE and the offset of each addressable
8590 subfield must be zero. Note that bit fields are not
8591 addressable, and unions always start at offset zero. If any
8592 of the subfields is a floating point type, the struct/union
8593 cannot be an integer type. */
8595 /* For each field in the object, check:
8596 1) Is it FP? --> yes, nRc = 1;
8597 2) Is it addressable (bitpos != 0) and
8598 not packed (bitsize == 0)?
8602 for (i
= 0; i
< type
->num_fields (); i
++)
8604 enum type_code field_type_code
;
8607 = check_typedef (type
->field (i
).type ())->code ();
8609 /* Is it a floating point type field? */
8610 if (field_type_code
== TYPE_CODE_FLT
)
8616 /* If bitpos != 0, then we have to care about it. */
8617 if (type
->field (i
).loc_bitpos () != 0)
8619 /* Bitfields are not addressable. If the field bitsize is
8620 zero, then the field is not packed. Hence it cannot be
8621 a bitfield or any other packed type. */
8622 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8635 /* Write into appropriate registers a function return value of type
8636 TYPE, given in virtual format. */
8639 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8640 const gdb_byte
*valbuf
)
8642 struct gdbarch
*gdbarch
= regs
->arch ();
8643 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8645 if (type
->code () == TYPE_CODE_FLT
)
8647 gdb_byte buf
[ARM_FP_REGISTER_SIZE
];
8648 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8650 switch (tdep
->fp_model
)
8654 target_float_convert (valbuf
, type
, buf
, arm_ext_type (gdbarch
));
8655 regs
->cooked_write (ARM_F0_REGNUM
, buf
);
8658 case ARM_FLOAT_SOFT_FPA
:
8659 case ARM_FLOAT_SOFT_VFP
:
8660 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8661 not using the VFP ABI code. */
8663 regs
->cooked_write (ARM_A1_REGNUM
, valbuf
);
8664 if (TYPE_LENGTH (type
) > 4)
8665 regs
->cooked_write (ARM_A1_REGNUM
+ 1,
8666 valbuf
+ ARM_INT_REGISTER_SIZE
);
8670 internal_error (__FILE__
, __LINE__
,
8671 _("arm_store_return_value: Floating "
8672 "point model not supported"));
8676 else if (type
->code () == TYPE_CODE_INT
8677 || type
->code () == TYPE_CODE_CHAR
8678 || type
->code () == TYPE_CODE_BOOL
8679 || type
->code () == TYPE_CODE_PTR
8680 || TYPE_IS_REFERENCE (type
)
8681 || type
->code () == TYPE_CODE_ENUM
)
8683 if (TYPE_LENGTH (type
) <= 4)
8685 /* Values of one word or less are zero/sign-extended and
8687 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
8688 LONGEST val
= unpack_long (type
, valbuf
);
8690 store_signed_integer (tmpbuf
, ARM_INT_REGISTER_SIZE
, byte_order
, val
);
8691 regs
->cooked_write (ARM_A1_REGNUM
, tmpbuf
);
8695 /* Integral values greater than one word are stored in consecutive
8696 registers starting with r0. This will always be a multiple of
8697 the regiser size. */
8698 int len
= TYPE_LENGTH (type
);
8699 int regno
= ARM_A1_REGNUM
;
8703 regs
->cooked_write (regno
++, valbuf
);
8704 len
-= ARM_INT_REGISTER_SIZE
;
8705 valbuf
+= ARM_INT_REGISTER_SIZE
;
8711 /* For a structure or union the behaviour is as if the value had
8712 been stored to word-aligned memory and then loaded into
8713 registers with 32-bit load instruction(s). */
8714 int len
= TYPE_LENGTH (type
);
8715 int regno
= ARM_A1_REGNUM
;
8716 bfd_byte tmpbuf
[ARM_INT_REGISTER_SIZE
];
8720 memcpy (tmpbuf
, valbuf
,
8721 len
> ARM_INT_REGISTER_SIZE
? ARM_INT_REGISTER_SIZE
: len
);
8722 regs
->cooked_write (regno
++, tmpbuf
);
8723 len
-= ARM_INT_REGISTER_SIZE
;
8724 valbuf
+= ARM_INT_REGISTER_SIZE
;
8730 /* Handle function return values. */
8732 static enum return_value_convention
8733 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8734 struct type
*valtype
, struct regcache
*regcache
,
8735 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8737 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8738 struct type
*func_type
= function
? value_type (function
) : NULL
;
8739 enum arm_vfp_cprc_base_type vfp_base_type
;
8742 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8743 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8745 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8746 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8748 for (i
= 0; i
< vfp_base_count
; i
++)
8750 if (reg_char
== 'q')
8753 arm_neon_quad_write (gdbarch
, regcache
, i
,
8754 writebuf
+ i
* unit_length
);
8757 arm_neon_quad_read (gdbarch
, regcache
, i
,
8758 readbuf
+ i
* unit_length
);
8765 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8766 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8769 regcache
->cooked_write (regnum
, writebuf
+ i
* unit_length
);
8771 regcache
->cooked_read (regnum
, readbuf
+ i
* unit_length
);
8774 return RETURN_VALUE_REGISTER_CONVENTION
;
8777 if (valtype
->code () == TYPE_CODE_STRUCT
8778 || valtype
->code () == TYPE_CODE_UNION
8779 || valtype
->code () == TYPE_CODE_ARRAY
)
8781 /* From the AAPCS document:
8785 A Composite Type larger than 4 bytes, or whose size cannot be
8786 determined statically by both caller and callee, is stored in memory
8787 at an address passed as an extra argument when the function was
8788 called (Parameter Passing, rule A.4). The memory to be used for the
8789 result may be modified at any point during the function call.
8793 A.4: If the subroutine is a function that returns a result in memory,
8794 then the address for the result is placed in r0 and the NCRN is set
8796 if (tdep
->struct_return
== pcc_struct_return
8797 || arm_return_in_memory (gdbarch
, valtype
))
8803 regcache
->cooked_read (ARM_A1_REGNUM
, &addr
);
8804 read_memory (addr
, readbuf
, TYPE_LENGTH (valtype
));
8806 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
8809 else if (valtype
->code () == TYPE_CODE_COMPLEX
)
8811 if (arm_return_in_memory (gdbarch
, valtype
))
8812 return RETURN_VALUE_STRUCT_CONVENTION
;
8816 arm_store_return_value (valtype
, regcache
, writebuf
);
8819 arm_extract_return_value (valtype
, regcache
, readbuf
);
8821 return RETURN_VALUE_REGISTER_CONVENTION
;
8826 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8828 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8829 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8830 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8832 gdb_byte buf
[ARM_INT_REGISTER_SIZE
];
8834 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8836 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8837 ARM_INT_REGISTER_SIZE
))
8840 *pc
= extract_unsigned_integer (buf
, ARM_INT_REGISTER_SIZE
, byte_order
);
8843 /* A call to cmse secure entry function "foo" at "a" is modified by
8850 b) bl yyyy <__acle_se_foo>
8852 section .gnu.sgstubs:
8854 yyyy: sg // secure gateway
8855 b.w xxxx <__acle_se_foo> // original_branch_dest
8860 When the control at "b", the pc contains "yyyy" (sg address) which is a
8861 trampoline and does not exist in source code. This function returns the
8862 target pc "xxxx". For more details please refer to section 5.4
8863 (Entry functions) and section 3.4.4 (C level development flow of secure code)
8864 of "armv8-m-security-extensions-requirements-on-development-tools-engineering-specification"
8865 document on www.developer.arm.com. */
8868 arm_skip_cmse_entry (CORE_ADDR pc
, const char *name
, struct objfile
*objfile
)
8870 int target_len
= strlen (name
) + strlen ("__acle_se_") + 1;
8871 char *target_name
= (char *) alloca (target_len
);
8872 xsnprintf (target_name
, target_len
, "%s%s", "__acle_se_", name
);
8874 struct bound_minimal_symbol minsym
8875 = lookup_minimal_symbol (target_name
, NULL
, objfile
);
8877 if (minsym
.minsym
!= nullptr)
8878 return minsym
.value_address ();
8883 /* Return true when SEC points to ".gnu.sgstubs" section. */
8886 arm_is_sgstubs_section (struct obj_section
*sec
)
8888 return (sec
!= nullptr
8889 && sec
->the_bfd_section
!= nullptr
8890 && sec
->the_bfd_section
->name
!= nullptr
8891 && streq (sec
->the_bfd_section
->name
, ".gnu.sgstubs"));
8894 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8895 return the target PC. Otherwise return 0. */
8898 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8902 CORE_ADDR start_addr
;
8904 /* Find the starting address and name of the function containing the PC. */
8905 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8907 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8909 start_addr
= arm_skip_bx_reg (frame
, pc
);
8910 if (start_addr
!= 0)
8916 /* If PC is in a Thumb call or return stub, return the address of the
8917 target PC, which is in a register. The thunk functions are called
8918 _call_via_xx, where x is the register name. The possible names
8919 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8920 functions, named __ARM_call_via_r[0-7]. */
8921 if (startswith (name
, "_call_via_")
8922 || startswith (name
, "__ARM_call_via_"))
8924 /* Use the name suffix to determine which register contains the
8926 static const char *table
[15] =
8927 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8928 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8931 int offset
= strlen (name
) - 2;
8933 for (regno
= 0; regno
<= 14; regno
++)
8934 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8935 return get_frame_register_unsigned (frame
, regno
);
8938 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8939 non-interworking calls to foo. We could decode the stubs
8940 to find the target but it's easier to use the symbol table. */
8941 namelen
= strlen (name
);
8942 if (name
[0] == '_' && name
[1] == '_'
8943 && ((namelen
> 2 + strlen ("_from_thumb")
8944 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8945 || (namelen
> 2 + strlen ("_from_arm")
8946 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8949 int target_len
= namelen
- 2;
8950 struct bound_minimal_symbol minsym
;
8951 struct objfile
*objfile
;
8952 struct obj_section
*sec
;
8954 if (name
[namelen
- 1] == 'b')
8955 target_len
-= strlen ("_from_thumb");
8957 target_len
-= strlen ("_from_arm");
8959 target_name
= (char *) alloca (target_len
+ 1);
8960 memcpy (target_name
, name
+ 2, target_len
);
8961 target_name
[target_len
] = '\0';
8963 sec
= find_pc_section (pc
);
8964 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8965 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8966 if (minsym
.minsym
!= NULL
)
8967 return minsym
.value_address ();
8972 struct obj_section
*section
= find_pc_section (pc
);
8974 /* Check whether SECTION points to the ".gnu.sgstubs" section. */
8975 if (arm_is_sgstubs_section (section
))
8976 return arm_skip_cmse_entry (pc
, name
, section
->objfile
);
8978 return 0; /* not a stub */
8982 arm_update_current_architecture (void)
8984 /* If the current architecture is not ARM, we have nothing to do. */
8985 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8988 /* Update the architecture. */
8990 if (!gdbarch_update_p (info
))
8991 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8995 set_fp_model_sfunc (const char *args
, int from_tty
,
8996 struct cmd_list_element
*c
)
9000 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9001 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9003 arm_fp_model
= (enum arm_float_model
) fp_model
;
9007 if (fp_model
== ARM_FLOAT_LAST
)
9008 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9011 arm_update_current_architecture ();
9015 show_fp_model (struct ui_file
*file
, int from_tty
,
9016 struct cmd_list_element
*c
, const char *value
)
9018 arm_gdbarch_tdep
*tdep
9019 = (arm_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
9021 if (arm_fp_model
== ARM_FLOAT_AUTO
9022 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9023 gdb_printf (file
, _("\
9024 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9025 fp_model_strings
[tdep
->fp_model
]);
9027 gdb_printf (file
, _("\
9028 The current ARM floating point model is \"%s\".\n"),
9029 fp_model_strings
[arm_fp_model
]);
9033 arm_set_abi (const char *args
, int from_tty
,
9034 struct cmd_list_element
*c
)
9038 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9039 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9041 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
9045 if (arm_abi
== ARM_ABI_LAST
)
9046 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9049 arm_update_current_architecture ();
9053 arm_show_abi (struct ui_file
*file
, int from_tty
,
9054 struct cmd_list_element
*c
, const char *value
)
9056 arm_gdbarch_tdep
*tdep
9057 = (arm_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
9059 if (arm_abi_global
== ARM_ABI_AUTO
9060 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9061 gdb_printf (file
, _("\
9062 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9063 arm_abi_strings
[tdep
->arm_abi
]);
9065 gdb_printf (file
, _("The current ARM ABI is \"%s\".\n"),
9070 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9071 struct cmd_list_element
*c
, const char *value
)
9074 _("The current execution mode assumed "
9075 "(when symbols are unavailable) is \"%s\".\n"),
9076 arm_fallback_mode_string
);
9080 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9081 struct cmd_list_element
*c
, const char *value
)
9084 _("The current execution mode assumed "
9085 "(even when symbols are available) is \"%s\".\n"),
9086 arm_force_mode_string
);
9090 arm_show_unwind_secure_frames (struct ui_file
*file
, int from_tty
,
9091 struct cmd_list_element
*c
, const char *value
)
9094 _("Usage of non-secure to secure exception stack unwinding is %s.\n"),
9095 arm_unwind_secure_frames
? "on" : "off");
9098 /* If the user changes the register disassembly style used for info
9099 register and other commands, we have to also switch the style used
9100 in opcodes for disassembly output. This function is run in the "set
9101 arm disassembly" command, and does that. */
9104 set_disassembly_style_sfunc (const char *args
, int from_tty
,
9105 struct cmd_list_element
*c
)
9107 /* Convert the short style name into the long style name (eg, reg-names-*)
9108 before calling the generic set_disassembler_options() function. */
9109 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
9110 set_disassembler_options (&long_name
[0]);
9114 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
9115 struct cmd_list_element
*c
, const char *value
)
9117 struct gdbarch
*gdbarch
= get_current_arch ();
9118 char *options
= get_disassembler_options (gdbarch
);
9119 const char *style
= "";
9123 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
9124 if (startswith (opt
, "reg-names-"))
9126 style
= &opt
[strlen ("reg-names-")];
9127 len
= strcspn (style
, ",");
9130 gdb_printf (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
9133 /* Return the ARM register name corresponding to register I. */
9135 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9137 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9139 if (is_s_pseudo (gdbarch
, i
))
9141 static const char *const s_pseudo_names
[] = {
9142 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9143 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9144 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9145 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9148 return s_pseudo_names
[i
- tdep
->s_pseudo_base
];
9151 if (is_q_pseudo (gdbarch
, i
))
9153 static const char *const q_pseudo_names
[] = {
9154 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9155 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9158 return q_pseudo_names
[i
- tdep
->q_pseudo_base
];
9161 if (is_mve_pseudo (gdbarch
, i
))
9164 /* RA_AUTH_CODE is used for unwinding only. Do not assign it a name. */
9165 if (is_pacbti_pseudo (gdbarch
, i
))
9168 if (i
>= ARRAY_SIZE (arm_register_names
))
9169 /* These registers are only supported on targets which supply
9170 an XML description. */
9173 /* Non-pseudo registers. */
9174 return arm_register_names
[i
];
9177 /* Test whether the coff symbol specific value corresponds to a Thumb
9181 coff_sym_is_thumb (int val
)
9183 return (val
== C_THUMBEXT
9184 || val
== C_THUMBSTAT
9185 || val
== C_THUMBEXTFUNC
9186 || val
== C_THUMBSTATFUNC
9187 || val
== C_THUMBLABEL
);
9190 /* arm_coff_make_msymbol_special()
9191 arm_elf_make_msymbol_special()
9193 These functions test whether the COFF or ELF symbol corresponds to
9194 an address in thumb code, and set a "special" bit in a minimal
9195 symbol to indicate that it does. */
9198 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9200 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
9202 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
9203 == ST_BRANCH_TO_THUMB
)
9204 MSYMBOL_SET_SPECIAL (msym
);
9208 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9210 if (coff_sym_is_thumb (val
))
9211 MSYMBOL_SET_SPECIAL (msym
);
9215 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9218 const char *name
= bfd_asymbol_name (sym
);
9219 struct arm_per_bfd
*data
;
9220 struct arm_mapping_symbol new_map_sym
;
9222 gdb_assert (name
[0] == '$');
9223 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9226 data
= arm_bfd_data_key
.get (objfile
->obfd
);
9228 data
= arm_bfd_data_key
.emplace (objfile
->obfd
,
9229 objfile
->obfd
->section_count
);
9230 arm_mapping_symbol_vec
&map
9231 = data
->section_maps
[bfd_asymbol_section (sym
)->index
];
9233 new_map_sym
.value
= sym
->value
;
9234 new_map_sym
.type
= name
[1];
9236 /* Insert at the end, the vector will be sorted on first use. */
9237 map
.push_back (new_map_sym
);
9241 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9243 struct gdbarch
*gdbarch
= regcache
->arch ();
9244 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9246 /* If necessary, set the T bit. */
9249 ULONGEST val
, t_bit
;
9250 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9251 t_bit
= arm_psr_thumb_bit (gdbarch
);
9252 if (arm_pc_is_thumb (gdbarch
, pc
))
9253 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9256 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9261 /* Read the contents of a NEON quad register, by reading from two
9262 double registers. This is used to implement the quad pseudo
9263 registers, and for argument passing in case the quad registers are
9264 missing; vectors are passed in quad registers when using the VFP
9265 ABI, even if a NEON unit is not present. REGNUM is the index of
9266 the quad register, in [0, 15]. */
9268 static enum register_status
9269 arm_neon_quad_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
9270 int regnum
, gdb_byte
*buf
)
9273 gdb_byte reg_buf
[8];
9274 int offset
, double_regnum
;
9275 enum register_status status
;
9277 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9278 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9281 /* d0 is always the least significant half of q0. */
9282 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9287 status
= regcache
->raw_read (double_regnum
, reg_buf
);
9288 if (status
!= REG_VALID
)
9290 memcpy (buf
+ offset
, reg_buf
, 8);
9292 offset
= 8 - offset
;
9293 status
= regcache
->raw_read (double_regnum
+ 1, reg_buf
);
9294 if (status
!= REG_VALID
)
9296 memcpy (buf
+ offset
, reg_buf
, 8);
9301 /* Read the contents of the MVE pseudo register REGNUM and store it
9304 static enum register_status
9305 arm_mve_pseudo_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
9306 int regnum
, gdb_byte
*buf
)
9308 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9310 /* P0 is the first 16 bits of VPR. */
9311 return regcache
->raw_read_part (tdep
->mve_vpr_regnum
, 0, 2, buf
);
9314 static enum register_status
9315 arm_pseudo_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
9316 int regnum
, gdb_byte
*buf
)
9318 const int num_regs
= gdbarch_num_regs (gdbarch
);
9320 gdb_byte reg_buf
[8];
9321 int offset
, double_regnum
;
9322 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9324 gdb_assert (regnum
>= num_regs
);
9326 if (is_q_pseudo (gdbarch
, regnum
))
9328 /* Quad-precision register. */
9329 return arm_neon_quad_read (gdbarch
, regcache
,
9330 regnum
- tdep
->q_pseudo_base
, buf
);
9332 else if (is_mve_pseudo (gdbarch
, regnum
))
9333 return arm_mve_pseudo_read (gdbarch
, regcache
, regnum
, buf
);
9336 enum register_status status
;
9338 regnum
-= tdep
->s_pseudo_base
;
9339 /* Single-precision register. */
9340 gdb_assert (regnum
< 32);
9342 /* s0 is always the least significant half of d0. */
9343 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9344 offset
= (regnum
& 1) ? 0 : 4;
9346 offset
= (regnum
& 1) ? 4 : 0;
9348 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9349 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9352 status
= regcache
->raw_read (double_regnum
, reg_buf
);
9353 if (status
== REG_VALID
)
9354 memcpy (buf
, reg_buf
+ offset
, 4);
9359 /* Store the contents of BUF to a NEON quad register, by writing to
9360 two double registers. This is used to implement the quad pseudo
9361 registers, and for argument passing in case the quad registers are
9362 missing; vectors are passed in quad registers when using the VFP
9363 ABI, even if a NEON unit is not present. REGNUM is the index
9364 of the quad register, in [0, 15]. */
9367 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9368 int regnum
, const gdb_byte
*buf
)
9371 int offset
, double_regnum
;
9373 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9374 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9377 /* d0 is always the least significant half of q0. */
9378 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9383 regcache
->raw_write (double_regnum
, buf
+ offset
);
9384 offset
= 8 - offset
;
9385 regcache
->raw_write (double_regnum
+ 1, buf
+ offset
);
9388 /* Store the contents of BUF to the MVE pseudo register REGNUM. */
9391 arm_mve_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9392 int regnum
, const gdb_byte
*buf
)
9394 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9396 /* P0 is the first 16 bits of VPR. */
9397 regcache
->raw_write_part (tdep
->mve_vpr_regnum
, 0, 2, buf
);
9401 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9402 int regnum
, const gdb_byte
*buf
)
9404 const int num_regs
= gdbarch_num_regs (gdbarch
);
9406 gdb_byte reg_buf
[8];
9407 int offset
, double_regnum
;
9408 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9410 gdb_assert (regnum
>= num_regs
);
9412 if (is_q_pseudo (gdbarch
, regnum
))
9414 /* Quad-precision register. */
9415 arm_neon_quad_write (gdbarch
, regcache
,
9416 regnum
- tdep
->q_pseudo_base
, buf
);
9418 else if (is_mve_pseudo (gdbarch
, regnum
))
9419 arm_mve_pseudo_write (gdbarch
, regcache
, regnum
, buf
);
9422 regnum
-= tdep
->s_pseudo_base
;
9423 /* Single-precision register. */
9424 gdb_assert (regnum
< 32);
9426 /* s0 is always the least significant half of d0. */
9427 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9428 offset
= (regnum
& 1) ? 0 : 4;
9430 offset
= (regnum
& 1) ? 4 : 0;
9432 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9433 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9436 regcache
->raw_read (double_regnum
, reg_buf
);
9437 memcpy (reg_buf
+ offset
, buf
, 4);
9438 regcache
->raw_write (double_regnum
, reg_buf
);
9442 static struct value
*
9443 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9445 const int *reg_p
= (const int *) baton
;
9446 return value_of_register (*reg_p
, frame
);
9449 static enum gdb_osabi
9450 arm_elf_osabi_sniffer (bfd
*abfd
)
9452 unsigned int elfosabi
;
9453 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9455 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9457 if (elfosabi
== ELFOSABI_ARM
)
9458 /* GNU tools use this value. Check note sections in this case,
9461 for (asection
*sect
: gdb_bfd_sections (abfd
))
9462 generic_elf_osabi_sniff_abi_tag_sections (abfd
, sect
, &osabi
);
9465 /* Anything else will be handled by the generic ELF sniffer. */
9470 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9471 const struct reggroup
*group
)
9473 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9474 this, FPS register belongs to save_regroup, restore_reggroup, and
9475 all_reggroup, of course. */
9476 if (regnum
== ARM_FPS_REGNUM
)
9477 return (group
== float_reggroup
9478 || group
== save_reggroup
9479 || group
== restore_reggroup
9480 || group
== all_reggroup
);
9482 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9485 /* For backward-compatibility we allow two 'g' packet lengths with
9486 the remote protocol depending on whether FPA registers are
9487 supplied. M-profile targets do not have FPA registers, but some
9488 stubs already exist in the wild which use a 'g' packet which
9489 supplies them albeit with dummy values. The packet format which
9490 includes FPA registers should be considered deprecated for
9491 M-profile targets. */
9494 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9496 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9500 const target_desc
*tdesc
;
9502 /* If we know from the executable this is an M-profile target,
9503 cater for remote targets whose register set layout is the
9504 same as the FPA layout. */
9505 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_WITH_FPA
);
9506 register_remote_g_packet_guess (gdbarch
,
9507 ARM_CORE_REGS_SIZE
+ ARM_FP_REGS_SIZE
,
9510 /* The regular M-profile layout. */
9511 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_M_PROFILE
);
9512 register_remote_g_packet_guess (gdbarch
, ARM_CORE_REGS_SIZE
,
9515 /* M-profile plus M4F VFP. */
9516 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_VFP_D16
);
9517 register_remote_g_packet_guess (gdbarch
,
9518 ARM_CORE_REGS_SIZE
+ ARM_VFP2_REGS_SIZE
,
9520 /* M-profile plus MVE. */
9521 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_MVE
);
9522 register_remote_g_packet_guess (gdbarch
, ARM_CORE_REGS_SIZE
9523 + ARM_VFP2_REGS_SIZE
9524 + ARM_INT_REGISTER_SIZE
, tdesc
);
9526 /* M-profile system (stack pointers). */
9527 tdesc
= arm_read_mprofile_description (ARM_M_TYPE_SYSTEM
);
9528 register_remote_g_packet_guess (gdbarch
, 2 * ARM_INT_REGISTER_SIZE
, tdesc
);
9531 /* Otherwise we don't have a useful guess. */
9534 /* Implement the code_of_frame_writable gdbarch method. */
9537 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
9539 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
9541 if (tdep
->is_m
&& get_frame_type (frame
) == SIGTRAMP_FRAME
)
9543 /* M-profile exception frames return to some magic PCs, where
9544 isn't writable at all. */
9551 /* Implement gdbarch_gnu_triplet_regexp. If the arch name is arm then allow it
9552 to be postfixed by a version (eg armv7hl). */
9555 arm_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
9557 if (strcmp (gdbarch_bfd_arch_info (gdbarch
)->arch_name
, "arm") == 0)
9558 return "arm(v[^- ]*)?";
9559 return gdbarch_bfd_arch_info (gdbarch
)->arch_name
;
9562 /* Implement the "get_pc_address_flags" gdbarch method. */
9565 arm_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
9567 if (get_frame_pc_masked (frame
))
9573 /* Initialize the current architecture based on INFO. If possible,
9574 re-use an architecture from ARCHES, which is a list of
9575 architectures already created during this debugging session.
9577 Called e.g. at program startup, when reading a core file, and when
9578 reading a binary file. */
9580 static struct gdbarch
*
9581 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9583 struct gdbarch
*gdbarch
;
9584 struct gdbarch_list
*best_arch
;
9585 enum arm_abi_kind arm_abi
= arm_abi_global
;
9586 enum arm_float_model fp_model
= arm_fp_model
;
9587 tdesc_arch_data_up tdesc_data
;
9590 bool have_sec_ext
= false;
9591 int vfp_register_count
= 0;
9592 bool have_s_pseudos
= false, have_q_pseudos
= false;
9593 bool have_wmmx_registers
= false;
9594 bool have_neon
= false;
9595 bool have_fpa_registers
= true;
9596 const struct target_desc
*tdesc
= info
.target_desc
;
9597 bool have_vfp
= false;
9598 bool have_mve
= false;
9599 bool have_pacbti
= false;
9600 int mve_vpr_regnum
= -1;
9601 int register_count
= ARM_NUM_REGS
;
9602 bool have_m_profile_msp
= false;
9603 int m_profile_msp_regnum
= -1;
9604 int m_profile_psp_regnum
= -1;
9605 int m_profile_msp_ns_regnum
= -1;
9606 int m_profile_psp_ns_regnum
= -1;
9607 int m_profile_msp_s_regnum
= -1;
9608 int m_profile_psp_s_regnum
= -1;
9610 /* If we have an object to base this architecture on, try to determine
9613 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9615 int ei_osabi
, e_flags
;
9617 switch (bfd_get_flavour (info
.abfd
))
9619 case bfd_target_coff_flavour
:
9620 /* Assume it's an old APCS-style ABI. */
9622 arm_abi
= ARM_ABI_APCS
;
9625 case bfd_target_elf_flavour
:
9626 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9627 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9629 if (ei_osabi
== ELFOSABI_ARM
)
9631 /* GNU tools used to use this value, but do not for EABI
9632 objects. There's nowhere to tag an EABI version
9633 anyway, so assume APCS. */
9634 arm_abi
= ARM_ABI_APCS
;
9636 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9638 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9642 case EF_ARM_EABI_UNKNOWN
:
9643 /* Assume GNU tools. */
9644 arm_abi
= ARM_ABI_APCS
;
9647 case EF_ARM_EABI_VER4
:
9648 case EF_ARM_EABI_VER5
:
9649 arm_abi
= ARM_ABI_AAPCS
;
9650 /* EABI binaries default to VFP float ordering.
9651 They may also contain build attributes that can
9652 be used to identify if the VFP argument-passing
9654 if (fp_model
== ARM_FLOAT_AUTO
)
9657 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9661 case AEABI_VFP_args_base
:
9662 /* "The user intended FP parameter/result
9663 passing to conform to AAPCS, base
9665 fp_model
= ARM_FLOAT_SOFT_VFP
;
9667 case AEABI_VFP_args_vfp
:
9668 /* "The user intended FP parameter/result
9669 passing to conform to AAPCS, VFP
9671 fp_model
= ARM_FLOAT_VFP
;
9673 case AEABI_VFP_args_toolchain
:
9674 /* "The user intended FP parameter/result
9675 passing to conform to tool chain-specific
9676 conventions" - we don't know any such
9677 conventions, so leave it as "auto". */
9679 case AEABI_VFP_args_compatible
:
9680 /* "Code is compatible with both the base
9681 and VFP variants; the user did not permit
9682 non-variadic functions to pass FP
9683 parameters/results" - leave it as
9687 /* Attribute value not mentioned in the
9688 November 2012 ABI, so leave it as
9693 fp_model
= ARM_FLOAT_SOFT_VFP
;
9699 /* Leave it as "auto". */
9700 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9705 /* Detect M-profile programs. This only works if the
9706 executable file includes build attributes; GCC does
9707 copy them to the executable, but e.g. RealView does
9710 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9713 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9714 Tag_CPU_arch_profile
);
9716 /* GCC specifies the profile for v6-M; RealView only
9717 specifies the profile for architectures starting with
9718 V7 (as opposed to architectures with a tag
9719 numerically greater than TAG_CPU_ARCH_V7). */
9720 if (!tdesc_has_registers (tdesc
)
9721 && (attr_arch
== TAG_CPU_ARCH_V6_M
9722 || attr_arch
== TAG_CPU_ARCH_V6S_M
9723 || attr_arch
== TAG_CPU_ARCH_V7E_M
9724 || attr_arch
== TAG_CPU_ARCH_V8M_BASE
9725 || attr_arch
== TAG_CPU_ARCH_V8M_MAIN
9726 || attr_arch
== TAG_CPU_ARCH_V8_1M_MAIN
9727 || attr_profile
== 'M'))
9730 /* Look for attributes that indicate support for ARMv8.1-m
9732 if (!tdesc_has_registers (tdesc
) && is_m
)
9734 int attr_pac_extension
9735 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9738 int attr_bti_extension
9739 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9743 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9747 = bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9750 if (attr_pac_extension
!= 0 || attr_bti_extension
!= 0
9751 || attr_pacret_use
!= 0 || attr_bti_use
!= 0)
9757 if (fp_model
== ARM_FLOAT_AUTO
)
9759 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9762 /* Leave it as "auto". Strictly speaking this case
9763 means FPA, but almost nobody uses that now, and
9764 many toolchains fail to set the appropriate bits
9765 for the floating-point model they use. */
9767 case EF_ARM_SOFT_FLOAT
:
9768 fp_model
= ARM_FLOAT_SOFT_FPA
;
9770 case EF_ARM_VFP_FLOAT
:
9771 fp_model
= ARM_FLOAT_VFP
;
9773 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9774 fp_model
= ARM_FLOAT_SOFT_VFP
;
9779 if (e_flags
& EF_ARM_BE8
)
9780 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9785 /* Leave it as "auto". */
9790 /* Check any target description for validity. */
9791 if (tdesc_has_registers (tdesc
))
9793 /* For most registers we require GDB's default names; but also allow
9794 the numeric names for sp / lr / pc, as a convenience. */
9795 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9796 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9797 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9799 const struct tdesc_feature
*feature
;
9802 feature
= tdesc_find_feature (tdesc
,
9803 "org.gnu.gdb.arm.core");
9804 if (feature
== NULL
)
9806 feature
= tdesc_find_feature (tdesc
,
9807 "org.gnu.gdb.arm.m-profile");
9808 if (feature
== NULL
)
9814 tdesc_data
= tdesc_data_alloc ();
9817 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9818 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
9819 arm_register_names
[i
]);
9820 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
9823 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
9826 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
9830 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9831 ARM_PS_REGNUM
, "xpsr");
9833 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9834 ARM_PS_REGNUM
, "cpsr");
9841 feature
= tdesc_find_feature (tdesc
,
9842 "org.gnu.gdb.arm.m-system");
9843 if (feature
!= nullptr)
9846 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9847 register_count
, "msp");
9850 warning (_("M-profile m-system feature is missing required register msp."));
9853 have_m_profile_msp
= true;
9854 m_profile_msp_regnum
= register_count
++;
9857 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9858 register_count
, "psp");
9861 warning (_("M-profile m-system feature is missing required register psp."));
9864 m_profile_psp_regnum
= register_count
++;
9868 feature
= tdesc_find_feature (tdesc
,
9869 "org.gnu.gdb.arm.fpa");
9870 if (feature
!= NULL
)
9873 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9874 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
9875 arm_register_names
[i
]);
9880 have_fpa_registers
= false;
9882 feature
= tdesc_find_feature (tdesc
,
9883 "org.gnu.gdb.xscale.iwmmxt");
9884 if (feature
!= NULL
)
9886 static const char *const iwmmxt_names
[] = {
9887 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9888 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9889 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9890 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9894 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9896 &= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
9897 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9899 /* Check for the control registers, but do not fail if they
9901 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9902 tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
9903 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9905 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9907 &= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
9908 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9913 have_wmmx_registers
= true;
9916 /* If we have a VFP unit, check whether the single precision registers
9917 are present. If not, then we will synthesize them as pseudo
9919 feature
= tdesc_find_feature (tdesc
,
9920 "org.gnu.gdb.arm.vfp");
9921 if (feature
!= NULL
)
9923 static const char *const vfp_double_names
[] = {
9924 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9925 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9926 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9927 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9930 /* Require the double precision registers. There must be either
9933 for (i
= 0; i
< 32; i
++)
9935 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9937 vfp_double_names
[i
]);
9941 if (!valid_p
&& i
== 16)
9944 /* Also require FPSCR. */
9945 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9946 ARM_FPSCR_REGNUM
, "fpscr");
9952 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9953 have_s_pseudos
= true;
9955 vfp_register_count
= i
;
9957 /* If we have VFP, also check for NEON. The architecture allows
9958 NEON without VFP (integer vector operations only), but GDB
9959 does not support that. */
9960 feature
= tdesc_find_feature (tdesc
,
9961 "org.gnu.gdb.arm.neon");
9962 if (feature
!= NULL
)
9964 /* NEON requires 32 double-precision registers. */
9968 /* If there are quad registers defined by the stub, use
9969 their type; otherwise (normally) provide them with
9970 the default type. */
9971 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9972 have_q_pseudos
= true;
9976 /* Check for MVE after all the checks for GPR's, VFP and Neon.
9977 MVE (Helium) is an M-profile extension. */
9980 /* Do we have the MVE feature? */
9981 feature
= tdesc_find_feature (tdesc
,"org.gnu.gdb.arm.m-profile-mve");
9983 if (feature
!= nullptr)
9985 /* If we have MVE, we must always have the VPR register. */
9986 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
9987 register_count
, "vpr");
9990 warning (_("MVE feature is missing required register vpr."));
9995 mve_vpr_regnum
= register_count
;
9998 /* We can't have Q pseudo registers available here, as that
9999 would mean we have NEON features, and that is only available
10000 on A and R profiles. */
10001 gdb_assert (!have_q_pseudos
);
10003 /* Given we have a M-profile target description, if MVE is
10004 enabled and there are VFP registers, we should have Q
10005 pseudo registers (Q0 ~ Q7). */
10007 have_q_pseudos
= true;
10010 /* Do we have the ARMv8.1-m PACBTI feature? */
10011 feature
= tdesc_find_feature (tdesc
,
10012 "org.gnu.gdb.arm.m-profile-pacbti");
10013 if (feature
!= nullptr)
10015 /* By advertising this feature, the target acknowledges the
10016 presence of the ARMv8.1-m PACBTI extensions.
10018 We don't care for any particular registers in this group, so
10019 the target is free to include whatever it deems appropriate.
10021 The expectation is for this feature to include the PAC
10023 have_pacbti
= true;
10026 /* Do we have the Security extension? */
10027 feature
= tdesc_find_feature (tdesc
,
10028 "org.gnu.gdb.arm.secext");
10029 if (feature
!= nullptr)
10031 /* Secure/Non-secure stack pointers. */
10033 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
10034 register_count
, "msp_ns");
10037 warning (_("M-profile secext feature is missing required register msp_ns."));
10040 m_profile_msp_ns_regnum
= register_count
++;
10043 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
10044 register_count
, "psp_ns");
10047 warning (_("M-profile secext feature is missing required register psp_ns."));
10050 m_profile_psp_ns_regnum
= register_count
++;
10053 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
10054 register_count
, "msp_s");
10057 warning (_("M-profile secext feature is missing required register msp_s."));
10060 m_profile_msp_s_regnum
= register_count
++;
10063 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
10064 register_count
, "psp_s");
10067 warning (_("M-profile secext feature is missing required register psp_s."));
10070 m_profile_psp_s_regnum
= register_count
++;
10072 have_sec_ext
= true;
10078 /* If there is already a candidate, use it. */
10079 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10081 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10083 arm_gdbarch_tdep
*tdep
10084 = (arm_gdbarch_tdep
*) gdbarch_tdep (best_arch
->gdbarch
);
10086 if (arm_abi
!= ARM_ABI_AUTO
&& arm_abi
!= tdep
->arm_abi
)
10089 if (fp_model
!= ARM_FLOAT_AUTO
&& fp_model
!= tdep
->fp_model
)
10092 /* There are various other properties in tdep that we do not
10093 need to check here: those derived from a target description,
10094 since gdbarches with a different target description are
10095 automatically disqualified. */
10097 /* Do check is_m, though, since it might come from the binary. */
10098 if (is_m
!= tdep
->is_m
)
10101 /* Also check for ARMv8.1-m PACBTI support, since it might come from
10103 if (have_pacbti
!= tdep
->have_pacbti
)
10106 /* Found a match. */
10110 if (best_arch
!= NULL
)
10111 return best_arch
->gdbarch
;
10113 arm_gdbarch_tdep
*tdep
= new arm_gdbarch_tdep
;
10114 gdbarch
= gdbarch_alloc (&info
, tdep
);
10116 /* Record additional information about the architecture we are defining.
10117 These are gdbarch discriminators, like the OSABI. */
10118 tdep
->arm_abi
= arm_abi
;
10119 tdep
->fp_model
= fp_model
;
10121 tdep
->have_sec_ext
= have_sec_ext
;
10122 tdep
->have_fpa_registers
= have_fpa_registers
;
10123 tdep
->have_wmmx_registers
= have_wmmx_registers
;
10124 gdb_assert (vfp_register_count
== 0
10125 || vfp_register_count
== 16
10126 || vfp_register_count
== 32);
10127 tdep
->vfp_register_count
= vfp_register_count
;
10128 tdep
->have_s_pseudos
= have_s_pseudos
;
10129 tdep
->have_q_pseudos
= have_q_pseudos
;
10130 tdep
->have_neon
= have_neon
;
10132 /* Adjust the MVE feature settings. */
10135 tdep
->have_mve
= true;
10136 tdep
->mve_vpr_regnum
= mve_vpr_regnum
;
10139 /* Adjust the PACBTI feature settings. */
10140 tdep
->have_pacbti
= have_pacbti
;
10142 /* Adjust the M-profile stack pointers settings. */
10143 if (have_m_profile_msp
)
10145 tdep
->m_profile_msp_regnum
= m_profile_msp_regnum
;
10146 tdep
->m_profile_psp_regnum
= m_profile_psp_regnum
;
10147 tdep
->m_profile_msp_ns_regnum
= m_profile_msp_ns_regnum
;
10148 tdep
->m_profile_psp_ns_regnum
= m_profile_psp_ns_regnum
;
10149 tdep
->m_profile_msp_s_regnum
= m_profile_msp_s_regnum
;
10150 tdep
->m_profile_psp_s_regnum
= m_profile_psp_s_regnum
;
10153 arm_register_g_packet_guesses (gdbarch
);
10156 switch (info
.byte_order_for_code
)
10158 case BFD_ENDIAN_BIG
:
10159 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10160 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10161 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10162 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10166 case BFD_ENDIAN_LITTLE
:
10167 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10168 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10169 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10170 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10175 internal_error (__FILE__
, __LINE__
,
10176 _("arm_gdbarch_init: bad byte order for float format"));
10179 /* On ARM targets char defaults to unsigned. */
10180 set_gdbarch_char_signed (gdbarch
, 0);
10182 /* wchar_t is unsigned under the AAPCS. */
10183 if (tdep
->arm_abi
== ARM_ABI_AAPCS
)
10184 set_gdbarch_wchar_signed (gdbarch
, 0);
10186 set_gdbarch_wchar_signed (gdbarch
, 1);
10188 /* Compute type alignment. */
10189 set_gdbarch_type_align (gdbarch
, arm_type_align
);
10191 /* Note: for displaced stepping, this includes the breakpoint, and one word
10192 of additional scratch space. This setting isn't used for anything beside
10193 displaced stepping at present. */
10194 set_gdbarch_max_insn_length (gdbarch
, 4 * ARM_DISPLACED_MODIFIED_INSNS
);
10196 /* This should be low enough for everything. */
10197 tdep
->lowest_pc
= 0x20;
10198 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10200 /* The default, for both APCS and AAPCS, is to return small
10201 structures in registers. */
10202 tdep
->struct_return
= reg_struct_return
;
10204 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10205 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10208 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
10210 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10212 frame_base_set_default (gdbarch
, &arm_normal_base
);
10214 /* Address manipulation. */
10215 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10217 /* Advance PC across function entry code. */
10218 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10220 /* Detect whether PC is at a point where the stack has been destroyed. */
10221 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
10223 /* Skip trampolines. */
10224 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10226 /* The stack grows downward. */
10227 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10229 /* Breakpoint manipulation. */
10230 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
10231 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
10232 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
10233 arm_breakpoint_kind_from_current_state
);
10235 /* Information about registers, etc. */
10236 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10237 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10238 set_gdbarch_num_regs (gdbarch
, register_count
);
10239 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10240 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10242 /* This "info float" is FPA-specific. Use the generic version if we
10243 do not have FPA. */
10244 if (tdep
->have_fpa_registers
)
10245 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10247 /* Internal <-> external register number maps. */
10248 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10249 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10251 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10253 /* Returning results. */
10254 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10257 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10259 /* Minsymbol frobbing. */
10260 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10261 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10262 arm_coff_make_msymbol_special
);
10263 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10265 /* Thumb-2 IT block support. */
10266 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10267 arm_adjust_breakpoint_address
);
10269 /* Virtual tables. */
10270 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10272 /* Hook in the ABI-specific overrides, if they have been registered. */
10273 gdbarch_init_osabi (info
, gdbarch
);
10275 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10277 /* Add some default predicates. */
10279 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10280 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10281 dwarf2_append_unwinders (gdbarch
);
10282 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10283 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
10284 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10286 /* Now we have tuned the configuration, set a few final things,
10287 based on what the OS ABI has told us. */
10289 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10290 binaries are always marked. */
10291 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10292 tdep
->arm_abi
= ARM_ABI_APCS
;
10294 /* Watchpoints are not steppable. */
10295 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10297 /* We used to default to FPA for generic ARM, but almost nobody
10298 uses that now, and we now provide a way for the user to force
10299 the model. So default to the most useful variant. */
10300 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10301 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10303 if (tdep
->jb_pc
>= 0)
10304 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10306 /* Floating point sizes and format. */
10307 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10308 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10310 set_gdbarch_double_format
10311 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10312 set_gdbarch_long_double_format
10313 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10317 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10318 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10321 /* Hook used to decorate frames with signed return addresses, only available
10322 for ARMv8.1-m PACBTI. */
10323 if (is_m
&& have_pacbti
)
10324 set_gdbarch_get_pc_address_flags (gdbarch
, arm_get_pc_address_flags
);
10326 if (tdesc_data
!= nullptr)
10328 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10330 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
10331 register_count
= gdbarch_num_regs (gdbarch
);
10333 /* Override tdesc_register_type to adjust the types of VFP
10334 registers for NEON. */
10335 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10338 /* Initialize the pseudo register data. */
10339 int num_pseudos
= 0;
10340 if (tdep
->have_s_pseudos
)
10342 /* VFP single precision pseudo registers (S0~S31). */
10343 tdep
->s_pseudo_base
= register_count
;
10344 tdep
->s_pseudo_count
= 32;
10345 num_pseudos
+= tdep
->s_pseudo_count
;
10347 if (tdep
->have_q_pseudos
)
10349 /* NEON quad precision pseudo registers (Q0~Q15). */
10350 tdep
->q_pseudo_base
= register_count
+ num_pseudos
;
10353 tdep
->q_pseudo_count
= 16;
10355 tdep
->q_pseudo_count
= ARM_MVE_NUM_Q_REGS
;
10357 num_pseudos
+= tdep
->q_pseudo_count
;
10361 /* Do we have any MVE pseudo registers? */
10364 tdep
->mve_pseudo_base
= register_count
+ num_pseudos
;
10365 tdep
->mve_pseudo_count
= 1;
10366 num_pseudos
+= tdep
->mve_pseudo_count
;
10369 /* Do we have any ARMv8.1-m PACBTI pseudo registers. */
10372 tdep
->pacbti_pseudo_base
= register_count
+ num_pseudos
;
10373 tdep
->pacbti_pseudo_count
= 1;
10374 num_pseudos
+= tdep
->pacbti_pseudo_count
;
10377 /* Set some pseudo register hooks, if we have pseudo registers. */
10378 if (tdep
->have_s_pseudos
|| have_mve
|| have_pacbti
)
10380 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10381 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10382 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10385 /* Add standard register aliases. We add aliases even for those
10386 names which are used by the current architecture - it's simpler,
10387 and does no harm, since nothing ever lists user registers. */
10388 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10389 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10390 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10392 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
10393 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
10395 set_gdbarch_gnu_triplet_regexp (gdbarch
, arm_gnu_triplet_regexp
);
10401 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10403 arm_gdbarch_tdep
*tdep
= (arm_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
10408 gdb_printf (file
, _("arm_dump_tdep: fp_model = %i\n"),
10409 (int) tdep
->fp_model
);
10410 gdb_printf (file
, _("arm_dump_tdep: have_fpa_registers = %i\n"),
10411 (int) tdep
->have_fpa_registers
);
10412 gdb_printf (file
, _("arm_dump_tdep: have_wmmx_registers = %i\n"),
10413 (int) tdep
->have_wmmx_registers
);
10414 gdb_printf (file
, _("arm_dump_tdep: vfp_register_count = %i\n"),
10415 (int) tdep
->vfp_register_count
);
10416 gdb_printf (file
, _("arm_dump_tdep: have_s_pseudos = %s\n"),
10417 tdep
->have_s_pseudos
? "true" : "false");
10418 gdb_printf (file
, _("arm_dump_tdep: s_pseudo_base = %i\n"),
10419 (int) tdep
->s_pseudo_base
);
10420 gdb_printf (file
, _("arm_dump_tdep: s_pseudo_count = %i\n"),
10421 (int) tdep
->s_pseudo_count
);
10422 gdb_printf (file
, _("arm_dump_tdep: have_q_pseudos = %s\n"),
10423 tdep
->have_q_pseudos
? "true" : "false");
10424 gdb_printf (file
, _("arm_dump_tdep: q_pseudo_base = %i\n"),
10425 (int) tdep
->q_pseudo_base
);
10426 gdb_printf (file
, _("arm_dump_tdep: q_pseudo_count = %i\n"),
10427 (int) tdep
->q_pseudo_count
);
10428 gdb_printf (file
, _("arm_dump_tdep: have_neon = %i\n"),
10429 (int) tdep
->have_neon
);
10430 gdb_printf (file
, _("arm_dump_tdep: have_mve = %s\n"),
10431 tdep
->have_mve
? "yes" : "no");
10432 gdb_printf (file
, _("arm_dump_tdep: mve_vpr_regnum = %i\n"),
10433 tdep
->mve_vpr_regnum
);
10434 gdb_printf (file
, _("arm_dump_tdep: mve_pseudo_base = %i\n"),
10435 tdep
->mve_pseudo_base
);
10436 gdb_printf (file
, _("arm_dump_tdep: mve_pseudo_count = %i\n"),
10437 tdep
->mve_pseudo_count
);
10438 gdb_printf (file
, _("arm_dump_tdep: m_profile_msp_regnum = %i\n"),
10439 tdep
->m_profile_msp_regnum
);
10440 gdb_printf (file
, _("arm_dump_tdep: m_profile_psp_regnum = %i\n"),
10441 tdep
->m_profile_psp_regnum
);
10442 gdb_printf (file
, _("arm_dump_tdep: m_profile_msp_ns_regnum = %i\n"),
10443 tdep
->m_profile_msp_ns_regnum
);
10444 gdb_printf (file
, _("arm_dump_tdep: m_profile_psp_ns_regnum = %i\n"),
10445 tdep
->m_profile_psp_ns_regnum
);
10446 gdb_printf (file
, _("arm_dump_tdep: m_profile_msp_s_regnum = %i\n"),
10447 tdep
->m_profile_msp_s_regnum
);
10448 gdb_printf (file
, _("arm_dump_tdep: m_profile_psp_s_regnum = %i\n"),
10449 tdep
->m_profile_psp_s_regnum
);
10450 gdb_printf (file
, _("arm_dump_tdep: Lowest pc = 0x%lx\n"),
10451 (unsigned long) tdep
->lowest_pc
);
10452 gdb_printf (file
, _("arm_dump_tdep: have_pacbti = %s\n"),
10453 tdep
->have_pacbti
? "yes" : "no");
10454 gdb_printf (file
, _("arm_dump_tdep: pacbti_pseudo_base = %i\n"),
10455 tdep
->pacbti_pseudo_base
);
10456 gdb_printf (file
, _("arm_dump_tdep: pacbti_pseudo_count = %i\n"),
10457 tdep
->pacbti_pseudo_count
);
10458 gdb_printf (file
, _("arm_dump_tdep: is_m = %s\n"),
10459 tdep
->is_m
? "yes" : "no");
10463 namespace selftests
10465 static void arm_record_test (void);
10466 static void arm_analyze_prologue_test ();
10470 void _initialize_arm_tdep ();
10472 _initialize_arm_tdep ()
10476 char regdesc
[1024], *rdptr
= regdesc
;
10477 size_t rest
= sizeof (regdesc
);
10479 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10481 /* Add ourselves to objfile event chain. */
10482 gdb::observers::new_objfile
.attach (arm_exidx_new_objfile
, "arm-tdep");
10484 /* Register an ELF OS ABI sniffer for ARM binaries. */
10485 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10486 bfd_target_elf_flavour
,
10487 arm_elf_osabi_sniffer
);
10489 /* Add root prefix command for all "set arm"/"show arm" commands. */
10490 add_setshow_prefix_cmd ("arm", no_class
,
10491 _("Various ARM-specific commands."),
10492 _("Various ARM-specific commands."),
10493 &setarmcmdlist
, &showarmcmdlist
,
10494 &setlist
, &showlist
);
10496 arm_disassembler_options
= xstrdup ("reg-names-std");
10497 const disasm_options_t
*disasm_options
10498 = &disassembler_options_arm ()->options
;
10499 int num_disassembly_styles
= 0;
10500 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
10501 if (startswith (disasm_options
->name
[i
], "reg-names-"))
10502 num_disassembly_styles
++;
10504 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
10505 valid_disassembly_styles
= XNEWVEC (const char *,
10506 num_disassembly_styles
+ 1);
10507 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
10508 if (startswith (disasm_options
->name
[i
], "reg-names-"))
10510 size_t offset
= strlen ("reg-names-");
10511 const char *style
= disasm_options
->name
[i
];
10512 valid_disassembly_styles
[j
++] = &style
[offset
];
10513 if (strcmp (&style
[offset
], "std") == 0)
10514 disassembly_style
= &style
[offset
];
10515 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
10516 disasm_options
->description
[i
]);
10520 /* Mark the end of valid options. */
10521 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
10523 /* Create the help text. */
10524 std::string helptext
= string_printf ("%s%s%s",
10525 _("The valid values are:\n"),
10527 _("The default is \"std\"."));
10529 add_setshow_enum_cmd("disassembler", no_class
,
10530 valid_disassembly_styles
, &disassembly_style
,
10531 _("Set the disassembly style."),
10532 _("Show the disassembly style."),
10534 set_disassembly_style_sfunc
,
10535 show_disassembly_style_sfunc
,
10536 &setarmcmdlist
, &showarmcmdlist
);
10538 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10539 _("Set usage of ARM 32-bit mode."),
10540 _("Show usage of ARM 32-bit mode."),
10541 _("When off, a 26-bit PC will be used."),
10543 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10545 &setarmcmdlist
, &showarmcmdlist
);
10547 /* Add a command to allow the user to force the FPU model. */
10548 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10549 _("Set the floating point type."),
10550 _("Show the floating point type."),
10551 _("auto - Determine the FP typefrom the OS-ABI.\n\
10552 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10553 fpa - FPA co-processor (GCC compiled).\n\
10554 softvfp - Software FP with pure-endian doubles.\n\
10555 vfp - VFP co-processor."),
10556 set_fp_model_sfunc
, show_fp_model
,
10557 &setarmcmdlist
, &showarmcmdlist
);
10559 /* Add a command to allow the user to force the ABI. */
10560 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10562 _("Show the ABI."),
10563 NULL
, arm_set_abi
, arm_show_abi
,
10564 &setarmcmdlist
, &showarmcmdlist
);
10566 /* Add two commands to allow the user to force the assumed
10568 add_setshow_enum_cmd ("fallback-mode", class_support
,
10569 arm_mode_strings
, &arm_fallback_mode_string
,
10570 _("Set the mode assumed when symbols are unavailable."),
10571 _("Show the mode assumed when symbols are unavailable."),
10572 NULL
, NULL
, arm_show_fallback_mode
,
10573 &setarmcmdlist
, &showarmcmdlist
);
10574 add_setshow_enum_cmd ("force-mode", class_support
,
10575 arm_mode_strings
, &arm_force_mode_string
,
10576 _("Set the mode assumed even when symbols are available."),
10577 _("Show the mode assumed even when symbols are available."),
10578 NULL
, NULL
, arm_show_force_mode
,
10579 &setarmcmdlist
, &showarmcmdlist
);
10581 /* Add a command to stop triggering security exceptions when
10582 unwinding exception stacks. */
10583 add_setshow_boolean_cmd ("unwind-secure-frames", no_class
, &arm_unwind_secure_frames
,
10584 _("Set usage of non-secure to secure exception stack unwinding."),
10585 _("Show usage of non-secure to secure exception stack unwinding."),
10586 _("When on, the debugger can trigger memory access traps."),
10587 NULL
, arm_show_unwind_secure_frames
,
10588 &setarmcmdlist
, &showarmcmdlist
);
10590 /* Debugging flag. */
10591 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10592 _("Set ARM debugging."),
10593 _("Show ARM debugging."),
10594 _("When on, arm-specific debugging is enabled."),
10596 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10597 &setdebuglist
, &showdebuglist
);
10600 selftests::register_test ("arm-record", selftests::arm_record_test
);
10601 selftests::register_test ("arm_analyze_prologue", selftests::arm_analyze_prologue_test
);
10606 /* ARM-reversible process record data structures. */
10608 #define ARM_INSN_SIZE_BYTES 4
10609 #define THUMB_INSN_SIZE_BYTES 2
10610 #define THUMB2_INSN_SIZE_BYTES 4
10613 /* Position of the bit within a 32-bit ARM instruction
10614 that defines whether the instruction is a load or store. */
10615 #define INSN_S_L_BIT_NUM 20
10617 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10620 unsigned int reg_len = LENGTH; \
10623 REGS = XNEWVEC (uint32_t, reg_len); \
10624 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10629 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10632 unsigned int mem_len = LENGTH; \
10635 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10636 memcpy(&MEMS->len, &RECORD_BUF[0], \
10637 sizeof(struct arm_mem_r) * LENGTH); \
10642 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10643 #define INSN_RECORDED(ARM_RECORD) \
10644 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10646 /* ARM memory record structure. */
10649 uint32_t len
; /* Record length. */
10650 uint32_t addr
; /* Memory address. */
10653 /* ARM instruction record contains opcode of current insn
10654 and execution state (before entry to decode_insn()),
10655 contains list of to-be-modified registers and
10656 memory blocks (on return from decode_insn()). */
10658 typedef struct insn_decode_record_t
10660 struct gdbarch
*gdbarch
;
10661 struct regcache
*regcache
;
10662 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10663 uint32_t arm_insn
; /* Should accommodate thumb. */
10664 uint32_t cond
; /* Condition code. */
10665 uint32_t opcode
; /* Insn opcode. */
10666 uint32_t decode
; /* Insn decode bits. */
10667 uint32_t mem_rec_count
; /* No of mem records. */
10668 uint32_t reg_rec_count
; /* No of reg records. */
10669 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10670 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10671 } insn_decode_record
;
10674 /* Checks ARM SBZ and SBO mandatory fields. */
10677 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10679 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10698 enum arm_record_result
10700 ARM_RECORD_SUCCESS
= 0,
10701 ARM_RECORD_FAILURE
= 1
10708 } arm_record_strx_t
;
10719 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10720 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10723 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10724 ULONGEST u_regval
[2]= {0};
10726 uint32_t reg_src1
= 0, reg_src2
= 0;
10727 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10729 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10730 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10732 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10734 /* 1) Handle misc store, immediate offset. */
10735 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10736 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10737 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10738 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10740 if (ARM_PC_REGNUM
== reg_src1
)
10742 /* If R15 was used as Rn, hence current PC+8. */
10743 u_regval
[0] = u_regval
[0] + 8;
10745 offset_8
= (immed_high
<< 4) | immed_low
;
10746 /* Calculate target store address. */
10747 if (14 == arm_insn_r
->opcode
)
10749 tgt_mem_addr
= u_regval
[0] + offset_8
;
10753 tgt_mem_addr
= u_regval
[0] - offset_8
;
10755 if (ARM_RECORD_STRH
== str_type
)
10757 record_buf_mem
[0] = 2;
10758 record_buf_mem
[1] = tgt_mem_addr
;
10759 arm_insn_r
->mem_rec_count
= 1;
10761 else if (ARM_RECORD_STRD
== str_type
)
10763 record_buf_mem
[0] = 4;
10764 record_buf_mem
[1] = tgt_mem_addr
;
10765 record_buf_mem
[2] = 4;
10766 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10767 arm_insn_r
->mem_rec_count
= 2;
10770 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10772 /* 2) Store, register offset. */
10774 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10776 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10777 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10778 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10779 if (15 == reg_src2
)
10781 /* If R15 was used as Rn, hence current PC+8. */
10782 u_regval
[0] = u_regval
[0] + 8;
10784 /* Calculate target store address, Rn +/- Rm, register offset. */
10785 if (12 == arm_insn_r
->opcode
)
10787 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10791 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10793 if (ARM_RECORD_STRH
== str_type
)
10795 record_buf_mem
[0] = 2;
10796 record_buf_mem
[1] = tgt_mem_addr
;
10797 arm_insn_r
->mem_rec_count
= 1;
10799 else if (ARM_RECORD_STRD
== str_type
)
10801 record_buf_mem
[0] = 4;
10802 record_buf_mem
[1] = tgt_mem_addr
;
10803 record_buf_mem
[2] = 4;
10804 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10805 arm_insn_r
->mem_rec_count
= 2;
10808 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10809 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10811 /* 3) Store, immediate pre-indexed. */
10812 /* 5) Store, immediate post-indexed. */
10813 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10814 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10815 offset_8
= (immed_high
<< 4) | immed_low
;
10816 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10817 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10818 /* Calculate target store address, Rn +/- Rm, register offset. */
10819 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10821 tgt_mem_addr
= u_regval
[0] + offset_8
;
10825 tgt_mem_addr
= u_regval
[0] - offset_8
;
10827 if (ARM_RECORD_STRH
== str_type
)
10829 record_buf_mem
[0] = 2;
10830 record_buf_mem
[1] = tgt_mem_addr
;
10831 arm_insn_r
->mem_rec_count
= 1;
10833 else if (ARM_RECORD_STRD
== str_type
)
10835 record_buf_mem
[0] = 4;
10836 record_buf_mem
[1] = tgt_mem_addr
;
10837 record_buf_mem
[2] = 4;
10838 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10839 arm_insn_r
->mem_rec_count
= 2;
10841 /* Record Rn also as it changes. */
10842 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10843 arm_insn_r
->reg_rec_count
= 1;
10845 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10846 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10848 /* 4) Store, register pre-indexed. */
10849 /* 6) Store, register post -indexed. */
10850 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10851 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10852 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10853 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10854 /* Calculate target store address, Rn +/- Rm, register offset. */
10855 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10857 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10861 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10863 if (ARM_RECORD_STRH
== str_type
)
10865 record_buf_mem
[0] = 2;
10866 record_buf_mem
[1] = tgt_mem_addr
;
10867 arm_insn_r
->mem_rec_count
= 1;
10869 else if (ARM_RECORD_STRD
== str_type
)
10871 record_buf_mem
[0] = 4;
10872 record_buf_mem
[1] = tgt_mem_addr
;
10873 record_buf_mem
[2] = 4;
10874 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10875 arm_insn_r
->mem_rec_count
= 2;
10877 /* Record Rn also as it changes. */
10878 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10879 arm_insn_r
->reg_rec_count
= 1;
10884 /* Handling ARM extension space insns. */
10887 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10889 int ret
= 0; /* Return value: -1:record failure ; 0:success */
10890 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10891 uint32_t record_buf
[8], record_buf_mem
[8];
10892 uint32_t reg_src1
= 0;
10893 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10894 ULONGEST u_regval
= 0;
10896 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10897 /* Handle unconditional insn extension space. */
10899 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10900 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10901 if (arm_insn_r
->cond
)
10903 /* PLD has no affect on architectural state, it just affects
10905 if (5 == ((opcode1
& 0xE0) >> 5))
10908 record_buf
[0] = ARM_PS_REGNUM
;
10909 record_buf
[1] = ARM_LR_REGNUM
;
10910 arm_insn_r
->reg_rec_count
= 2;
10912 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10916 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10917 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10920 /* Undefined instruction on ARM V5; need to handle if later
10921 versions define it. */
10924 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10925 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10926 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10928 /* Handle arithmetic insn extension space. */
10929 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10930 && !INSN_RECORDED(arm_insn_r
))
10932 /* Handle MLA(S) and MUL(S). */
10933 if (in_inclusive_range (insn_op1
, 0U, 3U))
10935 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10936 record_buf
[1] = ARM_PS_REGNUM
;
10937 arm_insn_r
->reg_rec_count
= 2;
10939 else if (in_inclusive_range (insn_op1
, 4U, 15U))
10941 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10942 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10943 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10944 record_buf
[2] = ARM_PS_REGNUM
;
10945 arm_insn_r
->reg_rec_count
= 3;
10949 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10950 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10951 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10953 /* Handle control insn extension space. */
10955 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10956 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10958 if (!bit (arm_insn_r
->arm_insn
,25))
10960 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10962 if ((0 == insn_op1
) || (2 == insn_op1
))
10965 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10966 arm_insn_r
->reg_rec_count
= 1;
10968 else if (1 == insn_op1
)
10970 /* CSPR is going to be changed. */
10971 record_buf
[0] = ARM_PS_REGNUM
;
10972 arm_insn_r
->reg_rec_count
= 1;
10974 else if (3 == insn_op1
)
10976 /* SPSR is going to be changed. */
10977 /* We need to get SPSR value, which is yet to be done. */
10981 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10986 record_buf
[0] = ARM_PS_REGNUM
;
10987 arm_insn_r
->reg_rec_count
= 1;
10989 else if (3 == insn_op1
)
10992 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10993 arm_insn_r
->reg_rec_count
= 1;
10996 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10999 record_buf
[0] = ARM_PS_REGNUM
;
11000 record_buf
[1] = ARM_LR_REGNUM
;
11001 arm_insn_r
->reg_rec_count
= 2;
11003 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11005 /* QADD, QSUB, QDADD, QDSUB */
11006 record_buf
[0] = ARM_PS_REGNUM
;
11007 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11008 arm_insn_r
->reg_rec_count
= 2;
11010 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11013 record_buf
[0] = ARM_PS_REGNUM
;
11014 record_buf
[1] = ARM_LR_REGNUM
;
11015 arm_insn_r
->reg_rec_count
= 2;
11017 /* Save SPSR also;how? */
11020 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11021 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11022 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11023 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11026 if (0 == insn_op1
|| 1 == insn_op1
)
11028 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11029 /* We dont do optimization for SMULW<y> where we
11031 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11032 record_buf
[1] = ARM_PS_REGNUM
;
11033 arm_insn_r
->reg_rec_count
= 2;
11035 else if (2 == insn_op1
)
11038 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11039 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11040 arm_insn_r
->reg_rec_count
= 2;
11042 else if (3 == insn_op1
)
11045 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11046 arm_insn_r
->reg_rec_count
= 1;
11052 /* MSR : immediate form. */
11055 /* CSPR is going to be changed. */
11056 record_buf
[0] = ARM_PS_REGNUM
;
11057 arm_insn_r
->reg_rec_count
= 1;
11059 else if (3 == insn_op1
)
11061 /* SPSR is going to be changed. */
11062 /* we need to get SPSR value, which is yet to be done */
11068 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11069 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11070 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11072 /* Handle load/store insn extension space. */
11074 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11075 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11076 && !INSN_RECORDED(arm_insn_r
))
11081 /* These insn, changes register and memory as well. */
11082 /* SWP or SWPB insn. */
11083 /* Get memory address given by Rn. */
11084 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11085 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11086 /* SWP insn ?, swaps word. */
11087 if (8 == arm_insn_r
->opcode
)
11089 record_buf_mem
[0] = 4;
11093 /* SWPB insn, swaps only byte. */
11094 record_buf_mem
[0] = 1;
11096 record_buf_mem
[1] = u_regval
;
11097 arm_insn_r
->mem_rec_count
= 1;
11098 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11099 arm_insn_r
->reg_rec_count
= 1;
11101 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11104 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11107 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11110 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11111 record_buf
[1] = record_buf
[0] + 1;
11112 arm_insn_r
->reg_rec_count
= 2;
11114 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11117 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11120 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11122 /* LDRH, LDRSB, LDRSH. */
11123 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11124 arm_insn_r
->reg_rec_count
= 1;
11129 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11130 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11131 && !INSN_RECORDED(arm_insn_r
))
11134 /* Handle coprocessor insn extension space. */
11137 /* To be done for ARMv5 and later; as of now we return -1. */
11141 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11142 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11147 /* Handling opcode 000 insns. */
11150 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11152 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11153 uint32_t record_buf
[8], record_buf_mem
[8];
11154 ULONGEST u_regval
[2] = {0};
11156 uint32_t reg_src1
= 0;
11157 uint32_t opcode1
= 0;
11159 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11160 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11161 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11163 if (!((opcode1
& 0x19) == 0x10))
11165 /* Data-processing (register) and Data-processing (register-shifted
11167 /* Out of 11 shifter operands mode, all the insn modifies destination
11168 register, which is specified by 13-16 decode. */
11169 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11170 record_buf
[1] = ARM_PS_REGNUM
;
11171 arm_insn_r
->reg_rec_count
= 2;
11173 else if ((arm_insn_r
->decode
< 8) && ((opcode1
& 0x19) == 0x10))
11175 /* Miscellaneous instructions */
11177 if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11178 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11180 /* Handle BLX, branch and link/exchange. */
11181 if (9 == arm_insn_r
->opcode
)
11183 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11184 and R14 stores the return address. */
11185 record_buf
[0] = ARM_PS_REGNUM
;
11186 record_buf
[1] = ARM_LR_REGNUM
;
11187 arm_insn_r
->reg_rec_count
= 2;
11190 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11192 /* Handle enhanced software breakpoint insn, BKPT. */
11193 /* CPSR is changed to be executed in ARM state, disabling normal
11194 interrupts, entering abort mode. */
11195 /* According to high vector configuration PC is set. */
11196 /* user hit breakpoint and type reverse, in
11197 that case, we need to go back with previous CPSR and
11198 Program Counter. */
11199 record_buf
[0] = ARM_PS_REGNUM
;
11200 record_buf
[1] = ARM_LR_REGNUM
;
11201 arm_insn_r
->reg_rec_count
= 2;
11203 /* Save SPSR also; how? */
11206 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11207 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11209 /* Handle BX, branch and link/exchange. */
11210 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11211 record_buf
[0] = ARM_PS_REGNUM
;
11212 arm_insn_r
->reg_rec_count
= 1;
11214 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11215 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11216 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11218 /* Count leading zeros: CLZ. */
11219 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11220 arm_insn_r
->reg_rec_count
= 1;
11222 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11223 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11224 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11225 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0))
11227 /* Handle MRS insn. */
11228 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11229 arm_insn_r
->reg_rec_count
= 1;
11232 else if (9 == arm_insn_r
->decode
&& opcode1
< 0x10)
11234 /* Multiply and multiply-accumulate */
11236 /* Handle multiply instructions. */
11237 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11238 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11240 /* Handle MLA and MUL. */
11241 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11242 record_buf
[1] = ARM_PS_REGNUM
;
11243 arm_insn_r
->reg_rec_count
= 2;
11245 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11247 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11248 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11249 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11250 record_buf
[2] = ARM_PS_REGNUM
;
11251 arm_insn_r
->reg_rec_count
= 3;
11254 else if (9 == arm_insn_r
->decode
&& opcode1
> 0x10)
11256 /* Synchronization primitives */
11258 /* Handling SWP, SWPB. */
11259 /* These insn, changes register and memory as well. */
11260 /* SWP or SWPB insn. */
11262 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11263 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11264 /* SWP insn ?, swaps word. */
11265 if (8 == arm_insn_r
->opcode
)
11267 record_buf_mem
[0] = 4;
11271 /* SWPB insn, swaps only byte. */
11272 record_buf_mem
[0] = 1;
11274 record_buf_mem
[1] = u_regval
[0];
11275 arm_insn_r
->mem_rec_count
= 1;
11276 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11277 arm_insn_r
->reg_rec_count
= 1;
11279 else if (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
11280 || 15 == arm_insn_r
->decode
)
11282 if ((opcode1
& 0x12) == 2)
11284 /* Extra load/store (unprivileged) */
11289 /* Extra load/store */
11290 switch (bits (arm_insn_r
->arm_insn
, 5, 6))
11293 if ((opcode1
& 0x05) == 0x0 || (opcode1
& 0x05) == 0x4)
11295 /* STRH (register), STRH (immediate) */
11296 arm_record_strx (arm_insn_r
, &record_buf
[0],
11297 &record_buf_mem
[0], ARM_RECORD_STRH
);
11299 else if ((opcode1
& 0x05) == 0x1)
11301 /* LDRH (register) */
11302 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11303 arm_insn_r
->reg_rec_count
= 1;
11305 if (bit (arm_insn_r
->arm_insn
, 21))
11307 /* Write back to Rn. */
11308 record_buf
[arm_insn_r
->reg_rec_count
++]
11309 = bits (arm_insn_r
->arm_insn
, 16, 19);
11312 else if ((opcode1
& 0x05) == 0x5)
11314 /* LDRH (immediate), LDRH (literal) */
11315 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11317 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11318 arm_insn_r
->reg_rec_count
= 1;
11322 /*LDRH (immediate) */
11323 if (bit (arm_insn_r
->arm_insn
, 21))
11325 /* Write back to Rn. */
11326 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
11334 if ((opcode1
& 0x05) == 0x0)
11336 /* LDRD (register) */
11337 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11338 record_buf
[1] = record_buf
[0] + 1;
11339 arm_insn_r
->reg_rec_count
= 2;
11341 if (bit (arm_insn_r
->arm_insn
, 21))
11343 /* Write back to Rn. */
11344 record_buf
[arm_insn_r
->reg_rec_count
++]
11345 = bits (arm_insn_r
->arm_insn
, 16, 19);
11348 else if ((opcode1
& 0x05) == 0x1)
11350 /* LDRSB (register) */
11351 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11352 arm_insn_r
->reg_rec_count
= 1;
11354 if (bit (arm_insn_r
->arm_insn
, 21))
11356 /* Write back to Rn. */
11357 record_buf
[arm_insn_r
->reg_rec_count
++]
11358 = bits (arm_insn_r
->arm_insn
, 16, 19);
11361 else if ((opcode1
& 0x05) == 0x4 || (opcode1
& 0x05) == 0x5)
11363 /* LDRD (immediate), LDRD (literal), LDRSB (immediate),
11365 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11367 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11368 arm_insn_r
->reg_rec_count
= 1;
11372 /*LDRD (immediate), LDRSB (immediate) */
11373 if (bit (arm_insn_r
->arm_insn
, 21))
11375 /* Write back to Rn. */
11376 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
11384 if ((opcode1
& 0x05) == 0x0)
11386 /* STRD (register) */
11387 arm_record_strx (arm_insn_r
, &record_buf
[0],
11388 &record_buf_mem
[0], ARM_RECORD_STRD
);
11390 else if ((opcode1
& 0x05) == 0x1)
11392 /* LDRSH (register) */
11393 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11394 arm_insn_r
->reg_rec_count
= 1;
11396 if (bit (arm_insn_r
->arm_insn
, 21))
11398 /* Write back to Rn. */
11399 record_buf
[arm_insn_r
->reg_rec_count
++]
11400 = bits (arm_insn_r
->arm_insn
, 16, 19);
11403 else if ((opcode1
& 0x05) == 0x4)
11405 /* STRD (immediate) */
11406 arm_record_strx (arm_insn_r
, &record_buf
[0],
11407 &record_buf_mem
[0], ARM_RECORD_STRD
);
11409 else if ((opcode1
& 0x05) == 0x5)
11411 /* LDRSH (immediate), LDRSH (literal) */
11412 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11413 arm_insn_r
->reg_rec_count
= 1;
11415 if (bit (arm_insn_r
->arm_insn
, 21))
11417 /* Write back to Rn. */
11418 record_buf
[arm_insn_r
->reg_rec_count
++]
11419 = bits (arm_insn_r
->arm_insn
, 16, 19);
11435 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11436 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11440 /* Handling opcode 001 insns. */
11443 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11445 uint32_t record_buf
[8], record_buf_mem
[8];
11447 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11448 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11450 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11451 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11452 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11455 /* Handle MSR insn. */
11456 if (9 == arm_insn_r
->opcode
)
11458 /* CSPR is going to be changed. */
11459 record_buf
[0] = ARM_PS_REGNUM
;
11460 arm_insn_r
->reg_rec_count
= 1;
11464 /* SPSR is going to be changed. */
11467 else if (arm_insn_r
->opcode
<= 15)
11469 /* Normal data processing insns. */
11470 /* Out of 11 shifter operands mode, all the insn modifies destination
11471 register, which is specified by 13-16 decode. */
11472 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11473 record_buf
[1] = ARM_PS_REGNUM
;
11474 arm_insn_r
->reg_rec_count
= 2;
11481 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11482 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11487 arm_record_media (insn_decode_record
*arm_insn_r
)
11489 uint32_t record_buf
[8];
11491 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
11494 /* Parallel addition and subtraction, signed */
11496 /* Parallel addition and subtraction, unsigned */
11499 /* Packing, unpacking, saturation and reversal */
11501 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11503 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
11509 /* Signed multiplies */
11511 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
11512 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
11514 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
11516 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11517 else if (op1
== 0x4)
11518 record_buf
[arm_insn_r
->reg_rec_count
++]
11519 = bits (arm_insn_r
->arm_insn
, 12, 15);
11525 if (bit (arm_insn_r
->arm_insn
, 21)
11526 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
11529 record_buf
[arm_insn_r
->reg_rec_count
++]
11530 = bits (arm_insn_r
->arm_insn
, 12, 15);
11532 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
11533 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
11535 /* USAD8 and USADA8 */
11536 record_buf
[arm_insn_r
->reg_rec_count
++]
11537 = bits (arm_insn_r
->arm_insn
, 16, 19);
11544 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
11545 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
11547 /* Permanently UNDEFINED */
11552 /* BFC, BFI and UBFX */
11553 record_buf
[arm_insn_r
->reg_rec_count
++]
11554 = bits (arm_insn_r
->arm_insn
, 12, 15);
11563 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11568 /* Handle ARM mode instructions with opcode 010. */
11571 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11573 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11575 uint32_t reg_base
, reg_dest
;
11576 uint32_t offset_12
, tgt_mem_addr
;
11577 uint32_t record_buf
[8], record_buf_mem
[8];
11578 unsigned char wback
;
11581 /* Calculate wback. */
11582 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11583 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11585 arm_insn_r
->reg_rec_count
= 0;
11586 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11588 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11590 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11593 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11594 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11596 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11597 preceeds a LDR instruction having R15 as reg_base, it
11598 emulates a branch and link instruction, and hence we need to save
11599 CPSR and PC as well. */
11600 if (ARM_PC_REGNUM
== reg_dest
)
11601 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11603 /* If wback is true, also save the base register, which is going to be
11606 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11610 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11612 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11613 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11615 /* Handle bit U. */
11616 if (bit (arm_insn_r
->arm_insn
, 23))
11618 /* U == 1: Add the offset. */
11619 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11623 /* U == 0: subtract the offset. */
11624 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11627 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11629 if (bit (arm_insn_r
->arm_insn
, 22))
11631 /* STRB and STRBT: 1 byte. */
11632 record_buf_mem
[0] = 1;
11636 /* STR and STRT: 4 bytes. */
11637 record_buf_mem
[0] = 4;
11640 /* Handle bit P. */
11641 if (bit (arm_insn_r
->arm_insn
, 24))
11642 record_buf_mem
[1] = tgt_mem_addr
;
11644 record_buf_mem
[1] = (uint32_t) u_regval
;
11646 arm_insn_r
->mem_rec_count
= 1;
11648 /* If wback is true, also save the base register, which is going to be
11651 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11654 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11655 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11659 /* Handling opcode 011 insns. */
11662 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11664 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11666 uint32_t shift_imm
= 0;
11667 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11668 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11669 uint32_t record_buf
[8], record_buf_mem
[8];
11672 ULONGEST u_regval
[2];
11674 if (bit (arm_insn_r
->arm_insn
, 4))
11675 return arm_record_media (arm_insn_r
);
11677 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11678 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11680 /* Handle enhanced store insns and LDRD DSP insn,
11681 order begins according to addressing modes for store insns
11685 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11687 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11688 /* LDR insn has a capability to do branching, if
11689 MOV LR, PC is preceded by LDR insn having Rn as R15
11690 in that case, it emulates branch and link insn, and hence we
11691 need to save CSPR and PC as well. */
11692 if (15 != reg_dest
)
11694 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11695 arm_insn_r
->reg_rec_count
= 1;
11699 record_buf
[0] = reg_dest
;
11700 record_buf
[1] = ARM_PS_REGNUM
;
11701 arm_insn_r
->reg_rec_count
= 2;
11706 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11708 /* Store insn, register offset and register pre-indexed,
11709 register post-indexed. */
11711 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11713 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11714 regcache_raw_read_unsigned (reg_cache
, reg_src1
11716 regcache_raw_read_unsigned (reg_cache
, reg_src2
11718 if (15 == reg_src2
)
11720 /* If R15 was used as Rn, hence current PC+8. */
11721 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11722 u_regval
[0] = u_regval
[0] + 8;
11724 /* Calculate target store address, Rn +/- Rm, register offset. */
11726 if (bit (arm_insn_r
->arm_insn
, 23))
11728 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11732 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11735 switch (arm_insn_r
->opcode
)
11749 record_buf_mem
[0] = 4;
11764 record_buf_mem
[0] = 1;
11768 gdb_assert_not_reached ("no decoding pattern found");
11771 record_buf_mem
[1] = tgt_mem_addr
;
11772 arm_insn_r
->mem_rec_count
= 1;
11774 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11775 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11776 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11777 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11778 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11779 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11782 /* Rn is going to be changed in pre-indexed mode and
11783 post-indexed mode as well. */
11784 record_buf
[0] = reg_src2
;
11785 arm_insn_r
->reg_rec_count
= 1;
11790 /* Store insn, scaled register offset; scaled pre-indexed. */
11791 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11793 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11795 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11796 /* Get shift_imm. */
11797 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11798 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11799 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11800 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11801 /* Offset_12 used as shift. */
11805 /* Offset_12 used as index. */
11806 offset_12
= u_regval
[0] << shift_imm
;
11810 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11816 if (bit (u_regval
[0], 31))
11818 offset_12
= 0xFFFFFFFF;
11827 /* This is arithmetic shift. */
11828 offset_12
= s_word
>> shift_imm
;
11835 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11837 /* Get C flag value and shift it by 31. */
11838 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11839 | (u_regval
[0]) >> 1);
11843 offset_12
= (u_regval
[0] >> shift_imm
) \
11845 (sizeof(uint32_t) - shift_imm
));
11850 gdb_assert_not_reached ("no decoding pattern found");
11854 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11856 if (bit (arm_insn_r
->arm_insn
, 23))
11858 tgt_mem_addr
= u_regval
[1] + offset_12
;
11862 tgt_mem_addr
= u_regval
[1] - offset_12
;
11865 switch (arm_insn_r
->opcode
)
11879 record_buf_mem
[0] = 4;
11894 record_buf_mem
[0] = 1;
11898 gdb_assert_not_reached ("no decoding pattern found");
11901 record_buf_mem
[1] = tgt_mem_addr
;
11902 arm_insn_r
->mem_rec_count
= 1;
11904 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11905 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11906 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11907 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11908 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11909 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11912 /* Rn is going to be changed in register scaled pre-indexed
11913 mode,and scaled post indexed mode. */
11914 record_buf
[0] = reg_src2
;
11915 arm_insn_r
->reg_rec_count
= 1;
11920 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11921 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11925 /* Handle ARM mode instructions with opcode 100. */
11928 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11930 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11931 uint32_t register_count
= 0, register_bits
;
11932 uint32_t reg_base
, addr_mode
;
11933 uint32_t record_buf
[24], record_buf_mem
[48];
11937 /* Fetch the list of registers. */
11938 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11939 arm_insn_r
->reg_rec_count
= 0;
11941 /* Fetch the base register that contains the address we are loading data
11943 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11945 /* Calculate wback. */
11946 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11948 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11950 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11952 /* Find out which registers are going to be loaded from memory. */
11953 while (register_bits
)
11955 if (register_bits
& 0x00000001)
11956 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11957 register_bits
= register_bits
>> 1;
11962 /* If wback is true, also save the base register, which is going to be
11965 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11967 /* Save the CPSR register. */
11968 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11972 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11974 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11976 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11978 /* Find out how many registers are going to be stored to memory. */
11979 while (register_bits
)
11981 if (register_bits
& 0x00000001)
11983 register_bits
= register_bits
>> 1;
11988 /* STMDA (STMED): Decrement after. */
11990 record_buf_mem
[1] = (uint32_t) u_regval
11991 - register_count
* ARM_INT_REGISTER_SIZE
+ 4;
11993 /* STM (STMIA, STMEA): Increment after. */
11995 record_buf_mem
[1] = (uint32_t) u_regval
;
11997 /* STMDB (STMFD): Decrement before. */
11999 record_buf_mem
[1] = (uint32_t) u_regval
12000 - register_count
* ARM_INT_REGISTER_SIZE
;
12002 /* STMIB (STMFA): Increment before. */
12004 record_buf_mem
[1] = (uint32_t) u_regval
+ ARM_INT_REGISTER_SIZE
;
12007 gdb_assert_not_reached ("no decoding pattern found");
12011 record_buf_mem
[0] = register_count
* ARM_INT_REGISTER_SIZE
;
12012 arm_insn_r
->mem_rec_count
= 1;
12014 /* If wback is true, also save the base register, which is going to be
12017 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
12020 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12021 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12025 /* Handling opcode 101 insns. */
12028 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
12030 uint32_t record_buf
[8];
12032 /* Handle B, BL, BLX(1) insns. */
12033 /* B simply branches so we do nothing here. */
12034 /* Note: BLX(1) doesnt fall here but instead it falls into
12035 extension space. */
12036 if (bit (arm_insn_r
->arm_insn
, 24))
12038 record_buf
[0] = ARM_LR_REGNUM
;
12039 arm_insn_r
->reg_rec_count
= 1;
12042 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12048 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
12050 gdb_printf (gdb_stderr
,
12051 _("Process record does not support instruction "
12052 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
12053 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
12058 /* Record handler for vector data transfer instructions. */
12061 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
12063 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
12064 uint32_t record_buf
[4];
12066 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
12067 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
12068 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
12069 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
12070 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
12072 /* Handle VMOV instruction. */
12073 if (bit_l
&& bit_c
)
12075 record_buf
[0] = reg_t
;
12076 arm_insn_r
->reg_rec_count
= 1;
12078 else if (bit_l
&& !bit_c
)
12080 /* Handle VMOV instruction. */
12081 if (bits_a
== 0x00)
12083 record_buf
[0] = reg_t
;
12084 arm_insn_r
->reg_rec_count
= 1;
12086 /* Handle VMRS instruction. */
12087 else if (bits_a
== 0x07)
12090 reg_t
= ARM_PS_REGNUM
;
12092 record_buf
[0] = reg_t
;
12093 arm_insn_r
->reg_rec_count
= 1;
12096 else if (!bit_l
&& !bit_c
)
12098 /* Handle VMOV instruction. */
12099 if (bits_a
== 0x00)
12101 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
12103 arm_insn_r
->reg_rec_count
= 1;
12105 /* Handle VMSR instruction. */
12106 else if (bits_a
== 0x07)
12108 record_buf
[0] = ARM_FPSCR_REGNUM
;
12109 arm_insn_r
->reg_rec_count
= 1;
12112 else if (!bit_l
&& bit_c
)
12114 /* Handle VMOV instruction. */
12115 if (!(bits_a
& 0x04))
12117 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12119 arm_insn_r
->reg_rec_count
= 1;
12121 /* Handle VDUP instruction. */
12124 if (bit (arm_insn_r
->arm_insn
, 21))
12126 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12127 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12128 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12129 arm_insn_r
->reg_rec_count
= 2;
12133 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12134 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12135 arm_insn_r
->reg_rec_count
= 1;
12140 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12144 /* Record handler for extension register load/store instructions. */
12147 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12149 uint32_t opcode
, single_reg
;
12150 uint8_t op_vldm_vstm
;
12151 uint32_t record_buf
[8], record_buf_mem
[128];
12152 ULONGEST u_regval
= 0;
12154 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12156 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12157 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
12158 op_vldm_vstm
= opcode
& 0x1b;
12160 /* Handle VMOV instructions. */
12161 if ((opcode
& 0x1e) == 0x04)
12163 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
12165 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12166 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12167 arm_insn_r
->reg_rec_count
= 2;
12171 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
12172 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
12176 /* The first S register number m is REG_M:M (M is bit 5),
12177 the corresponding D register number is REG_M:M / 2, which
12179 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
12180 /* The second S register number is REG_M:M + 1, the
12181 corresponding D register number is (REG_M:M + 1) / 2.
12182 IOW, if bit M is 1, the first and second S registers
12183 are mapped to different D registers, otherwise, they are
12184 in the same D register. */
12187 record_buf
[arm_insn_r
->reg_rec_count
++]
12188 = ARM_D0_REGNUM
+ reg_m
+ 1;
12193 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
12194 arm_insn_r
->reg_rec_count
= 1;
12198 /* Handle VSTM and VPUSH instructions. */
12199 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12200 || op_vldm_vstm
== 0x12)
12202 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12203 uint32_t memory_index
= 0;
12205 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12206 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12207 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12208 imm_off32
= imm_off8
<< 2;
12209 memory_count
= imm_off8
;
12211 if (bit (arm_insn_r
->arm_insn
, 23))
12212 start_address
= u_regval
;
12214 start_address
= u_regval
- imm_off32
;
12216 if (bit (arm_insn_r
->arm_insn
, 21))
12218 record_buf
[0] = reg_rn
;
12219 arm_insn_r
->reg_rec_count
= 1;
12222 while (memory_count
> 0)
12226 record_buf_mem
[memory_index
] = 4;
12227 record_buf_mem
[memory_index
+ 1] = start_address
;
12228 start_address
= start_address
+ 4;
12229 memory_index
= memory_index
+ 2;
12233 record_buf_mem
[memory_index
] = 4;
12234 record_buf_mem
[memory_index
+ 1] = start_address
;
12235 record_buf_mem
[memory_index
+ 2] = 4;
12236 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
12237 start_address
= start_address
+ 8;
12238 memory_index
= memory_index
+ 4;
12242 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12244 /* Handle VLDM instructions. */
12245 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12246 || op_vldm_vstm
== 0x13)
12248 uint32_t reg_count
, reg_vd
;
12249 uint32_t reg_index
= 0;
12250 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12252 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12253 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12255 /* REG_VD is the first D register number. If the instruction
12256 loads memory to S registers (SINGLE_REG is TRUE), the register
12257 number is (REG_VD << 1 | bit D), so the corresponding D
12258 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
12260 reg_vd
= reg_vd
| (bit_d
<< 4);
12262 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
12263 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12265 /* If the instruction loads memory to D register, REG_COUNT should
12266 be divided by 2, according to the ARM Architecture Reference
12267 Manual. If the instruction loads memory to S register, divide by
12268 2 as well because two S registers are mapped to D register. */
12269 reg_count
= reg_count
/ 2;
12270 if (single_reg
&& bit_d
)
12272 /* Increase the register count if S register list starts from
12273 an odd number (bit d is one). */
12277 while (reg_count
> 0)
12279 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12282 arm_insn_r
->reg_rec_count
= reg_index
;
12284 /* VSTR Vector store register. */
12285 else if ((opcode
& 0x13) == 0x10)
12287 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
12288 uint32_t memory_index
= 0;
12290 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12291 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12292 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12293 imm_off32
= imm_off8
<< 2;
12295 if (bit (arm_insn_r
->arm_insn
, 23))
12296 start_address
= u_regval
+ imm_off32
;
12298 start_address
= u_regval
- imm_off32
;
12302 record_buf_mem
[memory_index
] = 4;
12303 record_buf_mem
[memory_index
+ 1] = start_address
;
12304 arm_insn_r
->mem_rec_count
= 1;
12308 record_buf_mem
[memory_index
] = 4;
12309 record_buf_mem
[memory_index
+ 1] = start_address
;
12310 record_buf_mem
[memory_index
+ 2] = 4;
12311 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
12312 arm_insn_r
->mem_rec_count
= 2;
12315 /* VLDR Vector load register. */
12316 else if ((opcode
& 0x13) == 0x11)
12318 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12322 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12323 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12327 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12328 /* Record register D rather than pseudo register S. */
12329 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
12331 arm_insn_r
->reg_rec_count
= 1;
12334 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12335 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12339 /* Record handler for arm/thumb mode VFP data processing instructions. */
12342 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12344 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12345 uint32_t record_buf
[4];
12346 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12347 enum insn_types curr_insn_type
= INSN_INV
;
12349 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12350 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12351 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12352 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12353 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12354 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12355 /* Mask off the "D" bit. */
12356 opc1
= opc1
& ~0x04;
12358 /* Handle VMLA, VMLS. */
12361 if (bit (arm_insn_r
->arm_insn
, 10))
12363 if (bit (arm_insn_r
->arm_insn
, 6))
12364 curr_insn_type
= INSN_T0
;
12366 curr_insn_type
= INSN_T1
;
12371 curr_insn_type
= INSN_T1
;
12373 curr_insn_type
= INSN_T2
;
12376 /* Handle VNMLA, VNMLS, VNMUL. */
12377 else if (opc1
== 0x01)
12380 curr_insn_type
= INSN_T1
;
12382 curr_insn_type
= INSN_T2
;
12385 else if (opc1
== 0x02 && !(opc3
& 0x01))
12387 if (bit (arm_insn_r
->arm_insn
, 10))
12389 if (bit (arm_insn_r
->arm_insn
, 6))
12390 curr_insn_type
= INSN_T0
;
12392 curr_insn_type
= INSN_T1
;
12397 curr_insn_type
= INSN_T1
;
12399 curr_insn_type
= INSN_T2
;
12402 /* Handle VADD, VSUB. */
12403 else if (opc1
== 0x03)
12405 if (!bit (arm_insn_r
->arm_insn
, 9))
12407 if (bit (arm_insn_r
->arm_insn
, 6))
12408 curr_insn_type
= INSN_T0
;
12410 curr_insn_type
= INSN_T1
;
12415 curr_insn_type
= INSN_T1
;
12417 curr_insn_type
= INSN_T2
;
12421 else if (opc1
== 0x08)
12424 curr_insn_type
= INSN_T1
;
12426 curr_insn_type
= INSN_T2
;
12428 /* Handle all other vfp data processing instructions. */
12429 else if (opc1
== 0x0b)
12432 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12434 if (bit (arm_insn_r
->arm_insn
, 4))
12436 if (bit (arm_insn_r
->arm_insn
, 6))
12437 curr_insn_type
= INSN_T0
;
12439 curr_insn_type
= INSN_T1
;
12444 curr_insn_type
= INSN_T1
;
12446 curr_insn_type
= INSN_T2
;
12449 /* Handle VNEG and VABS. */
12450 else if ((opc2
== 0x01 && opc3
== 0x01)
12451 || (opc2
== 0x00 && opc3
== 0x03))
12453 if (!bit (arm_insn_r
->arm_insn
, 11))
12455 if (bit (arm_insn_r
->arm_insn
, 6))
12456 curr_insn_type
= INSN_T0
;
12458 curr_insn_type
= INSN_T1
;
12463 curr_insn_type
= INSN_T1
;
12465 curr_insn_type
= INSN_T2
;
12468 /* Handle VSQRT. */
12469 else if (opc2
== 0x01 && opc3
== 0x03)
12472 curr_insn_type
= INSN_T1
;
12474 curr_insn_type
= INSN_T2
;
12477 else if (opc2
== 0x07 && opc3
== 0x03)
12480 curr_insn_type
= INSN_T1
;
12482 curr_insn_type
= INSN_T2
;
12484 else if (opc3
& 0x01)
12487 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12489 if (!bit (arm_insn_r
->arm_insn
, 18))
12490 curr_insn_type
= INSN_T2
;
12494 curr_insn_type
= INSN_T1
;
12496 curr_insn_type
= INSN_T2
;
12500 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12503 curr_insn_type
= INSN_T1
;
12505 curr_insn_type
= INSN_T2
;
12507 /* Handle VCVTB, VCVTT. */
12508 else if ((opc2
& 0x0e) == 0x02)
12509 curr_insn_type
= INSN_T2
;
12510 /* Handle VCMP, VCMPE. */
12511 else if ((opc2
& 0x0e) == 0x04)
12512 curr_insn_type
= INSN_T3
;
12516 switch (curr_insn_type
)
12519 reg_vd
= reg_vd
| (bit_d
<< 4);
12520 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12521 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12522 arm_insn_r
->reg_rec_count
= 2;
12526 reg_vd
= reg_vd
| (bit_d
<< 4);
12527 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12528 arm_insn_r
->reg_rec_count
= 1;
12532 reg_vd
= (reg_vd
<< 1) | bit_d
;
12533 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12534 arm_insn_r
->reg_rec_count
= 1;
12538 record_buf
[0] = ARM_FPSCR_REGNUM
;
12539 arm_insn_r
->reg_rec_count
= 1;
12543 gdb_assert_not_reached ("no decoding pattern found");
12547 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12551 /* Handling opcode 110 insns. */
12554 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12556 uint32_t op1
, op1_ebit
, coproc
;
12558 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12559 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12560 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12562 if ((coproc
& 0x0e) == 0x0a)
12564 /* Handle extension register ld/st instructions. */
12566 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12568 /* 64-bit transfers between arm core and extension registers. */
12569 if ((op1
& 0x3e) == 0x04)
12570 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12574 /* Handle coprocessor ld/st instructions. */
12579 return arm_record_unsupported_insn (arm_insn_r
);
12582 return arm_record_unsupported_insn (arm_insn_r
);
12585 /* Move to coprocessor from two arm core registers. */
12587 return arm_record_unsupported_insn (arm_insn_r
);
12589 /* Move to two arm core registers from coprocessor. */
12594 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12595 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12596 arm_insn_r
->reg_rec_count
= 2;
12598 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12602 return arm_record_unsupported_insn (arm_insn_r
);
12605 /* Handling opcode 111 insns. */
12608 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12610 uint32_t op
, op1_ebit
, coproc
, bits_24_25
;
12611 arm_gdbarch_tdep
*tdep
12612 = (arm_gdbarch_tdep
*) gdbarch_tdep (arm_insn_r
->gdbarch
);
12613 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12615 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12616 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12617 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12618 op
= bit (arm_insn_r
->arm_insn
, 4);
12619 bits_24_25
= bits (arm_insn_r
->arm_insn
, 24, 25);
12621 /* Handle arm SWI/SVC system call instructions. */
12622 if (bits_24_25
== 0x3)
12624 if (tdep
->arm_syscall_record
!= NULL
)
12626 ULONGEST svc_operand
, svc_number
;
12628 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12630 if (svc_operand
) /* OABI. */
12631 svc_number
= svc_operand
- 0x900000;
12633 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12635 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12639 gdb_printf (gdb_stderr
, _("no syscall record support\n"));
12643 else if (bits_24_25
== 0x02)
12647 if ((coproc
& 0x0e) == 0x0a)
12649 /* 8, 16, and 32-bit transfer */
12650 return arm_record_vdata_transfer_insn (arm_insn_r
);
12657 uint32_t record_buf
[1];
12659 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12660 if (record_buf
[0] == 15)
12661 record_buf
[0] = ARM_PS_REGNUM
;
12663 arm_insn_r
->reg_rec_count
= 1;
12664 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12677 if ((coproc
& 0x0e) == 0x0a)
12679 /* VFP data-processing instructions. */
12680 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12691 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12695 if ((coproc
& 0x0e) != 0x0a)
12701 else if (op1
== 4 || op1
== 5)
12703 if ((coproc
& 0x0e) == 0x0a)
12705 /* 64-bit transfers between ARM core and extension */
12714 else if (op1
== 0 || op1
== 1)
12721 if ((coproc
& 0x0e) == 0x0a)
12723 /* Extension register load/store */
12727 /* STC, STC2, LDC, LDC2 */
12736 /* Handling opcode 000 insns. */
12739 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12741 uint32_t record_buf
[8];
12742 uint32_t reg_src1
= 0;
12744 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12746 record_buf
[0] = ARM_PS_REGNUM
;
12747 record_buf
[1] = reg_src1
;
12748 thumb_insn_r
->reg_rec_count
= 2;
12750 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12756 /* Handling opcode 001 insns. */
12759 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12761 uint32_t record_buf
[8];
12762 uint32_t reg_src1
= 0;
12764 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12766 record_buf
[0] = ARM_PS_REGNUM
;
12767 record_buf
[1] = reg_src1
;
12768 thumb_insn_r
->reg_rec_count
= 2;
12770 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12775 /* Handling opcode 010 insns. */
12778 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12780 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12781 uint32_t record_buf
[8], record_buf_mem
[8];
12783 uint32_t reg_src1
= 0, reg_src2
= 0;
12784 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12786 ULONGEST u_regval
[2] = {0};
12788 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12790 if (bit (thumb_insn_r
->arm_insn
, 12))
12792 /* Handle load/store register offset. */
12793 uint32_t opB
= bits (thumb_insn_r
->arm_insn
, 9, 11);
12795 if (in_inclusive_range (opB
, 4U, 7U))
12797 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12798 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12799 record_buf
[0] = reg_src1
;
12800 thumb_insn_r
->reg_rec_count
= 1;
12802 else if (in_inclusive_range (opB
, 0U, 2U))
12804 /* STR(2), STRB(2), STRH(2) . */
12805 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12806 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12807 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12808 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12810 record_buf_mem
[0] = 4; /* STR (2). */
12812 record_buf_mem
[0] = 1; /* STRB (2). */
12814 record_buf_mem
[0] = 2; /* STRH (2). */
12815 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12816 thumb_insn_r
->mem_rec_count
= 1;
12819 else if (bit (thumb_insn_r
->arm_insn
, 11))
12821 /* Handle load from literal pool. */
12823 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12824 record_buf
[0] = reg_src1
;
12825 thumb_insn_r
->reg_rec_count
= 1;
12829 /* Special data instructions and branch and exchange */
12830 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12831 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12832 if ((3 == opcode2
) && (!opcode3
))
12834 /* Branch with exchange. */
12835 record_buf
[0] = ARM_PS_REGNUM
;
12836 thumb_insn_r
->reg_rec_count
= 1;
12840 /* Format 8; special data processing insns. */
12841 record_buf
[0] = ARM_PS_REGNUM
;
12842 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
12843 | bits (thumb_insn_r
->arm_insn
, 0, 2));
12844 thumb_insn_r
->reg_rec_count
= 2;
12849 /* Format 5; data processing insns. */
12850 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12851 if (bit (thumb_insn_r
->arm_insn
, 7))
12853 reg_src1
= reg_src1
+ 8;
12855 record_buf
[0] = ARM_PS_REGNUM
;
12856 record_buf
[1] = reg_src1
;
12857 thumb_insn_r
->reg_rec_count
= 2;
12860 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12861 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12867 /* Handling opcode 001 insns. */
12870 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12872 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12873 uint32_t record_buf
[8], record_buf_mem
[8];
12875 uint32_t reg_src1
= 0;
12876 uint32_t opcode
= 0, immed_5
= 0;
12878 ULONGEST u_regval
= 0;
12880 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12885 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12886 record_buf
[0] = reg_src1
;
12887 thumb_insn_r
->reg_rec_count
= 1;
12892 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12893 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12894 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12895 record_buf_mem
[0] = 4;
12896 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12897 thumb_insn_r
->mem_rec_count
= 1;
12900 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12901 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12907 /* Handling opcode 100 insns. */
12910 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12912 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12913 uint32_t record_buf
[8], record_buf_mem
[8];
12915 uint32_t reg_src1
= 0;
12916 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12918 ULONGEST u_regval
= 0;
12920 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12925 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12926 record_buf
[0] = reg_src1
;
12927 thumb_insn_r
->reg_rec_count
= 1;
12929 else if (1 == opcode
)
12932 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12933 record_buf
[0] = reg_src1
;
12934 thumb_insn_r
->reg_rec_count
= 1;
12936 else if (2 == opcode
)
12939 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12940 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12941 record_buf_mem
[0] = 4;
12942 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12943 thumb_insn_r
->mem_rec_count
= 1;
12945 else if (0 == opcode
)
12948 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12949 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12950 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12951 record_buf_mem
[0] = 2;
12952 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12953 thumb_insn_r
->mem_rec_count
= 1;
12956 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12957 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12963 /* Handling opcode 101 insns. */
12966 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12968 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12970 uint32_t opcode
= 0;
12971 uint32_t register_bits
= 0, register_count
= 0;
12972 uint32_t index
= 0, start_address
= 0;
12973 uint32_t record_buf
[24], record_buf_mem
[48];
12976 ULONGEST u_regval
= 0;
12978 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12980 if (opcode
== 0 || opcode
== 1)
12982 /* ADR and ADD (SP plus immediate) */
12984 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12985 record_buf
[0] = reg_src1
;
12986 thumb_insn_r
->reg_rec_count
= 1;
12990 /* Miscellaneous 16-bit instructions */
12991 uint32_t opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 11);
12996 /* SETEND and CPS */
12999 /* ADD/SUB (SP plus immediate) */
13000 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
13001 record_buf
[0] = ARM_SP_REGNUM
;
13002 thumb_insn_r
->reg_rec_count
= 1;
13004 case 1: /* fall through */
13005 case 3: /* fall through */
13006 case 9: /* fall through */
13011 /* SXTH, SXTB, UXTH, UXTB */
13012 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
13013 thumb_insn_r
->reg_rec_count
= 1;
13015 case 4: /* fall through */
13018 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
13019 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
13020 while (register_bits
)
13022 if (register_bits
& 0x00000001)
13024 register_bits
= register_bits
>> 1;
13026 start_address
= u_regval
- \
13027 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
13028 thumb_insn_r
->mem_rec_count
= register_count
;
13029 while (register_count
)
13031 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
13032 record_buf_mem
[(register_count
* 2) - 2] = 4;
13033 start_address
= start_address
+ 4;
13036 record_buf
[0] = ARM_SP_REGNUM
;
13037 thumb_insn_r
->reg_rec_count
= 1;
13040 /* REV, REV16, REVSH */
13041 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
13042 thumb_insn_r
->reg_rec_count
= 1;
13044 case 12: /* fall through */
13047 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
13048 while (register_bits
)
13050 if (register_bits
& 0x00000001)
13051 record_buf
[index
++] = register_count
;
13052 register_bits
= register_bits
>> 1;
13055 record_buf
[index
++] = ARM_PS_REGNUM
;
13056 record_buf
[index
++] = ARM_SP_REGNUM
;
13057 thumb_insn_r
->reg_rec_count
= index
;
13061 /* Handle enhanced software breakpoint insn, BKPT. */
13062 /* CPSR is changed to be executed in ARM state, disabling normal
13063 interrupts, entering abort mode. */
13064 /* According to high vector configuration PC is set. */
13065 /* User hits breakpoint and type reverse, in that case, we need to go back with
13066 previous CPSR and Program Counter. */
13067 record_buf
[0] = ARM_PS_REGNUM
;
13068 record_buf
[1] = ARM_LR_REGNUM
;
13069 thumb_insn_r
->reg_rec_count
= 2;
13070 /* We need to save SPSR value, which is not yet done. */
13071 gdb_printf (gdb_stderr
,
13072 _("Process record does not support instruction "
13073 "0x%0x at address %s.\n"),
13074 thumb_insn_r
->arm_insn
,
13075 paddress (thumb_insn_r
->gdbarch
,
13076 thumb_insn_r
->this_addr
));
13080 /* If-Then, and hints */
13087 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13088 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
13094 /* Handling opcode 110 insns. */
13097 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
13099 arm_gdbarch_tdep
*tdep
13100 = (arm_gdbarch_tdep
*) gdbarch_tdep (thumb_insn_r
->gdbarch
);
13101 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
13103 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
13104 uint32_t reg_src1
= 0;
13105 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
13106 uint32_t index
= 0, start_address
= 0;
13107 uint32_t record_buf
[24], record_buf_mem
[48];
13109 ULONGEST u_regval
= 0;
13111 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
13112 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
13118 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
13120 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
13121 while (register_bits
)
13123 if (register_bits
& 0x00000001)
13124 record_buf
[index
++] = register_count
;
13125 register_bits
= register_bits
>> 1;
13128 record_buf
[index
++] = reg_src1
;
13129 thumb_insn_r
->reg_rec_count
= index
;
13131 else if (0 == opcode2
)
13133 /* It handles both STMIA. */
13134 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
13136 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
13137 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
13138 while (register_bits
)
13140 if (register_bits
& 0x00000001)
13142 register_bits
= register_bits
>> 1;
13144 start_address
= u_regval
;
13145 thumb_insn_r
->mem_rec_count
= register_count
;
13146 while (register_count
)
13148 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
13149 record_buf_mem
[(register_count
* 2) - 2] = 4;
13150 start_address
= start_address
+ 4;
13154 else if (0x1F == opcode1
)
13156 /* Handle arm syscall insn. */
13157 if (tdep
->arm_syscall_record
!= NULL
)
13159 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
13160 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
13164 gdb_printf (gdb_stderr
, _("no syscall record support\n"));
13169 /* B (1), conditional branch is automatically taken care in process_record,
13170 as PC is saved there. */
13172 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13173 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
13179 /* Handling opcode 111 insns. */
13182 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
13184 uint32_t record_buf
[8];
13185 uint32_t bits_h
= 0;
13187 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
13189 if (2 == bits_h
|| 3 == bits_h
)
13192 record_buf
[0] = ARM_LR_REGNUM
;
13193 thumb_insn_r
->reg_rec_count
= 1;
13195 else if (1 == bits_h
)
13198 record_buf
[0] = ARM_PS_REGNUM
;
13199 record_buf
[1] = ARM_LR_REGNUM
;
13200 thumb_insn_r
->reg_rec_count
= 2;
13203 /* B(2) is automatically taken care in process_record, as PC is
13206 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13211 /* Handler for thumb2 load/store multiple instructions. */
13214 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13216 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13218 uint32_t reg_rn
, op
;
13219 uint32_t register_bits
= 0, register_count
= 0;
13220 uint32_t index
= 0, start_address
= 0;
13221 uint32_t record_buf
[24], record_buf_mem
[48];
13223 ULONGEST u_regval
= 0;
13225 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13226 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13228 if (0 == op
|| 3 == op
)
13230 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13232 /* Handle RFE instruction. */
13233 record_buf
[0] = ARM_PS_REGNUM
;
13234 thumb2_insn_r
->reg_rec_count
= 1;
13238 /* Handle SRS instruction after reading banked SP. */
13239 return arm_record_unsupported_insn (thumb2_insn_r
);
13242 else if (1 == op
|| 2 == op
)
13244 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13246 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13247 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13248 while (register_bits
)
13250 if (register_bits
& 0x00000001)
13251 record_buf
[index
++] = register_count
;
13254 register_bits
= register_bits
>> 1;
13256 record_buf
[index
++] = reg_rn
;
13257 record_buf
[index
++] = ARM_PS_REGNUM
;
13258 thumb2_insn_r
->reg_rec_count
= index
;
13262 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13263 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13264 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13265 while (register_bits
)
13267 if (register_bits
& 0x00000001)
13270 register_bits
= register_bits
>> 1;
13275 /* Start address calculation for LDMDB/LDMEA. */
13276 start_address
= u_regval
;
13280 /* Start address calculation for LDMDB/LDMEA. */
13281 start_address
= u_regval
- register_count
* 4;
13284 thumb2_insn_r
->mem_rec_count
= register_count
;
13285 while (register_count
)
13287 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13288 record_buf_mem
[register_count
* 2 - 2] = 4;
13289 start_address
= start_address
+ 4;
13292 record_buf
[0] = reg_rn
;
13293 record_buf
[1] = ARM_PS_REGNUM
;
13294 thumb2_insn_r
->reg_rec_count
= 2;
13298 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13300 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13302 return ARM_RECORD_SUCCESS
;
13305 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13309 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13311 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13313 uint32_t reg_rd
, reg_rn
, offset_imm
;
13314 uint32_t reg_dest1
, reg_dest2
;
13315 uint32_t address
, offset_addr
;
13316 uint32_t record_buf
[8], record_buf_mem
[8];
13317 uint32_t op1
, op2
, op3
;
13319 ULONGEST u_regval
[2];
13321 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13322 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13323 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13325 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13327 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13329 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13330 record_buf
[0] = reg_dest1
;
13331 record_buf
[1] = ARM_PS_REGNUM
;
13332 thumb2_insn_r
->reg_rec_count
= 2;
13335 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13337 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13338 record_buf
[2] = reg_dest2
;
13339 thumb2_insn_r
->reg_rec_count
= 3;
13344 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13345 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13347 if (0 == op1
&& 0 == op2
)
13349 /* Handle STREX. */
13350 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13351 address
= u_regval
[0] + (offset_imm
* 4);
13352 record_buf_mem
[0] = 4;
13353 record_buf_mem
[1] = address
;
13354 thumb2_insn_r
->mem_rec_count
= 1;
13355 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13356 record_buf
[0] = reg_rd
;
13357 thumb2_insn_r
->reg_rec_count
= 1;
13359 else if (1 == op1
&& 0 == op2
)
13361 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13362 record_buf
[0] = reg_rd
;
13363 thumb2_insn_r
->reg_rec_count
= 1;
13364 address
= u_regval
[0];
13365 record_buf_mem
[1] = address
;
13369 /* Handle STREXB. */
13370 record_buf_mem
[0] = 1;
13371 thumb2_insn_r
->mem_rec_count
= 1;
13375 /* Handle STREXH. */
13376 record_buf_mem
[0] = 2 ;
13377 thumb2_insn_r
->mem_rec_count
= 1;
13381 /* Handle STREXD. */
13382 address
= u_regval
[0];
13383 record_buf_mem
[0] = 4;
13384 record_buf_mem
[2] = 4;
13385 record_buf_mem
[3] = address
+ 4;
13386 thumb2_insn_r
->mem_rec_count
= 2;
13391 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13393 if (bit (thumb2_insn_r
->arm_insn
, 24))
13395 if (bit (thumb2_insn_r
->arm_insn
, 23))
13396 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13398 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13400 address
= offset_addr
;
13403 address
= u_regval
[0];
13405 record_buf_mem
[0] = 4;
13406 record_buf_mem
[1] = address
;
13407 record_buf_mem
[2] = 4;
13408 record_buf_mem
[3] = address
+ 4;
13409 thumb2_insn_r
->mem_rec_count
= 2;
13410 record_buf
[0] = reg_rn
;
13411 thumb2_insn_r
->reg_rec_count
= 1;
13415 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13417 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13419 return ARM_RECORD_SUCCESS
;
13422 /* Handler for thumb2 data processing (shift register and modified immediate)
13426 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13428 uint32_t reg_rd
, op
;
13429 uint32_t record_buf
[8];
13431 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13432 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13434 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13436 record_buf
[0] = ARM_PS_REGNUM
;
13437 thumb2_insn_r
->reg_rec_count
= 1;
13441 record_buf
[0] = reg_rd
;
13442 record_buf
[1] = ARM_PS_REGNUM
;
13443 thumb2_insn_r
->reg_rec_count
= 2;
13446 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13448 return ARM_RECORD_SUCCESS
;
13451 /* Generic handler for thumb2 instructions which effect destination and PS
13455 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13458 uint32_t record_buf
[8];
13460 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13462 record_buf
[0] = reg_rd
;
13463 record_buf
[1] = ARM_PS_REGNUM
;
13464 thumb2_insn_r
->reg_rec_count
= 2;
13466 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13468 return ARM_RECORD_SUCCESS
;
13471 /* Handler for thumb2 branch and miscellaneous control instructions. */
13474 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13476 uint32_t op
, op1
, op2
;
13477 uint32_t record_buf
[8];
13479 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13480 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13481 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13483 /* Handle MSR insn. */
13484 if (!(op1
& 0x2) && 0x38 == op
)
13488 /* CPSR is going to be changed. */
13489 record_buf
[0] = ARM_PS_REGNUM
;
13490 thumb2_insn_r
->reg_rec_count
= 1;
13494 arm_record_unsupported_insn(thumb2_insn_r
);
13498 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13501 record_buf
[0] = ARM_PS_REGNUM
;
13502 record_buf
[1] = ARM_LR_REGNUM
;
13503 thumb2_insn_r
->reg_rec_count
= 2;
13506 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13508 return ARM_RECORD_SUCCESS
;
13511 /* Handler for thumb2 store single data item instructions. */
13514 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13516 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13518 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13519 uint32_t address
, offset_addr
;
13520 uint32_t record_buf
[8], record_buf_mem
[8];
13523 ULONGEST u_regval
[2];
13525 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13526 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13527 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13528 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13530 if (bit (thumb2_insn_r
->arm_insn
, 23))
13533 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13534 offset_addr
= u_regval
[0] + offset_imm
;
13535 address
= offset_addr
;
13540 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13542 /* Handle STRB (register). */
13543 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13544 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13545 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13546 offset_addr
= u_regval
[1] << shift_imm
;
13547 address
= u_regval
[0] + offset_addr
;
13551 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13552 if (bit (thumb2_insn_r
->arm_insn
, 10))
13554 if (bit (thumb2_insn_r
->arm_insn
, 9))
13555 offset_addr
= u_regval
[0] + offset_imm
;
13557 offset_addr
= u_regval
[0] - offset_imm
;
13559 address
= offset_addr
;
13562 address
= u_regval
[0];
13568 /* Store byte instructions. */
13571 record_buf_mem
[0] = 1;
13573 /* Store half word instructions. */
13576 record_buf_mem
[0] = 2;
13578 /* Store word instructions. */
13581 record_buf_mem
[0] = 4;
13585 gdb_assert_not_reached ("no decoding pattern found");
13589 record_buf_mem
[1] = address
;
13590 thumb2_insn_r
->mem_rec_count
= 1;
13591 record_buf
[0] = reg_rn
;
13592 thumb2_insn_r
->reg_rec_count
= 1;
13594 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13596 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13598 return ARM_RECORD_SUCCESS
;
13601 /* Handler for thumb2 load memory hints instructions. */
13604 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13606 uint32_t record_buf
[8];
13607 uint32_t reg_rt
, reg_rn
;
13609 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13610 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13612 if (ARM_PC_REGNUM
!= reg_rt
)
13614 record_buf
[0] = reg_rt
;
13615 record_buf
[1] = reg_rn
;
13616 record_buf
[2] = ARM_PS_REGNUM
;
13617 thumb2_insn_r
->reg_rec_count
= 3;
13619 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13621 return ARM_RECORD_SUCCESS
;
13624 return ARM_RECORD_FAILURE
;
13627 /* Handler for thumb2 load word instructions. */
13630 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13632 uint32_t record_buf
[8];
13634 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13635 record_buf
[1] = ARM_PS_REGNUM
;
13636 thumb2_insn_r
->reg_rec_count
= 2;
13638 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13640 return ARM_RECORD_SUCCESS
;
13643 /* Handler for thumb2 long multiply, long multiply accumulate, and
13644 divide instructions. */
13647 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13649 uint32_t opcode1
= 0, opcode2
= 0;
13650 uint32_t record_buf
[8];
13652 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13653 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13655 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13657 /* Handle SMULL, UMULL, SMULAL. */
13658 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13659 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13660 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13661 record_buf
[2] = ARM_PS_REGNUM
;
13662 thumb2_insn_r
->reg_rec_count
= 3;
13664 else if (1 == opcode1
|| 3 == opcode2
)
13666 /* Handle SDIV and UDIV. */
13667 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13668 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13669 record_buf
[2] = ARM_PS_REGNUM
;
13670 thumb2_insn_r
->reg_rec_count
= 3;
13673 return ARM_RECORD_FAILURE
;
13675 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13677 return ARM_RECORD_SUCCESS
;
13680 /* Record handler for thumb32 coprocessor instructions. */
13683 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13685 if (bit (thumb2_insn_r
->arm_insn
, 25))
13686 return arm_record_coproc_data_proc (thumb2_insn_r
);
13688 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13691 /* Record handler for advance SIMD structure load/store instructions. */
13694 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13696 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13697 uint32_t l_bit
, a_bit
, b_bits
;
13698 uint32_t record_buf
[128], record_buf_mem
[128];
13699 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
13700 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13703 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13704 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13705 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13706 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13707 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13708 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13709 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13710 f_elem
= 8 / f_ebytes
;
13714 ULONGEST u_regval
= 0;
13715 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13716 address
= u_regval
;
13721 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13723 if (b_bits
== 0x07)
13725 else if (b_bits
== 0x0a)
13727 else if (b_bits
== 0x06)
13729 else if (b_bits
== 0x02)
13734 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13736 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13738 record_buf_mem
[index_m
++] = f_ebytes
;
13739 record_buf_mem
[index_m
++] = address
;
13740 address
= address
+ f_ebytes
;
13741 thumb2_insn_r
->mem_rec_count
+= 1;
13746 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13748 if (b_bits
== 0x09 || b_bits
== 0x08)
13750 else if (b_bits
== 0x03)
13755 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13756 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13758 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13760 record_buf_mem
[index_m
++] = f_ebytes
;
13761 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13762 thumb2_insn_r
->mem_rec_count
+= 1;
13764 address
= address
+ (2 * f_ebytes
);
13768 else if ((b_bits
& 0x0e) == 0x04)
13770 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13772 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13774 record_buf_mem
[index_m
++] = f_ebytes
;
13775 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13776 thumb2_insn_r
->mem_rec_count
+= 1;
13778 address
= address
+ (3 * f_ebytes
);
13782 else if (!(b_bits
& 0x0e))
13784 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13786 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13788 record_buf_mem
[index_m
++] = f_ebytes
;
13789 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13790 thumb2_insn_r
->mem_rec_count
+= 1;
13792 address
= address
+ (4 * f_ebytes
);
13798 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13800 if (bft_size
== 0x00)
13802 else if (bft_size
== 0x01)
13804 else if (bft_size
== 0x02)
13810 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13811 thumb2_insn_r
->mem_rec_count
= 1;
13813 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13814 thumb2_insn_r
->mem_rec_count
= 2;
13816 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13817 thumb2_insn_r
->mem_rec_count
= 3;
13819 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13820 thumb2_insn_r
->mem_rec_count
= 4;
13822 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13824 record_buf_mem
[index_m
] = f_ebytes
;
13825 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13834 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13835 thumb2_insn_r
->reg_rec_count
= 1;
13837 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13838 thumb2_insn_r
->reg_rec_count
= 2;
13840 else if ((b_bits
& 0x0e) == 0x04)
13841 thumb2_insn_r
->reg_rec_count
= 3;
13843 else if (!(b_bits
& 0x0e))
13844 thumb2_insn_r
->reg_rec_count
= 4;
13849 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13850 thumb2_insn_r
->reg_rec_count
= 1;
13852 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13853 thumb2_insn_r
->reg_rec_count
= 2;
13855 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13856 thumb2_insn_r
->reg_rec_count
= 3;
13858 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13859 thumb2_insn_r
->reg_rec_count
= 4;
13861 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13862 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13866 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13868 record_buf
[index_r
] = reg_rn
;
13869 thumb2_insn_r
->reg_rec_count
+= 1;
13872 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13874 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13879 /* Decodes thumb2 instruction type and invokes its record handler. */
13881 static unsigned int
13882 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13884 uint32_t op
, op1
, op2
;
13886 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13887 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13888 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13892 if (!(op2
& 0x64 ))
13894 /* Load/store multiple instruction. */
13895 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13897 else if ((op2
& 0x64) == 0x4)
13899 /* Load/store (dual/exclusive) and table branch instruction. */
13900 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13902 else if ((op2
& 0x60) == 0x20)
13904 /* Data-processing (shifted register). */
13905 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13907 else if (op2
& 0x40)
13909 /* Co-processor instructions. */
13910 return thumb2_record_coproc_insn (thumb2_insn_r
);
13913 else if (op1
== 0x02)
13917 /* Branches and miscellaneous control instructions. */
13918 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13920 else if (op2
& 0x20)
13922 /* Data-processing (plain binary immediate) instruction. */
13923 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13927 /* Data-processing (modified immediate). */
13928 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13931 else if (op1
== 0x03)
13933 if (!(op2
& 0x71 ))
13935 /* Store single data item. */
13936 return thumb2_record_str_single_data (thumb2_insn_r
);
13938 else if (!((op2
& 0x71) ^ 0x10))
13940 /* Advanced SIMD or structure load/store instructions. */
13941 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13943 else if (!((op2
& 0x67) ^ 0x01))
13945 /* Load byte, memory hints instruction. */
13946 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13948 else if (!((op2
& 0x67) ^ 0x03))
13950 /* Load halfword, memory hints instruction. */
13951 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13953 else if (!((op2
& 0x67) ^ 0x05))
13955 /* Load word instruction. */
13956 return thumb2_record_ld_word (thumb2_insn_r
);
13958 else if (!((op2
& 0x70) ^ 0x20))
13960 /* Data-processing (register) instruction. */
13961 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13963 else if (!((op2
& 0x78) ^ 0x30))
13965 /* Multiply, multiply accumulate, abs diff instruction. */
13966 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13968 else if (!((op2
& 0x78) ^ 0x38))
13970 /* Long multiply, long multiply accumulate, and divide. */
13971 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13973 else if (op2
& 0x40)
13975 /* Co-processor instructions. */
13976 return thumb2_record_coproc_insn (thumb2_insn_r
);
13984 /* Abstract memory reader. */
13986 class abstract_memory_reader
13989 /* Read LEN bytes of target memory at address MEMADDR, placing the
13990 results in GDB's memory at BUF. Return true on success. */
13992 virtual bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) = 0;
13995 /* Instruction reader from real target. */
13997 class instruction_reader
: public abstract_memory_reader
14000 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
14002 if (target_read_memory (memaddr
, buf
, len
))
14011 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
14012 and positive val on failure. */
14015 extract_arm_insn (abstract_memory_reader
& reader
,
14016 insn_decode_record
*insn_record
, uint32_t insn_size
)
14018 gdb_byte buf
[insn_size
];
14020 memset (&buf
[0], 0, insn_size
);
14022 if (!reader
.read (insn_record
->this_addr
, buf
, insn_size
))
14024 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
14026 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
14030 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
14032 /* Decode arm/thumb insn depending on condition cods and opcodes; and
14036 decode_insn (abstract_memory_reader
&reader
, insn_decode_record
*arm_record
,
14037 record_type_t record_type
, uint32_t insn_size
)
14040 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
14042 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
14044 arm_record_data_proc_misc_ld_str
, /* 000. */
14045 arm_record_data_proc_imm
, /* 001. */
14046 arm_record_ld_st_imm_offset
, /* 010. */
14047 arm_record_ld_st_reg_offset
, /* 011. */
14048 arm_record_ld_st_multiple
, /* 100. */
14049 arm_record_b_bl
, /* 101. */
14050 arm_record_asimd_vfp_coproc
, /* 110. */
14051 arm_record_coproc_data_proc
/* 111. */
14054 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
14056 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
14058 thumb_record_shift_add_sub
, /* 000. */
14059 thumb_record_add_sub_cmp_mov
, /* 001. */
14060 thumb_record_ld_st_reg_offset
, /* 010. */
14061 thumb_record_ld_st_imm_offset
, /* 011. */
14062 thumb_record_ld_st_stack
, /* 100. */
14063 thumb_record_misc
, /* 101. */
14064 thumb_record_ldm_stm_swi
, /* 110. */
14065 thumb_record_branch
/* 111. */
14068 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
14069 uint32_t insn_id
= 0;
14071 if (extract_arm_insn (reader
, arm_record
, insn_size
))
14075 gdb_printf (gdb_stdlog
,
14076 _("Process record: error reading memory at "
14077 "addr %s len = %d.\n"),
14078 paddress (arm_record
->gdbarch
,
14079 arm_record
->this_addr
), insn_size
);
14083 else if (ARM_RECORD
== record_type
)
14085 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
14086 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
14088 if (arm_record
->cond
== 0xf)
14089 ret
= arm_record_extension_space (arm_record
);
14092 /* If this insn has fallen into extension space
14093 then we need not decode it anymore. */
14094 ret
= arm_handle_insn
[insn_id
] (arm_record
);
14096 if (ret
!= ARM_RECORD_SUCCESS
)
14098 arm_record_unsupported_insn (arm_record
);
14102 else if (THUMB_RECORD
== record_type
)
14104 /* As thumb does not have condition codes, we set negative. */
14105 arm_record
->cond
= -1;
14106 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
14107 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
14108 if (ret
!= ARM_RECORD_SUCCESS
)
14110 arm_record_unsupported_insn (arm_record
);
14114 else if (THUMB2_RECORD
== record_type
)
14116 /* As thumb does not have condition codes, we set negative. */
14117 arm_record
->cond
= -1;
14119 /* Swap first half of 32bit thumb instruction with second half. */
14120 arm_record
->arm_insn
14121 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
14123 ret
= thumb2_record_decode_insn_handler (arm_record
);
14125 if (ret
!= ARM_RECORD_SUCCESS
)
14127 arm_record_unsupported_insn (arm_record
);
14133 /* Throw assertion. */
14134 gdb_assert_not_reached ("not a valid instruction, could not decode");
14141 namespace selftests
{
14143 /* Provide both 16-bit and 32-bit thumb instructions. */
14145 class instruction_reader_thumb
: public abstract_memory_reader
14148 template<size_t SIZE
>
14149 instruction_reader_thumb (enum bfd_endian endian
,
14150 const uint16_t (&insns
)[SIZE
])
14151 : m_endian (endian
), m_insns (insns
), m_insns_size (SIZE
)
14154 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
14156 SELF_CHECK (len
== 4 || len
== 2);
14157 SELF_CHECK (memaddr
% 2 == 0);
14158 SELF_CHECK ((memaddr
/ 2) < m_insns_size
);
14160 store_unsigned_integer (buf
, 2, m_endian
, m_insns
[memaddr
/ 2]);
14163 store_unsigned_integer (&buf
[2], 2, m_endian
,
14164 m_insns
[memaddr
/ 2 + 1]);
14170 enum bfd_endian m_endian
;
14171 const uint16_t *m_insns
;
14172 size_t m_insns_size
;
14176 arm_record_test (void)
14178 struct gdbarch_info info
;
14179 info
.bfd_arch_info
= bfd_scan_arch ("arm");
14181 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
14183 SELF_CHECK (gdbarch
!= NULL
);
14185 /* 16-bit Thumb instructions. */
14187 insn_decode_record arm_record
;
14189 memset (&arm_record
, 0, sizeof (insn_decode_record
));
14190 arm_record
.gdbarch
= gdbarch
;
14192 static const uint16_t insns
[] = {
14193 /* db b2 uxtb r3, r3 */
14195 /* cd 58 ldr r5, [r1, r3] */
14199 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
14200 instruction_reader_thumb
reader (endian
, insns
);
14201 int ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
14202 THUMB_INSN_SIZE_BYTES
);
14204 SELF_CHECK (ret
== 0);
14205 SELF_CHECK (arm_record
.mem_rec_count
== 0);
14206 SELF_CHECK (arm_record
.reg_rec_count
== 1);
14207 SELF_CHECK (arm_record
.arm_regs
[0] == 3);
14209 arm_record
.this_addr
+= 2;
14210 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
14211 THUMB_INSN_SIZE_BYTES
);
14213 SELF_CHECK (ret
== 0);
14214 SELF_CHECK (arm_record
.mem_rec_count
== 0);
14215 SELF_CHECK (arm_record
.reg_rec_count
== 1);
14216 SELF_CHECK (arm_record
.arm_regs
[0] == 5);
14219 /* 32-bit Thumb-2 instructions. */
14221 insn_decode_record arm_record
;
14223 memset (&arm_record
, 0, sizeof (insn_decode_record
));
14224 arm_record
.gdbarch
= gdbarch
;
14226 static const uint16_t insns
[] = {
14227 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
14231 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
14232 instruction_reader_thumb
reader (endian
, insns
);
14233 int ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
14234 THUMB2_INSN_SIZE_BYTES
);
14236 SELF_CHECK (ret
== 0);
14237 SELF_CHECK (arm_record
.mem_rec_count
== 0);
14238 SELF_CHECK (arm_record
.reg_rec_count
== 1);
14239 SELF_CHECK (arm_record
.arm_regs
[0] == 7);
14243 /* Instruction reader from manually cooked instruction sequences. */
14245 class test_arm_instruction_reader
: public arm_instruction_reader
14248 explicit test_arm_instruction_reader (gdb::array_view
<const uint32_t> insns
)
14252 uint32_t read (CORE_ADDR memaddr
, enum bfd_endian byte_order
) const override
14254 SELF_CHECK (memaddr
% 4 == 0);
14255 SELF_CHECK (memaddr
/ 4 < m_insns
.size ());
14257 return m_insns
[memaddr
/ 4];
14261 const gdb::array_view
<const uint32_t> m_insns
;
14265 arm_analyze_prologue_test ()
14267 for (bfd_endian endianness
: {BFD_ENDIAN_LITTLE
, BFD_ENDIAN_BIG
})
14269 struct gdbarch_info info
;
14270 info
.byte_order
= endianness
;
14271 info
.byte_order_for_code
= endianness
;
14272 info
.bfd_arch_info
= bfd_scan_arch ("arm");
14274 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
14276 SELF_CHECK (gdbarch
!= NULL
);
14278 /* The "sub" instruction contains an immediate value rotate count of 0,
14279 which resulted in a 32-bit shift of a 32-bit value, caught by
14281 const uint32_t insns
[] = {
14282 0xe92d4ff0, /* push {r4, r5, r6, r7, r8, r9, sl, fp, lr} */
14283 0xe1a05000, /* mov r5, r0 */
14284 0xe5903020, /* ldr r3, [r0, #32] */
14285 0xe24dd044, /* sub sp, sp, #68 ; 0x44 */
14288 test_arm_instruction_reader
mem_reader (insns
);
14289 arm_prologue_cache cache
;
14290 arm_cache_init (&cache
, gdbarch
);
14292 arm_analyze_prologue (gdbarch
, 0, sizeof (insns
) - 1, &cache
, mem_reader
);
14296 } // namespace selftests
14297 #endif /* GDB_SELF_TEST */
14299 /* Cleans up local record registers and memory allocations. */
14302 deallocate_reg_mem (insn_decode_record
*record
)
14304 xfree (record
->arm_regs
);
14305 xfree (record
->arm_mems
);
14309 /* Parse the current instruction and record the values of the registers and
14310 memory that will be changed in current instruction to record_arch_list".
14311 Return -1 if something is wrong. */
14314 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
14315 CORE_ADDR insn_addr
)
14318 uint32_t no_of_rec
= 0;
14319 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
14320 ULONGEST t_bit
= 0, insn_id
= 0;
14322 ULONGEST u_regval
= 0;
14324 insn_decode_record arm_record
;
14326 memset (&arm_record
, 0, sizeof (insn_decode_record
));
14327 arm_record
.regcache
= regcache
;
14328 arm_record
.this_addr
= insn_addr
;
14329 arm_record
.gdbarch
= gdbarch
;
14332 if (record_debug
> 1)
14334 gdb_printf (gdb_stdlog
, "Process record: arm_process_record "
14336 paddress (gdbarch
, arm_record
.this_addr
));
14339 instruction_reader reader
;
14340 if (extract_arm_insn (reader
, &arm_record
, 2))
14344 gdb_printf (gdb_stdlog
,
14345 _("Process record: error reading memory at "
14346 "addr %s len = %d.\n"),
14347 paddress (arm_record
.gdbarch
,
14348 arm_record
.this_addr
), 2);
14353 /* Check the insn, whether it is thumb or arm one. */
14355 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
14356 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
14359 if (!(u_regval
& t_bit
))
14361 /* We are decoding arm insn. */
14362 ret
= decode_insn (reader
, &arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
14366 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
14367 /* is it thumb2 insn? */
14368 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
14370 ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
14371 THUMB2_INSN_SIZE_BYTES
);
14375 /* We are decoding thumb insn. */
14376 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
14377 THUMB_INSN_SIZE_BYTES
);
14383 /* Record registers. */
14384 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
14385 if (arm_record
.arm_regs
)
14387 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
14389 if (record_full_arch_list_add_reg
14390 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
14394 /* Record memories. */
14395 if (arm_record
.arm_mems
)
14397 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
14399 if (record_full_arch_list_add_mem
14400 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
14401 arm_record
.arm_mems
[no_of_rec
].len
))
14406 if (record_full_arch_list_add_end ())
14411 deallocate_reg_mem (&arm_record
);
14416 /* See arm-tdep.h. */
14418 const target_desc
*
14419 arm_read_description (arm_fp_type fp_type
)
14421 struct target_desc
*tdesc
= tdesc_arm_list
[fp_type
];
14423 if (tdesc
== nullptr)
14425 tdesc
= arm_create_target_description (fp_type
);
14426 tdesc_arm_list
[fp_type
] = tdesc
;
14432 /* See arm-tdep.h. */
14434 const target_desc
*
14435 arm_read_mprofile_description (arm_m_profile_type m_type
)
14437 struct target_desc
*tdesc
= tdesc_arm_mprofile_list
[m_type
];
14439 if (tdesc
== nullptr)
14441 tdesc
= arm_create_mprofile_target_description (m_type
);
14442 tdesc_arm_mprofile_list
[m_type
] = tdesc
;