1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data
*arm_objfile_data_key
;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
80 DEF_VEC_O(arm_mapping_symbol_s
);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s
) **section_maps
;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element
*setarmcmdlist
= NULL
;
89 static struct cmd_list_element
*showarmcmdlist
= NULL
;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings
[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
105 static const char *current_fp_model
= "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
118 static const char *arm_abi_string
= "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings
[] =
128 static const char *arm_fallback_mode_string
= "auto";
129 static const char *arm_force_mode_string
= "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options
;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases
[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names
[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles
;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style
;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element
*);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat
*, const void *,
208 static void convert_to_extended (const struct floatformat
*, void *,
211 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
212 struct regcache
*regcache
,
213 int regnum
, gdb_byte
*buf
);
214 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
215 struct regcache
*regcache
,
216 int regnum
, const gdb_byte
*buf
);
218 struct arm_prologue_cache
220 /* The stack pointer at the time this frame was created; i.e. the
221 caller's stack pointer when this function was called. It is used
222 to identify this frame. */
225 /* The frame base for this frame is just prev_sp - frame size.
226 FRAMESIZE is the distance from the frame pointer to the
227 initial stack pointer. */
231 /* The register used to hold the frame pointer for this frame. */
234 /* Saved register offsets. */
235 struct trad_frame_saved_reg
*saved_regs
;
238 /* Architecture version for displaced stepping. This effects the behaviour of
239 certain instructions, and really should not be hard-wired. */
241 #define DISPLACED_STEPPING_ARCH_VERSION 5
243 /* Addresses for calling Thumb functions have the bit 0 set.
244 Here are some macros to test, set, or clear bit 0 of addresses. */
245 #define IS_THUMB_ADDR(addr) ((addr) & 1)
246 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
247 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
249 /* Set to true if the 32-bit mode is in use. */
253 /* Determine if FRAME is executing in Thumb mode. */
256 arm_frame_is_thumb (struct frame_info
*frame
)
260 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
261 directly (from a signal frame or dummy frame) or by interpreting
262 the saved LR (from a prologue or DWARF frame). So consult it and
263 trust the unwinders. */
264 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
266 return (cpsr
& CPSR_T
) != 0;
269 /* Callback for VEC_lower_bound. */
272 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
273 const struct arm_mapping_symbol
*rhs
)
275 return lhs
->value
< rhs
->value
;
278 /* Determine if the program counter specified in MEMADDR is in a Thumb
279 function. This function should be called for addresses unrelated to
280 any executing frame; otherwise, prefer arm_frame_is_thumb. */
283 arm_pc_is_thumb (CORE_ADDR memaddr
)
285 struct obj_section
*sec
;
286 struct minimal_symbol
*sym
;
288 /* If bit 0 of the address is set, assume this is a Thumb address. */
289 if (IS_THUMB_ADDR (memaddr
))
292 /* If the user wants to override the symbol table, let him. */
293 if (strcmp (arm_force_mode_string
, "arm") == 0)
295 if (strcmp (arm_force_mode_string
, "thumb") == 0)
298 /* If there are mapping symbols, consult them. */
299 sec
= find_pc_section (memaddr
);
302 struct arm_per_objfile
*data
;
303 VEC(arm_mapping_symbol_s
) *map
;
304 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
308 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
311 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
312 if (!VEC_empty (arm_mapping_symbol_s
, map
))
314 struct arm_mapping_symbol
*map_sym
;
316 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
317 arm_compare_mapping_symbols
);
319 /* VEC_lower_bound finds the earliest ordered insertion
320 point. If the following symbol starts at this exact
321 address, we use that; otherwise, the preceding
322 mapping symbol covers this address. */
323 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
325 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
326 if (map_sym
->value
== map_key
.value
)
327 return map_sym
->type
== 't';
332 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
333 return map_sym
->type
== 't';
339 /* Thumb functions have a "special" bit set in minimal symbols. */
340 sym
= lookup_minimal_symbol_by_pc (memaddr
);
342 return (MSYMBOL_IS_SPECIAL (sym
));
344 /* If the user wants to override the fallback mode, let them. */
345 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
347 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
350 /* If we couldn't find any symbol, but we're talking to a running
351 target, then trust the current value of $cpsr. This lets
352 "display/i $pc" always show the correct mode (though if there is
353 a symbol table we will not reach here, so it still may not be
354 displayed in the mode it will be executed). */
355 if (target_has_registers
)
356 return arm_frame_is_thumb (get_current_frame ());
358 /* Otherwise we're out of luck; we assume ARM. */
362 /* Remove useless bits from addresses in a running program. */
364 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
367 return UNMAKE_THUMB_ADDR (val
);
369 return (val
& 0x03fffffc);
372 /* When reading symbols, we need to zap the low bit of the address,
373 which may be set to 1 for Thumb functions. */
375 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
380 /* Analyze a Thumb prologue, looking for a recognizable stack frame
381 and frame pointer. Scan until we encounter a store that could
382 clobber the stack frame unexpectedly, or an unknown instruction. */
385 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
386 CORE_ADDR start
, CORE_ADDR limit
,
387 struct arm_prologue_cache
*cache
)
389 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
392 struct pv_area
*stack
;
393 struct cleanup
*back_to
;
396 for (i
= 0; i
< 16; i
++)
397 regs
[i
] = pv_register (i
, 0);
398 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
399 back_to
= make_cleanup_free_pv_area (stack
);
401 while (start
< limit
)
405 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
407 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
412 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
415 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
416 whether to save LR (R14). */
417 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
419 /* Calculate offsets of saved R0-R7 and LR. */
420 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
421 if (mask
& (1 << regno
))
423 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
425 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
428 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
431 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
432 if (insn
& 0x80) /* Check for SUB. */
433 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
436 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
439 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
440 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
442 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
444 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
445 int src_reg
= (insn
& 0x78) >> 3;
446 regs
[dst_reg
] = regs
[src_reg
];
448 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
450 /* Handle stores to the stack. Normally pushes are used,
451 but with GCC -mtpcs-frame, there may be other stores
452 in the prologue to create the frame. */
453 int regno
= (insn
>> 8) & 0x7;
456 offset
= (insn
& 0xff) << 2;
457 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
459 if (pv_area_store_would_trash (stack
, addr
))
462 pv_area_store (stack
, addr
, 4, regs
[regno
]);
466 /* We don't know what this instruction is. We're finished
467 scanning. NOTE: Recognizing more safe-to-ignore
468 instructions here will improve support for optimized
478 do_cleanups (back_to
);
482 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
484 /* Frame pointer is fp. Frame size is constant. */
485 cache
->framereg
= ARM_FP_REGNUM
;
486 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
488 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
490 /* Frame pointer is r7. Frame size is constant. */
491 cache
->framereg
= THUMB_FP_REGNUM
;
492 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
494 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
496 /* Try the stack pointer... this is a bit desperate. */
497 cache
->framereg
= ARM_SP_REGNUM
;
498 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
502 /* We're just out of luck. We don't know where the frame is. */
503 cache
->framereg
= -1;
504 cache
->framesize
= 0;
507 for (i
= 0; i
< 16; i
++)
508 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
509 cache
->saved_regs
[i
].addr
= offset
;
511 do_cleanups (back_to
);
515 /* Advance the PC across any function entry prologue instructions to
516 reach some "real" code.
518 The APCS (ARM Procedure Call Standard) defines the following
522 [stmfd sp!, {a1,a2,a3,a4}]
523 stmfd sp!, {...,fp,ip,lr,pc}
524 [stfe f7, [sp, #-12]!]
525 [stfe f6, [sp, #-12]!]
526 [stfe f5, [sp, #-12]!]
527 [stfe f4, [sp, #-12]!]
528 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
531 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
533 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
536 CORE_ADDR func_addr
, limit_pc
;
537 struct symtab_and_line sal
;
539 /* If we're in a dummy frame, don't even try to skip the prologue. */
540 if (deprecated_pc_in_call_dummy (gdbarch
, pc
))
543 /* See if we can determine the end of the prologue via the symbol table.
544 If so, then return either PC, or the PC after the prologue, whichever
546 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
548 CORE_ADDR post_prologue_pc
549 = skip_prologue_using_sal (gdbarch
, func_addr
);
550 if (post_prologue_pc
!= 0)
551 return max (pc
, post_prologue_pc
);
554 /* Can't determine prologue from the symbol table, need to examine
557 /* Find an upper limit on the function prologue using the debug
558 information. If the debug information could not be used to provide
559 that bound, then use an arbitrary large number as the upper bound. */
560 /* Like arm_scan_prologue, stop no later than pc + 64. */
561 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
563 limit_pc
= pc
+ 64; /* Magic. */
566 /* Check if this is Thumb code. */
567 if (arm_pc_is_thumb (pc
))
568 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
570 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
572 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
574 /* "mov ip, sp" is no longer a required part of the prologue. */
575 if (inst
== 0xe1a0c00d) /* mov ip, sp */
578 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
581 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
584 /* Some prologues begin with "str lr, [sp, #-4]!". */
585 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
588 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
591 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
594 /* Any insns after this point may float into the code, if it makes
595 for better instruction scheduling, so we skip them only if we
596 find them, but still consider the function to be frame-ful. */
598 /* We may have either one sfmfd instruction here, or several stfe
599 insns, depending on the version of floating point code we
601 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
604 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
607 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
610 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
613 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
614 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
615 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
618 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
619 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
620 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
623 /* Un-recognized instruction; stop scanning. */
627 return skip_pc
; /* End of prologue */
631 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
632 This function decodes a Thumb function prologue to determine:
633 1) the size of the stack frame
634 2) which registers are saved on it
635 3) the offsets of saved regs
636 4) the offset from the stack pointer to the frame pointer
638 A typical Thumb function prologue would create this stack frame
639 (offsets relative to FP)
640 old SP -> 24 stack parameters
643 R7 -> 0 local variables (16 bytes)
644 SP -> -12 additional stack space (12 bytes)
645 The frame size would thus be 36 bytes, and the frame offset would be
646 12 bytes. The frame register is R7.
648 The comments for thumb_skip_prolog() describe the algorithm we use
649 to detect the end of the prolog. */
653 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
654 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
656 CORE_ADDR prologue_start
;
657 CORE_ADDR prologue_end
;
658 CORE_ADDR current_pc
;
660 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
663 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
665 if (sal
.line
== 0) /* no line info, use current PC */
666 prologue_end
= prev_pc
;
667 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
668 prologue_end
= sal
.end
; /* (probably means no prologue) */
671 /* We're in the boondocks: we have no idea where the start of the
675 prologue_end
= min (prologue_end
, prev_pc
);
677 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
680 /* This function decodes an ARM function prologue to determine:
681 1) the size of the stack frame
682 2) which registers are saved on it
683 3) the offsets of saved regs
684 4) the offset from the stack pointer to the frame pointer
685 This information is stored in the "extra" fields of the frame_info.
687 There are two basic forms for the ARM prologue. The fixed argument
688 function call will look like:
691 stmfd sp!, {fp, ip, lr, pc}
695 Which would create this stack frame (offsets relative to FP):
696 IP -> 4 (caller's stack)
697 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
698 -4 LR (return address in caller)
699 -8 IP (copy of caller's SP)
701 SP -> -28 Local variables
703 The frame size would thus be 32 bytes, and the frame offset would be
704 28 bytes. The stmfd call can also save any of the vN registers it
705 plans to use, which increases the frame size accordingly.
707 Note: The stored PC is 8 off of the STMFD instruction that stored it
708 because the ARM Store instructions always store PC + 8 when you read
711 A variable argument function call will look like:
714 stmfd sp!, {a1, a2, a3, a4}
715 stmfd sp!, {fp, ip, lr, pc}
718 Which would create this stack frame (offsets relative to FP):
719 IP -> 20 (caller's stack)
724 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
725 -4 LR (return address in caller)
726 -8 IP (copy of caller's SP)
728 SP -> -28 Local variables
730 The frame size would thus be 48 bytes, and the frame offset would be
733 There is another potential complication, which is that the optimizer
734 will try to separate the store of fp in the "stmfd" instruction from
735 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
736 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
738 Also, note, the original version of the ARM toolchain claimed that there
741 instruction at the end of the prologue. I have never seen GCC produce
742 this, and the ARM docs don't mention it. We still test for it below in
748 arm_scan_prologue (struct frame_info
*this_frame
,
749 struct arm_prologue_cache
*cache
)
751 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
752 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
753 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
755 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
756 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
757 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
758 pv_t regs
[ARM_FPS_REGNUM
];
759 struct pv_area
*stack
;
760 struct cleanup
*back_to
;
763 /* Assume there is no frame until proven otherwise. */
764 cache
->framereg
= ARM_SP_REGNUM
;
765 cache
->framesize
= 0;
767 /* Check for Thumb prologue. */
768 if (arm_frame_is_thumb (this_frame
))
770 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
774 /* Find the function prologue. If we can't find the function in
775 the symbol table, peek in the stack frame to find the PC. */
776 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
779 /* One way to find the end of the prologue (which works well
780 for unoptimized code) is to do the following:
782 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
785 prologue_end = prev_pc;
786 else if (sal.end < prologue_end)
787 prologue_end = sal.end;
789 This mechanism is very accurate so long as the optimizer
790 doesn't move any instructions from the function body into the
791 prologue. If this happens, sal.end will be the last
792 instruction in the first hunk of prologue code just before
793 the first instruction that the scheduler has moved from
794 the body to the prologue.
796 In order to make sure that we scan all of the prologue
797 instructions, we use a slightly less accurate mechanism which
798 may scan more than necessary. To help compensate for this
799 lack of accuracy, the prologue scanning loop below contains
800 several clauses which'll cause the loop to terminate early if
801 an implausible prologue instruction is encountered.
807 is a suitable endpoint since it accounts for the largest
808 possible prologue plus up to five instructions inserted by
811 if (prologue_end
> prologue_start
+ 64)
813 prologue_end
= prologue_start
+ 64; /* See above. */
818 /* We have no symbol information. Our only option is to assume this
819 function has a standard stack frame and the normal frame register.
820 Then, we can find the value of our frame pointer on entrance to
821 the callee (or at the present moment if this is the innermost frame).
822 The value stored there should be the address of the stmfd + 8. */
824 LONGEST return_value
;
826 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
827 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
831 prologue_start
= gdbarch_addr_bits_remove
832 (gdbarch
, return_value
) - 8;
833 prologue_end
= prologue_start
+ 64; /* See above. */
837 if (prev_pc
< prologue_end
)
838 prologue_end
= prev_pc
;
840 /* Now search the prologue looking for instructions that set up the
841 frame pointer, adjust the stack pointer, and save registers.
843 Be careful, however, and if it doesn't look like a prologue,
844 don't try to scan it. If, for instance, a frameless function
845 begins with stmfd sp!, then we will tell ourselves there is
846 a frame, which will confuse stack traceback, as well as "finish"
847 and other operations that rely on a knowledge of the stack
850 In the APCS, the prologue should start with "mov ip, sp" so
851 if we don't see this as the first insn, we will stop.
853 [Note: This doesn't seem to be true any longer, so it's now an
854 optional part of the prologue. - Kevin Buettner, 2001-11-20]
856 [Note further: The "mov ip,sp" only seems to be missing in
857 frameless functions at optimization level "-O2" or above,
858 in which case it is often (but not always) replaced by
859 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
861 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
862 regs
[regno
] = pv_register (regno
, 0);
863 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
864 back_to
= make_cleanup_free_pv_area (stack
);
866 for (current_pc
= prologue_start
;
867 current_pc
< prologue_end
;
871 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
873 if (insn
== 0xe1a0c00d) /* mov ip, sp */
875 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
878 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
880 unsigned imm
= insn
& 0xff; /* immediate value */
881 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
882 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
883 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
886 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
888 unsigned imm
= insn
& 0xff; /* immediate value */
889 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
890 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
891 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
894 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
896 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
898 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
899 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
902 else if ((insn
& 0xffff0000) == 0xe92d0000)
903 /* stmfd sp!, {..., fp, ip, lr, pc}
905 stmfd sp!, {a1, a2, a3, a4} */
907 int mask
= insn
& 0xffff;
909 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
912 /* Calculate offsets of saved registers. */
913 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
914 if (mask
& (1 << regno
))
916 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
917 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
920 else if ((insn
& 0xffffc000) == 0xe54b0000 /* strb rx,[r11,#-n] */
921 || (insn
& 0xffffc0f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
922 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
924 /* No need to add this to saved_regs -- it's just an arg reg. */
927 else if ((insn
& 0xffffc000) == 0xe5cd0000 /* strb rx,[sp,#n] */
928 || (insn
& 0xffffc0f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
929 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
931 /* No need to add this to saved_regs -- it's just an arg reg. */
934 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
936 unsigned imm
= insn
& 0xff; /* immediate value */
937 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
938 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
939 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
941 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
943 unsigned imm
= insn
& 0xff; /* immediate value */
944 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
945 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
946 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
948 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
949 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
951 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
954 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
955 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
956 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
958 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
959 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
962 unsigned int fp_start_reg
, fp_bound_reg
;
964 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
967 if ((insn
& 0x800) == 0x800) /* N0 is set */
969 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
976 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
982 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
983 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
984 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
986 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
987 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
988 regs
[fp_start_reg
++]);
991 else if ((insn
& 0xf0000000) != 0xe0000000)
992 break; /* Condition not true, exit early */
993 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
994 break; /* Don't scan past a block load */
996 /* The optimizer might shove anything into the prologue,
997 so we just skip what we don't recognize. */
1001 /* The frame size is just the distance from the frame register
1002 to the original stack pointer. */
1003 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1005 /* Frame pointer is fp. */
1006 cache
->framereg
= ARM_FP_REGNUM
;
1007 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1009 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1011 /* Try the stack pointer... this is a bit desperate. */
1012 cache
->framereg
= ARM_SP_REGNUM
;
1013 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1017 /* We're just out of luck. We don't know where the frame is. */
1018 cache
->framereg
= -1;
1019 cache
->framesize
= 0;
1022 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1023 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1024 cache
->saved_regs
[regno
].addr
= offset
;
1026 do_cleanups (back_to
);
1029 static struct arm_prologue_cache
*
1030 arm_make_prologue_cache (struct frame_info
*this_frame
)
1033 struct arm_prologue_cache
*cache
;
1034 CORE_ADDR unwound_fp
;
1036 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1037 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1039 arm_scan_prologue (this_frame
, cache
);
1041 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1042 if (unwound_fp
== 0)
1045 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1047 /* Calculate actual addresses of saved registers using offsets
1048 determined by arm_scan_prologue. */
1049 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1050 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1051 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1056 /* Our frame ID for a normal frame is the current function's starting PC
1057 and the caller's SP when we were called. */
1060 arm_prologue_this_id (struct frame_info
*this_frame
,
1062 struct frame_id
*this_id
)
1064 struct arm_prologue_cache
*cache
;
1068 if (*this_cache
== NULL
)
1069 *this_cache
= arm_make_prologue_cache (this_frame
);
1070 cache
= *this_cache
;
1072 /* This is meant to halt the backtrace at "_start". */
1073 pc
= get_frame_pc (this_frame
);
1074 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1077 /* If we've hit a wall, stop. */
1078 if (cache
->prev_sp
== 0)
1081 func
= get_frame_func (this_frame
);
1082 id
= frame_id_build (cache
->prev_sp
, func
);
1086 static struct value
*
1087 arm_prologue_prev_register (struct frame_info
*this_frame
,
1091 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1092 struct arm_prologue_cache
*cache
;
1094 if (*this_cache
== NULL
)
1095 *this_cache
= arm_make_prologue_cache (this_frame
);
1096 cache
= *this_cache
;
1098 /* If we are asked to unwind the PC, then we need to return the LR
1099 instead. The prologue may save PC, but it will point into this
1100 frame's prologue, not the next frame's resume location. Also
1101 strip the saved T bit. A valid LR may have the low bit set, but
1102 a valid PC never does. */
1103 if (prev_regnum
== ARM_PC_REGNUM
)
1107 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1108 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1109 arm_addr_bits_remove (gdbarch
, lr
));
1112 /* SP is generally not saved to the stack, but this frame is
1113 identified by the next frame's stack pointer at the time of the call.
1114 The value was already reconstructed into PREV_SP. */
1115 if (prev_regnum
== ARM_SP_REGNUM
)
1116 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1118 /* The CPSR may have been changed by the call instruction and by the
1119 called function. The only bit we can reconstruct is the T bit,
1120 by checking the low bit of LR as of the call. This is a reliable
1121 indicator of Thumb-ness except for some ARM v4T pre-interworking
1122 Thumb code, which could get away with a clear low bit as long as
1123 the called function did not use bx. Guess that all other
1124 bits are unchanged; the condition flags are presumably lost,
1125 but the processor status is likely valid. */
1126 if (prev_regnum
== ARM_PS_REGNUM
)
1130 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1131 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1132 if (IS_THUMB_ADDR (lr
))
1136 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1139 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1143 struct frame_unwind arm_prologue_unwind
= {
1145 arm_prologue_this_id
,
1146 arm_prologue_prev_register
,
1148 default_frame_sniffer
1151 static struct arm_prologue_cache
*
1152 arm_make_stub_cache (struct frame_info
*this_frame
)
1155 struct arm_prologue_cache
*cache
;
1156 CORE_ADDR unwound_fp
;
1158 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1159 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1161 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1166 /* Our frame ID for a stub frame is the current SP and LR. */
1169 arm_stub_this_id (struct frame_info
*this_frame
,
1171 struct frame_id
*this_id
)
1173 struct arm_prologue_cache
*cache
;
1175 if (*this_cache
== NULL
)
1176 *this_cache
= arm_make_stub_cache (this_frame
);
1177 cache
= *this_cache
;
1179 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1183 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1184 struct frame_info
*this_frame
,
1185 void **this_prologue_cache
)
1187 CORE_ADDR addr_in_block
;
1190 addr_in_block
= get_frame_address_in_block (this_frame
);
1191 if (in_plt_section (addr_in_block
, NULL
)
1192 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1198 struct frame_unwind arm_stub_unwind
= {
1201 arm_prologue_prev_register
,
1203 arm_stub_unwind_sniffer
1207 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1209 struct arm_prologue_cache
*cache
;
1211 if (*this_cache
== NULL
)
1212 *this_cache
= arm_make_prologue_cache (this_frame
);
1213 cache
= *this_cache
;
1215 return cache
->prev_sp
- cache
->framesize
;
1218 struct frame_base arm_normal_base
= {
1219 &arm_prologue_unwind
,
1220 arm_normal_frame_base
,
1221 arm_normal_frame_base
,
1222 arm_normal_frame_base
1225 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1226 dummy frame. The frame ID's base needs to match the TOS value
1227 saved by save_dummy_frame_tos() and returned from
1228 arm_push_dummy_call, and the PC needs to match the dummy frame's
1231 static struct frame_id
1232 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1234 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1235 get_frame_pc (this_frame
));
1238 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1239 be used to construct the previous frame's ID, after looking up the
1240 containing function). */
1243 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1246 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1247 return arm_addr_bits_remove (gdbarch
, pc
);
1251 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1253 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1256 static struct value
*
1257 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1260 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1266 /* The PC is normally copied from the return column, which
1267 describes saves of LR. However, that version may have an
1268 extra bit set to indicate Thumb state. The bit is not
1270 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1271 return frame_unwind_got_constant (this_frame
, regnum
,
1272 arm_addr_bits_remove (gdbarch
, lr
));
1275 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1276 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1277 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1278 if (IS_THUMB_ADDR (lr
))
1282 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1285 internal_error (__FILE__
, __LINE__
,
1286 _("Unexpected register %d"), regnum
);
1291 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1292 struct dwarf2_frame_state_reg
*reg
,
1293 struct frame_info
*this_frame
)
1299 reg
->how
= DWARF2_FRAME_REG_FN
;
1300 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1303 reg
->how
= DWARF2_FRAME_REG_CFA
;
1308 /* When arguments must be pushed onto the stack, they go on in reverse
1309 order. The code below implements a FILO (stack) to do this. */
1314 struct stack_item
*prev
;
1318 static struct stack_item
*
1319 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1321 struct stack_item
*si
;
1322 si
= xmalloc (sizeof (struct stack_item
));
1323 si
->data
= xmalloc (len
);
1326 memcpy (si
->data
, contents
, len
);
1330 static struct stack_item
*
1331 pop_stack_item (struct stack_item
*si
)
1333 struct stack_item
*dead
= si
;
1341 /* Return the alignment (in bytes) of the given type. */
1344 arm_type_align (struct type
*t
)
1350 t
= check_typedef (t
);
1351 switch (TYPE_CODE (t
))
1354 /* Should never happen. */
1355 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1359 case TYPE_CODE_ENUM
:
1363 case TYPE_CODE_RANGE
:
1364 case TYPE_CODE_BITSTRING
:
1366 case TYPE_CODE_CHAR
:
1367 case TYPE_CODE_BOOL
:
1368 return TYPE_LENGTH (t
);
1370 case TYPE_CODE_ARRAY
:
1371 case TYPE_CODE_COMPLEX
:
1372 /* TODO: What about vector types? */
1373 return arm_type_align (TYPE_TARGET_TYPE (t
));
1375 case TYPE_CODE_STRUCT
:
1376 case TYPE_CODE_UNION
:
1378 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1380 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1388 /* Possible base types for a candidate for passing and returning in
1391 enum arm_vfp_cprc_base_type
1400 /* The length of one element of base type B. */
1403 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
1407 case VFP_CPRC_SINGLE
:
1409 case VFP_CPRC_DOUBLE
:
1411 case VFP_CPRC_VEC64
:
1413 case VFP_CPRC_VEC128
:
1416 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1421 /* The character ('s', 'd' or 'q') for the type of VFP register used
1422 for passing base type B. */
1425 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
1429 case VFP_CPRC_SINGLE
:
1431 case VFP_CPRC_DOUBLE
:
1433 case VFP_CPRC_VEC64
:
1435 case VFP_CPRC_VEC128
:
1438 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1443 /* Determine whether T may be part of a candidate for passing and
1444 returning in VFP registers, ignoring the limit on the total number
1445 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1446 classification of the first valid component found; if it is not
1447 VFP_CPRC_UNKNOWN, all components must have the same classification
1448 as *BASE_TYPE. If it is found that T contains a type not permitted
1449 for passing and returning in VFP registers, a type differently
1450 classified from *BASE_TYPE, or two types differently classified
1451 from each other, return -1, otherwise return the total number of
1452 base-type elements found (possibly 0 in an empty structure or
1453 array). Vectors and complex types are not currently supported,
1454 matching the generic AAPCS support. */
1457 arm_vfp_cprc_sub_candidate (struct type
*t
,
1458 enum arm_vfp_cprc_base_type
*base_type
)
1460 t
= check_typedef (t
);
1461 switch (TYPE_CODE (t
))
1464 switch (TYPE_LENGTH (t
))
1467 if (*base_type
== VFP_CPRC_UNKNOWN
)
1468 *base_type
= VFP_CPRC_SINGLE
;
1469 else if (*base_type
!= VFP_CPRC_SINGLE
)
1474 if (*base_type
== VFP_CPRC_UNKNOWN
)
1475 *base_type
= VFP_CPRC_DOUBLE
;
1476 else if (*base_type
!= VFP_CPRC_DOUBLE
)
1485 case TYPE_CODE_ARRAY
:
1489 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
1492 if (TYPE_LENGTH (t
) == 0)
1494 gdb_assert (count
== 0);
1497 else if (count
== 0)
1499 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1500 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
1501 return TYPE_LENGTH (t
) / unitlen
;
1505 case TYPE_CODE_STRUCT
:
1510 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1512 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1514 if (sub_count
== -1)
1518 if (TYPE_LENGTH (t
) == 0)
1520 gdb_assert (count
== 0);
1523 else if (count
== 0)
1525 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1526 if (TYPE_LENGTH (t
) != unitlen
* count
)
1531 case TYPE_CODE_UNION
:
1536 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1538 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1540 if (sub_count
== -1)
1542 count
= (count
> sub_count
? count
: sub_count
);
1544 if (TYPE_LENGTH (t
) == 0)
1546 gdb_assert (count
== 0);
1549 else if (count
== 0)
1551 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1552 if (TYPE_LENGTH (t
) != unitlen
* count
)
1564 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1565 if passed to or returned from a non-variadic function with the VFP
1566 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1567 *BASE_TYPE to the base type for T and *COUNT to the number of
1568 elements of that base type before returning. */
1571 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
1574 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
1575 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
1576 if (c
<= 0 || c
> 4)
1583 /* Return 1 if the VFP ABI should be used for passing arguments to and
1584 returning values from a function of type FUNC_TYPE, 0
1588 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
1590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1591 /* Variadic functions always use the base ABI. Assume that functions
1592 without debug info are not variadic. */
1593 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
1595 /* The VFP ABI is only supported as a variant of AAPCS. */
1596 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
1598 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
1601 /* We currently only support passing parameters in integer registers, which
1602 conforms with GCC's default model, and VFP argument passing following
1603 the VFP variant of AAPCS. Several other variants exist and
1604 we should probably support some of them based on the selected ABI. */
1607 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1608 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1609 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1610 CORE_ADDR struct_addr
)
1612 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1616 struct stack_item
*si
= NULL
;
1619 unsigned vfp_regs_free
= (1 << 16) - 1;
1621 /* Determine the type of this function and whether the VFP ABI
1623 ftype
= check_typedef (value_type (function
));
1624 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
1625 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
1626 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
1628 /* Set the return address. For the ARM, the return breakpoint is
1629 always at BP_ADDR. */
1630 /* XXX Fix for Thumb. */
1631 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1633 /* Walk through the list of args and determine how large a temporary
1634 stack is required. Need to take care here as structs may be
1635 passed on the stack, and we have to to push them. */
1638 argreg
= ARM_A1_REGNUM
;
1641 /* The struct_return pointer occupies the first parameter
1642 passing register. */
1646 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
1647 gdbarch_register_name (gdbarch
, argreg
),
1648 paddress (gdbarch
, struct_addr
));
1649 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1653 for (argnum
= 0; argnum
< nargs
; argnum
++)
1656 struct type
*arg_type
;
1657 struct type
*target_type
;
1658 enum type_code typecode
;
1661 enum arm_vfp_cprc_base_type vfp_base_type
;
1663 int may_use_core_reg
= 1;
1665 arg_type
= check_typedef (value_type (args
[argnum
]));
1666 len
= TYPE_LENGTH (arg_type
);
1667 target_type
= TYPE_TARGET_TYPE (arg_type
);
1668 typecode
= TYPE_CODE (arg_type
);
1669 val
= value_contents_writeable (args
[argnum
]);
1671 align
= arm_type_align (arg_type
);
1672 /* Round alignment up to a whole number of words. */
1673 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1674 /* Different ABIs have different maximum alignments. */
1675 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1677 /* The APCS ABI only requires word alignment. */
1678 align
= INT_REGISTER_SIZE
;
1682 /* The AAPCS requires at most doubleword alignment. */
1683 if (align
> INT_REGISTER_SIZE
* 2)
1684 align
= INT_REGISTER_SIZE
* 2;
1688 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
1696 /* Because this is a CPRC it cannot go in a core register or
1697 cause a core register to be skipped for alignment.
1698 Either it goes in VFP registers and the rest of this loop
1699 iteration is skipped for this argument, or it goes on the
1700 stack (and the stack alignment code is correct for this
1702 may_use_core_reg
= 0;
1704 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
1705 shift
= unit_length
/ 4;
1706 mask
= (1 << (shift
* vfp_base_count
)) - 1;
1707 for (regno
= 0; regno
< 16; regno
+= shift
)
1708 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
1717 vfp_regs_free
&= ~(mask
<< regno
);
1718 reg_scaled
= regno
/ shift
;
1719 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
1720 for (i
= 0; i
< vfp_base_count
; i
++)
1724 if (reg_char
== 'q')
1725 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
1726 val
+ i
* unit_length
);
1729 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
1730 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
1732 regcache_cooked_write (regcache
, regnum
,
1733 val
+ i
* unit_length
);
1740 /* This CPRC could not go in VFP registers, so all VFP
1741 registers are now marked as used. */
1746 /* Push stack padding for dowubleword alignment. */
1747 if (nstack
& (align
- 1))
1749 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1750 nstack
+= INT_REGISTER_SIZE
;
1753 /* Doubleword aligned quantities must go in even register pairs. */
1754 if (may_use_core_reg
1755 && argreg
<= ARM_LAST_ARG_REGNUM
1756 && align
> INT_REGISTER_SIZE
1760 /* If the argument is a pointer to a function, and it is a
1761 Thumb function, create a LOCAL copy of the value and set
1762 the THUMB bit in it. */
1763 if (TYPE_CODE_PTR
== typecode
1764 && target_type
!= NULL
1765 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1767 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
1768 if (arm_pc_is_thumb (regval
))
1771 store_unsigned_integer (val
, len
, byte_order
,
1772 MAKE_THUMB_ADDR (regval
));
1776 /* Copy the argument to general registers or the stack in
1777 register-sized pieces. Large arguments are split between
1778 registers and stack. */
1781 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1783 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
1785 /* The argument is being passed in a general purpose
1788 = extract_unsigned_integer (val
, partial_len
, byte_order
);
1789 if (byte_order
== BFD_ENDIAN_BIG
)
1790 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1792 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1794 gdbarch_register_name
1796 phex (regval
, INT_REGISTER_SIZE
));
1797 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1802 /* Push the arguments onto the stack. */
1804 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1806 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1807 nstack
+= INT_REGISTER_SIZE
;
1814 /* If we have an odd number of words to push, then decrement the stack
1815 by one word now, so first stack argument will be dword aligned. */
1822 write_memory (sp
, si
->data
, si
->len
);
1823 si
= pop_stack_item (si
);
1826 /* Finally, update teh SP register. */
1827 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1833 /* Always align the frame to an 8-byte boundary. This is required on
1834 some platforms and harmless on the rest. */
1837 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1839 /* Align the stack to eight bytes. */
1840 return sp
& ~ (CORE_ADDR
) 7;
1844 print_fpu_flags (int flags
)
1846 if (flags
& (1 << 0))
1847 fputs ("IVO ", stdout
);
1848 if (flags
& (1 << 1))
1849 fputs ("DVZ ", stdout
);
1850 if (flags
& (1 << 2))
1851 fputs ("OFL ", stdout
);
1852 if (flags
& (1 << 3))
1853 fputs ("UFL ", stdout
);
1854 if (flags
& (1 << 4))
1855 fputs ("INX ", stdout
);
1859 /* Print interesting information about the floating point processor
1860 (if present) or emulator. */
1862 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1863 struct frame_info
*frame
, const char *args
)
1865 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1868 type
= (status
>> 24) & 127;
1869 if (status
& (1 << 31))
1870 printf (_("Hardware FPU type %d\n"), type
);
1872 printf (_("Software FPU type %d\n"), type
);
1873 /* i18n: [floating point unit] mask */
1874 fputs (_("mask: "), stdout
);
1875 print_fpu_flags (status
>> 16);
1876 /* i18n: [floating point unit] flags */
1877 fputs (_("flags: "), stdout
);
1878 print_fpu_flags (status
);
1881 /* Construct the ARM extended floating point type. */
1882 static struct type
*
1883 arm_ext_type (struct gdbarch
*gdbarch
)
1885 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1887 if (!tdep
->arm_ext_type
)
1889 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
1890 floatformats_arm_ext
);
1892 return tdep
->arm_ext_type
;
1895 static struct type
*
1896 arm_neon_double_type (struct gdbarch
*gdbarch
)
1898 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1900 if (tdep
->neon_double_type
== NULL
)
1902 struct type
*t
, *elem
;
1904 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
1906 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1907 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
1908 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1909 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
1910 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1911 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
1912 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1913 append_composite_type_field (t
, "u64", elem
);
1914 elem
= builtin_type (gdbarch
)->builtin_float
;
1915 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
1916 elem
= builtin_type (gdbarch
)->builtin_double
;
1917 append_composite_type_field (t
, "f64", elem
);
1919 TYPE_VECTOR (t
) = 1;
1920 TYPE_NAME (t
) = "neon_d";
1921 tdep
->neon_double_type
= t
;
1924 return tdep
->neon_double_type
;
1927 /* FIXME: The vector types are not correctly ordered on big-endian
1928 targets. Just as s0 is the low bits of d0, d0[0] is also the low
1929 bits of d0 - regardless of what unit size is being held in d0. So
1930 the offset of the first uint8 in d0 is 7, but the offset of the
1931 first float is 4. This code works as-is for little-endian
1934 static struct type
*
1935 arm_neon_quad_type (struct gdbarch
*gdbarch
)
1937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1939 if (tdep
->neon_quad_type
== NULL
)
1941 struct type
*t
, *elem
;
1943 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
1945 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1946 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
1947 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1948 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
1949 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1950 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
1951 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1952 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
1953 elem
= builtin_type (gdbarch
)->builtin_float
;
1954 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
1955 elem
= builtin_type (gdbarch
)->builtin_double
;
1956 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
1958 TYPE_VECTOR (t
) = 1;
1959 TYPE_NAME (t
) = "neon_q";
1960 tdep
->neon_quad_type
= t
;
1963 return tdep
->neon_quad_type
;
1966 /* Return the GDB type object for the "standard" data type of data in
1969 static struct type
*
1970 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1972 int num_regs
= gdbarch_num_regs (gdbarch
);
1974 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
1975 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
1976 return builtin_type (gdbarch
)->builtin_float
;
1978 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
1979 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
1980 return arm_neon_quad_type (gdbarch
);
1982 /* If the target description has register information, we are only
1983 in this function so that we can override the types of
1984 double-precision registers for NEON. */
1985 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
1987 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
1989 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
1990 && TYPE_CODE (t
) == TYPE_CODE_FLT
1991 && gdbarch_tdep (gdbarch
)->have_neon
)
1992 return arm_neon_double_type (gdbarch
);
1997 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1999 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2000 return builtin_type (gdbarch
)->builtin_void
;
2002 return arm_ext_type (gdbarch
);
2004 else if (regnum
== ARM_SP_REGNUM
)
2005 return builtin_type (gdbarch
)->builtin_data_ptr
;
2006 else if (regnum
== ARM_PC_REGNUM
)
2007 return builtin_type (gdbarch
)->builtin_func_ptr
;
2008 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2009 /* These registers are only supported on targets which supply
2010 an XML description. */
2011 return builtin_type (gdbarch
)->builtin_int0
;
2013 return builtin_type (gdbarch
)->builtin_uint32
;
2016 /* Map a DWARF register REGNUM onto the appropriate GDB register
2020 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2022 /* Core integer regs. */
2023 if (reg
>= 0 && reg
<= 15)
2026 /* Legacy FPA encoding. These were once used in a way which
2027 overlapped with VFP register numbering, so their use is
2028 discouraged, but GDB doesn't support the ARM toolchain
2029 which used them for VFP. */
2030 if (reg
>= 16 && reg
<= 23)
2031 return ARM_F0_REGNUM
+ reg
- 16;
2033 /* New assignments for the FPA registers. */
2034 if (reg
>= 96 && reg
<= 103)
2035 return ARM_F0_REGNUM
+ reg
- 96;
2037 /* WMMX register assignments. */
2038 if (reg
>= 104 && reg
<= 111)
2039 return ARM_WCGR0_REGNUM
+ reg
- 104;
2041 if (reg
>= 112 && reg
<= 127)
2042 return ARM_WR0_REGNUM
+ reg
- 112;
2044 if (reg
>= 192 && reg
<= 199)
2045 return ARM_WC0_REGNUM
+ reg
- 192;
2047 /* VFP v2 registers. A double precision value is actually
2048 in d1 rather than s2, but the ABI only defines numbering
2049 for the single precision registers. This will "just work"
2050 in GDB for little endian targets (we'll read eight bytes,
2051 starting in s0 and then progressing to s1), but will be
2052 reversed on big endian targets with VFP. This won't
2053 be a problem for the new Neon quad registers; you're supposed
2054 to use DW_OP_piece for those. */
2055 if (reg
>= 64 && reg
<= 95)
2059 sprintf (name_buf
, "s%d", reg
- 64);
2060 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2064 /* VFP v3 / Neon registers. This range is also used for VFP v2
2065 registers, except that it now describes d0 instead of s0. */
2066 if (reg
>= 256 && reg
<= 287)
2070 sprintf (name_buf
, "d%d", reg
- 256);
2071 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2078 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2080 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2083 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2085 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2086 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2088 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2089 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2091 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2092 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2094 if (reg
< NUM_GREGS
)
2095 return SIM_ARM_R0_REGNUM
+ reg
;
2098 if (reg
< NUM_FREGS
)
2099 return SIM_ARM_FP0_REGNUM
+ reg
;
2102 if (reg
< NUM_SREGS
)
2103 return SIM_ARM_FPS_REGNUM
+ reg
;
2106 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2109 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2110 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2111 It is thought that this is is the floating-point register format on
2112 little-endian systems. */
2115 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2116 void *dbl
, int endianess
)
2120 if (endianess
== BFD_ENDIAN_BIG
)
2121 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2123 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2125 floatformat_from_doublest (fmt
, &d
, dbl
);
2129 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2134 floatformat_to_doublest (fmt
, ptr
, &d
);
2135 if (endianess
== BFD_ENDIAN_BIG
)
2136 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2138 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2143 condition_true (unsigned long cond
, unsigned long status_reg
)
2145 if (cond
== INST_AL
|| cond
== INST_NV
)
2151 return ((status_reg
& FLAG_Z
) != 0);
2153 return ((status_reg
& FLAG_Z
) == 0);
2155 return ((status_reg
& FLAG_C
) != 0);
2157 return ((status_reg
& FLAG_C
) == 0);
2159 return ((status_reg
& FLAG_N
) != 0);
2161 return ((status_reg
& FLAG_N
) == 0);
2163 return ((status_reg
& FLAG_V
) != 0);
2165 return ((status_reg
& FLAG_V
) == 0);
2167 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2169 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2171 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2173 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2175 return (((status_reg
& FLAG_Z
) == 0)
2176 && (((status_reg
& FLAG_N
) == 0)
2177 == ((status_reg
& FLAG_V
) == 0)));
2179 return (((status_reg
& FLAG_Z
) != 0)
2180 || (((status_reg
& FLAG_N
) == 0)
2181 != ((status_reg
& FLAG_V
) == 0)));
2186 /* Support routines for single stepping. Calculate the next PC value. */
2187 #define submask(x) ((1L << ((x) + 1)) - 1)
2188 #define bit(obj,st) (((obj) >> (st)) & 1)
2189 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
2190 #define sbits(obj,st,fn) \
2191 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
2192 #define BranchDest(addr,instr) \
2193 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
2196 static unsigned long
2197 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2198 unsigned long pc_val
, unsigned long status_reg
)
2200 unsigned long res
, shift
;
2201 int rm
= bits (inst
, 0, 3);
2202 unsigned long shifttype
= bits (inst
, 5, 6);
2206 int rs
= bits (inst
, 8, 11);
2207 shift
= (rs
== 15 ? pc_val
+ 8
2208 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2211 shift
= bits (inst
, 7, 11);
2214 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
2215 + (bit (inst
, 4) ? 12 : 8))
2216 : get_frame_register_unsigned (frame
, rm
));
2221 res
= shift
>= 32 ? 0 : res
<< shift
;
2225 res
= shift
>= 32 ? 0 : res
>> shift
;
2231 res
= ((res
& 0x80000000L
)
2232 ? ~((~res
) >> shift
) : res
>> shift
);
2235 case 3: /* ROR/RRX */
2238 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2240 res
= (res
>> shift
) | (res
<< (32 - shift
));
2244 return res
& 0xffffffff;
2247 /* Return number of 1-bits in VAL. */
2250 bitcount (unsigned long val
)
2253 for (nbits
= 0; val
!= 0; nbits
++)
2254 val
&= val
- 1; /* delete rightmost 1-bit in val */
2259 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2261 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2262 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2263 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2264 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2265 unsigned short inst1
;
2266 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2267 unsigned long offset
;
2269 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2271 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
2275 /* Fetch the saved PC from the stack. It's stored above
2276 all of the other registers. */
2277 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
2278 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
2279 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
2280 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2282 error (_("Infinite loop detected"));
2284 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
2286 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2287 unsigned long cond
= bits (inst1
, 8, 11);
2288 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
2289 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
2291 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
2293 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
2295 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
2297 unsigned short inst2
;
2298 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
2299 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
2300 nextpc
= pc_val
+ offset
;
2301 /* For BLX make sure to clear the low bits. */
2302 if (bits (inst2
, 11, 12) == 1)
2303 nextpc
= nextpc
& 0xfffffffc;
2305 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
2307 if (bits (inst1
, 3, 6) == 0x0f)
2310 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
2312 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2314 error (_("Infinite loop detected"));
2321 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2323 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2324 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2325 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2326 unsigned long pc_val
;
2327 unsigned long this_instr
;
2328 unsigned long status
;
2331 if (arm_frame_is_thumb (frame
))
2332 return thumb_get_next_pc (frame
, pc
);
2334 pc_val
= (unsigned long) pc
;
2335 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
2337 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2338 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
2340 if (bits (this_instr
, 28, 31) == INST_NV
)
2341 switch (bits (this_instr
, 24, 27))
2346 /* Branch with Link and change to Thumb. */
2347 nextpc
= BranchDest (pc
, this_instr
);
2348 nextpc
|= bit (this_instr
, 24) << 1;
2350 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2352 error (_("Infinite loop detected"));
2358 /* Coprocessor register transfer. */
2359 if (bits (this_instr
, 12, 15) == 15)
2360 error (_("Invalid update to pc in instruction"));
2363 else if (condition_true (bits (this_instr
, 28, 31), status
))
2365 switch (bits (this_instr
, 24, 27))
2368 case 0x1: /* data processing */
2372 unsigned long operand1
, operand2
, result
= 0;
2376 if (bits (this_instr
, 12, 15) != 15)
2379 if (bits (this_instr
, 22, 25) == 0
2380 && bits (this_instr
, 4, 7) == 9) /* multiply */
2381 error (_("Invalid update to pc in instruction"));
2383 /* BX <reg>, BLX <reg> */
2384 if (bits (this_instr
, 4, 27) == 0x12fff1
2385 || bits (this_instr
, 4, 27) == 0x12fff3)
2387 rn
= bits (this_instr
, 0, 3);
2388 result
= (rn
== 15) ? pc_val
+ 8
2389 : get_frame_register_unsigned (frame
, rn
);
2390 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2394 error (_("Infinite loop detected"));
2399 /* Multiply into PC */
2400 c
= (status
& FLAG_C
) ? 1 : 0;
2401 rn
= bits (this_instr
, 16, 19);
2402 operand1
= (rn
== 15) ? pc_val
+ 8
2403 : get_frame_register_unsigned (frame
, rn
);
2405 if (bit (this_instr
, 25))
2407 unsigned long immval
= bits (this_instr
, 0, 7);
2408 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
2409 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
2412 else /* operand 2 is a shifted register */
2413 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
2415 switch (bits (this_instr
, 21, 24))
2418 result
= operand1
& operand2
;
2422 result
= operand1
^ operand2
;
2426 result
= operand1
- operand2
;
2430 result
= operand2
- operand1
;
2434 result
= operand1
+ operand2
;
2438 result
= operand1
+ operand2
+ c
;
2442 result
= operand1
- operand2
+ c
;
2446 result
= operand2
- operand1
+ c
;
2452 case 0xb: /* tst, teq, cmp, cmn */
2453 result
= (unsigned long) nextpc
;
2457 result
= operand1
| operand2
;
2461 /* Always step into a function. */
2466 result
= operand1
& ~operand2
;
2473 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2477 error (_("Infinite loop detected"));
2482 case 0x5: /* data transfer */
2485 if (bit (this_instr
, 20))
2488 if (bits (this_instr
, 12, 15) == 15)
2494 if (bit (this_instr
, 22))
2495 error (_("Invalid update to pc in instruction"));
2497 /* byte write to PC */
2498 rn
= bits (this_instr
, 16, 19);
2499 base
= (rn
== 15) ? pc_val
+ 8
2500 : get_frame_register_unsigned (frame
, rn
);
2501 if (bit (this_instr
, 24))
2504 int c
= (status
& FLAG_C
) ? 1 : 0;
2505 unsigned long offset
=
2506 (bit (this_instr
, 25)
2507 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2508 : bits (this_instr
, 0, 11));
2510 if (bit (this_instr
, 23))
2515 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2518 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2521 error (_("Infinite loop detected"));
2527 case 0x9: /* block transfer */
2528 if (bit (this_instr
, 20))
2531 if (bit (this_instr
, 15))
2536 if (bit (this_instr
, 23))
2539 unsigned long reglist
= bits (this_instr
, 0, 14);
2540 offset
= bitcount (reglist
) * 4;
2541 if (bit (this_instr
, 24)) /* pre */
2544 else if (bit (this_instr
, 24))
2548 unsigned long rn_val
=
2549 get_frame_register_unsigned (frame
,
2550 bits (this_instr
, 16, 19));
2552 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2556 nextpc
= gdbarch_addr_bits_remove
2559 error (_("Infinite loop detected"));
2564 case 0xb: /* branch & link */
2565 case 0xa: /* branch */
2567 nextpc
= BranchDest (pc
, this_instr
);
2569 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2571 error (_("Infinite loop detected"));
2577 case 0xe: /* coproc ops */
2582 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2590 /* single_step() is called just before we want to resume the inferior,
2591 if we want to single-step it but there is no hardware or kernel
2592 single-step support. We find the target of the coming instruction
2593 and breakpoint it. */
2596 arm_software_single_step (struct frame_info
*frame
)
2598 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2600 /* NOTE: This may insert the wrong breakpoint instruction when
2601 single-stepping over a mode-changing instruction, if the
2602 CPSR heuristics are used. */
2604 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2605 insert_single_step_breakpoint (gdbarch
, next_pc
);
2610 /* ARM displaced stepping support.
2612 Generally ARM displaced stepping works as follows:
2614 1. When an instruction is to be single-stepped, it is first decoded by
2615 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
2616 Depending on the type of instruction, it is then copied to a scratch
2617 location, possibly in a modified form. The copy_* set of functions
2618 performs such modification, as necessary. A breakpoint is placed after
2619 the modified instruction in the scratch space to return control to GDB.
2620 Note in particular that instructions which modify the PC will no longer
2621 do so after modification.
2623 2. The instruction is single-stepped, by setting the PC to the scratch
2624 location address, and resuming. Control returns to GDB when the
2627 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
2628 function used for the current instruction. This function's job is to
2629 put the CPU/memory state back to what it would have been if the
2630 instruction had been executed unmodified in its original location. */
2632 /* NOP instruction (mov r0, r0). */
2633 #define ARM_NOP 0xe1a00000
2635 /* Helper for register reads for displaced stepping. In particular, this
2636 returns the PC as it would be seen by the instruction at its original
2640 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
2646 if (debug_displaced
)
2647 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
2648 (unsigned long) from
+ 8);
2649 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
2653 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
2654 if (debug_displaced
)
2655 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
2656 regno
, (unsigned long) ret
);
2662 displaced_in_arm_mode (struct regcache
*regs
)
2666 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
2668 return (ps
& CPSR_T
) == 0;
2671 /* Write to the PC as from a branch instruction. */
2674 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
2676 if (displaced_in_arm_mode (regs
))
2677 /* Note: If bits 0/1 are set, this branch would be unpredictable for
2678 architecture versions < 6. */
2679 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
2681 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
2684 /* Write to the PC as from a branch-exchange instruction. */
2687 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
2691 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
2695 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| CPSR_T
);
2696 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
2698 else if ((val
& 2) == 0)
2700 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
2701 ps
& ~(ULONGEST
) CPSR_T
);
2702 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
2706 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
2707 mode, align dest to 4 bytes). */
2708 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
2709 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
2710 ps
& ~(ULONGEST
) CPSR_T
);
2711 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
2715 /* Write to the PC as if from a load instruction. */
2718 load_write_pc (struct regcache
*regs
, ULONGEST val
)
2720 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
2721 bx_write_pc (regs
, val
);
2723 branch_write_pc (regs
, val
);
2726 /* Write to the PC as if from an ALU instruction. */
2729 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
2731 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
2732 bx_write_pc (regs
, val
);
2734 branch_write_pc (regs
, val
);
2737 /* Helper for writing to registers for displaced stepping. Writing to the PC
2738 has a varying effects depending on the instruction which does the write:
2739 this is controlled by the WRITE_PC argument. */
2742 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
2743 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
2747 if (debug_displaced
)
2748 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
2749 (unsigned long) val
);
2752 case BRANCH_WRITE_PC
:
2753 branch_write_pc (regs
, val
);
2757 bx_write_pc (regs
, val
);
2761 load_write_pc (regs
, val
);
2765 alu_write_pc (regs
, val
);
2768 case CANNOT_WRITE_PC
:
2769 warning (_("Instruction wrote to PC in an unexpected way when "
2770 "single-stepping"));
2774 internal_error (__FILE__
, __LINE__
,
2775 _("Invalid argument to displaced_write_reg"));
2778 dsc
->wrote_to_pc
= 1;
2782 if (debug_displaced
)
2783 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
2784 regno
, (unsigned long) val
);
2785 regcache_cooked_write_unsigned (regs
, regno
, val
);
2789 /* This function is used to concisely determine if an instruction INSN
2790 references PC. Register fields of interest in INSN should have the
2791 corresponding fields of BITMASK set to 0b1111. The function returns return 1
2792 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
2796 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
2798 uint32_t lowbit
= 1;
2800 while (bitmask
!= 0)
2804 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
2810 mask
= lowbit
* 0xf;
2812 if ((insn
& mask
) == mask
)
2821 /* The simplest copy function. Many instructions have the same effect no
2822 matter what address they are executed at: in those cases, use this. */
2825 copy_unmodified (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
2826 const char *iname
, struct displaced_step_closure
*dsc
)
2828 if (debug_displaced
)
2829 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
2830 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
2833 dsc
->modinsn
[0] = insn
;
2838 /* Preload instructions with immediate offset. */
2841 cleanup_preload (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
2842 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
2844 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
2845 if (!dsc
->u
.preload
.immed
)
2846 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
2850 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
2851 struct displaced_step_closure
*dsc
)
2853 unsigned int rn
= bits (insn
, 16, 19);
2855 CORE_ADDR from
= dsc
->insn_addr
;
2857 if (!insn_references_pc (insn
, 0x000f0000ul
))
2858 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
2860 if (debug_displaced
)
2861 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
2862 (unsigned long) insn
);
2864 /* Preload instructions:
2866 {pli/pld} [rn, #+/-imm]
2868 {pli/pld} [r0, #+/-imm]. */
2870 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
2871 rn_val
= displaced_read_reg (regs
, from
, rn
);
2872 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
2874 dsc
->u
.preload
.immed
= 1;
2876 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
2878 dsc
->cleanup
= &cleanup_preload
;
2883 /* Preload instructions with register offset. */
2886 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
2887 struct displaced_step_closure
*dsc
)
2889 unsigned int rn
= bits (insn
, 16, 19);
2890 unsigned int rm
= bits (insn
, 0, 3);
2891 ULONGEST rn_val
, rm_val
;
2892 CORE_ADDR from
= dsc
->insn_addr
;
2894 if (!insn_references_pc (insn
, 0x000f000ful
))
2895 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
2897 if (debug_displaced
)
2898 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
2899 (unsigned long) insn
);
2901 /* Preload register-offset instructions:
2903 {pli/pld} [rn, rm {, shift}]
2905 {pli/pld} [r0, r1 {, shift}]. */
2907 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
2908 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
2909 rn_val
= displaced_read_reg (regs
, from
, rn
);
2910 rm_val
= displaced_read_reg (regs
, from
, rm
);
2911 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
2912 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
2914 dsc
->u
.preload
.immed
= 0;
2916 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
2918 dsc
->cleanup
= &cleanup_preload
;
2923 /* Copy/cleanup coprocessor load and store instructions. */
2926 cleanup_copro_load_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
2927 struct regcache
*regs
,
2928 struct displaced_step_closure
*dsc
)
2930 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
2932 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
2934 if (dsc
->u
.ldst
.writeback
)
2935 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
2939 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
2940 struct regcache
*regs
,
2941 struct displaced_step_closure
*dsc
)
2943 unsigned int rn
= bits (insn
, 16, 19);
2945 CORE_ADDR from
= dsc
->insn_addr
;
2947 if (!insn_references_pc (insn
, 0x000f0000ul
))
2948 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
2950 if (debug_displaced
)
2951 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
2952 "load/store insn %.8lx\n", (unsigned long) insn
);
2954 /* Coprocessor load/store instructions:
2956 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
2958 {stc/stc2} [r0, #+/-imm].
2960 ldc/ldc2 are handled identically. */
2962 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
2963 rn_val
= displaced_read_reg (regs
, from
, rn
);
2964 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
2966 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
2967 dsc
->u
.ldst
.rn
= rn
;
2969 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
2971 dsc
->cleanup
= &cleanup_copro_load_store
;
2976 /* Clean up branch instructions (actually perform the branch, by setting
2980 cleanup_branch (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
2981 struct displaced_step_closure
*dsc
)
2983 ULONGEST from
= dsc
->insn_addr
;
2984 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
2985 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
2986 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
2987 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
2992 if (dsc
->u
.branch
.link
)
2994 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
2995 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
2998 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
3001 /* Copy B/BL/BLX instructions with immediate destinations. */
3004 copy_b_bl_blx (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3005 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3007 unsigned int cond
= bits (insn
, 28, 31);
3008 int exchange
= (cond
== 0xf);
3009 int link
= exchange
|| bit (insn
, 24);
3010 CORE_ADDR from
= dsc
->insn_addr
;
3013 if (debug_displaced
)
3014 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
3015 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
3016 (unsigned long) insn
);
3018 /* Implement "BL<cond> <label>" as:
3020 Preparation: cond <- instruction condition
3021 Insn: mov r0, r0 (nop)
3022 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
3024 B<cond> similar, but don't set r14 in cleanup. */
3027 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
3028 then arrange the switch into Thumb mode. */
3029 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
3031 offset
= bits (insn
, 0, 23) << 2;
3033 if (bit (offset
, 25))
3034 offset
= offset
| ~0x3ffffff;
3036 dsc
->u
.branch
.cond
= cond
;
3037 dsc
->u
.branch
.link
= link
;
3038 dsc
->u
.branch
.exchange
= exchange
;
3039 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
3041 dsc
->modinsn
[0] = ARM_NOP
;
3043 dsc
->cleanup
= &cleanup_branch
;
3048 /* Copy BX/BLX with register-specified destinations. */
3051 copy_bx_blx_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3052 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3054 unsigned int cond
= bits (insn
, 28, 31);
3057 int link
= bit (insn
, 5);
3058 unsigned int rm
= bits (insn
, 0, 3);
3059 CORE_ADDR from
= dsc
->insn_addr
;
3061 if (debug_displaced
)
3062 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
3063 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
3065 /* Implement {BX,BLX}<cond> <reg>" as:
3067 Preparation: cond <- instruction condition
3068 Insn: mov r0, r0 (nop)
3069 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
3071 Don't set r14 in cleanup for BX. */
3073 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
3075 dsc
->u
.branch
.cond
= cond
;
3076 dsc
->u
.branch
.link
= link
;
3077 dsc
->u
.branch
.exchange
= 1;
3079 dsc
->modinsn
[0] = ARM_NOP
;
3081 dsc
->cleanup
= &cleanup_branch
;
3086 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
3089 cleanup_alu_imm (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3090 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3092 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3093 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3094 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3095 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3099 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3100 struct displaced_step_closure
*dsc
)
3102 unsigned int rn
= bits (insn
, 16, 19);
3103 unsigned int rd
= bits (insn
, 12, 15);
3104 unsigned int op
= bits (insn
, 21, 24);
3105 int is_mov
= (op
== 0xd);
3106 ULONGEST rd_val
, rn_val
;
3107 CORE_ADDR from
= dsc
->insn_addr
;
3109 if (!insn_references_pc (insn
, 0x000ff000ul
))
3110 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
3112 if (debug_displaced
)
3113 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
3114 "%.8lx\n", is_mov
? "move" : "ALU",
3115 (unsigned long) insn
);
3117 /* Instruction is of form:
3119 <op><cond> rd, [rn,] #imm
3123 Preparation: tmp1, tmp2 <- r0, r1;
3125 Insn: <op><cond> r0, r1, #imm
3126 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
3129 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3130 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3131 rn_val
= displaced_read_reg (regs
, from
, rn
);
3132 rd_val
= displaced_read_reg (regs
, from
, rd
);
3133 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3134 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3138 dsc
->modinsn
[0] = insn
& 0xfff00fff;
3140 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
3142 dsc
->cleanup
= &cleanup_alu_imm
;
3147 /* Copy/cleanup arithmetic/logic insns with register RHS. */
3150 cleanup_alu_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3151 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3156 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3158 for (i
= 0; i
< 3; i
++)
3159 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3161 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3165 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3166 struct displaced_step_closure
*dsc
)
3168 unsigned int rn
= bits (insn
, 16, 19);
3169 unsigned int rm
= bits (insn
, 0, 3);
3170 unsigned int rd
= bits (insn
, 12, 15);
3171 unsigned int op
= bits (insn
, 21, 24);
3172 int is_mov
= (op
== 0xd);
3173 ULONGEST rd_val
, rn_val
, rm_val
;
3174 CORE_ADDR from
= dsc
->insn_addr
;
3176 if (!insn_references_pc (insn
, 0x000ff00ful
))
3177 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
3179 if (debug_displaced
)
3180 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
3181 is_mov
? "move" : "ALU", (unsigned long) insn
);
3183 /* Instruction is of form:
3185 <op><cond> rd, [rn,] rm [, <shift>]
3189 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
3190 r0, r1, r2 <- rd, rn, rm
3191 Insn: <op><cond> r0, r1, r2 [, <shift>]
3192 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
3195 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3196 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3197 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3198 rd_val
= displaced_read_reg (regs
, from
, rd
);
3199 rn_val
= displaced_read_reg (regs
, from
, rn
);
3200 rm_val
= displaced_read_reg (regs
, from
, rm
);
3201 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3202 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3203 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3207 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
3209 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
3211 dsc
->cleanup
= &cleanup_alu_reg
;
3216 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
3219 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3220 struct regcache
*regs
,
3221 struct displaced_step_closure
*dsc
)
3223 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3226 for (i
= 0; i
< 4; i
++)
3227 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3229 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3233 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
3234 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3236 unsigned int rn
= bits (insn
, 16, 19);
3237 unsigned int rm
= bits (insn
, 0, 3);
3238 unsigned int rd
= bits (insn
, 12, 15);
3239 unsigned int rs
= bits (insn
, 8, 11);
3240 unsigned int op
= bits (insn
, 21, 24);
3241 int is_mov
= (op
== 0xd), i
;
3242 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
3243 CORE_ADDR from
= dsc
->insn_addr
;
3245 if (!insn_references_pc (insn
, 0x000fff0ful
))
3246 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
3248 if (debug_displaced
)
3249 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
3250 "%.8lx\n", is_mov
? "move" : "ALU",
3251 (unsigned long) insn
);
3253 /* Instruction is of form:
3255 <op><cond> rd, [rn,] rm, <shift> rs
3259 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
3260 r0, r1, r2, r3 <- rd, rn, rm, rs
3261 Insn: <op><cond> r0, r1, r2, <shift> r3
3263 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
3267 for (i
= 0; i
< 4; i
++)
3268 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
3270 rd_val
= displaced_read_reg (regs
, from
, rd
);
3271 rn_val
= displaced_read_reg (regs
, from
, rn
);
3272 rm_val
= displaced_read_reg (regs
, from
, rm
);
3273 rs_val
= displaced_read_reg (regs
, from
, rs
);
3274 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3275 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3276 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3277 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
3281 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
3283 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
3285 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
3290 /* Clean up load instructions. */
3293 cleanup_load (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3294 struct displaced_step_closure
*dsc
)
3296 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
3297 CORE_ADDR from
= dsc
->insn_addr
;
3299 rt_val
= displaced_read_reg (regs
, from
, 0);
3300 if (dsc
->u
.ldst
.xfersize
== 8)
3301 rt_val2
= displaced_read_reg (regs
, from
, 1);
3302 rn_val
= displaced_read_reg (regs
, from
, 2);
3304 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3305 if (dsc
->u
.ldst
.xfersize
> 4)
3306 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3307 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3308 if (!dsc
->u
.ldst
.immed
)
3309 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3311 /* Handle register writeback. */
3312 if (dsc
->u
.ldst
.writeback
)
3313 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3314 /* Put result in right place. */
3315 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
3316 if (dsc
->u
.ldst
.xfersize
== 8)
3317 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
3320 /* Clean up store instructions. */
3323 cleanup_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3324 struct displaced_step_closure
*dsc
)
3326 CORE_ADDR from
= dsc
->insn_addr
;
3327 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
3329 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3330 if (dsc
->u
.ldst
.xfersize
> 4)
3331 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3332 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3333 if (!dsc
->u
.ldst
.immed
)
3334 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3335 if (!dsc
->u
.ldst
.restore_r4
)
3336 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
3339 if (dsc
->u
.ldst
.writeback
)
3340 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3343 /* Copy "extra" load/store instructions. These are halfword/doubleword
3344 transfers, which have a different encoding to byte/word transfers. */
3347 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
3348 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3350 unsigned int op1
= bits (insn
, 20, 24);
3351 unsigned int op2
= bits (insn
, 5, 6);
3352 unsigned int rt
= bits (insn
, 12, 15);
3353 unsigned int rn
= bits (insn
, 16, 19);
3354 unsigned int rm
= bits (insn
, 0, 3);
3355 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
3356 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
3357 int immed
= (op1
& 0x4) != 0;
3359 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
3360 CORE_ADDR from
= dsc
->insn_addr
;
3362 if (!insn_references_pc (insn
, 0x000ff00ful
))
3363 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
3365 if (debug_displaced
)
3366 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
3367 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
3368 (unsigned long) insn
);
3370 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
3373 internal_error (__FILE__
, __LINE__
,
3374 _("copy_extra_ld_st: instruction decode error"));
3376 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3377 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3378 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3380 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3382 rt_val
= displaced_read_reg (regs
, from
, rt
);
3383 if (bytesize
[opcode
] == 8)
3384 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
3385 rn_val
= displaced_read_reg (regs
, from
, rn
);
3387 rm_val
= displaced_read_reg (regs
, from
, rm
);
3389 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
3390 if (bytesize
[opcode
] == 8)
3391 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
3392 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
3394 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
3397 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
3398 dsc
->u
.ldst
.rn
= rn
;
3399 dsc
->u
.ldst
.immed
= immed
;
3400 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
3401 dsc
->u
.ldst
.restore_r4
= 0;
3404 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
3406 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
3407 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
3409 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
3411 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
3412 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
3414 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
3419 /* Copy byte/word loads and stores. */
3422 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
3423 struct regcache
*regs
,
3424 struct displaced_step_closure
*dsc
, int load
, int byte
,
3427 int immed
= !bit (insn
, 25);
3428 unsigned int rt
= bits (insn
, 12, 15);
3429 unsigned int rn
= bits (insn
, 16, 19);
3430 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
3431 ULONGEST rt_val
, rn_val
, rm_val
= 0;
3432 CORE_ADDR from
= dsc
->insn_addr
;
3434 if (!insn_references_pc (insn
, 0x000ff00ful
))
3435 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
3437 if (debug_displaced
)
3438 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
3439 load
? (byte
? "ldrb" : "ldr")
3440 : (byte
? "strb" : "str"), usermode
? "t" : "",
3441 (unsigned long) insn
);
3443 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3444 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3446 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3448 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
3450 rt_val
= displaced_read_reg (regs
, from
, rt
);
3451 rn_val
= displaced_read_reg (regs
, from
, rn
);
3453 rm_val
= displaced_read_reg (regs
, from
, rm
);
3455 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
3456 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
3458 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
3461 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
3462 dsc
->u
.ldst
.rn
= rn
;
3463 dsc
->u
.ldst
.immed
= immed
;
3464 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
3466 /* To write PC we can do:
3468 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
3469 scratch+4: ldr r4, temp
3470 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
3471 scratch+12: add r4, r4, #8 (r4 = offset)
3472 scratch+16: add r0, r0, r4
3473 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
3476 Otherwise we don't know what value to write for PC, since the offset is
3477 architecture-dependent (sometimes PC+8, sometimes PC+12). */
3479 if (load
|| rt
!= 15)
3481 dsc
->u
.ldst
.restore_r4
= 0;
3484 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
3486 {ldr,str}[b]<cond> r0, [r2, #imm]. */
3487 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
3489 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
3491 {ldr,str}[b]<cond> r0, [r2, r3]. */
3492 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
3496 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
3497 dsc
->u
.ldst
.restore_r4
= 1;
3499 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
3500 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
3501 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
3502 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
3503 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
3507 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
3509 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
3511 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
3512 dsc
->modinsn
[7] = 0x0; /* scratch space. */
3517 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
3522 /* Cleanup LDM instructions with fully-populated register list. This is an
3523 unfortunate corner case: it's impossible to implement correctly by modifying
3524 the instruction. The issue is as follows: we have an instruction,
3528 which we must rewrite to avoid loading PC. A possible solution would be to
3529 do the load in two halves, something like (with suitable cleanup
3533 ldm[id][ab] r8!, {r0-r7}
3535 ldm[id][ab] r8, {r7-r14}
3538 but at present there's no suitable place for <temp>, since the scratch space
3539 is overwritten before the cleanup routine is called. For now, we simply
3540 emulate the instruction. */
3543 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
3544 struct displaced_step_closure
*dsc
)
3546 ULONGEST from
= dsc
->insn_addr
;
3547 int inc
= dsc
->u
.block
.increment
;
3548 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
3549 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
3550 uint32_t regmask
= dsc
->u
.block
.regmask
;
3551 int regno
= inc
? 0 : 15;
3552 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
3553 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
3554 && (regmask
& 0x8000) != 0;
3555 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3556 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
3557 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3562 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
3563 sensible we can do here. Complain loudly. */
3564 if (exception_return
)
3565 error (_("Cannot single-step exception return"));
3567 /* We don't handle any stores here for now. */
3568 gdb_assert (dsc
->u
.block
.load
!= 0);
3570 if (debug_displaced
)
3571 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
3572 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
3573 dsc
->u
.block
.increment
? "inc" : "dec",
3574 dsc
->u
.block
.before
? "before" : "after");
3581 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
3584 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
3587 xfer_addr
+= bump_before
;
3589 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
3590 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
3592 xfer_addr
+= bump_after
;
3594 regmask
&= ~(1 << regno
);
3597 if (dsc
->u
.block
.writeback
)
3598 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
3602 /* Clean up an STM which included the PC in the register list. */
3605 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
3606 struct displaced_step_closure
*dsc
)
3608 ULONGEST from
= dsc
->insn_addr
;
3609 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3610 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
3611 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
3612 CORE_ADDR stm_insn_addr
;
3615 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3617 /* If condition code fails, there's nothing else to do. */
3618 if (!store_executed
)
3621 if (dsc
->u
.block
.increment
)
3623 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
3625 if (dsc
->u
.block
.before
)
3630 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
3632 if (dsc
->u
.block
.before
)
3636 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
3637 stm_insn_addr
= dsc
->scratch_base
;
3638 offset
= pc_val
- stm_insn_addr
;
3640 if (debug_displaced
)
3641 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
3642 "STM instruction\n", offset
);
3644 /* Rewrite the stored PC to the proper value for the non-displaced original
3646 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
3647 dsc
->insn_addr
+ offset
);
3650 /* Clean up an LDM which includes the PC in the register list. We clumped all
3651 the registers in the transferred list into a contiguous range r0...rX (to
3652 avoid loading PC directly and losing control of the debugged program), so we
3653 must undo that here. */
3656 cleanup_block_load_pc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3657 struct regcache
*regs
,
3658 struct displaced_step_closure
*dsc
)
3660 ULONGEST from
= dsc
->insn_addr
;
3661 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3662 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
3663 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
3664 unsigned int regs_loaded
= bitcount (mask
);
3665 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
3667 /* The method employed here will fail if the register list is fully populated
3668 (we need to avoid loading PC directly). */
3669 gdb_assert (num_to_shuffle
< 16);
3674 clobbered
= (1 << num_to_shuffle
) - 1;
3676 while (num_to_shuffle
> 0)
3678 if ((mask
& (1 << write_reg
)) != 0)
3680 unsigned int read_reg
= num_to_shuffle
- 1;
3682 if (read_reg
!= write_reg
)
3684 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
3685 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
3686 if (debug_displaced
)
3687 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
3688 "loaded register r%d to r%d\n"), read_reg
,
3691 else if (debug_displaced
)
3692 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
3693 "r%d already in the right place\n"),
3696 clobbered
&= ~(1 << write_reg
);
3704 /* Restore any registers we scribbled over. */
3705 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
3707 if ((clobbered
& (1 << write_reg
)) != 0)
3709 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
3711 if (debug_displaced
)
3712 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
3713 "clobbered register r%d\n"), write_reg
);
3714 clobbered
&= ~(1 << write_reg
);
3718 /* Perform register writeback manually. */
3719 if (dsc
->u
.block
.writeback
)
3721 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
3723 if (dsc
->u
.block
.increment
)
3724 new_rn_val
+= regs_loaded
* 4;
3726 new_rn_val
-= regs_loaded
* 4;
3728 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
3733 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
3734 in user-level code (in particular exception return, ldm rn, {...pc}^). */
3737 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3738 struct displaced_step_closure
*dsc
)
3740 int load
= bit (insn
, 20);
3741 int user
= bit (insn
, 22);
3742 int increment
= bit (insn
, 23);
3743 int before
= bit (insn
, 24);
3744 int writeback
= bit (insn
, 21);
3745 int rn
= bits (insn
, 16, 19);
3746 CORE_ADDR from
= dsc
->insn_addr
;
3748 /* Block transfers which don't mention PC can be run directly out-of-line. */
3749 if (rn
!= 15 && (insn
& 0x8000) == 0)
3750 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
3754 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
3755 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
3758 if (debug_displaced
)
3759 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
3760 "%.8lx\n", (unsigned long) insn
);
3762 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
3763 dsc
->u
.block
.rn
= rn
;
3765 dsc
->u
.block
.load
= load
;
3766 dsc
->u
.block
.user
= user
;
3767 dsc
->u
.block
.increment
= increment
;
3768 dsc
->u
.block
.before
= before
;
3769 dsc
->u
.block
.writeback
= writeback
;
3770 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
3772 dsc
->u
.block
.regmask
= insn
& 0xffff;
3776 if ((insn
& 0xffff) == 0xffff)
3778 /* LDM with a fully-populated register list. This case is
3779 particularly tricky. Implement for now by fully emulating the
3780 instruction (which might not behave perfectly in all cases, but
3781 these instructions should be rare enough for that not to matter
3783 dsc
->modinsn
[0] = ARM_NOP
;
3785 dsc
->cleanup
= &cleanup_block_load_all
;
3789 /* LDM of a list of registers which includes PC. Implement by
3790 rewriting the list of registers to be transferred into a
3791 contiguous chunk r0...rX before doing the transfer, then shuffling
3792 registers into the correct places in the cleanup routine. */
3793 unsigned int regmask
= insn
& 0xffff;
3794 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
3795 unsigned int to
= 0, from
= 0, i
, new_rn
;
3797 for (i
= 0; i
< num_in_list
; i
++)
3798 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
3800 /* Writeback makes things complicated. We need to avoid clobbering
3801 the base register with one of the registers in our modified
3802 register list, but just using a different register can't work in
3805 ldm r14!, {r0-r13,pc}
3807 which would need to be rewritten as:
3811 but that can't work, because there's no free register for N.
3813 Solve this by turning off the writeback bit, and emulating
3814 writeback manually in the cleanup routine. */
3819 new_regmask
= (1 << num_in_list
) - 1;
3821 if (debug_displaced
)
3822 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
3823 "{..., pc}: original reg list %.4x, modified "
3824 "list %.4x\n"), rn
, writeback
? "!" : "",
3825 (int) insn
& 0xffff, new_regmask
);
3827 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
3829 dsc
->cleanup
= &cleanup_block_load_pc
;
3834 /* STM of a list of registers which includes PC. Run the instruction
3835 as-is, but out of line: this will store the wrong value for the PC,
3836 so we must manually fix up the memory in the cleanup routine.
3837 Doing things this way has the advantage that we can auto-detect
3838 the offset of the PC write (which is architecture-dependent) in
3839 the cleanup routine. */
3840 dsc
->modinsn
[0] = insn
;
3842 dsc
->cleanup
= &cleanup_block_store_pc
;
3848 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
3849 for Linux, where some SVC instructions must be treated specially. */
3852 cleanup_svc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3853 struct displaced_step_closure
*dsc
)
3855 CORE_ADDR from
= dsc
->insn_addr
;
3856 CORE_ADDR resume_addr
= from
+ 4;
3858 if (debug_displaced
)
3859 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
3860 "%.8lx\n", (unsigned long) resume_addr
);
3862 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
3866 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
3867 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3869 CORE_ADDR from
= dsc
->insn_addr
;
3871 /* Allow OS-specific code to override SVC handling. */
3872 if (dsc
->u
.svc
.copy_svc_os
)
3873 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
3875 if (debug_displaced
)
3876 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
3877 (unsigned long) insn
);
3879 /* Preparation: none.
3880 Insn: unmodified svc.
3881 Cleanup: pc <- insn_addr + 4. */
3883 dsc
->modinsn
[0] = insn
;
3885 dsc
->cleanup
= &cleanup_svc
;
3886 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
3888 dsc
->wrote_to_pc
= 1;
3893 /* Copy undefined instructions. */
3896 copy_undef (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3897 struct displaced_step_closure
*dsc
)
3899 if (debug_displaced
)
3900 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
3901 (unsigned long) insn
);
3903 dsc
->modinsn
[0] = insn
;
3908 /* Copy unpredictable instructions. */
3911 copy_unpred (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3912 struct displaced_step_closure
*dsc
)
3914 if (debug_displaced
)
3915 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
3916 "%.8lx\n", (unsigned long) insn
);
3918 dsc
->modinsn
[0] = insn
;
3923 /* The decode_* functions are instruction decoding helpers. They mostly follow
3924 the presentation in the ARM ARM. */
3927 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
3928 struct regcache
*regs
,
3929 struct displaced_step_closure
*dsc
)
3931 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
3932 unsigned int rn
= bits (insn
, 16, 19);
3934 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
3935 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
3936 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
3937 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
3938 else if ((op1
& 0x60) == 0x20)
3939 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
3940 else if ((op1
& 0x71) == 0x40)
3941 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
3942 else if ((op1
& 0x77) == 0x41)
3943 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
3944 else if ((op1
& 0x77) == 0x45)
3945 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
3946 else if ((op1
& 0x77) == 0x51)
3949 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
3951 return copy_unpred (gdbarch
, insn
, dsc
);
3953 else if ((op1
& 0x77) == 0x55)
3954 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
3955 else if (op1
== 0x57)
3958 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
3959 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
3960 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
3961 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
3962 default: return copy_unpred (gdbarch
, insn
, dsc
);
3964 else if ((op1
& 0x63) == 0x43)
3965 return copy_unpred (gdbarch
, insn
, dsc
);
3966 else if ((op2
& 0x1) == 0x0)
3967 switch (op1
& ~0x80)
3970 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
3972 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
3973 case 0x71: case 0x75:
3975 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
3976 case 0x63: case 0x67: case 0x73: case 0x77:
3977 return copy_unpred (gdbarch
, insn
, dsc
);
3979 return copy_undef (gdbarch
, insn
, dsc
);
3982 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
3986 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
3987 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3989 if (bit (insn
, 27) == 0)
3990 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
3991 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
3992 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
3995 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
3998 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
4000 case 0x4: case 0x5: case 0x6: case 0x7:
4001 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4004 switch ((insn
& 0xe00000) >> 21)
4006 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
4008 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4011 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4014 return copy_undef (gdbarch
, insn
, dsc
);
4019 int rn_f
= (bits (insn
, 16, 19) == 0xf);
4020 switch ((insn
& 0xe00000) >> 21)
4023 /* ldc/ldc2 imm (undefined for rn == pc). */
4024 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
4025 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4028 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4030 case 0x4: case 0x5: case 0x6: case 0x7:
4031 /* ldc/ldc2 lit (undefined for rn != pc). */
4032 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
4033 : copy_undef (gdbarch
, insn
, dsc
);
4036 return copy_undef (gdbarch
, insn
, dsc
);
4041 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
4044 if (bits (insn
, 16, 19) == 0xf)
4046 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4048 return copy_undef (gdbarch
, insn
, dsc
);
4052 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4054 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4058 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4060 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4063 return copy_undef (gdbarch
, insn
, dsc
);
4067 /* Decode miscellaneous instructions in dp/misc encoding space. */
4070 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
4071 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4073 unsigned int op2
= bits (insn
, 4, 6);
4074 unsigned int op
= bits (insn
, 21, 22);
4075 unsigned int op1
= bits (insn
, 16, 19);
4080 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
4083 if (op
== 0x1) /* bx. */
4084 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
4086 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
4088 return copy_undef (gdbarch
, insn
, dsc
);
4092 /* Not really supported. */
4093 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
4095 return copy_undef (gdbarch
, insn
, dsc
);
4099 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
4101 return copy_undef (gdbarch
, insn
, dsc
);
4104 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
4108 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
4110 /* Not really supported. */
4111 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
4114 return copy_undef (gdbarch
, insn
, dsc
);
4119 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4120 struct displaced_step_closure
*dsc
)
4123 switch (bits (insn
, 20, 24))
4126 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
4129 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
4131 case 0x12: case 0x16:
4132 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
4135 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
4139 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
4141 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
4142 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
4143 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
4144 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
4145 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
4146 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
4147 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
4148 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
4149 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
4150 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
4151 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
4152 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
4153 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
4154 /* 2nd arg means "unpriveleged". */
4155 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
4159 /* Should be unreachable. */
4164 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
4165 struct regcache
*regs
,
4166 struct displaced_step_closure
*dsc
)
4168 int a
= bit (insn
, 25), b
= bit (insn
, 4);
4169 uint32_t op1
= bits (insn
, 20, 24);
4170 int rn_f
= bits (insn
, 16, 19) == 0xf;
4172 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
4173 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
4174 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
4175 else if ((!a
&& (op1
& 0x17) == 0x02)
4176 || (a
&& (op1
& 0x17) == 0x02 && !b
))
4177 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
4178 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
4179 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
4180 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
4181 else if ((!a
&& (op1
& 0x17) == 0x03)
4182 || (a
&& (op1
& 0x17) == 0x03 && !b
))
4183 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
4184 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
4185 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
4186 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
4187 else if ((!a
&& (op1
& 0x17) == 0x06)
4188 || (a
&& (op1
& 0x17) == 0x06 && !b
))
4189 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
4190 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
4191 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
4192 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
4193 else if ((!a
&& (op1
& 0x17) == 0x07)
4194 || (a
&& (op1
& 0x17) == 0x07 && !b
))
4195 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
4197 /* Should be unreachable. */
4202 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
4203 struct displaced_step_closure
*dsc
)
4205 switch (bits (insn
, 20, 24))
4207 case 0x00: case 0x01: case 0x02: case 0x03:
4208 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
4210 case 0x04: case 0x05: case 0x06: case 0x07:
4211 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
4213 case 0x08: case 0x09: case 0x0a: case 0x0b:
4214 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
4215 return copy_unmodified (gdbarch
, insn
,
4216 "decode/pack/unpack/saturate/reverse", dsc
);
4219 if (bits (insn
, 5, 7) == 0) /* op2. */
4221 if (bits (insn
, 12, 15) == 0xf)
4222 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
4224 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
4227 return copy_undef (gdbarch
, insn
, dsc
);
4229 case 0x1a: case 0x1b:
4230 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4231 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
4233 return copy_undef (gdbarch
, insn
, dsc
);
4235 case 0x1c: case 0x1d:
4236 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
4238 if (bits (insn
, 0, 3) == 0xf)
4239 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
4241 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
4244 return copy_undef (gdbarch
, insn
, dsc
);
4246 case 0x1e: case 0x1f:
4247 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4248 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
4250 return copy_undef (gdbarch
, insn
, dsc
);
4253 /* Should be unreachable. */
4258 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
4259 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4262 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4264 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
4268 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
4269 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4271 unsigned int opcode
= bits (insn
, 20, 24);
4275 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
4276 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
4278 case 0x08: case 0x0a: case 0x0c: case 0x0e:
4279 case 0x12: case 0x16:
4280 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
4282 case 0x09: case 0x0b: case 0x0d: case 0x0f:
4283 case 0x13: case 0x17:
4284 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
4286 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
4287 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
4288 /* Note: no writeback for these instructions. Bit 25 will always be
4289 zero though (via caller), so the following works OK. */
4290 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4293 /* Should be unreachable. */
4298 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4299 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4301 unsigned int op1
= bits (insn
, 20, 25);
4302 int op
= bit (insn
, 4);
4303 unsigned int coproc
= bits (insn
, 8, 11);
4304 unsigned int rn
= bits (insn
, 16, 19);
4306 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
4307 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
4308 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
4309 && (coproc
& 0xe) != 0xa)
4311 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4312 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
4313 && (coproc
& 0xe) != 0xa)
4314 /* ldc/ldc2 imm/lit. */
4315 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4316 else if ((op1
& 0x3e) == 0x00)
4317 return copy_undef (gdbarch
, insn
, dsc
);
4318 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
4319 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
4320 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
4321 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4322 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
4323 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4324 else if ((op1
& 0x30) == 0x20 && !op
)
4326 if ((coproc
& 0xe) == 0xa)
4327 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
4329 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4331 else if ((op1
& 0x30) == 0x20 && op
)
4332 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
4333 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
4334 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4335 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
4336 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4337 else if ((op1
& 0x30) == 0x30)
4338 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
4340 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
4344 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
4345 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
4346 struct displaced_step_closure
*dsc
)
4350 if (!displaced_in_arm_mode (regs
))
4351 error (_("Displaced stepping is only supported in ARM mode"));
4353 /* Most displaced instructions use a 1-instruction scratch space, so set this
4354 here and override below if/when necessary. */
4356 dsc
->insn_addr
= from
;
4357 dsc
->scratch_base
= to
;
4358 dsc
->cleanup
= NULL
;
4359 dsc
->wrote_to_pc
= 0;
4361 if ((insn
& 0xf0000000) == 0xf0000000)
4362 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
4363 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
4365 case 0x0: case 0x1: case 0x2: case 0x3:
4366 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
4369 case 0x4: case 0x5: case 0x6:
4370 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
4374 err
= decode_media (gdbarch
, insn
, dsc
);
4377 case 0x8: case 0x9: case 0xa: case 0xb:
4378 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
4381 case 0xc: case 0xd: case 0xe: case 0xf:
4382 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
4387 internal_error (__FILE__
, __LINE__
,
4388 _("arm_process_displaced_insn: Instruction decode error"));
4391 /* Actually set up the scratch space for a displaced instruction. */
4394 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
4395 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
4397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4399 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4401 /* Poke modified instruction(s). */
4402 for (i
= 0; i
< dsc
->numinsns
; i
++)
4404 if (debug_displaced
)
4405 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
4406 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
4407 (unsigned long) to
+ i
* 4);
4408 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
4412 /* Put breakpoint afterwards. */
4413 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
4414 tdep
->arm_breakpoint_size
);
4416 if (debug_displaced
)
4417 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
4418 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
4421 /* Entry point for copying an instruction into scratch space for displaced
4424 struct displaced_step_closure
*
4425 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
4426 CORE_ADDR from
, CORE_ADDR to
,
4427 struct regcache
*regs
)
4429 struct displaced_step_closure
*dsc
4430 = xmalloc (sizeof (struct displaced_step_closure
));
4431 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4432 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
4434 if (debug_displaced
)
4435 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
4436 "at %.8lx\n", (unsigned long) insn
,
4437 (unsigned long) from
);
4439 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
4440 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
4445 /* Entry point for cleaning things up after a displaced instruction has been
4449 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
4450 struct displaced_step_closure
*dsc
,
4451 CORE_ADDR from
, CORE_ADDR to
,
4452 struct regcache
*regs
)
4455 dsc
->cleanup (gdbarch
, regs
, dsc
);
4457 if (!dsc
->wrote_to_pc
)
4458 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
4461 #include "bfd-in2.h"
4462 #include "libcoff.h"
4465 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
4467 if (arm_pc_is_thumb (memaddr
))
4469 static asymbol
*asym
;
4470 static combined_entry_type ce
;
4471 static struct coff_symbol_struct csym
;
4472 static struct bfd fake_bfd
;
4473 static bfd_target fake_target
;
4475 if (csym
.native
== NULL
)
4477 /* Create a fake symbol vector containing a Thumb symbol.
4478 This is solely so that the code in print_insn_little_arm()
4479 and print_insn_big_arm() in opcodes/arm-dis.c will detect
4480 the presence of a Thumb symbol and switch to decoding
4481 Thumb instructions. */
4483 fake_target
.flavour
= bfd_target_coff_flavour
;
4484 fake_bfd
.xvec
= &fake_target
;
4485 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
4487 csym
.symbol
.the_bfd
= &fake_bfd
;
4488 csym
.symbol
.name
= "fake";
4489 asym
= (asymbol
*) & csym
;
4492 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
4493 info
->symbols
= &asym
;
4496 info
->symbols
= NULL
;
4498 if (info
->endian
== BFD_ENDIAN_BIG
)
4499 return print_insn_big_arm (memaddr
, info
);
4501 return print_insn_little_arm (memaddr
, info
);
4504 /* The following define instruction sequences that will cause ARM
4505 cpu's to take an undefined instruction trap. These are used to
4506 signal a breakpoint to GDB.
4508 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
4509 modes. A different instruction is required for each mode. The ARM
4510 cpu's can also be big or little endian. Thus four different
4511 instructions are needed to support all cases.
4513 Note: ARMv4 defines several new instructions that will take the
4514 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
4515 not in fact add the new instructions. The new undefined
4516 instructions in ARMv4 are all instructions that had no defined
4517 behaviour in earlier chips. There is no guarantee that they will
4518 raise an exception, but may be treated as NOP's. In practice, it
4519 may only safe to rely on instructions matching:
4521 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
4522 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4523 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
4525 Even this may only true if the condition predicate is true. The
4526 following use a condition predicate of ALWAYS so it is always TRUE.
4528 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
4529 and NetBSD all use a software interrupt rather than an undefined
4530 instruction to force a trap. This can be handled by by the
4531 abi-specific code during establishment of the gdbarch vector. */
4533 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
4534 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
4535 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
4536 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
4538 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
4539 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
4540 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
4541 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
4543 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
4544 the program counter value to determine whether a 16-bit or 32-bit
4545 breakpoint should be used. It returns a pointer to a string of
4546 bytes that encode a breakpoint instruction, stores the length of
4547 the string to *lenptr, and adjusts the program counter (if
4548 necessary) to point to the actual memory location where the
4549 breakpoint should be inserted. */
4551 static const unsigned char *
4552 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4554 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4556 if (arm_pc_is_thumb (*pcptr
))
4558 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
4559 *lenptr
= tdep
->thumb_breakpoint_size
;
4560 return tdep
->thumb_breakpoint
;
4564 *lenptr
= tdep
->arm_breakpoint_size
;
4565 return tdep
->arm_breakpoint
;
4569 /* Extract from an array REGBUF containing the (raw) register state a
4570 function return value of type TYPE, and copy that, in virtual
4571 format, into VALBUF. */
4574 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
4577 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
4578 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4580 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
4582 switch (gdbarch_tdep (gdbarch
)->fp_model
)
4586 /* The value is in register F0 in internal format. We need to
4587 extract the raw value and then convert it to the desired
4589 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
4591 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
4592 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
4593 valbuf
, gdbarch_byte_order (gdbarch
));
4597 case ARM_FLOAT_SOFT_FPA
:
4598 case ARM_FLOAT_SOFT_VFP
:
4599 /* ARM_FLOAT_VFP can arise if this is a variadic function so
4600 not using the VFP ABI code. */
4602 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
4603 if (TYPE_LENGTH (type
) > 4)
4604 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
4605 valbuf
+ INT_REGISTER_SIZE
);
4610 (__FILE__
, __LINE__
,
4611 _("arm_extract_return_value: Floating point model not supported"));
4615 else if (TYPE_CODE (type
) == TYPE_CODE_INT
4616 || TYPE_CODE (type
) == TYPE_CODE_CHAR
4617 || TYPE_CODE (type
) == TYPE_CODE_BOOL
4618 || TYPE_CODE (type
) == TYPE_CODE_PTR
4619 || TYPE_CODE (type
) == TYPE_CODE_REF
4620 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
4622 /* If the the type is a plain integer, then the access is
4623 straight-forward. Otherwise we have to play around a bit more. */
4624 int len
= TYPE_LENGTH (type
);
4625 int regno
= ARM_A1_REGNUM
;
4630 /* By using store_unsigned_integer we avoid having to do
4631 anything special for small big-endian values. */
4632 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
4633 store_unsigned_integer (valbuf
,
4634 (len
> INT_REGISTER_SIZE
4635 ? INT_REGISTER_SIZE
: len
),
4637 len
-= INT_REGISTER_SIZE
;
4638 valbuf
+= INT_REGISTER_SIZE
;
4643 /* For a structure or union the behaviour is as if the value had
4644 been stored to word-aligned memory and then loaded into
4645 registers with 32-bit load instruction(s). */
4646 int len
= TYPE_LENGTH (type
);
4647 int regno
= ARM_A1_REGNUM
;
4648 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
4652 regcache_cooked_read (regs
, regno
++, tmpbuf
);
4653 memcpy (valbuf
, tmpbuf
,
4654 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
4655 len
-= INT_REGISTER_SIZE
;
4656 valbuf
+= INT_REGISTER_SIZE
;
4662 /* Will a function return an aggregate type in memory or in a
4663 register? Return 0 if an aggregate type can be returned in a
4664 register, 1 if it must be returned in memory. */
4667 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
4670 enum type_code code
;
4672 CHECK_TYPEDEF (type
);
4674 /* In the ARM ABI, "integer" like aggregate types are returned in
4675 registers. For an aggregate type to be integer like, its size
4676 must be less than or equal to INT_REGISTER_SIZE and the
4677 offset of each addressable subfield must be zero. Note that bit
4678 fields are not addressable, and all addressable subfields of
4679 unions always start at offset zero.
4681 This function is based on the behaviour of GCC 2.95.1.
4682 See: gcc/arm.c: arm_return_in_memory() for details.
4684 Note: All versions of GCC before GCC 2.95.2 do not set up the
4685 parameters correctly for a function returning the following
4686 structure: struct { float f;}; This should be returned in memory,
4687 not a register. Richard Earnshaw sent me a patch, but I do not
4688 know of any way to detect if a function like the above has been
4689 compiled with the correct calling convention. */
4691 /* All aggregate types that won't fit in a register must be returned
4693 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
4698 /* The AAPCS says all aggregates not larger than a word are returned
4700 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
4703 /* The only aggregate types that can be returned in a register are
4704 structs and unions. Arrays must be returned in memory. */
4705 code
= TYPE_CODE (type
);
4706 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
4711 /* Assume all other aggregate types can be returned in a register.
4712 Run a check for structures, unions and arrays. */
4715 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
4718 /* Need to check if this struct/union is "integer" like. For
4719 this to be true, its size must be less than or equal to
4720 INT_REGISTER_SIZE and the offset of each addressable
4721 subfield must be zero. Note that bit fields are not
4722 addressable, and unions always start at offset zero. If any
4723 of the subfields is a floating point type, the struct/union
4724 cannot be an integer type. */
4726 /* For each field in the object, check:
4727 1) Is it FP? --> yes, nRc = 1;
4728 2) Is it addressable (bitpos != 0) and
4729 not packed (bitsize == 0)?
4733 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
4735 enum type_code field_type_code
;
4736 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
4738 /* Is it a floating point type field? */
4739 if (field_type_code
== TYPE_CODE_FLT
)
4745 /* If bitpos != 0, then we have to care about it. */
4746 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
4748 /* Bitfields are not addressable. If the field bitsize is
4749 zero, then the field is not packed. Hence it cannot be
4750 a bitfield or any other packed type. */
4751 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
4763 /* Write into appropriate registers a function return value of type
4764 TYPE, given in virtual format. */
4767 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
4768 const gdb_byte
*valbuf
)
4770 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
4771 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4773 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4775 char buf
[MAX_REGISTER_SIZE
];
4777 switch (gdbarch_tdep (gdbarch
)->fp_model
)
4781 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
4782 gdbarch_byte_order (gdbarch
));
4783 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
4786 case ARM_FLOAT_SOFT_FPA
:
4787 case ARM_FLOAT_SOFT_VFP
:
4788 /* ARM_FLOAT_VFP can arise if this is a variadic function so
4789 not using the VFP ABI code. */
4791 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
4792 if (TYPE_LENGTH (type
) > 4)
4793 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
4794 valbuf
+ INT_REGISTER_SIZE
);
4799 (__FILE__
, __LINE__
,
4800 _("arm_store_return_value: Floating point model not supported"));
4804 else if (TYPE_CODE (type
) == TYPE_CODE_INT
4805 || TYPE_CODE (type
) == TYPE_CODE_CHAR
4806 || TYPE_CODE (type
) == TYPE_CODE_BOOL
4807 || TYPE_CODE (type
) == TYPE_CODE_PTR
4808 || TYPE_CODE (type
) == TYPE_CODE_REF
4809 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
4811 if (TYPE_LENGTH (type
) <= 4)
4813 /* Values of one word or less are zero/sign-extended and
4815 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
4816 LONGEST val
= unpack_long (type
, valbuf
);
4818 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
4819 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
4823 /* Integral values greater than one word are stored in consecutive
4824 registers starting with r0. This will always be a multiple of
4825 the regiser size. */
4826 int len
= TYPE_LENGTH (type
);
4827 int regno
= ARM_A1_REGNUM
;
4831 regcache_cooked_write (regs
, regno
++, valbuf
);
4832 len
-= INT_REGISTER_SIZE
;
4833 valbuf
+= INT_REGISTER_SIZE
;
4839 /* For a structure or union the behaviour is as if the value had
4840 been stored to word-aligned memory and then loaded into
4841 registers with 32-bit load instruction(s). */
4842 int len
= TYPE_LENGTH (type
);
4843 int regno
= ARM_A1_REGNUM
;
4844 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
4848 memcpy (tmpbuf
, valbuf
,
4849 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
4850 regcache_cooked_write (regs
, regno
++, tmpbuf
);
4851 len
-= INT_REGISTER_SIZE
;
4852 valbuf
+= INT_REGISTER_SIZE
;
4858 /* Handle function return values. */
4860 static enum return_value_convention
4861 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4862 struct type
*valtype
, struct regcache
*regcache
,
4863 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4865 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4866 enum arm_vfp_cprc_base_type vfp_base_type
;
4869 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
4870 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
4872 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
4873 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
4875 for (i
= 0; i
< vfp_base_count
; i
++)
4877 if (reg_char
== 'q')
4880 arm_neon_quad_write (gdbarch
, regcache
, i
,
4881 writebuf
+ i
* unit_length
);
4884 arm_neon_quad_read (gdbarch
, regcache
, i
,
4885 readbuf
+ i
* unit_length
);
4892 sprintf (name_buf
, "%c%d", reg_char
, i
);
4893 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4896 regcache_cooked_write (regcache
, regnum
,
4897 writebuf
+ i
* unit_length
);
4899 regcache_cooked_read (regcache
, regnum
,
4900 readbuf
+ i
* unit_length
);
4903 return RETURN_VALUE_REGISTER_CONVENTION
;
4906 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
4907 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
4908 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
4910 if (tdep
->struct_return
== pcc_struct_return
4911 || arm_return_in_memory (gdbarch
, valtype
))
4912 return RETURN_VALUE_STRUCT_CONVENTION
;
4916 arm_store_return_value (valtype
, regcache
, writebuf
);
4919 arm_extract_return_value (valtype
, regcache
, readbuf
);
4921 return RETURN_VALUE_REGISTER_CONVENTION
;
4926 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
4928 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4930 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4932 char buf
[INT_REGISTER_SIZE
];
4934 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
4936 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
4940 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
4944 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
4945 return the target PC. Otherwise return 0. */
4948 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
4952 CORE_ADDR start_addr
;
4954 /* Find the starting address and name of the function containing the PC. */
4955 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4958 /* If PC is in a Thumb call or return stub, return the address of the
4959 target PC, which is in a register. The thunk functions are called
4960 _call_via_xx, where x is the register name. The possible names
4961 are r0-r9, sl, fp, ip, sp, and lr. */
4962 if (strncmp (name
, "_call_via_", 10) == 0)
4964 /* Use the name suffix to determine which register contains the
4966 static char *table
[15] =
4967 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4968 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
4971 int offset
= strlen (name
) - 2;
4973 for (regno
= 0; regno
<= 14; regno
++)
4974 if (strcmp (&name
[offset
], table
[regno
]) == 0)
4975 return get_frame_register_unsigned (frame
, regno
);
4978 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
4979 non-interworking calls to foo. We could decode the stubs
4980 to find the target but it's easier to use the symbol table. */
4981 namelen
= strlen (name
);
4982 if (name
[0] == '_' && name
[1] == '_'
4983 && ((namelen
> 2 + strlen ("_from_thumb")
4984 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
4985 strlen ("_from_thumb")) == 0)
4986 || (namelen
> 2 + strlen ("_from_arm")
4987 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
4988 strlen ("_from_arm")) == 0)))
4991 int target_len
= namelen
- 2;
4992 struct minimal_symbol
*minsym
;
4993 struct objfile
*objfile
;
4994 struct obj_section
*sec
;
4996 if (name
[namelen
- 1] == 'b')
4997 target_len
-= strlen ("_from_thumb");
4999 target_len
-= strlen ("_from_arm");
5001 target_name
= alloca (target_len
+ 1);
5002 memcpy (target_name
, name
+ 2, target_len
);
5003 target_name
[target_len
] = '\0';
5005 sec
= find_pc_section (pc
);
5006 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
5007 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
5009 return SYMBOL_VALUE_ADDRESS (minsym
);
5014 return 0; /* not a stub */
5018 set_arm_command (char *args
, int from_tty
)
5020 printf_unfiltered (_("\
5021 \"set arm\" must be followed by an apporpriate subcommand.\n"));
5022 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
5026 show_arm_command (char *args
, int from_tty
)
5028 cmd_show_list (showarmcmdlist
, from_tty
, "");
5032 arm_update_current_architecture (void)
5034 struct gdbarch_info info
;
5036 /* If the current architecture is not ARM, we have nothing to do. */
5037 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
5040 /* Update the architecture. */
5041 gdbarch_info_init (&info
);
5043 if (!gdbarch_update_p (info
))
5044 internal_error (__FILE__
, __LINE__
, "could not update architecture");
5048 set_fp_model_sfunc (char *args
, int from_tty
,
5049 struct cmd_list_element
*c
)
5051 enum arm_float_model fp_model
;
5053 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
5054 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
5056 arm_fp_model
= fp_model
;
5060 if (fp_model
== ARM_FLOAT_LAST
)
5061 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
5064 arm_update_current_architecture ();
5068 show_fp_model (struct ui_file
*file
, int from_tty
,
5069 struct cmd_list_element
*c
, const char *value
)
5071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5073 if (arm_fp_model
== ARM_FLOAT_AUTO
5074 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5075 fprintf_filtered (file
, _("\
5076 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
5077 fp_model_strings
[tdep
->fp_model
]);
5079 fprintf_filtered (file
, _("\
5080 The current ARM floating point model is \"%s\".\n"),
5081 fp_model_strings
[arm_fp_model
]);
5085 arm_set_abi (char *args
, int from_tty
,
5086 struct cmd_list_element
*c
)
5088 enum arm_abi_kind arm_abi
;
5090 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
5091 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
5093 arm_abi_global
= arm_abi
;
5097 if (arm_abi
== ARM_ABI_LAST
)
5098 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
5101 arm_update_current_architecture ();
5105 arm_show_abi (struct ui_file
*file
, int from_tty
,
5106 struct cmd_list_element
*c
, const char *value
)
5108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5110 if (arm_abi_global
== ARM_ABI_AUTO
5111 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5112 fprintf_filtered (file
, _("\
5113 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
5114 arm_abi_strings
[tdep
->arm_abi
]);
5116 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
5121 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
5122 struct cmd_list_element
*c
, const char *value
)
5124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5126 fprintf_filtered (file
, _("\
5127 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
5128 arm_fallback_mode_string
);
5132 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
5133 struct cmd_list_element
*c
, const char *value
)
5135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5137 fprintf_filtered (file
, _("\
5138 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
5139 arm_force_mode_string
);
5142 /* If the user changes the register disassembly style used for info
5143 register and other commands, we have to also switch the style used
5144 in opcodes for disassembly output. This function is run in the "set
5145 arm disassembly" command, and does that. */
5148 set_disassembly_style_sfunc (char *args
, int from_tty
,
5149 struct cmd_list_element
*c
)
5151 set_disassembly_style ();
5154 /* Return the ARM register name corresponding to register I. */
5156 arm_register_name (struct gdbarch
*gdbarch
, int i
)
5158 const int num_regs
= gdbarch_num_regs (gdbarch
);
5160 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
5161 && i
>= num_regs
&& i
< num_regs
+ 32)
5163 static const char *const vfp_pseudo_names
[] = {
5164 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5165 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5166 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5167 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5170 return vfp_pseudo_names
[i
- num_regs
];
5173 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
5174 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
5176 static const char *const neon_pseudo_names
[] = {
5177 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5178 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
5181 return neon_pseudo_names
[i
- num_regs
- 32];
5184 if (i
>= ARRAY_SIZE (arm_register_names
))
5185 /* These registers are only supported on targets which supply
5186 an XML description. */
5189 return arm_register_names
[i
];
5193 set_disassembly_style (void)
5197 /* Find the style that the user wants. */
5198 for (current
= 0; current
< num_disassembly_options
; current
++)
5199 if (disassembly_style
== valid_disassembly_styles
[current
])
5201 gdb_assert (current
< num_disassembly_options
);
5203 /* Synchronize the disassembler. */
5204 set_arm_regname_option (current
);
5207 /* Test whether the coff symbol specific value corresponds to a Thumb
5211 coff_sym_is_thumb (int val
)
5213 return (val
== C_THUMBEXT
5214 || val
== C_THUMBSTAT
5215 || val
== C_THUMBEXTFUNC
5216 || val
== C_THUMBSTATFUNC
5217 || val
== C_THUMBLABEL
);
5220 /* arm_coff_make_msymbol_special()
5221 arm_elf_make_msymbol_special()
5223 These functions test whether the COFF or ELF symbol corresponds to
5224 an address in thumb code, and set a "special" bit in a minimal
5225 symbol to indicate that it does. */
5228 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
5230 /* Thumb symbols are of type STT_LOPROC, (synonymous with
5232 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
5234 MSYMBOL_SET_SPECIAL (msym
);
5238 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
5240 if (coff_sym_is_thumb (val
))
5241 MSYMBOL_SET_SPECIAL (msym
);
5245 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
5247 struct arm_per_objfile
*data
= arg
;
5250 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
5251 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
5255 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
5258 const char *name
= bfd_asymbol_name (sym
);
5259 struct arm_per_objfile
*data
;
5260 VEC(arm_mapping_symbol_s
) **map_p
;
5261 struct arm_mapping_symbol new_map_sym
;
5263 gdb_assert (name
[0] == '$');
5264 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
5267 data
= objfile_data (objfile
, arm_objfile_data_key
);
5270 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
5271 struct arm_per_objfile
);
5272 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
5273 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
5274 objfile
->obfd
->section_count
,
5275 VEC(arm_mapping_symbol_s
) *);
5277 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
5279 new_map_sym
.value
= sym
->value
;
5280 new_map_sym
.type
= name
[1];
5282 /* Assume that most mapping symbols appear in order of increasing
5283 value. If they were randomly distributed, it would be faster to
5284 always push here and then sort at first use. */
5285 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
5287 struct arm_mapping_symbol
*prev_map_sym
;
5289 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
5290 if (prev_map_sym
->value
>= sym
->value
)
5293 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
5294 arm_compare_mapping_symbols
);
5295 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
5300 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
5304 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
5306 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
5308 /* If necessary, set the T bit. */
5312 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
5313 if (arm_pc_is_thumb (pc
))
5314 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
5316 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
5317 val
& ~(ULONGEST
) CPSR_T
);
5321 /* Read the contents of a NEON quad register, by reading from two
5322 double registers. This is used to implement the quad pseudo
5323 registers, and for argument passing in case the quad registers are
5324 missing; vectors are passed in quad registers when using the VFP
5325 ABI, even if a NEON unit is not present. REGNUM is the index of
5326 the quad register, in [0, 15]. */
5329 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5330 int regnum
, gdb_byte
*buf
)
5333 gdb_byte reg_buf
[8];
5334 int offset
, double_regnum
;
5336 sprintf (name_buf
, "d%d", regnum
<< 1);
5337 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5340 /* d0 is always the least significant half of q0. */
5341 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5346 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5347 memcpy (buf
+ offset
, reg_buf
, 8);
5349 offset
= 8 - offset
;
5350 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
5351 memcpy (buf
+ offset
, reg_buf
, 8);
5355 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5356 int regnum
, gdb_byte
*buf
)
5358 const int num_regs
= gdbarch_num_regs (gdbarch
);
5360 gdb_byte reg_buf
[8];
5361 int offset
, double_regnum
;
5363 gdb_assert (regnum
>= num_regs
);
5366 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
5367 /* Quad-precision register. */
5368 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
5371 /* Single-precision register. */
5372 gdb_assert (regnum
< 32);
5374 /* s0 is always the least significant half of d0. */
5375 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5376 offset
= (regnum
& 1) ? 0 : 4;
5378 offset
= (regnum
& 1) ? 4 : 0;
5380 sprintf (name_buf
, "d%d", regnum
>> 1);
5381 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5384 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5385 memcpy (buf
, reg_buf
+ offset
, 4);
5389 /* Store the contents of BUF to a NEON quad register, by writing to
5390 two double registers. This is used to implement the quad pseudo
5391 registers, and for argument passing in case the quad registers are
5392 missing; vectors are passed in quad registers when using the VFP
5393 ABI, even if a NEON unit is not present. REGNUM is the index
5394 of the quad register, in [0, 15]. */
5397 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5398 int regnum
, const gdb_byte
*buf
)
5401 gdb_byte reg_buf
[8];
5402 int offset
, double_regnum
;
5404 sprintf (name_buf
, "d%d", regnum
<< 1);
5405 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5408 /* d0 is always the least significant half of q0. */
5409 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5414 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
5415 offset
= 8 - offset
;
5416 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
5420 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5421 int regnum
, const gdb_byte
*buf
)
5423 const int num_regs
= gdbarch_num_regs (gdbarch
);
5425 gdb_byte reg_buf
[8];
5426 int offset
, double_regnum
;
5428 gdb_assert (regnum
>= num_regs
);
5431 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
5432 /* Quad-precision register. */
5433 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
5436 /* Single-precision register. */
5437 gdb_assert (regnum
< 32);
5439 /* s0 is always the least significant half of d0. */
5440 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5441 offset
= (regnum
& 1) ? 0 : 4;
5443 offset
= (regnum
& 1) ? 4 : 0;
5445 sprintf (name_buf
, "d%d", regnum
>> 1);
5446 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5449 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5450 memcpy (reg_buf
+ offset
, buf
, 4);
5451 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
5455 static struct value
*
5456 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
5458 const int *reg_p
= baton
;
5459 return value_of_register (*reg_p
, frame
);
5462 static enum gdb_osabi
5463 arm_elf_osabi_sniffer (bfd
*abfd
)
5465 unsigned int elfosabi
;
5466 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
5468 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
5470 if (elfosabi
== ELFOSABI_ARM
)
5471 /* GNU tools use this value. Check note sections in this case,
5473 bfd_map_over_sections (abfd
,
5474 generic_elf_osabi_sniff_abi_tag_sections
,
5477 /* Anything else will be handled by the generic ELF sniffer. */
5482 /* Initialize the current architecture based on INFO. If possible,
5483 re-use an architecture from ARCHES, which is a list of
5484 architectures already created during this debugging session.
5486 Called e.g. at program startup, when reading a core file, and when
5487 reading a binary file. */
5489 static struct gdbarch
*
5490 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5492 struct gdbarch_tdep
*tdep
;
5493 struct gdbarch
*gdbarch
;
5494 struct gdbarch_list
*best_arch
;
5495 enum arm_abi_kind arm_abi
= arm_abi_global
;
5496 enum arm_float_model fp_model
= arm_fp_model
;
5497 struct tdesc_arch_data
*tdesc_data
= NULL
;
5499 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
5501 int have_fpa_registers
= 1;
5503 /* Check any target description for validity. */
5504 if (tdesc_has_registers (info
.target_desc
))
5506 /* For most registers we require GDB's default names; but also allow
5507 the numeric names for sp / lr / pc, as a convenience. */
5508 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
5509 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
5510 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
5512 const struct tdesc_feature
*feature
;
5515 feature
= tdesc_find_feature (info
.target_desc
,
5516 "org.gnu.gdb.arm.core");
5517 if (feature
== NULL
)
5520 tdesc_data
= tdesc_data_alloc ();
5523 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
5524 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5525 arm_register_names
[i
]);
5526 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5529 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5532 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5535 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5536 ARM_PS_REGNUM
, "cpsr");
5540 tdesc_data_cleanup (tdesc_data
);
5544 feature
= tdesc_find_feature (info
.target_desc
,
5545 "org.gnu.gdb.arm.fpa");
5546 if (feature
!= NULL
)
5549 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
5550 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5551 arm_register_names
[i
]);
5554 tdesc_data_cleanup (tdesc_data
);
5559 have_fpa_registers
= 0;
5561 feature
= tdesc_find_feature (info
.target_desc
,
5562 "org.gnu.gdb.xscale.iwmmxt");
5563 if (feature
!= NULL
)
5565 static const char *const iwmmxt_names
[] = {
5566 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
5567 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
5568 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
5569 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
5573 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
5575 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
5576 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5578 /* Check for the control registers, but do not fail if they
5580 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
5581 tdesc_numbered_register (feature
, tdesc_data
, i
,
5582 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5584 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
5586 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
5587 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5591 tdesc_data_cleanup (tdesc_data
);
5596 /* If we have a VFP unit, check whether the single precision registers
5597 are present. If not, then we will synthesize them as pseudo
5599 feature
= tdesc_find_feature (info
.target_desc
,
5600 "org.gnu.gdb.arm.vfp");
5601 if (feature
!= NULL
)
5603 static const char *const vfp_double_names
[] = {
5604 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5605 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5606 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5607 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5610 /* Require the double precision registers. There must be either
5613 for (i
= 0; i
< 32; i
++)
5615 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5617 vfp_double_names
[i
]);
5622 if (!valid_p
&& i
!= 16)
5624 tdesc_data_cleanup (tdesc_data
);
5628 if (tdesc_unnumbered_register (feature
, "s0") == 0)
5629 have_vfp_pseudos
= 1;
5631 have_vfp_registers
= 1;
5633 /* If we have VFP, also check for NEON. The architecture allows
5634 NEON without VFP (integer vector operations only), but GDB
5635 does not support that. */
5636 feature
= tdesc_find_feature (info
.target_desc
,
5637 "org.gnu.gdb.arm.neon");
5638 if (feature
!= NULL
)
5640 /* NEON requires 32 double-precision registers. */
5643 tdesc_data_cleanup (tdesc_data
);
5647 /* If there are quad registers defined by the stub, use
5648 their type; otherwise (normally) provide them with
5649 the default type. */
5650 if (tdesc_unnumbered_register (feature
, "q0") == 0)
5651 have_neon_pseudos
= 1;
5658 /* If we have an object to base this architecture on, try to determine
5661 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
5663 int ei_osabi
, e_flags
;
5665 switch (bfd_get_flavour (info
.abfd
))
5667 case bfd_target_aout_flavour
:
5668 /* Assume it's an old APCS-style ABI. */
5669 arm_abi
= ARM_ABI_APCS
;
5672 case bfd_target_coff_flavour
:
5673 /* Assume it's an old APCS-style ABI. */
5675 arm_abi
= ARM_ABI_APCS
;
5678 case bfd_target_elf_flavour
:
5679 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
5680 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5682 if (ei_osabi
== ELFOSABI_ARM
)
5684 /* GNU tools used to use this value, but do not for EABI
5685 objects. There's nowhere to tag an EABI version
5686 anyway, so assume APCS. */
5687 arm_abi
= ARM_ABI_APCS
;
5689 else if (ei_osabi
== ELFOSABI_NONE
)
5691 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
5695 case EF_ARM_EABI_UNKNOWN
:
5696 /* Assume GNU tools. */
5697 arm_abi
= ARM_ABI_APCS
;
5700 case EF_ARM_EABI_VER4
:
5701 case EF_ARM_EABI_VER5
:
5702 arm_abi
= ARM_ABI_AAPCS
;
5703 /* EABI binaries default to VFP float ordering.
5704 They may also contain build attributes that can
5705 be used to identify if the VFP argument-passing
5707 if (fp_model
== ARM_FLOAT_AUTO
)
5710 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
5715 /* "The user intended FP parameter/result
5716 passing to conform to AAPCS, base
5718 fp_model
= ARM_FLOAT_SOFT_VFP
;
5721 /* "The user intended FP parameter/result
5722 passing to conform to AAPCS, VFP
5724 fp_model
= ARM_FLOAT_VFP
;
5727 /* "The user intended FP parameter/result
5728 passing to conform to tool chain-specific
5729 conventions" - we don't know any such
5730 conventions, so leave it as "auto". */
5733 /* Attribute value not mentioned in the
5734 October 2008 ABI, so leave it as
5739 fp_model
= ARM_FLOAT_SOFT_VFP
;
5745 /* Leave it as "auto". */
5746 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
5751 if (fp_model
== ARM_FLOAT_AUTO
)
5753 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5755 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
5758 /* Leave it as "auto". Strictly speaking this case
5759 means FPA, but almost nobody uses that now, and
5760 many toolchains fail to set the appropriate bits
5761 for the floating-point model they use. */
5763 case EF_ARM_SOFT_FLOAT
:
5764 fp_model
= ARM_FLOAT_SOFT_FPA
;
5766 case EF_ARM_VFP_FLOAT
:
5767 fp_model
= ARM_FLOAT_VFP
;
5769 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
5770 fp_model
= ARM_FLOAT_SOFT_VFP
;
5775 if (e_flags
& EF_ARM_BE8
)
5776 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
5781 /* Leave it as "auto". */
5786 /* If there is already a candidate, use it. */
5787 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
5789 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
5791 if (arm_abi
!= ARM_ABI_AUTO
5792 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
5795 if (fp_model
!= ARM_FLOAT_AUTO
5796 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
5799 /* There are various other properties in tdep that we do not
5800 need to check here: those derived from a target description,
5801 since gdbarches with a different target description are
5802 automatically disqualified. */
5804 /* Found a match. */
5808 if (best_arch
!= NULL
)
5810 if (tdesc_data
!= NULL
)
5811 tdesc_data_cleanup (tdesc_data
);
5812 return best_arch
->gdbarch
;
5815 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
5816 gdbarch
= gdbarch_alloc (&info
, tdep
);
5818 /* Record additional information about the architecture we are defining.
5819 These are gdbarch discriminators, like the OSABI. */
5820 tdep
->arm_abi
= arm_abi
;
5821 tdep
->fp_model
= fp_model
;
5822 tdep
->have_fpa_registers
= have_fpa_registers
;
5823 tdep
->have_vfp_registers
= have_vfp_registers
;
5824 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
5825 tdep
->have_neon_pseudos
= have_neon_pseudos
;
5826 tdep
->have_neon
= have_neon
;
5829 switch (info
.byte_order_for_code
)
5831 case BFD_ENDIAN_BIG
:
5832 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
5833 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
5834 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
5835 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
5839 case BFD_ENDIAN_LITTLE
:
5840 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
5841 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
5842 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
5843 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
5848 internal_error (__FILE__
, __LINE__
,
5849 _("arm_gdbarch_init: bad byte order for float format"));
5852 /* On ARM targets char defaults to unsigned. */
5853 set_gdbarch_char_signed (gdbarch
, 0);
5855 /* Note: for displaced stepping, this includes the breakpoint, and one word
5856 of additional scratch space. This setting isn't used for anything beside
5857 displaced stepping at present. */
5858 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
5860 /* This should be low enough for everything. */
5861 tdep
->lowest_pc
= 0x20;
5862 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
5864 /* The default, for both APCS and AAPCS, is to return small
5865 structures in registers. */
5866 tdep
->struct_return
= reg_struct_return
;
5868 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
5869 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
5871 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
5873 /* Frame handling. */
5874 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
5875 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
5876 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
5878 frame_base_set_default (gdbarch
, &arm_normal_base
);
5880 /* Address manipulation. */
5881 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
5882 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
5884 /* Advance PC across function entry code. */
5885 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
5887 /* Skip trampolines. */
5888 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
5890 /* The stack grows downward. */
5891 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5893 /* Breakpoint manipulation. */
5894 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
5896 /* Information about registers, etc. */
5897 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
5898 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
5899 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
5900 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
5901 set_gdbarch_register_type (gdbarch
, arm_register_type
);
5903 /* This "info float" is FPA-specific. Use the generic version if we
5905 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
5906 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
5908 /* Internal <-> external register number maps. */
5909 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
5910 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
5912 set_gdbarch_register_name (gdbarch
, arm_register_name
);
5914 /* Returning results. */
5915 set_gdbarch_return_value (gdbarch
, arm_return_value
);
5918 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
5920 /* Minsymbol frobbing. */
5921 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
5922 set_gdbarch_coff_make_msymbol_special (gdbarch
,
5923 arm_coff_make_msymbol_special
);
5924 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
5926 /* Virtual tables. */
5927 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5929 /* Hook in the ABI-specific overrides, if they have been registered. */
5930 gdbarch_init_osabi (info
, gdbarch
);
5932 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
5934 /* Add some default predicates. */
5935 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
5936 dwarf2_append_unwinders (gdbarch
);
5937 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
5939 /* Now we have tuned the configuration, set a few final things,
5940 based on what the OS ABI has told us. */
5942 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
5943 binaries are always marked. */
5944 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
5945 tdep
->arm_abi
= ARM_ABI_APCS
;
5947 /* We used to default to FPA for generic ARM, but almost nobody
5948 uses that now, and we now provide a way for the user to force
5949 the model. So default to the most useful variant. */
5950 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
5951 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
5953 if (tdep
->jb_pc
>= 0)
5954 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
5956 /* Floating point sizes and format. */
5957 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
5958 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
5960 set_gdbarch_double_format
5961 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
5962 set_gdbarch_long_double_format
5963 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
5967 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
5968 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
5971 if (have_vfp_pseudos
)
5973 /* NOTE: These are the only pseudo registers used by
5974 the ARM target at the moment. If more are added, a
5975 little more care in numbering will be needed. */
5977 int num_pseudos
= 32;
5978 if (have_neon_pseudos
)
5980 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
5981 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
5982 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
5987 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
5989 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5991 /* Override tdesc_register_type to adjust the types of VFP
5992 registers for NEON. */
5993 set_gdbarch_register_type (gdbarch
, arm_register_type
);
5996 /* Add standard register aliases. We add aliases even for those
5997 nanes which are used by the current architecture - it's simpler,
5998 and does no harm, since nothing ever lists user registers. */
5999 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
6000 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
6001 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
6007 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6009 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6014 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
6015 (unsigned long) tdep
->lowest_pc
);
6018 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
6021 _initialize_arm_tdep (void)
6023 struct ui_file
*stb
;
6025 struct cmd_list_element
*new_set
, *new_show
;
6026 const char *setname
;
6027 const char *setdesc
;
6028 const char *const *regnames
;
6030 static char *helptext
;
6031 char regdesc
[1024], *rdptr
= regdesc
;
6032 size_t rest
= sizeof (regdesc
);
6034 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
6036 arm_objfile_data_key
6037 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
6039 /* Register an ELF OS ABI sniffer for ARM binaries. */
6040 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
6041 bfd_target_elf_flavour
,
6042 arm_elf_osabi_sniffer
);
6044 /* Get the number of possible sets of register names defined in opcodes. */
6045 num_disassembly_options
= get_arm_regname_num_options ();
6047 /* Add root prefix command for all "set arm"/"show arm" commands. */
6048 add_prefix_cmd ("arm", no_class
, set_arm_command
,
6049 _("Various ARM-specific commands."),
6050 &setarmcmdlist
, "set arm ", 0, &setlist
);
6052 add_prefix_cmd ("arm", no_class
, show_arm_command
,
6053 _("Various ARM-specific commands."),
6054 &showarmcmdlist
, "show arm ", 0, &showlist
);
6056 /* Sync the opcode insn printer with our register viewer. */
6057 parse_arm_disassembler_option ("reg-names-std");
6059 /* Initialize the array that will be passed to
6060 add_setshow_enum_cmd(). */
6061 valid_disassembly_styles
6062 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
6063 for (i
= 0; i
< num_disassembly_options
; i
++)
6065 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
6066 valid_disassembly_styles
[i
] = setname
;
6067 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
6070 /* When we find the default names, tell the disassembler to use
6072 if (!strcmp (setname
, "std"))
6074 disassembly_style
= setname
;
6075 set_arm_regname_option (i
);
6078 /* Mark the end of valid options. */
6079 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
6081 /* Create the help text. */
6082 stb
= mem_fileopen ();
6083 fprintf_unfiltered (stb
, "%s%s%s",
6084 _("The valid values are:\n"),
6086 _("The default is \"std\"."));
6087 helptext
= ui_file_xstrdup (stb
, NULL
);
6088 ui_file_delete (stb
);
6090 add_setshow_enum_cmd("disassembler", no_class
,
6091 valid_disassembly_styles
, &disassembly_style
,
6092 _("Set the disassembly style."),
6093 _("Show the disassembly style."),
6095 set_disassembly_style_sfunc
,
6096 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
6097 &setarmcmdlist
, &showarmcmdlist
);
6099 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
6100 _("Set usage of ARM 32-bit mode."),
6101 _("Show usage of ARM 32-bit mode."),
6102 _("When off, a 26-bit PC will be used."),
6104 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
6105 &setarmcmdlist
, &showarmcmdlist
);
6107 /* Add a command to allow the user to force the FPU model. */
6108 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
6109 _("Set the floating point type."),
6110 _("Show the floating point type."),
6111 _("auto - Determine the FP typefrom the OS-ABI.\n\
6112 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
6113 fpa - FPA co-processor (GCC compiled).\n\
6114 softvfp - Software FP with pure-endian doubles.\n\
6115 vfp - VFP co-processor."),
6116 set_fp_model_sfunc
, show_fp_model
,
6117 &setarmcmdlist
, &showarmcmdlist
);
6119 /* Add a command to allow the user to force the ABI. */
6120 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
6123 NULL
, arm_set_abi
, arm_show_abi
,
6124 &setarmcmdlist
, &showarmcmdlist
);
6126 /* Add two commands to allow the user to force the assumed
6128 add_setshow_enum_cmd ("fallback-mode", class_support
,
6129 arm_mode_strings
, &arm_fallback_mode_string
,
6130 _("Set the mode assumed when symbols are unavailable."),
6131 _("Show the mode assumed when symbols are unavailable."),
6132 NULL
, NULL
, arm_show_fallback_mode
,
6133 &setarmcmdlist
, &showarmcmdlist
);
6134 add_setshow_enum_cmd ("force-mode", class_support
,
6135 arm_mode_strings
, &arm_force_mode_string
,
6136 _("Set the mode assumed even when symbols are available."),
6137 _("Show the mode assumed even when symbols are available."),
6138 NULL
, NULL
, arm_show_force_mode
,
6139 &setarmcmdlist
, &showarmcmdlist
);
6141 /* Debugging flag. */
6142 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
6143 _("Set ARM debugging."),
6144 _("Show ARM debugging."),
6145 _("When on, arm-specific debugging is enabled."),
6147 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
6148 &setdebuglist
, &showdebuglist
);