1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data
*arm_objfile_data_key
;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
80 DEF_VEC_O(arm_mapping_symbol_s
);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s
) **section_maps
;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element
*setarmcmdlist
= NULL
;
89 static struct cmd_list_element
*showarmcmdlist
= NULL
;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings
[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
105 static const char *current_fp_model
= "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
118 static const char *arm_abi_string
= "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings
[] =
128 static const char *arm_fallback_mode_string
= "auto";
129 static const char *arm_force_mode_string
= "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options
;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases
[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names
[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles
;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style
;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element
*);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat
*, const void *,
208 static void convert_to_extended (const struct floatformat
*, void *,
211 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
212 struct regcache
*regcache
,
213 int regnum
, gdb_byte
*buf
);
214 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
215 struct regcache
*regcache
,
216 int regnum
, const gdb_byte
*buf
);
218 struct arm_prologue_cache
220 /* The stack pointer at the time this frame was created; i.e. the
221 caller's stack pointer when this function was called. It is used
222 to identify this frame. */
225 /* The frame base for this frame is just prev_sp - frame size.
226 FRAMESIZE is the distance from the frame pointer to the
227 initial stack pointer. */
231 /* The register used to hold the frame pointer for this frame. */
234 /* Saved register offsets. */
235 struct trad_frame_saved_reg
*saved_regs
;
238 /* Architecture version for displaced stepping. This effects the behaviour of
239 certain instructions, and really should not be hard-wired. */
241 #define DISPLACED_STEPPING_ARCH_VERSION 5
243 /* Addresses for calling Thumb functions have the bit 0 set.
244 Here are some macros to test, set, or clear bit 0 of addresses. */
245 #define IS_THUMB_ADDR(addr) ((addr) & 1)
246 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
247 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
249 /* Set to true if the 32-bit mode is in use. */
253 /* Determine if FRAME is executing in Thumb mode. */
256 arm_frame_is_thumb (struct frame_info
*frame
)
260 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
261 directly (from a signal frame or dummy frame) or by interpreting
262 the saved LR (from a prologue or DWARF frame). So consult it and
263 trust the unwinders. */
264 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
266 return (cpsr
& CPSR_T
) != 0;
269 /* Callback for VEC_lower_bound. */
272 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
273 const struct arm_mapping_symbol
*rhs
)
275 return lhs
->value
< rhs
->value
;
278 /* Determine if the program counter specified in MEMADDR is in a Thumb
279 function. This function should be called for addresses unrelated to
280 any executing frame; otherwise, prefer arm_frame_is_thumb. */
283 arm_pc_is_thumb (CORE_ADDR memaddr
)
285 struct obj_section
*sec
;
286 struct minimal_symbol
*sym
;
288 /* If bit 0 of the address is set, assume this is a Thumb address. */
289 if (IS_THUMB_ADDR (memaddr
))
292 /* If the user wants to override the symbol table, let him. */
293 if (strcmp (arm_force_mode_string
, "arm") == 0)
295 if (strcmp (arm_force_mode_string
, "thumb") == 0)
298 /* If there are mapping symbols, consult them. */
299 sec
= find_pc_section (memaddr
);
302 struct arm_per_objfile
*data
;
303 VEC(arm_mapping_symbol_s
) *map
;
304 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
308 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
311 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
312 if (!VEC_empty (arm_mapping_symbol_s
, map
))
314 struct arm_mapping_symbol
*map_sym
;
316 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
317 arm_compare_mapping_symbols
);
319 /* VEC_lower_bound finds the earliest ordered insertion
320 point. If the following symbol starts at this exact
321 address, we use that; otherwise, the preceding
322 mapping symbol covers this address. */
323 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
325 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
326 if (map_sym
->value
== map_key
.value
)
327 return map_sym
->type
== 't';
332 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
333 return map_sym
->type
== 't';
339 /* Thumb functions have a "special" bit set in minimal symbols. */
340 sym
= lookup_minimal_symbol_by_pc (memaddr
);
342 return (MSYMBOL_IS_SPECIAL (sym
));
344 /* If the user wants to override the fallback mode, let them. */
345 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
347 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
350 /* If we couldn't find any symbol, but we're talking to a running
351 target, then trust the current value of $cpsr. This lets
352 "display/i $pc" always show the correct mode (though if there is
353 a symbol table we will not reach here, so it still may not be
354 displayed in the mode it will be executed). */
355 if (target_has_registers
)
356 return arm_frame_is_thumb (get_current_frame ());
358 /* Otherwise we're out of luck; we assume ARM. */
362 /* Remove useless bits from addresses in a running program. */
364 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
367 return UNMAKE_THUMB_ADDR (val
);
369 return (val
& 0x03fffffc);
372 /* When reading symbols, we need to zap the low bit of the address,
373 which may be set to 1 for Thumb functions. */
375 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
380 /* Analyze a Thumb prologue, looking for a recognizable stack frame
381 and frame pointer. Scan until we encounter a store that could
382 clobber the stack frame unexpectedly, or an unknown instruction. */
385 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
386 CORE_ADDR start
, CORE_ADDR limit
,
387 struct arm_prologue_cache
*cache
)
389 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
392 struct pv_area
*stack
;
393 struct cleanup
*back_to
;
396 for (i
= 0; i
< 16; i
++)
397 regs
[i
] = pv_register (i
, 0);
398 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
399 back_to
= make_cleanup_free_pv_area (stack
);
401 while (start
< limit
)
405 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
407 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
412 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
415 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
416 whether to save LR (R14). */
417 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
419 /* Calculate offsets of saved R0-R7 and LR. */
420 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
421 if (mask
& (1 << regno
))
423 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
425 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
428 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
431 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
432 if (insn
& 0x80) /* Check for SUB. */
433 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
436 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
439 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
440 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
442 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
444 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
445 int src_reg
= (insn
& 0x78) >> 3;
446 regs
[dst_reg
] = regs
[src_reg
];
448 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
450 /* Handle stores to the stack. Normally pushes are used,
451 but with GCC -mtpcs-frame, there may be other stores
452 in the prologue to create the frame. */
453 int regno
= (insn
>> 8) & 0x7;
456 offset
= (insn
& 0xff) << 2;
457 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
459 if (pv_area_store_would_trash (stack
, addr
))
462 pv_area_store (stack
, addr
, 4, regs
[regno
]);
466 /* We don't know what this instruction is. We're finished
467 scanning. NOTE: Recognizing more safe-to-ignore
468 instructions here will improve support for optimized
478 do_cleanups (back_to
);
482 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
484 /* Frame pointer is fp. Frame size is constant. */
485 cache
->framereg
= ARM_FP_REGNUM
;
486 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
488 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
490 /* Frame pointer is r7. Frame size is constant. */
491 cache
->framereg
= THUMB_FP_REGNUM
;
492 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
494 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
496 /* Try the stack pointer... this is a bit desperate. */
497 cache
->framereg
= ARM_SP_REGNUM
;
498 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
502 /* We're just out of luck. We don't know where the frame is. */
503 cache
->framereg
= -1;
504 cache
->framesize
= 0;
507 for (i
= 0; i
< 16; i
++)
508 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
509 cache
->saved_regs
[i
].addr
= offset
;
511 do_cleanups (back_to
);
515 /* Advance the PC across any function entry prologue instructions to
516 reach some "real" code.
518 The APCS (ARM Procedure Call Standard) defines the following
522 [stmfd sp!, {a1,a2,a3,a4}]
523 stmfd sp!, {...,fp,ip,lr,pc}
524 [stfe f7, [sp, #-12]!]
525 [stfe f6, [sp, #-12]!]
526 [stfe f5, [sp, #-12]!]
527 [stfe f4, [sp, #-12]!]
528 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
531 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
533 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
536 CORE_ADDR func_addr
, limit_pc
;
537 struct symtab_and_line sal
;
539 /* If we're in a dummy frame, don't even try to skip the prologue. */
540 if (deprecated_pc_in_call_dummy (gdbarch
, pc
))
543 /* See if we can determine the end of the prologue via the symbol table.
544 If so, then return either PC, or the PC after the prologue, whichever
546 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
548 CORE_ADDR post_prologue_pc
549 = skip_prologue_using_sal (gdbarch
, func_addr
);
550 if (post_prologue_pc
!= 0)
551 return max (pc
, post_prologue_pc
);
554 /* Can't determine prologue from the symbol table, need to examine
557 /* Find an upper limit on the function prologue using the debug
558 information. If the debug information could not be used to provide
559 that bound, then use an arbitrary large number as the upper bound. */
560 /* Like arm_scan_prologue, stop no later than pc + 64. */
561 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
563 limit_pc
= pc
+ 64; /* Magic. */
566 /* Check if this is Thumb code. */
567 if (arm_pc_is_thumb (pc
))
568 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
570 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
572 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
574 /* "mov ip, sp" is no longer a required part of the prologue. */
575 if (inst
== 0xe1a0c00d) /* mov ip, sp */
578 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
581 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
584 /* Some prologues begin with "str lr, [sp, #-4]!". */
585 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
588 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
591 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
594 /* Any insns after this point may float into the code, if it makes
595 for better instruction scheduling, so we skip them only if we
596 find them, but still consider the function to be frame-ful. */
598 /* We may have either one sfmfd instruction here, or several stfe
599 insns, depending on the version of floating point code we
601 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
604 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
607 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
610 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
613 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
614 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
615 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
618 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
619 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
620 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
623 /* Un-recognized instruction; stop scanning. */
627 return skip_pc
; /* End of prologue */
631 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
632 This function decodes a Thumb function prologue to determine:
633 1) the size of the stack frame
634 2) which registers are saved on it
635 3) the offsets of saved regs
636 4) the offset from the stack pointer to the frame pointer
638 A typical Thumb function prologue would create this stack frame
639 (offsets relative to FP)
640 old SP -> 24 stack parameters
643 R7 -> 0 local variables (16 bytes)
644 SP -> -12 additional stack space (12 bytes)
645 The frame size would thus be 36 bytes, and the frame offset would be
646 12 bytes. The frame register is R7.
648 The comments for thumb_skip_prolog() describe the algorithm we use
649 to detect the end of the prolog. */
653 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
654 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
656 CORE_ADDR prologue_start
;
657 CORE_ADDR prologue_end
;
658 CORE_ADDR current_pc
;
660 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
663 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
665 if (sal
.line
== 0) /* no line info, use current PC */
666 prologue_end
= prev_pc
;
667 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
668 prologue_end
= sal
.end
; /* (probably means no prologue) */
671 /* We're in the boondocks: we have no idea where the start of the
675 prologue_end
= min (prologue_end
, prev_pc
);
677 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
680 /* This function decodes an ARM function prologue to determine:
681 1) the size of the stack frame
682 2) which registers are saved on it
683 3) the offsets of saved regs
684 4) the offset from the stack pointer to the frame pointer
685 This information is stored in the "extra" fields of the frame_info.
687 There are two basic forms for the ARM prologue. The fixed argument
688 function call will look like:
691 stmfd sp!, {fp, ip, lr, pc}
695 Which would create this stack frame (offsets relative to FP):
696 IP -> 4 (caller's stack)
697 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
698 -4 LR (return address in caller)
699 -8 IP (copy of caller's SP)
701 SP -> -28 Local variables
703 The frame size would thus be 32 bytes, and the frame offset would be
704 28 bytes. The stmfd call can also save any of the vN registers it
705 plans to use, which increases the frame size accordingly.
707 Note: The stored PC is 8 off of the STMFD instruction that stored it
708 because the ARM Store instructions always store PC + 8 when you read
711 A variable argument function call will look like:
714 stmfd sp!, {a1, a2, a3, a4}
715 stmfd sp!, {fp, ip, lr, pc}
718 Which would create this stack frame (offsets relative to FP):
719 IP -> 20 (caller's stack)
724 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
725 -4 LR (return address in caller)
726 -8 IP (copy of caller's SP)
728 SP -> -28 Local variables
730 The frame size would thus be 48 bytes, and the frame offset would be
733 There is another potential complication, which is that the optimizer
734 will try to separate the store of fp in the "stmfd" instruction from
735 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
736 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
738 Also, note, the original version of the ARM toolchain claimed that there
741 instruction at the end of the prologue. I have never seen GCC produce
742 this, and the ARM docs don't mention it. We still test for it below in
748 arm_scan_prologue (struct frame_info
*this_frame
,
749 struct arm_prologue_cache
*cache
)
751 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
752 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
753 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
755 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
756 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
757 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
758 pv_t regs
[ARM_FPS_REGNUM
];
759 struct pv_area
*stack
;
760 struct cleanup
*back_to
;
763 /* Assume there is no frame until proven otherwise. */
764 cache
->framereg
= ARM_SP_REGNUM
;
765 cache
->framesize
= 0;
767 /* Check for Thumb prologue. */
768 if (arm_frame_is_thumb (this_frame
))
770 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
774 /* Find the function prologue. If we can't find the function in
775 the symbol table, peek in the stack frame to find the PC. */
776 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
779 /* One way to find the end of the prologue (which works well
780 for unoptimized code) is to do the following:
782 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
785 prologue_end = prev_pc;
786 else if (sal.end < prologue_end)
787 prologue_end = sal.end;
789 This mechanism is very accurate so long as the optimizer
790 doesn't move any instructions from the function body into the
791 prologue. If this happens, sal.end will be the last
792 instruction in the first hunk of prologue code just before
793 the first instruction that the scheduler has moved from
794 the body to the prologue.
796 In order to make sure that we scan all of the prologue
797 instructions, we use a slightly less accurate mechanism which
798 may scan more than necessary. To help compensate for this
799 lack of accuracy, the prologue scanning loop below contains
800 several clauses which'll cause the loop to terminate early if
801 an implausible prologue instruction is encountered.
807 is a suitable endpoint since it accounts for the largest
808 possible prologue plus up to five instructions inserted by
811 if (prologue_end
> prologue_start
+ 64)
813 prologue_end
= prologue_start
+ 64; /* See above. */
818 /* We have no symbol information. Our only option is to assume this
819 function has a standard stack frame and the normal frame register.
820 Then, we can find the value of our frame pointer on entrance to
821 the callee (or at the present moment if this is the innermost frame).
822 The value stored there should be the address of the stmfd + 8. */
824 LONGEST return_value
;
826 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
827 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
831 prologue_start
= gdbarch_addr_bits_remove
832 (gdbarch
, return_value
) - 8;
833 prologue_end
= prologue_start
+ 64; /* See above. */
837 if (prev_pc
< prologue_end
)
838 prologue_end
= prev_pc
;
840 /* Now search the prologue looking for instructions that set up the
841 frame pointer, adjust the stack pointer, and save registers.
843 Be careful, however, and if it doesn't look like a prologue,
844 don't try to scan it. If, for instance, a frameless function
845 begins with stmfd sp!, then we will tell ourselves there is
846 a frame, which will confuse stack traceback, as well as "finish"
847 and other operations that rely on a knowledge of the stack
850 In the APCS, the prologue should start with "mov ip, sp" so
851 if we don't see this as the first insn, we will stop.
853 [Note: This doesn't seem to be true any longer, so it's now an
854 optional part of the prologue. - Kevin Buettner, 2001-11-20]
856 [Note further: The "mov ip,sp" only seems to be missing in
857 frameless functions at optimization level "-O2" or above,
858 in which case it is often (but not always) replaced by
859 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
861 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
862 regs
[regno
] = pv_register (regno
, 0);
863 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
864 back_to
= make_cleanup_free_pv_area (stack
);
866 for (current_pc
= prologue_start
;
867 current_pc
< prologue_end
;
871 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
873 if (insn
== 0xe1a0c00d) /* mov ip, sp */
875 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
878 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
880 unsigned imm
= insn
& 0xff; /* immediate value */
881 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
882 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
883 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
886 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
888 unsigned imm
= insn
& 0xff; /* immediate value */
889 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
890 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
891 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
894 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
896 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
898 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
899 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
902 else if ((insn
& 0xffff0000) == 0xe92d0000)
903 /* stmfd sp!, {..., fp, ip, lr, pc}
905 stmfd sp!, {a1, a2, a3, a4} */
907 int mask
= insn
& 0xffff;
909 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
912 /* Calculate offsets of saved registers. */
913 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
914 if (mask
& (1 << regno
))
916 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
917 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
920 else if ((insn
& 0xffffc000) == 0xe54b0000 /* strb rx,[r11,#-n] */
921 || (insn
& 0xffffc0f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
922 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
924 /* No need to add this to saved_regs -- it's just an arg reg. */
927 else if ((insn
& 0xffffc000) == 0xe5cd0000 /* strb rx,[sp,#n] */
928 || (insn
& 0xffffc0f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
929 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
931 /* No need to add this to saved_regs -- it's just an arg reg. */
934 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
936 unsigned imm
= insn
& 0xff; /* immediate value */
937 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
938 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
939 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
941 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
943 unsigned imm
= insn
& 0xff; /* immediate value */
944 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
945 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
946 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
948 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
949 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
951 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
954 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
955 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
956 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
958 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
959 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
962 unsigned int fp_start_reg
, fp_bound_reg
;
964 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
967 if ((insn
& 0x800) == 0x800) /* N0 is set */
969 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
976 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
982 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
983 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
984 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
986 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
987 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
988 regs
[fp_start_reg
++]);
991 else if ((insn
& 0xf0000000) != 0xe0000000)
992 break; /* Condition not true, exit early */
993 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
994 break; /* Don't scan past a block load */
996 /* The optimizer might shove anything into the prologue,
997 so we just skip what we don't recognize. */
1001 /* The frame size is just the distance from the frame register
1002 to the original stack pointer. */
1003 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1005 /* Frame pointer is fp. */
1006 cache
->framereg
= ARM_FP_REGNUM
;
1007 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1009 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1011 /* Try the stack pointer... this is a bit desperate. */
1012 cache
->framereg
= ARM_SP_REGNUM
;
1013 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1017 /* We're just out of luck. We don't know where the frame is. */
1018 cache
->framereg
= -1;
1019 cache
->framesize
= 0;
1022 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1023 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1024 cache
->saved_regs
[regno
].addr
= offset
;
1026 do_cleanups (back_to
);
1029 static struct arm_prologue_cache
*
1030 arm_make_prologue_cache (struct frame_info
*this_frame
)
1033 struct arm_prologue_cache
*cache
;
1034 CORE_ADDR unwound_fp
;
1036 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1037 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1039 arm_scan_prologue (this_frame
, cache
);
1041 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1042 if (unwound_fp
== 0)
1045 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1047 /* Calculate actual addresses of saved registers using offsets
1048 determined by arm_scan_prologue. */
1049 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1050 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1051 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1056 /* Our frame ID for a normal frame is the current function's starting PC
1057 and the caller's SP when we were called. */
1060 arm_prologue_this_id (struct frame_info
*this_frame
,
1062 struct frame_id
*this_id
)
1064 struct arm_prologue_cache
*cache
;
1068 if (*this_cache
== NULL
)
1069 *this_cache
= arm_make_prologue_cache (this_frame
);
1070 cache
= *this_cache
;
1072 /* This is meant to halt the backtrace at "_start". */
1073 pc
= get_frame_pc (this_frame
);
1074 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1077 /* If we've hit a wall, stop. */
1078 if (cache
->prev_sp
== 0)
1081 func
= get_frame_func (this_frame
);
1082 id
= frame_id_build (cache
->prev_sp
, func
);
1086 static struct value
*
1087 arm_prologue_prev_register (struct frame_info
*this_frame
,
1091 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1092 struct arm_prologue_cache
*cache
;
1094 if (*this_cache
== NULL
)
1095 *this_cache
= arm_make_prologue_cache (this_frame
);
1096 cache
= *this_cache
;
1098 /* If we are asked to unwind the PC, then we need to return the LR
1099 instead. The prologue may save PC, but it will point into this
1100 frame's prologue, not the next frame's resume location. Also
1101 strip the saved T bit. A valid LR may have the low bit set, but
1102 a valid PC never does. */
1103 if (prev_regnum
== ARM_PC_REGNUM
)
1107 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1108 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1109 arm_addr_bits_remove (gdbarch
, lr
));
1112 /* SP is generally not saved to the stack, but this frame is
1113 identified by the next frame's stack pointer at the time of the call.
1114 The value was already reconstructed into PREV_SP. */
1115 if (prev_regnum
== ARM_SP_REGNUM
)
1116 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1118 /* The CPSR may have been changed by the call instruction and by the
1119 called function. The only bit we can reconstruct is the T bit,
1120 by checking the low bit of LR as of the call. This is a reliable
1121 indicator of Thumb-ness except for some ARM v4T pre-interworking
1122 Thumb code, which could get away with a clear low bit as long as
1123 the called function did not use bx. Guess that all other
1124 bits are unchanged; the condition flags are presumably lost,
1125 but the processor status is likely valid. */
1126 if (prev_regnum
== ARM_PS_REGNUM
)
1130 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1131 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1132 if (IS_THUMB_ADDR (lr
))
1136 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1139 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1143 struct frame_unwind arm_prologue_unwind
= {
1145 arm_prologue_this_id
,
1146 arm_prologue_prev_register
,
1148 default_frame_sniffer
1151 static struct arm_prologue_cache
*
1152 arm_make_stub_cache (struct frame_info
*this_frame
)
1155 struct arm_prologue_cache
*cache
;
1156 CORE_ADDR unwound_fp
;
1158 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1159 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1161 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1166 /* Our frame ID for a stub frame is the current SP and LR. */
1169 arm_stub_this_id (struct frame_info
*this_frame
,
1171 struct frame_id
*this_id
)
1173 struct arm_prologue_cache
*cache
;
1175 if (*this_cache
== NULL
)
1176 *this_cache
= arm_make_stub_cache (this_frame
);
1177 cache
= *this_cache
;
1179 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1183 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1184 struct frame_info
*this_frame
,
1185 void **this_prologue_cache
)
1187 CORE_ADDR addr_in_block
;
1190 addr_in_block
= get_frame_address_in_block (this_frame
);
1191 if (in_plt_section (addr_in_block
, NULL
)
1192 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1198 struct frame_unwind arm_stub_unwind
= {
1201 arm_prologue_prev_register
,
1203 arm_stub_unwind_sniffer
1207 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1209 struct arm_prologue_cache
*cache
;
1211 if (*this_cache
== NULL
)
1212 *this_cache
= arm_make_prologue_cache (this_frame
);
1213 cache
= *this_cache
;
1215 return cache
->prev_sp
- cache
->framesize
;
1218 struct frame_base arm_normal_base
= {
1219 &arm_prologue_unwind
,
1220 arm_normal_frame_base
,
1221 arm_normal_frame_base
,
1222 arm_normal_frame_base
1225 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1226 dummy frame. The frame ID's base needs to match the TOS value
1227 saved by save_dummy_frame_tos() and returned from
1228 arm_push_dummy_call, and the PC needs to match the dummy frame's
1231 static struct frame_id
1232 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1234 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1235 get_frame_pc (this_frame
));
1238 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1239 be used to construct the previous frame's ID, after looking up the
1240 containing function). */
1243 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1246 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1247 return arm_addr_bits_remove (gdbarch
, pc
);
1251 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1253 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1256 static struct value
*
1257 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1260 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1266 /* The PC is normally copied from the return column, which
1267 describes saves of LR. However, that version may have an
1268 extra bit set to indicate Thumb state. The bit is not
1270 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1271 return frame_unwind_got_constant (this_frame
, regnum
,
1272 arm_addr_bits_remove (gdbarch
, lr
));
1275 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1276 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1277 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1278 if (IS_THUMB_ADDR (lr
))
1282 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1285 internal_error (__FILE__
, __LINE__
,
1286 _("Unexpected register %d"), regnum
);
1291 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1292 struct dwarf2_frame_state_reg
*reg
,
1293 struct frame_info
*this_frame
)
1299 reg
->how
= DWARF2_FRAME_REG_FN
;
1300 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1303 reg
->how
= DWARF2_FRAME_REG_CFA
;
1308 /* When arguments must be pushed onto the stack, they go on in reverse
1309 order. The code below implements a FILO (stack) to do this. */
1314 struct stack_item
*prev
;
1318 static struct stack_item
*
1319 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1321 struct stack_item
*si
;
1322 si
= xmalloc (sizeof (struct stack_item
));
1323 si
->data
= xmalloc (len
);
1326 memcpy (si
->data
, contents
, len
);
1330 static struct stack_item
*
1331 pop_stack_item (struct stack_item
*si
)
1333 struct stack_item
*dead
= si
;
1341 /* Return the alignment (in bytes) of the given type. */
1344 arm_type_align (struct type
*t
)
1350 t
= check_typedef (t
);
1351 switch (TYPE_CODE (t
))
1354 /* Should never happen. */
1355 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1359 case TYPE_CODE_ENUM
:
1363 case TYPE_CODE_RANGE
:
1364 case TYPE_CODE_BITSTRING
:
1366 case TYPE_CODE_CHAR
:
1367 case TYPE_CODE_BOOL
:
1368 return TYPE_LENGTH (t
);
1370 case TYPE_CODE_ARRAY
:
1371 case TYPE_CODE_COMPLEX
:
1372 /* TODO: What about vector types? */
1373 return arm_type_align (TYPE_TARGET_TYPE (t
));
1375 case TYPE_CODE_STRUCT
:
1376 case TYPE_CODE_UNION
:
1378 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1380 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1388 /* Possible base types for a candidate for passing and returning in
1391 enum arm_vfp_cprc_base_type
1400 /* The length of one element of base type B. */
1403 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
1407 case VFP_CPRC_SINGLE
:
1409 case VFP_CPRC_DOUBLE
:
1411 case VFP_CPRC_VEC64
:
1413 case VFP_CPRC_VEC128
:
1416 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1421 /* The character ('s', 'd' or 'q') for the type of VFP register used
1422 for passing base type B. */
1425 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
1429 case VFP_CPRC_SINGLE
:
1431 case VFP_CPRC_DOUBLE
:
1433 case VFP_CPRC_VEC64
:
1435 case VFP_CPRC_VEC128
:
1438 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1443 /* Determine whether T may be part of a candidate for passing and
1444 returning in VFP registers, ignoring the limit on the total number
1445 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1446 classification of the first valid component found; if it is not
1447 VFP_CPRC_UNKNOWN, all components must have the same classification
1448 as *BASE_TYPE. If it is found that T contains a type not permitted
1449 for passing and returning in VFP registers, a type differently
1450 classified from *BASE_TYPE, or two types differently classified
1451 from each other, return -1, otherwise return the total number of
1452 base-type elements found (possibly 0 in an empty structure or
1453 array). Vectors and complex types are not currently supported,
1454 matching the generic AAPCS support. */
1457 arm_vfp_cprc_sub_candidate (struct type
*t
,
1458 enum arm_vfp_cprc_base_type
*base_type
)
1460 t
= check_typedef (t
);
1461 switch (TYPE_CODE (t
))
1464 switch (TYPE_LENGTH (t
))
1467 if (*base_type
== VFP_CPRC_UNKNOWN
)
1468 *base_type
= VFP_CPRC_SINGLE
;
1469 else if (*base_type
!= VFP_CPRC_SINGLE
)
1474 if (*base_type
== VFP_CPRC_UNKNOWN
)
1475 *base_type
= VFP_CPRC_DOUBLE
;
1476 else if (*base_type
!= VFP_CPRC_DOUBLE
)
1485 case TYPE_CODE_ARRAY
:
1489 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
1492 if (TYPE_LENGTH (t
) == 0)
1494 gdb_assert (count
== 0);
1497 else if (count
== 0)
1499 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1500 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
1501 return TYPE_LENGTH (t
) / unitlen
;
1505 case TYPE_CODE_STRUCT
:
1510 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1512 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1514 if (sub_count
== -1)
1518 if (TYPE_LENGTH (t
) == 0)
1520 gdb_assert (count
== 0);
1523 else if (count
== 0)
1525 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1526 if (TYPE_LENGTH (t
) != unitlen
* count
)
1531 case TYPE_CODE_UNION
:
1536 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1538 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1540 if (sub_count
== -1)
1542 count
= (count
> sub_count
? count
: sub_count
);
1544 if (TYPE_LENGTH (t
) == 0)
1546 gdb_assert (count
== 0);
1549 else if (count
== 0)
1551 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1552 if (TYPE_LENGTH (t
) != unitlen
* count
)
1564 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1565 if passed to or returned from a non-variadic function with the VFP
1566 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1567 *BASE_TYPE to the base type for T and *COUNT to the number of
1568 elements of that base type before returning. */
1571 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
1574 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
1575 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
1576 if (c
<= 0 || c
> 4)
1583 /* Return 1 if the VFP ABI should be used for passing arguments to and
1584 returning values from a function of type FUNC_TYPE, 0
1588 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
1590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1591 /* Variadic functions always use the base ABI. Assume that functions
1592 without debug info are not variadic. */
1593 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
1595 /* The VFP ABI is only supported as a variant of AAPCS. */
1596 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
1598 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
1601 /* We currently only support passing parameters in integer registers, which
1602 conforms with GCC's default model, and VFP argument passing following
1603 the VFP variant of AAPCS. Several other variants exist and
1604 we should probably support some of them based on the selected ABI. */
1607 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1608 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1609 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1610 CORE_ADDR struct_addr
)
1612 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1616 struct stack_item
*si
= NULL
;
1619 unsigned vfp_regs_free
= (1 << 16) - 1;
1621 /* Determine the type of this function and whether the VFP ABI
1623 ftype
= check_typedef (value_type (function
));
1624 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
1625 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
1626 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
1628 /* Set the return address. For the ARM, the return breakpoint is
1629 always at BP_ADDR. */
1630 if (arm_pc_is_thumb (bp_addr
))
1632 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1634 /* Walk through the list of args and determine how large a temporary
1635 stack is required. Need to take care here as structs may be
1636 passed on the stack, and we have to to push them. */
1639 argreg
= ARM_A1_REGNUM
;
1642 /* The struct_return pointer occupies the first parameter
1643 passing register. */
1647 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
1648 gdbarch_register_name (gdbarch
, argreg
),
1649 paddress (gdbarch
, struct_addr
));
1650 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1654 for (argnum
= 0; argnum
< nargs
; argnum
++)
1657 struct type
*arg_type
;
1658 struct type
*target_type
;
1659 enum type_code typecode
;
1662 enum arm_vfp_cprc_base_type vfp_base_type
;
1664 int may_use_core_reg
= 1;
1666 arg_type
= check_typedef (value_type (args
[argnum
]));
1667 len
= TYPE_LENGTH (arg_type
);
1668 target_type
= TYPE_TARGET_TYPE (arg_type
);
1669 typecode
= TYPE_CODE (arg_type
);
1670 val
= value_contents_writeable (args
[argnum
]);
1672 align
= arm_type_align (arg_type
);
1673 /* Round alignment up to a whole number of words. */
1674 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1675 /* Different ABIs have different maximum alignments. */
1676 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1678 /* The APCS ABI only requires word alignment. */
1679 align
= INT_REGISTER_SIZE
;
1683 /* The AAPCS requires at most doubleword alignment. */
1684 if (align
> INT_REGISTER_SIZE
* 2)
1685 align
= INT_REGISTER_SIZE
* 2;
1689 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
1697 /* Because this is a CPRC it cannot go in a core register or
1698 cause a core register to be skipped for alignment.
1699 Either it goes in VFP registers and the rest of this loop
1700 iteration is skipped for this argument, or it goes on the
1701 stack (and the stack alignment code is correct for this
1703 may_use_core_reg
= 0;
1705 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
1706 shift
= unit_length
/ 4;
1707 mask
= (1 << (shift
* vfp_base_count
)) - 1;
1708 for (regno
= 0; regno
< 16; regno
+= shift
)
1709 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
1718 vfp_regs_free
&= ~(mask
<< regno
);
1719 reg_scaled
= regno
/ shift
;
1720 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
1721 for (i
= 0; i
< vfp_base_count
; i
++)
1725 if (reg_char
== 'q')
1726 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
1727 val
+ i
* unit_length
);
1730 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
1731 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
1733 regcache_cooked_write (regcache
, regnum
,
1734 val
+ i
* unit_length
);
1741 /* This CPRC could not go in VFP registers, so all VFP
1742 registers are now marked as used. */
1747 /* Push stack padding for dowubleword alignment. */
1748 if (nstack
& (align
- 1))
1750 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1751 nstack
+= INT_REGISTER_SIZE
;
1754 /* Doubleword aligned quantities must go in even register pairs. */
1755 if (may_use_core_reg
1756 && argreg
<= ARM_LAST_ARG_REGNUM
1757 && align
> INT_REGISTER_SIZE
1761 /* If the argument is a pointer to a function, and it is a
1762 Thumb function, create a LOCAL copy of the value and set
1763 the THUMB bit in it. */
1764 if (TYPE_CODE_PTR
== typecode
1765 && target_type
!= NULL
1766 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1768 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
1769 if (arm_pc_is_thumb (regval
))
1772 store_unsigned_integer (val
, len
, byte_order
,
1773 MAKE_THUMB_ADDR (regval
));
1777 /* Copy the argument to general registers or the stack in
1778 register-sized pieces. Large arguments are split between
1779 registers and stack. */
1782 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1784 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
1786 /* The argument is being passed in a general purpose
1789 = extract_unsigned_integer (val
, partial_len
, byte_order
);
1790 if (byte_order
== BFD_ENDIAN_BIG
)
1791 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1793 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1795 gdbarch_register_name
1797 phex (regval
, INT_REGISTER_SIZE
));
1798 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1803 /* Push the arguments onto the stack. */
1805 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1807 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1808 nstack
+= INT_REGISTER_SIZE
;
1815 /* If we have an odd number of words to push, then decrement the stack
1816 by one word now, so first stack argument will be dword aligned. */
1823 write_memory (sp
, si
->data
, si
->len
);
1824 si
= pop_stack_item (si
);
1827 /* Finally, update teh SP register. */
1828 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1834 /* Always align the frame to an 8-byte boundary. This is required on
1835 some platforms and harmless on the rest. */
1838 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1840 /* Align the stack to eight bytes. */
1841 return sp
& ~ (CORE_ADDR
) 7;
1845 print_fpu_flags (int flags
)
1847 if (flags
& (1 << 0))
1848 fputs ("IVO ", stdout
);
1849 if (flags
& (1 << 1))
1850 fputs ("DVZ ", stdout
);
1851 if (flags
& (1 << 2))
1852 fputs ("OFL ", stdout
);
1853 if (flags
& (1 << 3))
1854 fputs ("UFL ", stdout
);
1855 if (flags
& (1 << 4))
1856 fputs ("INX ", stdout
);
1860 /* Print interesting information about the floating point processor
1861 (if present) or emulator. */
1863 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1864 struct frame_info
*frame
, const char *args
)
1866 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1869 type
= (status
>> 24) & 127;
1870 if (status
& (1 << 31))
1871 printf (_("Hardware FPU type %d\n"), type
);
1873 printf (_("Software FPU type %d\n"), type
);
1874 /* i18n: [floating point unit] mask */
1875 fputs (_("mask: "), stdout
);
1876 print_fpu_flags (status
>> 16);
1877 /* i18n: [floating point unit] flags */
1878 fputs (_("flags: "), stdout
);
1879 print_fpu_flags (status
);
1882 /* Construct the ARM extended floating point type. */
1883 static struct type
*
1884 arm_ext_type (struct gdbarch
*gdbarch
)
1886 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1888 if (!tdep
->arm_ext_type
)
1890 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
1891 floatformats_arm_ext
);
1893 return tdep
->arm_ext_type
;
1896 static struct type
*
1897 arm_neon_double_type (struct gdbarch
*gdbarch
)
1899 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1901 if (tdep
->neon_double_type
== NULL
)
1903 struct type
*t
, *elem
;
1905 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
1907 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1908 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
1909 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1910 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
1911 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1912 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
1913 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1914 append_composite_type_field (t
, "u64", elem
);
1915 elem
= builtin_type (gdbarch
)->builtin_float
;
1916 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
1917 elem
= builtin_type (gdbarch
)->builtin_double
;
1918 append_composite_type_field (t
, "f64", elem
);
1920 TYPE_VECTOR (t
) = 1;
1921 TYPE_NAME (t
) = "neon_d";
1922 tdep
->neon_double_type
= t
;
1925 return tdep
->neon_double_type
;
1928 /* FIXME: The vector types are not correctly ordered on big-endian
1929 targets. Just as s0 is the low bits of d0, d0[0] is also the low
1930 bits of d0 - regardless of what unit size is being held in d0. So
1931 the offset of the first uint8 in d0 is 7, but the offset of the
1932 first float is 4. This code works as-is for little-endian
1935 static struct type
*
1936 arm_neon_quad_type (struct gdbarch
*gdbarch
)
1938 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1940 if (tdep
->neon_quad_type
== NULL
)
1942 struct type
*t
, *elem
;
1944 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
1946 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1947 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
1948 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1949 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
1950 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1951 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
1952 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1953 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
1954 elem
= builtin_type (gdbarch
)->builtin_float
;
1955 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
1956 elem
= builtin_type (gdbarch
)->builtin_double
;
1957 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
1959 TYPE_VECTOR (t
) = 1;
1960 TYPE_NAME (t
) = "neon_q";
1961 tdep
->neon_quad_type
= t
;
1964 return tdep
->neon_quad_type
;
1967 /* Return the GDB type object for the "standard" data type of data in
1970 static struct type
*
1971 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1973 int num_regs
= gdbarch_num_regs (gdbarch
);
1975 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
1976 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
1977 return builtin_type (gdbarch
)->builtin_float
;
1979 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
1980 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
1981 return arm_neon_quad_type (gdbarch
);
1983 /* If the target description has register information, we are only
1984 in this function so that we can override the types of
1985 double-precision registers for NEON. */
1986 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
1988 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
1990 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
1991 && TYPE_CODE (t
) == TYPE_CODE_FLT
1992 && gdbarch_tdep (gdbarch
)->have_neon
)
1993 return arm_neon_double_type (gdbarch
);
1998 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
2000 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2001 return builtin_type (gdbarch
)->builtin_void
;
2003 return arm_ext_type (gdbarch
);
2005 else if (regnum
== ARM_SP_REGNUM
)
2006 return builtin_type (gdbarch
)->builtin_data_ptr
;
2007 else if (regnum
== ARM_PC_REGNUM
)
2008 return builtin_type (gdbarch
)->builtin_func_ptr
;
2009 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2010 /* These registers are only supported on targets which supply
2011 an XML description. */
2012 return builtin_type (gdbarch
)->builtin_int0
;
2014 return builtin_type (gdbarch
)->builtin_uint32
;
2017 /* Map a DWARF register REGNUM onto the appropriate GDB register
2021 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2023 /* Core integer regs. */
2024 if (reg
>= 0 && reg
<= 15)
2027 /* Legacy FPA encoding. These were once used in a way which
2028 overlapped with VFP register numbering, so their use is
2029 discouraged, but GDB doesn't support the ARM toolchain
2030 which used them for VFP. */
2031 if (reg
>= 16 && reg
<= 23)
2032 return ARM_F0_REGNUM
+ reg
- 16;
2034 /* New assignments for the FPA registers. */
2035 if (reg
>= 96 && reg
<= 103)
2036 return ARM_F0_REGNUM
+ reg
- 96;
2038 /* WMMX register assignments. */
2039 if (reg
>= 104 && reg
<= 111)
2040 return ARM_WCGR0_REGNUM
+ reg
- 104;
2042 if (reg
>= 112 && reg
<= 127)
2043 return ARM_WR0_REGNUM
+ reg
- 112;
2045 if (reg
>= 192 && reg
<= 199)
2046 return ARM_WC0_REGNUM
+ reg
- 192;
2048 /* VFP v2 registers. A double precision value is actually
2049 in d1 rather than s2, but the ABI only defines numbering
2050 for the single precision registers. This will "just work"
2051 in GDB for little endian targets (we'll read eight bytes,
2052 starting in s0 and then progressing to s1), but will be
2053 reversed on big endian targets with VFP. This won't
2054 be a problem for the new Neon quad registers; you're supposed
2055 to use DW_OP_piece for those. */
2056 if (reg
>= 64 && reg
<= 95)
2060 sprintf (name_buf
, "s%d", reg
- 64);
2061 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2065 /* VFP v3 / Neon registers. This range is also used for VFP v2
2066 registers, except that it now describes d0 instead of s0. */
2067 if (reg
>= 256 && reg
<= 287)
2071 sprintf (name_buf
, "d%d", reg
- 256);
2072 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2079 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2081 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2084 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2086 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2087 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2089 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2090 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2092 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2093 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2095 if (reg
< NUM_GREGS
)
2096 return SIM_ARM_R0_REGNUM
+ reg
;
2099 if (reg
< NUM_FREGS
)
2100 return SIM_ARM_FP0_REGNUM
+ reg
;
2103 if (reg
< NUM_SREGS
)
2104 return SIM_ARM_FPS_REGNUM
+ reg
;
2107 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2110 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2111 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2112 It is thought that this is is the floating-point register format on
2113 little-endian systems. */
2116 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2117 void *dbl
, int endianess
)
2121 if (endianess
== BFD_ENDIAN_BIG
)
2122 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2124 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2126 floatformat_from_doublest (fmt
, &d
, dbl
);
2130 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2135 floatformat_to_doublest (fmt
, ptr
, &d
);
2136 if (endianess
== BFD_ENDIAN_BIG
)
2137 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2139 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2144 condition_true (unsigned long cond
, unsigned long status_reg
)
2146 if (cond
== INST_AL
|| cond
== INST_NV
)
2152 return ((status_reg
& FLAG_Z
) != 0);
2154 return ((status_reg
& FLAG_Z
) == 0);
2156 return ((status_reg
& FLAG_C
) != 0);
2158 return ((status_reg
& FLAG_C
) == 0);
2160 return ((status_reg
& FLAG_N
) != 0);
2162 return ((status_reg
& FLAG_N
) == 0);
2164 return ((status_reg
& FLAG_V
) != 0);
2166 return ((status_reg
& FLAG_V
) == 0);
2168 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2170 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2172 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2174 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2176 return (((status_reg
& FLAG_Z
) == 0)
2177 && (((status_reg
& FLAG_N
) == 0)
2178 == ((status_reg
& FLAG_V
) == 0)));
2180 return (((status_reg
& FLAG_Z
) != 0)
2181 || (((status_reg
& FLAG_N
) == 0)
2182 != ((status_reg
& FLAG_V
) == 0)));
2187 /* Support routines for single stepping. Calculate the next PC value. */
2188 #define submask(x) ((1L << ((x) + 1)) - 1)
2189 #define bit(obj,st) (((obj) >> (st)) & 1)
2190 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
2191 #define sbits(obj,st,fn) \
2192 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
2193 #define BranchDest(addr,instr) \
2194 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
2197 static unsigned long
2198 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2199 unsigned long pc_val
, unsigned long status_reg
)
2201 unsigned long res
, shift
;
2202 int rm
= bits (inst
, 0, 3);
2203 unsigned long shifttype
= bits (inst
, 5, 6);
2207 int rs
= bits (inst
, 8, 11);
2208 shift
= (rs
== 15 ? pc_val
+ 8
2209 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2212 shift
= bits (inst
, 7, 11);
2215 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
2216 + (bit (inst
, 4) ? 12 : 8))
2217 : get_frame_register_unsigned (frame
, rm
));
2222 res
= shift
>= 32 ? 0 : res
<< shift
;
2226 res
= shift
>= 32 ? 0 : res
>> shift
;
2232 res
= ((res
& 0x80000000L
)
2233 ? ~((~res
) >> shift
) : res
>> shift
);
2236 case 3: /* ROR/RRX */
2239 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2241 res
= (res
>> shift
) | (res
<< (32 - shift
));
2245 return res
& 0xffffffff;
2248 /* Return number of 1-bits in VAL. */
2251 bitcount (unsigned long val
)
2254 for (nbits
= 0; val
!= 0; nbits
++)
2255 val
&= val
- 1; /* delete rightmost 1-bit in val */
2259 /* Return the size in bytes of the complete Thumb instruction whose
2260 first halfword is INST1. */
2263 thumb_insn_size (unsigned short inst1
)
2265 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2272 thumb_advance_itstate (unsigned int itstate
)
2274 /* Preserve IT[7:5], the first three bits of the condition. Shift
2275 the upcoming condition flags left by one bit. */
2276 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
2278 /* If we have finished the IT block, clear the state. */
2279 if ((itstate
& 0x0f) == 0)
2285 /* Find the next PC after the current instruction executes. In some
2286 cases we can not statically determine the answer (see the IT state
2287 handling in this function); in that case, a breakpoint may be
2288 inserted in addition to the returned PC, which will be used to set
2289 another breakpoint by our caller. */
2292 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2294 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2295 struct address_space
*aspace
= get_frame_address_space (frame
);
2296 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2297 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2298 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2299 unsigned short inst1
;
2300 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2301 unsigned long offset
;
2302 ULONGEST status
, itstate
;
2304 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2306 /* Thumb-2 conditional execution support. There are eight bits in
2307 the CPSR which describe conditional execution state. Once
2308 reconstructed (they're in a funny order), the low five bits
2309 describe the low bit of the condition for each instruction and
2310 how many instructions remain. The high three bits describe the
2311 base condition. One of the low four bits will be set if an IT
2312 block is active. These bits read as zero on earlier
2314 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2315 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
2317 /* If-Then handling. On GNU/Linux, where this routine is used, we
2318 use an undefined instruction as a breakpoint. Unlike BKPT, IT
2319 can disable execution of the undefined instruction. So we might
2320 miss the breakpoint if we set it on a skipped conditional
2321 instruction. Because conditional instructions can change the
2322 flags, affecting the execution of further instructions, we may
2323 need to set two breakpoints. */
2325 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
2327 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
2329 /* An IT instruction. Because this instruction does not
2330 modify the flags, we can accurately predict the next
2331 executed instruction. */
2332 itstate
= inst1
& 0x00ff;
2333 pc
+= thumb_insn_size (inst1
);
2335 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2337 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2338 pc
+= thumb_insn_size (inst1
);
2339 itstate
= thumb_advance_itstate (itstate
);
2344 else if (itstate
!= 0)
2346 /* We are in a conditional block. Check the condition. */
2347 if (! condition_true (itstate
>> 4, status
))
2349 /* Advance to the next executed instruction. */
2350 pc
+= thumb_insn_size (inst1
);
2351 itstate
= thumb_advance_itstate (itstate
);
2353 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2355 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2356 pc
+= thumb_insn_size (inst1
);
2357 itstate
= thumb_advance_itstate (itstate
);
2362 else if ((itstate
& 0x0f) == 0x08)
2364 /* This is the last instruction of the conditional
2365 block, and it is executed. We can handle it normally
2366 because the following instruction is not conditional,
2367 and we must handle it normally because it is
2368 permitted to branch. Fall through. */
2374 /* There are conditional instructions after this one.
2375 If this instruction modifies the flags, then we can
2376 not predict what the next executed instruction will
2377 be. Fortunately, this instruction is architecturally
2378 forbidden to branch; we know it will fall through.
2379 Start by skipping past it. */
2380 pc
+= thumb_insn_size (inst1
);
2381 itstate
= thumb_advance_itstate (itstate
);
2383 /* Set a breakpoint on the following instruction. */
2384 gdb_assert ((itstate
& 0x0f) != 0);
2385 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
2386 cond_negated
= (itstate
>> 4) & 1;
2388 /* Skip all following instructions with the same
2389 condition. If there is a later instruction in the IT
2390 block with the opposite condition, set the other
2391 breakpoint there. If not, then set a breakpoint on
2392 the instruction after the IT block. */
2395 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2396 pc
+= thumb_insn_size (inst1
);
2397 itstate
= thumb_advance_itstate (itstate
);
2399 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
2405 else if (itstate
& 0x0f)
2407 /* We are in a conditional block. Check the condition. */
2408 int cond
= itstate
>> 4;
2410 if (! condition_true (cond
, status
))
2412 /* Advance to the next instruction. All the 32-bit
2413 instructions share a common prefix. */
2414 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2420 /* Otherwise, handle the instruction normally. */
2423 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
2427 /* Fetch the saved PC from the stack. It's stored above
2428 all of the other registers. */
2429 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
2430 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
2431 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
2432 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2434 error (_("Infinite loop detected"));
2436 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
2438 unsigned long cond
= bits (inst1
, 8, 11);
2439 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
2440 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
2442 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
2444 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
2446 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
2448 unsigned short inst2
;
2449 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
2451 /* Default to the next instruction. */
2454 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
2456 /* Branches and miscellaneous control instructions. */
2458 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
2461 int j1
, j2
, imm1
, imm2
;
2463 imm1
= sbits (inst1
, 0, 10);
2464 imm2
= bits (inst2
, 0, 10);
2465 j1
= bit (inst2
, 13);
2466 j2
= bit (inst2
, 11);
2468 offset
= ((imm1
<< 12) + (imm2
<< 1));
2469 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
2471 nextpc
= pc_val
+ offset
;
2472 /* For BLX make sure to clear the low bits. */
2473 if (bit (inst2
, 12) == 0)
2474 nextpc
= nextpc
& 0xfffffffc;
2476 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
2478 /* SUBS PC, LR, #imm8. */
2479 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
2480 nextpc
-= inst2
& 0x00ff;
2482 else if ((inst2
& 0xd000) == 0xc000 && (inst1
& 0x0380) != 0x0380)
2484 /* Conditional branch. */
2485 if (condition_true (bits (inst1
, 6, 9), status
))
2487 int sign
, j1
, j2
, imm1
, imm2
;
2489 sign
= sbits (inst1
, 10, 10);
2490 imm1
= bits (inst1
, 0, 5);
2491 imm2
= bits (inst2
, 0, 10);
2492 j1
= bit (inst2
, 13);
2493 j2
= bit (inst2
, 11);
2495 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
2496 offset
+= (imm1
<< 12) + (imm2
<< 1);
2498 nextpc
= pc_val
+ offset
;
2502 else if ((inst1
& 0xfe50) == 0xe810)
2504 /* Load multiple or RFE. */
2505 int rn
, offset
, load_pc
= 1;
2507 rn
= bits (inst1
, 0, 3);
2508 if (bit (inst1
, 7) && !bit (inst1
, 8))
2511 if (!bit (inst2
, 15))
2513 offset
= bitcount (inst2
) * 4 - 4;
2515 else if (!bit (inst1
, 7) && bit (inst1
, 8))
2518 if (!bit (inst2
, 15))
2522 else if (bit (inst1
, 7) && bit (inst1
, 8))
2527 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
2537 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
2538 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
2541 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
2543 /* MOV PC or MOVS PC. */
2544 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2546 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
2550 int rn
, load_pc
= 1;
2552 rn
= bits (inst1
, 0, 3);
2553 base
= get_frame_register_unsigned (frame
, rn
);
2556 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
2558 base
+= bits (inst2
, 0, 11);
2560 base
-= bits (inst2
, 0, 11);
2562 else if (bit (inst1
, 7))
2563 base
+= bits (inst2
, 0, 11);
2564 else if (bit (inst2
, 11))
2566 if (bit (inst2
, 10))
2569 base
+= bits (inst2
, 0, 7);
2571 base
-= bits (inst2
, 0, 7);
2574 else if ((inst2
& 0x0fc0) == 0x0000)
2576 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
2577 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
2584 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
2586 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2589 CORE_ADDR table
, offset
, length
;
2591 table
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 3));
2592 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2593 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
2594 nextpc
= pc_val
+ length
;
2596 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2599 CORE_ADDR table
, offset
, length
;
2601 table
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 3));
2602 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2603 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
2604 nextpc
= pc_val
+ length
;
2607 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
2609 if (bits (inst1
, 3, 6) == 0x0f)
2612 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
2614 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2616 error (_("Infinite loop detected"));
2618 else if ((inst1
& 0xf500) == 0xb100)
2621 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
2622 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
2624 if (bit (inst1
, 11) && reg
!= 0)
2625 nextpc
= pc_val
+ imm
;
2626 else if (!bit (inst1
, 11) && reg
== 0)
2627 nextpc
= pc_val
+ imm
;
2634 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2636 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2637 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2638 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2639 unsigned long pc_val
;
2640 unsigned long this_instr
;
2641 unsigned long status
;
2644 if (arm_frame_is_thumb (frame
))
2645 return thumb_get_next_pc (frame
, pc
);
2647 pc_val
= (unsigned long) pc
;
2648 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
2650 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2651 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
2653 if (bits (this_instr
, 28, 31) == INST_NV
)
2654 switch (bits (this_instr
, 24, 27))
2659 /* Branch with Link and change to Thumb. */
2660 nextpc
= BranchDest (pc
, this_instr
);
2661 nextpc
|= bit (this_instr
, 24) << 1;
2663 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2665 error (_("Infinite loop detected"));
2671 /* Coprocessor register transfer. */
2672 if (bits (this_instr
, 12, 15) == 15)
2673 error (_("Invalid update to pc in instruction"));
2676 else if (condition_true (bits (this_instr
, 28, 31), status
))
2678 switch (bits (this_instr
, 24, 27))
2681 case 0x1: /* data processing */
2685 unsigned long operand1
, operand2
, result
= 0;
2689 if (bits (this_instr
, 12, 15) != 15)
2692 if (bits (this_instr
, 22, 25) == 0
2693 && bits (this_instr
, 4, 7) == 9) /* multiply */
2694 error (_("Invalid update to pc in instruction"));
2696 /* BX <reg>, BLX <reg> */
2697 if (bits (this_instr
, 4, 27) == 0x12fff1
2698 || bits (this_instr
, 4, 27) == 0x12fff3)
2700 rn
= bits (this_instr
, 0, 3);
2701 result
= (rn
== 15) ? pc_val
+ 8
2702 : get_frame_register_unsigned (frame
, rn
);
2703 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2707 error (_("Infinite loop detected"));
2712 /* Multiply into PC */
2713 c
= (status
& FLAG_C
) ? 1 : 0;
2714 rn
= bits (this_instr
, 16, 19);
2715 operand1
= (rn
== 15) ? pc_val
+ 8
2716 : get_frame_register_unsigned (frame
, rn
);
2718 if (bit (this_instr
, 25))
2720 unsigned long immval
= bits (this_instr
, 0, 7);
2721 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
2722 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
2725 else /* operand 2 is a shifted register */
2726 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
2728 switch (bits (this_instr
, 21, 24))
2731 result
= operand1
& operand2
;
2735 result
= operand1
^ operand2
;
2739 result
= operand1
- operand2
;
2743 result
= operand2
- operand1
;
2747 result
= operand1
+ operand2
;
2751 result
= operand1
+ operand2
+ c
;
2755 result
= operand1
- operand2
+ c
;
2759 result
= operand2
- operand1
+ c
;
2765 case 0xb: /* tst, teq, cmp, cmn */
2766 result
= (unsigned long) nextpc
;
2770 result
= operand1
| operand2
;
2774 /* Always step into a function. */
2779 result
= operand1
& ~operand2
;
2786 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2790 error (_("Infinite loop detected"));
2795 case 0x5: /* data transfer */
2798 if (bit (this_instr
, 20))
2801 if (bits (this_instr
, 12, 15) == 15)
2807 if (bit (this_instr
, 22))
2808 error (_("Invalid update to pc in instruction"));
2810 /* byte write to PC */
2811 rn
= bits (this_instr
, 16, 19);
2812 base
= (rn
== 15) ? pc_val
+ 8
2813 : get_frame_register_unsigned (frame
, rn
);
2814 if (bit (this_instr
, 24))
2817 int c
= (status
& FLAG_C
) ? 1 : 0;
2818 unsigned long offset
=
2819 (bit (this_instr
, 25)
2820 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2821 : bits (this_instr
, 0, 11));
2823 if (bit (this_instr
, 23))
2828 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2831 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2834 error (_("Infinite loop detected"));
2840 case 0x9: /* block transfer */
2841 if (bit (this_instr
, 20))
2844 if (bit (this_instr
, 15))
2849 if (bit (this_instr
, 23))
2852 unsigned long reglist
= bits (this_instr
, 0, 14);
2853 offset
= bitcount (reglist
) * 4;
2854 if (bit (this_instr
, 24)) /* pre */
2857 else if (bit (this_instr
, 24))
2861 unsigned long rn_val
=
2862 get_frame_register_unsigned (frame
,
2863 bits (this_instr
, 16, 19));
2865 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2869 nextpc
= gdbarch_addr_bits_remove
2872 error (_("Infinite loop detected"));
2877 case 0xb: /* branch & link */
2878 case 0xa: /* branch */
2880 nextpc
= BranchDest (pc
, this_instr
);
2882 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2884 error (_("Infinite loop detected"));
2890 case 0xe: /* coproc ops */
2895 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2903 /* single_step() is called just before we want to resume the inferior,
2904 if we want to single-step it but there is no hardware or kernel
2905 single-step support. We find the target of the coming instruction
2906 and breakpoint it. */
2909 arm_software_single_step (struct frame_info
*frame
)
2911 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2912 struct address_space
*aspace
= get_frame_address_space (frame
);
2914 /* NOTE: This may insert the wrong breakpoint instruction when
2915 single-stepping over a mode-changing instruction, if the
2916 CPSR heuristics are used. */
2918 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2919 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2924 /* ARM displaced stepping support.
2926 Generally ARM displaced stepping works as follows:
2928 1. When an instruction is to be single-stepped, it is first decoded by
2929 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
2930 Depending on the type of instruction, it is then copied to a scratch
2931 location, possibly in a modified form. The copy_* set of functions
2932 performs such modification, as necessary. A breakpoint is placed after
2933 the modified instruction in the scratch space to return control to GDB.
2934 Note in particular that instructions which modify the PC will no longer
2935 do so after modification.
2937 2. The instruction is single-stepped, by setting the PC to the scratch
2938 location address, and resuming. Control returns to GDB when the
2941 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
2942 function used for the current instruction. This function's job is to
2943 put the CPU/memory state back to what it would have been if the
2944 instruction had been executed unmodified in its original location. */
2946 /* NOP instruction (mov r0, r0). */
2947 #define ARM_NOP 0xe1a00000
2949 /* Helper for register reads for displaced stepping. In particular, this
2950 returns the PC as it would be seen by the instruction at its original
2954 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
2960 if (debug_displaced
)
2961 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
2962 (unsigned long) from
+ 8);
2963 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
2967 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
2968 if (debug_displaced
)
2969 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
2970 regno
, (unsigned long) ret
);
2976 displaced_in_arm_mode (struct regcache
*regs
)
2980 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
2982 return (ps
& CPSR_T
) == 0;
2985 /* Write to the PC as from a branch instruction. */
2988 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
2990 if (displaced_in_arm_mode (regs
))
2991 /* Note: If bits 0/1 are set, this branch would be unpredictable for
2992 architecture versions < 6. */
2993 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
2995 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
2998 /* Write to the PC as from a branch-exchange instruction. */
3001 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
3005 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3009 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| CPSR_T
);
3010 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
3012 else if ((val
& 2) == 0)
3014 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3015 ps
& ~(ULONGEST
) CPSR_T
);
3016 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
3020 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
3021 mode, align dest to 4 bytes). */
3022 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
3023 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3024 ps
& ~(ULONGEST
) CPSR_T
);
3025 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
3029 /* Write to the PC as if from a load instruction. */
3032 load_write_pc (struct regcache
*regs
, ULONGEST val
)
3034 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
3035 bx_write_pc (regs
, val
);
3037 branch_write_pc (regs
, val
);
3040 /* Write to the PC as if from an ALU instruction. */
3043 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
3045 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
3046 bx_write_pc (regs
, val
);
3048 branch_write_pc (regs
, val
);
3051 /* Helper for writing to registers for displaced stepping. Writing to the PC
3052 has a varying effects depending on the instruction which does the write:
3053 this is controlled by the WRITE_PC argument. */
3056 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
3057 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
3061 if (debug_displaced
)
3062 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
3063 (unsigned long) val
);
3066 case BRANCH_WRITE_PC
:
3067 branch_write_pc (regs
, val
);
3071 bx_write_pc (regs
, val
);
3075 load_write_pc (regs
, val
);
3079 alu_write_pc (regs
, val
);
3082 case CANNOT_WRITE_PC
:
3083 warning (_("Instruction wrote to PC in an unexpected way when "
3084 "single-stepping"));
3088 internal_error (__FILE__
, __LINE__
,
3089 _("Invalid argument to displaced_write_reg"));
3092 dsc
->wrote_to_pc
= 1;
3096 if (debug_displaced
)
3097 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
3098 regno
, (unsigned long) val
);
3099 regcache_cooked_write_unsigned (regs
, regno
, val
);
3103 /* This function is used to concisely determine if an instruction INSN
3104 references PC. Register fields of interest in INSN should have the
3105 corresponding fields of BITMASK set to 0b1111. The function returns return 1
3106 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
3110 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
3112 uint32_t lowbit
= 1;
3114 while (bitmask
!= 0)
3118 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
3124 mask
= lowbit
* 0xf;
3126 if ((insn
& mask
) == mask
)
3135 /* The simplest copy function. Many instructions have the same effect no
3136 matter what address they are executed at: in those cases, use this. */
3139 copy_unmodified (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3140 const char *iname
, struct displaced_step_closure
*dsc
)
3142 if (debug_displaced
)
3143 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
3144 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
3147 dsc
->modinsn
[0] = insn
;
3152 /* Preload instructions with immediate offset. */
3155 cleanup_preload (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3156 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3158 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3159 if (!dsc
->u
.preload
.immed
)
3160 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3164 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3165 struct displaced_step_closure
*dsc
)
3167 unsigned int rn
= bits (insn
, 16, 19);
3169 CORE_ADDR from
= dsc
->insn_addr
;
3171 if (!insn_references_pc (insn
, 0x000f0000ul
))
3172 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
3174 if (debug_displaced
)
3175 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3176 (unsigned long) insn
);
3178 /* Preload instructions:
3180 {pli/pld} [rn, #+/-imm]
3182 {pli/pld} [r0, #+/-imm]. */
3184 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3185 rn_val
= displaced_read_reg (regs
, from
, rn
);
3186 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3188 dsc
->u
.preload
.immed
= 1;
3190 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3192 dsc
->cleanup
= &cleanup_preload
;
3197 /* Preload instructions with register offset. */
3200 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3201 struct displaced_step_closure
*dsc
)
3203 unsigned int rn
= bits (insn
, 16, 19);
3204 unsigned int rm
= bits (insn
, 0, 3);
3205 ULONGEST rn_val
, rm_val
;
3206 CORE_ADDR from
= dsc
->insn_addr
;
3208 if (!insn_references_pc (insn
, 0x000f000ful
))
3209 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
3211 if (debug_displaced
)
3212 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3213 (unsigned long) insn
);
3215 /* Preload register-offset instructions:
3217 {pli/pld} [rn, rm {, shift}]
3219 {pli/pld} [r0, r1 {, shift}]. */
3221 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3222 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3223 rn_val
= displaced_read_reg (regs
, from
, rn
);
3224 rm_val
= displaced_read_reg (regs
, from
, rm
);
3225 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3226 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
3228 dsc
->u
.preload
.immed
= 0;
3230 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
3232 dsc
->cleanup
= &cleanup_preload
;
3237 /* Copy/cleanup coprocessor load and store instructions. */
3240 cleanup_copro_load_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3241 struct regcache
*regs
,
3242 struct displaced_step_closure
*dsc
)
3244 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3246 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3248 if (dsc
->u
.ldst
.writeback
)
3249 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
3253 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
3254 struct regcache
*regs
,
3255 struct displaced_step_closure
*dsc
)
3257 unsigned int rn
= bits (insn
, 16, 19);
3259 CORE_ADDR from
= dsc
->insn_addr
;
3261 if (!insn_references_pc (insn
, 0x000f0000ul
))
3262 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
3264 if (debug_displaced
)
3265 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
3266 "load/store insn %.8lx\n", (unsigned long) insn
);
3268 /* Coprocessor load/store instructions:
3270 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
3272 {stc/stc2} [r0, #+/-imm].
3274 ldc/ldc2 are handled identically. */
3276 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3277 rn_val
= displaced_read_reg (regs
, from
, rn
);
3278 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3280 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
3281 dsc
->u
.ldst
.rn
= rn
;
3283 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3285 dsc
->cleanup
= &cleanup_copro_load_store
;
3290 /* Clean up branch instructions (actually perform the branch, by setting
3294 cleanup_branch (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3295 struct displaced_step_closure
*dsc
)
3297 ULONGEST from
= dsc
->insn_addr
;
3298 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3299 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
3300 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
3301 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
3306 if (dsc
->u
.branch
.link
)
3308 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
3309 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
3312 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
3315 /* Copy B/BL/BLX instructions with immediate destinations. */
3318 copy_b_bl_blx (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3319 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3321 unsigned int cond
= bits (insn
, 28, 31);
3322 int exchange
= (cond
== 0xf);
3323 int link
= exchange
|| bit (insn
, 24);
3324 CORE_ADDR from
= dsc
->insn_addr
;
3327 if (debug_displaced
)
3328 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
3329 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
3330 (unsigned long) insn
);
3332 /* Implement "BL<cond> <label>" as:
3334 Preparation: cond <- instruction condition
3335 Insn: mov r0, r0 (nop)
3336 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
3338 B<cond> similar, but don't set r14 in cleanup. */
3341 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
3342 then arrange the switch into Thumb mode. */
3343 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
3345 offset
= bits (insn
, 0, 23) << 2;
3347 if (bit (offset
, 25))
3348 offset
= offset
| ~0x3ffffff;
3350 dsc
->u
.branch
.cond
= cond
;
3351 dsc
->u
.branch
.link
= link
;
3352 dsc
->u
.branch
.exchange
= exchange
;
3353 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
3355 dsc
->modinsn
[0] = ARM_NOP
;
3357 dsc
->cleanup
= &cleanup_branch
;
3362 /* Copy BX/BLX with register-specified destinations. */
3365 copy_bx_blx_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3366 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3368 unsigned int cond
= bits (insn
, 28, 31);
3371 int link
= bit (insn
, 5);
3372 unsigned int rm
= bits (insn
, 0, 3);
3373 CORE_ADDR from
= dsc
->insn_addr
;
3375 if (debug_displaced
)
3376 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
3377 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
3379 /* Implement {BX,BLX}<cond> <reg>" as:
3381 Preparation: cond <- instruction condition
3382 Insn: mov r0, r0 (nop)
3383 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
3385 Don't set r14 in cleanup for BX. */
3387 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
3389 dsc
->u
.branch
.cond
= cond
;
3390 dsc
->u
.branch
.link
= link
;
3391 dsc
->u
.branch
.exchange
= 1;
3393 dsc
->modinsn
[0] = ARM_NOP
;
3395 dsc
->cleanup
= &cleanup_branch
;
3400 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
3403 cleanup_alu_imm (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3404 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3406 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3407 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3408 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3409 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3413 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3414 struct displaced_step_closure
*dsc
)
3416 unsigned int rn
= bits (insn
, 16, 19);
3417 unsigned int rd
= bits (insn
, 12, 15);
3418 unsigned int op
= bits (insn
, 21, 24);
3419 int is_mov
= (op
== 0xd);
3420 ULONGEST rd_val
, rn_val
;
3421 CORE_ADDR from
= dsc
->insn_addr
;
3423 if (!insn_references_pc (insn
, 0x000ff000ul
))
3424 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
3426 if (debug_displaced
)
3427 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
3428 "%.8lx\n", is_mov
? "move" : "ALU",
3429 (unsigned long) insn
);
3431 /* Instruction is of form:
3433 <op><cond> rd, [rn,] #imm
3437 Preparation: tmp1, tmp2 <- r0, r1;
3439 Insn: <op><cond> r0, r1, #imm
3440 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
3443 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3444 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3445 rn_val
= displaced_read_reg (regs
, from
, rn
);
3446 rd_val
= displaced_read_reg (regs
, from
, rd
);
3447 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3448 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3452 dsc
->modinsn
[0] = insn
& 0xfff00fff;
3454 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
3456 dsc
->cleanup
= &cleanup_alu_imm
;
3461 /* Copy/cleanup arithmetic/logic insns with register RHS. */
3464 cleanup_alu_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3465 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3470 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3472 for (i
= 0; i
< 3; i
++)
3473 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3475 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3479 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3480 struct displaced_step_closure
*dsc
)
3482 unsigned int rn
= bits (insn
, 16, 19);
3483 unsigned int rm
= bits (insn
, 0, 3);
3484 unsigned int rd
= bits (insn
, 12, 15);
3485 unsigned int op
= bits (insn
, 21, 24);
3486 int is_mov
= (op
== 0xd);
3487 ULONGEST rd_val
, rn_val
, rm_val
;
3488 CORE_ADDR from
= dsc
->insn_addr
;
3490 if (!insn_references_pc (insn
, 0x000ff00ful
))
3491 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
3493 if (debug_displaced
)
3494 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
3495 is_mov
? "move" : "ALU", (unsigned long) insn
);
3497 /* Instruction is of form:
3499 <op><cond> rd, [rn,] rm [, <shift>]
3503 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
3504 r0, r1, r2 <- rd, rn, rm
3505 Insn: <op><cond> r0, r1, r2 [, <shift>]
3506 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
3509 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3510 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3511 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3512 rd_val
= displaced_read_reg (regs
, from
, rd
);
3513 rn_val
= displaced_read_reg (regs
, from
, rn
);
3514 rm_val
= displaced_read_reg (regs
, from
, rm
);
3515 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3516 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3517 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3521 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
3523 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
3525 dsc
->cleanup
= &cleanup_alu_reg
;
3530 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
3533 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3534 struct regcache
*regs
,
3535 struct displaced_step_closure
*dsc
)
3537 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3540 for (i
= 0; i
< 4; i
++)
3541 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
3543 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3547 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
3548 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3550 unsigned int rn
= bits (insn
, 16, 19);
3551 unsigned int rm
= bits (insn
, 0, 3);
3552 unsigned int rd
= bits (insn
, 12, 15);
3553 unsigned int rs
= bits (insn
, 8, 11);
3554 unsigned int op
= bits (insn
, 21, 24);
3555 int is_mov
= (op
== 0xd), i
;
3556 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
3557 CORE_ADDR from
= dsc
->insn_addr
;
3559 if (!insn_references_pc (insn
, 0x000fff0ful
))
3560 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
3562 if (debug_displaced
)
3563 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
3564 "%.8lx\n", is_mov
? "move" : "ALU",
3565 (unsigned long) insn
);
3567 /* Instruction is of form:
3569 <op><cond> rd, [rn,] rm, <shift> rs
3573 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
3574 r0, r1, r2, r3 <- rd, rn, rm, rs
3575 Insn: <op><cond> r0, r1, r2, <shift> r3
3577 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
3581 for (i
= 0; i
< 4; i
++)
3582 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
3584 rd_val
= displaced_read_reg (regs
, from
, rd
);
3585 rn_val
= displaced_read_reg (regs
, from
, rn
);
3586 rm_val
= displaced_read_reg (regs
, from
, rm
);
3587 rs_val
= displaced_read_reg (regs
, from
, rs
);
3588 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
3589 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
3590 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
3591 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
3595 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
3597 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
3599 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
3604 /* Clean up load instructions. */
3607 cleanup_load (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3608 struct displaced_step_closure
*dsc
)
3610 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
3611 CORE_ADDR from
= dsc
->insn_addr
;
3613 rt_val
= displaced_read_reg (regs
, from
, 0);
3614 if (dsc
->u
.ldst
.xfersize
== 8)
3615 rt_val2
= displaced_read_reg (regs
, from
, 1);
3616 rn_val
= displaced_read_reg (regs
, from
, 2);
3618 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3619 if (dsc
->u
.ldst
.xfersize
> 4)
3620 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3621 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3622 if (!dsc
->u
.ldst
.immed
)
3623 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3625 /* Handle register writeback. */
3626 if (dsc
->u
.ldst
.writeback
)
3627 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3628 /* Put result in right place. */
3629 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
3630 if (dsc
->u
.ldst
.xfersize
== 8)
3631 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
3634 /* Clean up store instructions. */
3637 cleanup_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3638 struct displaced_step_closure
*dsc
)
3640 CORE_ADDR from
= dsc
->insn_addr
;
3641 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
3643 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3644 if (dsc
->u
.ldst
.xfersize
> 4)
3645 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3646 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
3647 if (!dsc
->u
.ldst
.immed
)
3648 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
3649 if (!dsc
->u
.ldst
.restore_r4
)
3650 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
3653 if (dsc
->u
.ldst
.writeback
)
3654 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
3657 /* Copy "extra" load/store instructions. These are halfword/doubleword
3658 transfers, which have a different encoding to byte/word transfers. */
3661 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
3662 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3664 unsigned int op1
= bits (insn
, 20, 24);
3665 unsigned int op2
= bits (insn
, 5, 6);
3666 unsigned int rt
= bits (insn
, 12, 15);
3667 unsigned int rn
= bits (insn
, 16, 19);
3668 unsigned int rm
= bits (insn
, 0, 3);
3669 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
3670 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
3671 int immed
= (op1
& 0x4) != 0;
3673 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
3674 CORE_ADDR from
= dsc
->insn_addr
;
3676 if (!insn_references_pc (insn
, 0x000ff00ful
))
3677 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
3679 if (debug_displaced
)
3680 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
3681 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
3682 (unsigned long) insn
);
3684 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
3687 internal_error (__FILE__
, __LINE__
,
3688 _("copy_extra_ld_st: instruction decode error"));
3690 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3691 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3692 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3694 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3696 rt_val
= displaced_read_reg (regs
, from
, rt
);
3697 if (bytesize
[opcode
] == 8)
3698 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
3699 rn_val
= displaced_read_reg (regs
, from
, rn
);
3701 rm_val
= displaced_read_reg (regs
, from
, rm
);
3703 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
3704 if (bytesize
[opcode
] == 8)
3705 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
3706 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
3708 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
3711 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
3712 dsc
->u
.ldst
.rn
= rn
;
3713 dsc
->u
.ldst
.immed
= immed
;
3714 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
3715 dsc
->u
.ldst
.restore_r4
= 0;
3718 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
3720 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
3721 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
3723 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
3725 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
3726 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
3728 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
3733 /* Copy byte/word loads and stores. */
3736 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
3737 struct regcache
*regs
,
3738 struct displaced_step_closure
*dsc
, int load
, int byte
,
3741 int immed
= !bit (insn
, 25);
3742 unsigned int rt
= bits (insn
, 12, 15);
3743 unsigned int rn
= bits (insn
, 16, 19);
3744 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
3745 ULONGEST rt_val
, rn_val
, rm_val
= 0;
3746 CORE_ADDR from
= dsc
->insn_addr
;
3748 if (!insn_references_pc (insn
, 0x000ff00ful
))
3749 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
3751 if (debug_displaced
)
3752 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
3753 load
? (byte
? "ldrb" : "ldr")
3754 : (byte
? "strb" : "str"), usermode
? "t" : "",
3755 (unsigned long) insn
);
3757 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3758 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
3760 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
3762 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
3764 rt_val
= displaced_read_reg (regs
, from
, rt
);
3765 rn_val
= displaced_read_reg (regs
, from
, rn
);
3767 rm_val
= displaced_read_reg (regs
, from
, rm
);
3769 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
3770 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
3772 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
3775 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
3776 dsc
->u
.ldst
.rn
= rn
;
3777 dsc
->u
.ldst
.immed
= immed
;
3778 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
3780 /* To write PC we can do:
3782 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
3783 scratch+4: ldr r4, temp
3784 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
3785 scratch+12: add r4, r4, #8 (r4 = offset)
3786 scratch+16: add r0, r0, r4
3787 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
3790 Otherwise we don't know what value to write for PC, since the offset is
3791 architecture-dependent (sometimes PC+8, sometimes PC+12). */
3793 if (load
|| rt
!= 15)
3795 dsc
->u
.ldst
.restore_r4
= 0;
3798 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
3800 {ldr,str}[b]<cond> r0, [r2, #imm]. */
3801 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
3803 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
3805 {ldr,str}[b]<cond> r0, [r2, r3]. */
3806 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
3810 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
3811 dsc
->u
.ldst
.restore_r4
= 1;
3813 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
3814 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
3815 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
3816 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
3817 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
3821 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
3823 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
3825 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
3826 dsc
->modinsn
[7] = 0x0; /* scratch space. */
3831 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
3836 /* Cleanup LDM instructions with fully-populated register list. This is an
3837 unfortunate corner case: it's impossible to implement correctly by modifying
3838 the instruction. The issue is as follows: we have an instruction,
3842 which we must rewrite to avoid loading PC. A possible solution would be to
3843 do the load in two halves, something like (with suitable cleanup
3847 ldm[id][ab] r8!, {r0-r7}
3849 ldm[id][ab] r8, {r7-r14}
3852 but at present there's no suitable place for <temp>, since the scratch space
3853 is overwritten before the cleanup routine is called. For now, we simply
3854 emulate the instruction. */
3857 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
3858 struct displaced_step_closure
*dsc
)
3860 ULONGEST from
= dsc
->insn_addr
;
3861 int inc
= dsc
->u
.block
.increment
;
3862 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
3863 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
3864 uint32_t regmask
= dsc
->u
.block
.regmask
;
3865 int regno
= inc
? 0 : 15;
3866 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
3867 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
3868 && (regmask
& 0x8000) != 0;
3869 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3870 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
3871 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3876 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
3877 sensible we can do here. Complain loudly. */
3878 if (exception_return
)
3879 error (_("Cannot single-step exception return"));
3881 /* We don't handle any stores here for now. */
3882 gdb_assert (dsc
->u
.block
.load
!= 0);
3884 if (debug_displaced
)
3885 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
3886 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
3887 dsc
->u
.block
.increment
? "inc" : "dec",
3888 dsc
->u
.block
.before
? "before" : "after");
3895 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
3898 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
3901 xfer_addr
+= bump_before
;
3903 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
3904 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
3906 xfer_addr
+= bump_after
;
3908 regmask
&= ~(1 << regno
);
3911 if (dsc
->u
.block
.writeback
)
3912 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
3916 /* Clean up an STM which included the PC in the register list. */
3919 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
3920 struct displaced_step_closure
*dsc
)
3922 ULONGEST from
= dsc
->insn_addr
;
3923 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3924 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
3925 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
3926 CORE_ADDR stm_insn_addr
;
3929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3931 /* If condition code fails, there's nothing else to do. */
3932 if (!store_executed
)
3935 if (dsc
->u
.block
.increment
)
3937 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
3939 if (dsc
->u
.block
.before
)
3944 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
3946 if (dsc
->u
.block
.before
)
3950 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
3951 stm_insn_addr
= dsc
->scratch_base
;
3952 offset
= pc_val
- stm_insn_addr
;
3954 if (debug_displaced
)
3955 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
3956 "STM instruction\n", offset
);
3958 /* Rewrite the stored PC to the proper value for the non-displaced original
3960 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
3961 dsc
->insn_addr
+ offset
);
3964 /* Clean up an LDM which includes the PC in the register list. We clumped all
3965 the registers in the transferred list into a contiguous range r0...rX (to
3966 avoid loading PC directly and losing control of the debugged program), so we
3967 must undo that here. */
3970 cleanup_block_load_pc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3971 struct regcache
*regs
,
3972 struct displaced_step_closure
*dsc
)
3974 ULONGEST from
= dsc
->insn_addr
;
3975 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3976 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
3977 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
3978 unsigned int regs_loaded
= bitcount (mask
);
3979 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
3981 /* The method employed here will fail if the register list is fully populated
3982 (we need to avoid loading PC directly). */
3983 gdb_assert (num_to_shuffle
< 16);
3988 clobbered
= (1 << num_to_shuffle
) - 1;
3990 while (num_to_shuffle
> 0)
3992 if ((mask
& (1 << write_reg
)) != 0)
3994 unsigned int read_reg
= num_to_shuffle
- 1;
3996 if (read_reg
!= write_reg
)
3998 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
3999 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
4000 if (debug_displaced
)
4001 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
4002 "loaded register r%d to r%d\n"), read_reg
,
4005 else if (debug_displaced
)
4006 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
4007 "r%d already in the right place\n"),
4010 clobbered
&= ~(1 << write_reg
);
4018 /* Restore any registers we scribbled over. */
4019 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
4021 if ((clobbered
& (1 << write_reg
)) != 0)
4023 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
4025 if (debug_displaced
)
4026 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
4027 "clobbered register r%d\n"), write_reg
);
4028 clobbered
&= ~(1 << write_reg
);
4032 /* Perform register writeback manually. */
4033 if (dsc
->u
.block
.writeback
)
4035 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
4037 if (dsc
->u
.block
.increment
)
4038 new_rn_val
+= regs_loaded
* 4;
4040 new_rn_val
-= regs_loaded
* 4;
4042 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
4047 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
4048 in user-level code (in particular exception return, ldm rn, {...pc}^). */
4051 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4052 struct displaced_step_closure
*dsc
)
4054 int load
= bit (insn
, 20);
4055 int user
= bit (insn
, 22);
4056 int increment
= bit (insn
, 23);
4057 int before
= bit (insn
, 24);
4058 int writeback
= bit (insn
, 21);
4059 int rn
= bits (insn
, 16, 19);
4060 CORE_ADDR from
= dsc
->insn_addr
;
4062 /* Block transfers which don't mention PC can be run directly out-of-line. */
4063 if (rn
!= 15 && (insn
& 0x8000) == 0)
4064 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
4068 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
4069 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
4072 if (debug_displaced
)
4073 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
4074 "%.8lx\n", (unsigned long) insn
);
4076 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
4077 dsc
->u
.block
.rn
= rn
;
4079 dsc
->u
.block
.load
= load
;
4080 dsc
->u
.block
.user
= user
;
4081 dsc
->u
.block
.increment
= increment
;
4082 dsc
->u
.block
.before
= before
;
4083 dsc
->u
.block
.writeback
= writeback
;
4084 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
4086 dsc
->u
.block
.regmask
= insn
& 0xffff;
4090 if ((insn
& 0xffff) == 0xffff)
4092 /* LDM with a fully-populated register list. This case is
4093 particularly tricky. Implement for now by fully emulating the
4094 instruction (which might not behave perfectly in all cases, but
4095 these instructions should be rare enough for that not to matter
4097 dsc
->modinsn
[0] = ARM_NOP
;
4099 dsc
->cleanup
= &cleanup_block_load_all
;
4103 /* LDM of a list of registers which includes PC. Implement by
4104 rewriting the list of registers to be transferred into a
4105 contiguous chunk r0...rX before doing the transfer, then shuffling
4106 registers into the correct places in the cleanup routine. */
4107 unsigned int regmask
= insn
& 0xffff;
4108 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
4109 unsigned int to
= 0, from
= 0, i
, new_rn
;
4111 for (i
= 0; i
< num_in_list
; i
++)
4112 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4114 /* Writeback makes things complicated. We need to avoid clobbering
4115 the base register with one of the registers in our modified
4116 register list, but just using a different register can't work in
4119 ldm r14!, {r0-r13,pc}
4121 which would need to be rewritten as:
4125 but that can't work, because there's no free register for N.
4127 Solve this by turning off the writeback bit, and emulating
4128 writeback manually in the cleanup routine. */
4133 new_regmask
= (1 << num_in_list
) - 1;
4135 if (debug_displaced
)
4136 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
4137 "{..., pc}: original reg list %.4x, modified "
4138 "list %.4x\n"), rn
, writeback
? "!" : "",
4139 (int) insn
& 0xffff, new_regmask
);
4141 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
4143 dsc
->cleanup
= &cleanup_block_load_pc
;
4148 /* STM of a list of registers which includes PC. Run the instruction
4149 as-is, but out of line: this will store the wrong value for the PC,
4150 so we must manually fix up the memory in the cleanup routine.
4151 Doing things this way has the advantage that we can auto-detect
4152 the offset of the PC write (which is architecture-dependent) in
4153 the cleanup routine. */
4154 dsc
->modinsn
[0] = insn
;
4156 dsc
->cleanup
= &cleanup_block_store_pc
;
4162 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
4163 for Linux, where some SVC instructions must be treated specially. */
4166 cleanup_svc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
4167 struct displaced_step_closure
*dsc
)
4169 CORE_ADDR from
= dsc
->insn_addr
;
4170 CORE_ADDR resume_addr
= from
+ 4;
4172 if (debug_displaced
)
4173 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
4174 "%.8lx\n", (unsigned long) resume_addr
);
4176 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
4180 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4181 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4183 CORE_ADDR from
= dsc
->insn_addr
;
4185 /* Allow OS-specific code to override SVC handling. */
4186 if (dsc
->u
.svc
.copy_svc_os
)
4187 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
4189 if (debug_displaced
)
4190 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
4191 (unsigned long) insn
);
4193 /* Preparation: none.
4194 Insn: unmodified svc.
4195 Cleanup: pc <- insn_addr + 4. */
4197 dsc
->modinsn
[0] = insn
;
4199 dsc
->cleanup
= &cleanup_svc
;
4200 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
4202 dsc
->wrote_to_pc
= 1;
4207 /* Copy undefined instructions. */
4210 copy_undef (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4211 struct displaced_step_closure
*dsc
)
4213 if (debug_displaced
)
4214 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
4215 (unsigned long) insn
);
4217 dsc
->modinsn
[0] = insn
;
4222 /* Copy unpredictable instructions. */
4225 copy_unpred (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4226 struct displaced_step_closure
*dsc
)
4228 if (debug_displaced
)
4229 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
4230 "%.8lx\n", (unsigned long) insn
);
4232 dsc
->modinsn
[0] = insn
;
4237 /* The decode_* functions are instruction decoding helpers. They mostly follow
4238 the presentation in the ARM ARM. */
4241 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
4242 struct regcache
*regs
,
4243 struct displaced_step_closure
*dsc
)
4245 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
4246 unsigned int rn
= bits (insn
, 16, 19);
4248 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
4249 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
4250 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
4251 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
4252 else if ((op1
& 0x60) == 0x20)
4253 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
4254 else if ((op1
& 0x71) == 0x40)
4255 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
4256 else if ((op1
& 0x77) == 0x41)
4257 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4258 else if ((op1
& 0x77) == 0x45)
4259 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
4260 else if ((op1
& 0x77) == 0x51)
4263 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4265 return copy_unpred (gdbarch
, insn
, dsc
);
4267 else if ((op1
& 0x77) == 0x55)
4268 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4269 else if (op1
== 0x57)
4272 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
4273 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
4274 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
4275 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
4276 default: return copy_unpred (gdbarch
, insn
, dsc
);
4278 else if ((op1
& 0x63) == 0x43)
4279 return copy_unpred (gdbarch
, insn
, dsc
);
4280 else if ((op2
& 0x1) == 0x0)
4281 switch (op1
& ~0x80)
4284 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4286 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
4287 case 0x71: case 0x75:
4289 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
4290 case 0x63: case 0x67: case 0x73: case 0x77:
4291 return copy_unpred (gdbarch
, insn
, dsc
);
4293 return copy_undef (gdbarch
, insn
, dsc
);
4296 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
4300 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
4301 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4303 if (bit (insn
, 27) == 0)
4304 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
4305 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
4306 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
4309 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
4312 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
4314 case 0x4: case 0x5: case 0x6: case 0x7:
4315 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4318 switch ((insn
& 0xe00000) >> 21)
4320 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
4322 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4325 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4328 return copy_undef (gdbarch
, insn
, dsc
);
4333 int rn_f
= (bits (insn
, 16, 19) == 0xf);
4334 switch ((insn
& 0xe00000) >> 21)
4337 /* ldc/ldc2 imm (undefined for rn == pc). */
4338 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
4339 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4342 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4344 case 0x4: case 0x5: case 0x6: case 0x7:
4345 /* ldc/ldc2 lit (undefined for rn != pc). */
4346 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
4347 : copy_undef (gdbarch
, insn
, dsc
);
4350 return copy_undef (gdbarch
, insn
, dsc
);
4355 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
4358 if (bits (insn
, 16, 19) == 0xf)
4360 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4362 return copy_undef (gdbarch
, insn
, dsc
);
4366 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4368 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4372 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4374 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4377 return copy_undef (gdbarch
, insn
, dsc
);
4381 /* Decode miscellaneous instructions in dp/misc encoding space. */
4384 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
4385 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4387 unsigned int op2
= bits (insn
, 4, 6);
4388 unsigned int op
= bits (insn
, 21, 22);
4389 unsigned int op1
= bits (insn
, 16, 19);
4394 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
4397 if (op
== 0x1) /* bx. */
4398 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
4400 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
4402 return copy_undef (gdbarch
, insn
, dsc
);
4406 /* Not really supported. */
4407 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
4409 return copy_undef (gdbarch
, insn
, dsc
);
4413 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
4415 return copy_undef (gdbarch
, insn
, dsc
);
4418 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
4422 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
4424 /* Not really supported. */
4425 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
4428 return copy_undef (gdbarch
, insn
, dsc
);
4433 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4434 struct displaced_step_closure
*dsc
)
4437 switch (bits (insn
, 20, 24))
4440 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
4443 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
4445 case 0x12: case 0x16:
4446 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
4449 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
4453 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
4455 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
4456 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
4457 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
4458 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
4459 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
4460 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
4461 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
4462 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
4463 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
4464 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
4465 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
4466 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
4467 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
4468 /* 2nd arg means "unpriveleged". */
4469 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
4473 /* Should be unreachable. */
4478 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
4479 struct regcache
*regs
,
4480 struct displaced_step_closure
*dsc
)
4482 int a
= bit (insn
, 25), b
= bit (insn
, 4);
4483 uint32_t op1
= bits (insn
, 20, 24);
4484 int rn_f
= bits (insn
, 16, 19) == 0xf;
4486 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
4487 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
4488 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
4489 else if ((!a
&& (op1
& 0x17) == 0x02)
4490 || (a
&& (op1
& 0x17) == 0x02 && !b
))
4491 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
4492 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
4493 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
4494 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
4495 else if ((!a
&& (op1
& 0x17) == 0x03)
4496 || (a
&& (op1
& 0x17) == 0x03 && !b
))
4497 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
4498 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
4499 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
4500 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
4501 else if ((!a
&& (op1
& 0x17) == 0x06)
4502 || (a
&& (op1
& 0x17) == 0x06 && !b
))
4503 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
4504 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
4505 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
4506 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
4507 else if ((!a
&& (op1
& 0x17) == 0x07)
4508 || (a
&& (op1
& 0x17) == 0x07 && !b
))
4509 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
4511 /* Should be unreachable. */
4516 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
4517 struct displaced_step_closure
*dsc
)
4519 switch (bits (insn
, 20, 24))
4521 case 0x00: case 0x01: case 0x02: case 0x03:
4522 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
4524 case 0x04: case 0x05: case 0x06: case 0x07:
4525 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
4527 case 0x08: case 0x09: case 0x0a: case 0x0b:
4528 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
4529 return copy_unmodified (gdbarch
, insn
,
4530 "decode/pack/unpack/saturate/reverse", dsc
);
4533 if (bits (insn
, 5, 7) == 0) /* op2. */
4535 if (bits (insn
, 12, 15) == 0xf)
4536 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
4538 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
4541 return copy_undef (gdbarch
, insn
, dsc
);
4543 case 0x1a: case 0x1b:
4544 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4545 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
4547 return copy_undef (gdbarch
, insn
, dsc
);
4549 case 0x1c: case 0x1d:
4550 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
4552 if (bits (insn
, 0, 3) == 0xf)
4553 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
4555 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
4558 return copy_undef (gdbarch
, insn
, dsc
);
4560 case 0x1e: case 0x1f:
4561 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
4562 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
4564 return copy_undef (gdbarch
, insn
, dsc
);
4567 /* Should be unreachable. */
4572 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
4573 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4576 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4578 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
4582 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
4583 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4585 unsigned int opcode
= bits (insn
, 20, 24);
4589 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
4590 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
4592 case 0x08: case 0x0a: case 0x0c: case 0x0e:
4593 case 0x12: case 0x16:
4594 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
4596 case 0x09: case 0x0b: case 0x0d: case 0x0f:
4597 case 0x13: case 0x17:
4598 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
4600 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
4601 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
4602 /* Note: no writeback for these instructions. Bit 25 will always be
4603 zero though (via caller), so the following works OK. */
4604 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4607 /* Should be unreachable. */
4612 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4613 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4615 unsigned int op1
= bits (insn
, 20, 25);
4616 int op
= bit (insn
, 4);
4617 unsigned int coproc
= bits (insn
, 8, 11);
4618 unsigned int rn
= bits (insn
, 16, 19);
4620 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
4621 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
4622 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
4623 && (coproc
& 0xe) != 0xa)
4625 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4626 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
4627 && (coproc
& 0xe) != 0xa)
4628 /* ldc/ldc2 imm/lit. */
4629 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4630 else if ((op1
& 0x3e) == 0x00)
4631 return copy_undef (gdbarch
, insn
, dsc
);
4632 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
4633 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
4634 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
4635 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4636 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
4637 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4638 else if ((op1
& 0x30) == 0x20 && !op
)
4640 if ((coproc
& 0xe) == 0xa)
4641 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
4643 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4645 else if ((op1
& 0x30) == 0x20 && op
)
4646 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
4647 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
4648 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4649 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
4650 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4651 else if ((op1
& 0x30) == 0x30)
4652 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
4654 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
4658 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
4659 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
4660 struct displaced_step_closure
*dsc
)
4664 if (!displaced_in_arm_mode (regs
))
4665 error (_("Displaced stepping is only supported in ARM mode"));
4667 /* Most displaced instructions use a 1-instruction scratch space, so set this
4668 here and override below if/when necessary. */
4670 dsc
->insn_addr
= from
;
4671 dsc
->scratch_base
= to
;
4672 dsc
->cleanup
= NULL
;
4673 dsc
->wrote_to_pc
= 0;
4675 if ((insn
& 0xf0000000) == 0xf0000000)
4676 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
4677 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
4679 case 0x0: case 0x1: case 0x2: case 0x3:
4680 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
4683 case 0x4: case 0x5: case 0x6:
4684 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
4688 err
= decode_media (gdbarch
, insn
, dsc
);
4691 case 0x8: case 0x9: case 0xa: case 0xb:
4692 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
4695 case 0xc: case 0xd: case 0xe: case 0xf:
4696 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
4701 internal_error (__FILE__
, __LINE__
,
4702 _("arm_process_displaced_insn: Instruction decode error"));
4705 /* Actually set up the scratch space for a displaced instruction. */
4708 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
4709 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
4711 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4713 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4715 /* Poke modified instruction(s). */
4716 for (i
= 0; i
< dsc
->numinsns
; i
++)
4718 if (debug_displaced
)
4719 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
4720 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
4721 (unsigned long) to
+ i
* 4);
4722 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
4726 /* Put breakpoint afterwards. */
4727 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
4728 tdep
->arm_breakpoint_size
);
4730 if (debug_displaced
)
4731 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
4732 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
4735 /* Entry point for copying an instruction into scratch space for displaced
4738 struct displaced_step_closure
*
4739 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
4740 CORE_ADDR from
, CORE_ADDR to
,
4741 struct regcache
*regs
)
4743 struct displaced_step_closure
*dsc
4744 = xmalloc (sizeof (struct displaced_step_closure
));
4745 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4746 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
4748 if (debug_displaced
)
4749 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
4750 "at %.8lx\n", (unsigned long) insn
,
4751 (unsigned long) from
);
4753 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
4754 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
4759 /* Entry point for cleaning things up after a displaced instruction has been
4763 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
4764 struct displaced_step_closure
*dsc
,
4765 CORE_ADDR from
, CORE_ADDR to
,
4766 struct regcache
*regs
)
4769 dsc
->cleanup (gdbarch
, regs
, dsc
);
4771 if (!dsc
->wrote_to_pc
)
4772 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
4775 #include "bfd-in2.h"
4776 #include "libcoff.h"
4779 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
4781 if (arm_pc_is_thumb (memaddr
))
4783 static asymbol
*asym
;
4784 static combined_entry_type ce
;
4785 static struct coff_symbol_struct csym
;
4786 static struct bfd fake_bfd
;
4787 static bfd_target fake_target
;
4789 if (csym
.native
== NULL
)
4791 /* Create a fake symbol vector containing a Thumb symbol.
4792 This is solely so that the code in print_insn_little_arm()
4793 and print_insn_big_arm() in opcodes/arm-dis.c will detect
4794 the presence of a Thumb symbol and switch to decoding
4795 Thumb instructions. */
4797 fake_target
.flavour
= bfd_target_coff_flavour
;
4798 fake_bfd
.xvec
= &fake_target
;
4799 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
4801 csym
.symbol
.the_bfd
= &fake_bfd
;
4802 csym
.symbol
.name
= "fake";
4803 asym
= (asymbol
*) & csym
;
4806 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
4807 info
->symbols
= &asym
;
4810 info
->symbols
= NULL
;
4812 if (info
->endian
== BFD_ENDIAN_BIG
)
4813 return print_insn_big_arm (memaddr
, info
);
4815 return print_insn_little_arm (memaddr
, info
);
4818 /* The following define instruction sequences that will cause ARM
4819 cpu's to take an undefined instruction trap. These are used to
4820 signal a breakpoint to GDB.
4822 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
4823 modes. A different instruction is required for each mode. The ARM
4824 cpu's can also be big or little endian. Thus four different
4825 instructions are needed to support all cases.
4827 Note: ARMv4 defines several new instructions that will take the
4828 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
4829 not in fact add the new instructions. The new undefined
4830 instructions in ARMv4 are all instructions that had no defined
4831 behaviour in earlier chips. There is no guarantee that they will
4832 raise an exception, but may be treated as NOP's. In practice, it
4833 may only safe to rely on instructions matching:
4835 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
4836 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4837 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
4839 Even this may only true if the condition predicate is true. The
4840 following use a condition predicate of ALWAYS so it is always TRUE.
4842 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
4843 and NetBSD all use a software interrupt rather than an undefined
4844 instruction to force a trap. This can be handled by by the
4845 abi-specific code during establishment of the gdbarch vector. */
4847 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
4848 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
4849 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
4850 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
4852 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
4853 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
4854 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
4855 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
4857 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
4858 the program counter value to determine whether a 16-bit or 32-bit
4859 breakpoint should be used. It returns a pointer to a string of
4860 bytes that encode a breakpoint instruction, stores the length of
4861 the string to *lenptr, and adjusts the program counter (if
4862 necessary) to point to the actual memory location where the
4863 breakpoint should be inserted. */
4865 static const unsigned char *
4866 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4868 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4869 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4871 if (arm_pc_is_thumb (*pcptr
))
4873 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
4875 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
4876 check whether we are replacing a 32-bit instruction. */
4877 if (tdep
->thumb2_breakpoint
!= NULL
)
4880 if (target_read_memory (*pcptr
, buf
, 2) == 0)
4882 unsigned short inst1
;
4883 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
4884 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4886 *lenptr
= tdep
->thumb2_breakpoint_size
;
4887 return tdep
->thumb2_breakpoint
;
4892 *lenptr
= tdep
->thumb_breakpoint_size
;
4893 return tdep
->thumb_breakpoint
;
4897 *lenptr
= tdep
->arm_breakpoint_size
;
4898 return tdep
->arm_breakpoint
;
4903 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
4906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4908 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
4910 if (arm_pc_is_thumb (*pcptr
) && *kindptr
== 4)
4911 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
4912 that this is not confused with a 32-bit ARM breakpoint. */
4916 /* Extract from an array REGBUF containing the (raw) register state a
4917 function return value of type TYPE, and copy that, in virtual
4918 format, into VALBUF. */
4921 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
4924 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
4925 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4927 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
4929 switch (gdbarch_tdep (gdbarch
)->fp_model
)
4933 /* The value is in register F0 in internal format. We need to
4934 extract the raw value and then convert it to the desired
4936 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
4938 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
4939 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
4940 valbuf
, gdbarch_byte_order (gdbarch
));
4944 case ARM_FLOAT_SOFT_FPA
:
4945 case ARM_FLOAT_SOFT_VFP
:
4946 /* ARM_FLOAT_VFP can arise if this is a variadic function so
4947 not using the VFP ABI code. */
4949 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
4950 if (TYPE_LENGTH (type
) > 4)
4951 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
4952 valbuf
+ INT_REGISTER_SIZE
);
4957 (__FILE__
, __LINE__
,
4958 _("arm_extract_return_value: Floating point model not supported"));
4962 else if (TYPE_CODE (type
) == TYPE_CODE_INT
4963 || TYPE_CODE (type
) == TYPE_CODE_CHAR
4964 || TYPE_CODE (type
) == TYPE_CODE_BOOL
4965 || TYPE_CODE (type
) == TYPE_CODE_PTR
4966 || TYPE_CODE (type
) == TYPE_CODE_REF
4967 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
4969 /* If the the type is a plain integer, then the access is
4970 straight-forward. Otherwise we have to play around a bit more. */
4971 int len
= TYPE_LENGTH (type
);
4972 int regno
= ARM_A1_REGNUM
;
4977 /* By using store_unsigned_integer we avoid having to do
4978 anything special for small big-endian values. */
4979 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
4980 store_unsigned_integer (valbuf
,
4981 (len
> INT_REGISTER_SIZE
4982 ? INT_REGISTER_SIZE
: len
),
4984 len
-= INT_REGISTER_SIZE
;
4985 valbuf
+= INT_REGISTER_SIZE
;
4990 /* For a structure or union the behaviour is as if the value had
4991 been stored to word-aligned memory and then loaded into
4992 registers with 32-bit load instruction(s). */
4993 int len
= TYPE_LENGTH (type
);
4994 int regno
= ARM_A1_REGNUM
;
4995 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
4999 regcache_cooked_read (regs
, regno
++, tmpbuf
);
5000 memcpy (valbuf
, tmpbuf
,
5001 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5002 len
-= INT_REGISTER_SIZE
;
5003 valbuf
+= INT_REGISTER_SIZE
;
5009 /* Will a function return an aggregate type in memory or in a
5010 register? Return 0 if an aggregate type can be returned in a
5011 register, 1 if it must be returned in memory. */
5014 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
5017 enum type_code code
;
5019 CHECK_TYPEDEF (type
);
5021 /* In the ARM ABI, "integer" like aggregate types are returned in
5022 registers. For an aggregate type to be integer like, its size
5023 must be less than or equal to INT_REGISTER_SIZE and the
5024 offset of each addressable subfield must be zero. Note that bit
5025 fields are not addressable, and all addressable subfields of
5026 unions always start at offset zero.
5028 This function is based on the behaviour of GCC 2.95.1.
5029 See: gcc/arm.c: arm_return_in_memory() for details.
5031 Note: All versions of GCC before GCC 2.95.2 do not set up the
5032 parameters correctly for a function returning the following
5033 structure: struct { float f;}; This should be returned in memory,
5034 not a register. Richard Earnshaw sent me a patch, but I do not
5035 know of any way to detect if a function like the above has been
5036 compiled with the correct calling convention. */
5038 /* All aggregate types that won't fit in a register must be returned
5040 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
5045 /* The AAPCS says all aggregates not larger than a word are returned
5047 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
5050 /* The only aggregate types that can be returned in a register are
5051 structs and unions. Arrays must be returned in memory. */
5052 code
= TYPE_CODE (type
);
5053 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
5058 /* Assume all other aggregate types can be returned in a register.
5059 Run a check for structures, unions and arrays. */
5062 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
5065 /* Need to check if this struct/union is "integer" like. For
5066 this to be true, its size must be less than or equal to
5067 INT_REGISTER_SIZE and the offset of each addressable
5068 subfield must be zero. Note that bit fields are not
5069 addressable, and unions always start at offset zero. If any
5070 of the subfields is a floating point type, the struct/union
5071 cannot be an integer type. */
5073 /* For each field in the object, check:
5074 1) Is it FP? --> yes, nRc = 1;
5075 2) Is it addressable (bitpos != 0) and
5076 not packed (bitsize == 0)?
5080 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
5082 enum type_code field_type_code
;
5083 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
5085 /* Is it a floating point type field? */
5086 if (field_type_code
== TYPE_CODE_FLT
)
5092 /* If bitpos != 0, then we have to care about it. */
5093 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
5095 /* Bitfields are not addressable. If the field bitsize is
5096 zero, then the field is not packed. Hence it cannot be
5097 a bitfield or any other packed type. */
5098 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
5110 /* Write into appropriate registers a function return value of type
5111 TYPE, given in virtual format. */
5114 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
5115 const gdb_byte
*valbuf
)
5117 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5118 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5120 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
5122 char buf
[MAX_REGISTER_SIZE
];
5124 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5128 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
5129 gdbarch_byte_order (gdbarch
));
5130 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
5133 case ARM_FLOAT_SOFT_FPA
:
5134 case ARM_FLOAT_SOFT_VFP
:
5135 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5136 not using the VFP ABI code. */
5138 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
5139 if (TYPE_LENGTH (type
) > 4)
5140 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
5141 valbuf
+ INT_REGISTER_SIZE
);
5146 (__FILE__
, __LINE__
,
5147 _("arm_store_return_value: Floating point model not supported"));
5151 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5152 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5153 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5154 || TYPE_CODE (type
) == TYPE_CODE_PTR
5155 || TYPE_CODE (type
) == TYPE_CODE_REF
5156 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5158 if (TYPE_LENGTH (type
) <= 4)
5160 /* Values of one word or less are zero/sign-extended and
5162 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5163 LONGEST val
= unpack_long (type
, valbuf
);
5165 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
5166 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
5170 /* Integral values greater than one word are stored in consecutive
5171 registers starting with r0. This will always be a multiple of
5172 the regiser size. */
5173 int len
= TYPE_LENGTH (type
);
5174 int regno
= ARM_A1_REGNUM
;
5178 regcache_cooked_write (regs
, regno
++, valbuf
);
5179 len
-= INT_REGISTER_SIZE
;
5180 valbuf
+= INT_REGISTER_SIZE
;
5186 /* For a structure or union the behaviour is as if the value had
5187 been stored to word-aligned memory and then loaded into
5188 registers with 32-bit load instruction(s). */
5189 int len
= TYPE_LENGTH (type
);
5190 int regno
= ARM_A1_REGNUM
;
5191 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5195 memcpy (tmpbuf
, valbuf
,
5196 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5197 regcache_cooked_write (regs
, regno
++, tmpbuf
);
5198 len
-= INT_REGISTER_SIZE
;
5199 valbuf
+= INT_REGISTER_SIZE
;
5205 /* Handle function return values. */
5207 static enum return_value_convention
5208 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
5209 struct type
*valtype
, struct regcache
*regcache
,
5210 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5213 enum arm_vfp_cprc_base_type vfp_base_type
;
5216 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
5217 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
5219 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
5220 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
5222 for (i
= 0; i
< vfp_base_count
; i
++)
5224 if (reg_char
== 'q')
5227 arm_neon_quad_write (gdbarch
, regcache
, i
,
5228 writebuf
+ i
* unit_length
);
5231 arm_neon_quad_read (gdbarch
, regcache
, i
,
5232 readbuf
+ i
* unit_length
);
5239 sprintf (name_buf
, "%c%d", reg_char
, i
);
5240 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5243 regcache_cooked_write (regcache
, regnum
,
5244 writebuf
+ i
* unit_length
);
5246 regcache_cooked_read (regcache
, regnum
,
5247 readbuf
+ i
* unit_length
);
5250 return RETURN_VALUE_REGISTER_CONVENTION
;
5253 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
5254 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
5255 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
5257 if (tdep
->struct_return
== pcc_struct_return
5258 || arm_return_in_memory (gdbarch
, valtype
))
5259 return RETURN_VALUE_STRUCT_CONVENTION
;
5263 arm_store_return_value (valtype
, regcache
, writebuf
);
5266 arm_extract_return_value (valtype
, regcache
, readbuf
);
5268 return RETURN_VALUE_REGISTER_CONVENTION
;
5273 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
5275 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5277 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5279 char buf
[INT_REGISTER_SIZE
];
5281 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
5283 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
5287 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
5291 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
5292 return the target PC. Otherwise return 0. */
5295 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
5299 CORE_ADDR start_addr
;
5301 /* Find the starting address and name of the function containing the PC. */
5302 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5305 /* If PC is in a Thumb call or return stub, return the address of the
5306 target PC, which is in a register. The thunk functions are called
5307 _call_via_xx, where x is the register name. The possible names
5308 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
5309 functions, named __ARM_call_via_r[0-7]. */
5310 if (strncmp (name
, "_call_via_", 10) == 0
5311 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
5313 /* Use the name suffix to determine which register contains the
5315 static char *table
[15] =
5316 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5317 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
5320 int offset
= strlen (name
) - 2;
5322 for (regno
= 0; regno
<= 14; regno
++)
5323 if (strcmp (&name
[offset
], table
[regno
]) == 0)
5324 return get_frame_register_unsigned (frame
, regno
);
5327 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
5328 non-interworking calls to foo. We could decode the stubs
5329 to find the target but it's easier to use the symbol table. */
5330 namelen
= strlen (name
);
5331 if (name
[0] == '_' && name
[1] == '_'
5332 && ((namelen
> 2 + strlen ("_from_thumb")
5333 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
5334 strlen ("_from_thumb")) == 0)
5335 || (namelen
> 2 + strlen ("_from_arm")
5336 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
5337 strlen ("_from_arm")) == 0)))
5340 int target_len
= namelen
- 2;
5341 struct minimal_symbol
*minsym
;
5342 struct objfile
*objfile
;
5343 struct obj_section
*sec
;
5345 if (name
[namelen
- 1] == 'b')
5346 target_len
-= strlen ("_from_thumb");
5348 target_len
-= strlen ("_from_arm");
5350 target_name
= alloca (target_len
+ 1);
5351 memcpy (target_name
, name
+ 2, target_len
);
5352 target_name
[target_len
] = '\0';
5354 sec
= find_pc_section (pc
);
5355 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
5356 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
5358 return SYMBOL_VALUE_ADDRESS (minsym
);
5363 return 0; /* not a stub */
5367 set_arm_command (char *args
, int from_tty
)
5369 printf_unfiltered (_("\
5370 \"set arm\" must be followed by an apporpriate subcommand.\n"));
5371 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
5375 show_arm_command (char *args
, int from_tty
)
5377 cmd_show_list (showarmcmdlist
, from_tty
, "");
5381 arm_update_current_architecture (void)
5383 struct gdbarch_info info
;
5385 /* If the current architecture is not ARM, we have nothing to do. */
5386 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
5389 /* Update the architecture. */
5390 gdbarch_info_init (&info
);
5392 if (!gdbarch_update_p (info
))
5393 internal_error (__FILE__
, __LINE__
, "could not update architecture");
5397 set_fp_model_sfunc (char *args
, int from_tty
,
5398 struct cmd_list_element
*c
)
5400 enum arm_float_model fp_model
;
5402 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
5403 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
5405 arm_fp_model
= fp_model
;
5409 if (fp_model
== ARM_FLOAT_LAST
)
5410 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
5413 arm_update_current_architecture ();
5417 show_fp_model (struct ui_file
*file
, int from_tty
,
5418 struct cmd_list_element
*c
, const char *value
)
5420 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5422 if (arm_fp_model
== ARM_FLOAT_AUTO
5423 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5424 fprintf_filtered (file
, _("\
5425 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
5426 fp_model_strings
[tdep
->fp_model
]);
5428 fprintf_filtered (file
, _("\
5429 The current ARM floating point model is \"%s\".\n"),
5430 fp_model_strings
[arm_fp_model
]);
5434 arm_set_abi (char *args
, int from_tty
,
5435 struct cmd_list_element
*c
)
5437 enum arm_abi_kind arm_abi
;
5439 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
5440 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
5442 arm_abi_global
= arm_abi
;
5446 if (arm_abi
== ARM_ABI_LAST
)
5447 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
5450 arm_update_current_architecture ();
5454 arm_show_abi (struct ui_file
*file
, int from_tty
,
5455 struct cmd_list_element
*c
, const char *value
)
5457 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5459 if (arm_abi_global
== ARM_ABI_AUTO
5460 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5461 fprintf_filtered (file
, _("\
5462 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
5463 arm_abi_strings
[tdep
->arm_abi
]);
5465 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
5470 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
5471 struct cmd_list_element
*c
, const char *value
)
5473 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5475 fprintf_filtered (file
, _("\
5476 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
5477 arm_fallback_mode_string
);
5481 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
5482 struct cmd_list_element
*c
, const char *value
)
5484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5486 fprintf_filtered (file
, _("\
5487 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
5488 arm_force_mode_string
);
5491 /* If the user changes the register disassembly style used for info
5492 register and other commands, we have to also switch the style used
5493 in opcodes for disassembly output. This function is run in the "set
5494 arm disassembly" command, and does that. */
5497 set_disassembly_style_sfunc (char *args
, int from_tty
,
5498 struct cmd_list_element
*c
)
5500 set_disassembly_style ();
5503 /* Return the ARM register name corresponding to register I. */
5505 arm_register_name (struct gdbarch
*gdbarch
, int i
)
5507 const int num_regs
= gdbarch_num_regs (gdbarch
);
5509 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
5510 && i
>= num_regs
&& i
< num_regs
+ 32)
5512 static const char *const vfp_pseudo_names
[] = {
5513 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5514 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5515 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5516 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5519 return vfp_pseudo_names
[i
- num_regs
];
5522 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
5523 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
5525 static const char *const neon_pseudo_names
[] = {
5526 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5527 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
5530 return neon_pseudo_names
[i
- num_regs
- 32];
5533 if (i
>= ARRAY_SIZE (arm_register_names
))
5534 /* These registers are only supported on targets which supply
5535 an XML description. */
5538 return arm_register_names
[i
];
5542 set_disassembly_style (void)
5546 /* Find the style that the user wants. */
5547 for (current
= 0; current
< num_disassembly_options
; current
++)
5548 if (disassembly_style
== valid_disassembly_styles
[current
])
5550 gdb_assert (current
< num_disassembly_options
);
5552 /* Synchronize the disassembler. */
5553 set_arm_regname_option (current
);
5556 /* Test whether the coff symbol specific value corresponds to a Thumb
5560 coff_sym_is_thumb (int val
)
5562 return (val
== C_THUMBEXT
5563 || val
== C_THUMBSTAT
5564 || val
== C_THUMBEXTFUNC
5565 || val
== C_THUMBSTATFUNC
5566 || val
== C_THUMBLABEL
);
5569 /* arm_coff_make_msymbol_special()
5570 arm_elf_make_msymbol_special()
5572 These functions test whether the COFF or ELF symbol corresponds to
5573 an address in thumb code, and set a "special" bit in a minimal
5574 symbol to indicate that it does. */
5577 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
5579 /* Thumb symbols are of type STT_LOPROC, (synonymous with
5581 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
5583 MSYMBOL_SET_SPECIAL (msym
);
5587 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
5589 if (coff_sym_is_thumb (val
))
5590 MSYMBOL_SET_SPECIAL (msym
);
5594 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
5596 struct arm_per_objfile
*data
= arg
;
5599 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
5600 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
5604 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
5607 const char *name
= bfd_asymbol_name (sym
);
5608 struct arm_per_objfile
*data
;
5609 VEC(arm_mapping_symbol_s
) **map_p
;
5610 struct arm_mapping_symbol new_map_sym
;
5612 gdb_assert (name
[0] == '$');
5613 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
5616 data
= objfile_data (objfile
, arm_objfile_data_key
);
5619 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
5620 struct arm_per_objfile
);
5621 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
5622 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
5623 objfile
->obfd
->section_count
,
5624 VEC(arm_mapping_symbol_s
) *);
5626 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
5628 new_map_sym
.value
= sym
->value
;
5629 new_map_sym
.type
= name
[1];
5631 /* Assume that most mapping symbols appear in order of increasing
5632 value. If they were randomly distributed, it would be faster to
5633 always push here and then sort at first use. */
5634 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
5636 struct arm_mapping_symbol
*prev_map_sym
;
5638 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
5639 if (prev_map_sym
->value
>= sym
->value
)
5642 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
5643 arm_compare_mapping_symbols
);
5644 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
5649 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
5653 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
5655 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
5657 /* If necessary, set the T bit. */
5661 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
5662 if (arm_pc_is_thumb (pc
))
5663 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
5665 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
5666 val
& ~(ULONGEST
) CPSR_T
);
5670 /* Read the contents of a NEON quad register, by reading from two
5671 double registers. This is used to implement the quad pseudo
5672 registers, and for argument passing in case the quad registers are
5673 missing; vectors are passed in quad registers when using the VFP
5674 ABI, even if a NEON unit is not present. REGNUM is the index of
5675 the quad register, in [0, 15]. */
5678 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5679 int regnum
, gdb_byte
*buf
)
5682 gdb_byte reg_buf
[8];
5683 int offset
, double_regnum
;
5685 sprintf (name_buf
, "d%d", regnum
<< 1);
5686 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5689 /* d0 is always the least significant half of q0. */
5690 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5695 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5696 memcpy (buf
+ offset
, reg_buf
, 8);
5698 offset
= 8 - offset
;
5699 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
5700 memcpy (buf
+ offset
, reg_buf
, 8);
5704 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5705 int regnum
, gdb_byte
*buf
)
5707 const int num_regs
= gdbarch_num_regs (gdbarch
);
5709 gdb_byte reg_buf
[8];
5710 int offset
, double_regnum
;
5712 gdb_assert (regnum
>= num_regs
);
5715 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
5716 /* Quad-precision register. */
5717 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
5720 /* Single-precision register. */
5721 gdb_assert (regnum
< 32);
5723 /* s0 is always the least significant half of d0. */
5724 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5725 offset
= (regnum
& 1) ? 0 : 4;
5727 offset
= (regnum
& 1) ? 4 : 0;
5729 sprintf (name_buf
, "d%d", regnum
>> 1);
5730 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5733 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5734 memcpy (buf
, reg_buf
+ offset
, 4);
5738 /* Store the contents of BUF to a NEON quad register, by writing to
5739 two double registers. This is used to implement the quad pseudo
5740 registers, and for argument passing in case the quad registers are
5741 missing; vectors are passed in quad registers when using the VFP
5742 ABI, even if a NEON unit is not present. REGNUM is the index
5743 of the quad register, in [0, 15]. */
5746 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5747 int regnum
, const gdb_byte
*buf
)
5750 gdb_byte reg_buf
[8];
5751 int offset
, double_regnum
;
5753 sprintf (name_buf
, "d%d", regnum
<< 1);
5754 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5757 /* d0 is always the least significant half of q0. */
5758 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5763 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
5764 offset
= 8 - offset
;
5765 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
5769 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5770 int regnum
, const gdb_byte
*buf
)
5772 const int num_regs
= gdbarch_num_regs (gdbarch
);
5774 gdb_byte reg_buf
[8];
5775 int offset
, double_regnum
;
5777 gdb_assert (regnum
>= num_regs
);
5780 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
5781 /* Quad-precision register. */
5782 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
5785 /* Single-precision register. */
5786 gdb_assert (regnum
< 32);
5788 /* s0 is always the least significant half of d0. */
5789 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5790 offset
= (regnum
& 1) ? 0 : 4;
5792 offset
= (regnum
& 1) ? 4 : 0;
5794 sprintf (name_buf
, "d%d", regnum
>> 1);
5795 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5798 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
5799 memcpy (reg_buf
+ offset
, buf
, 4);
5800 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
5804 static struct value
*
5805 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
5807 const int *reg_p
= baton
;
5808 return value_of_register (*reg_p
, frame
);
5811 static enum gdb_osabi
5812 arm_elf_osabi_sniffer (bfd
*abfd
)
5814 unsigned int elfosabi
;
5815 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
5817 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
5819 if (elfosabi
== ELFOSABI_ARM
)
5820 /* GNU tools use this value. Check note sections in this case,
5822 bfd_map_over_sections (abfd
,
5823 generic_elf_osabi_sniff_abi_tag_sections
,
5826 /* Anything else will be handled by the generic ELF sniffer. */
5831 /* Initialize the current architecture based on INFO. If possible,
5832 re-use an architecture from ARCHES, which is a list of
5833 architectures already created during this debugging session.
5835 Called e.g. at program startup, when reading a core file, and when
5836 reading a binary file. */
5838 static struct gdbarch
*
5839 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5841 struct gdbarch_tdep
*tdep
;
5842 struct gdbarch
*gdbarch
;
5843 struct gdbarch_list
*best_arch
;
5844 enum arm_abi_kind arm_abi
= arm_abi_global
;
5845 enum arm_float_model fp_model
= arm_fp_model
;
5846 struct tdesc_arch_data
*tdesc_data
= NULL
;
5848 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
5850 int have_fpa_registers
= 1;
5852 /* Check any target description for validity. */
5853 if (tdesc_has_registers (info
.target_desc
))
5855 /* For most registers we require GDB's default names; but also allow
5856 the numeric names for sp / lr / pc, as a convenience. */
5857 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
5858 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
5859 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
5861 const struct tdesc_feature
*feature
;
5864 feature
= tdesc_find_feature (info
.target_desc
,
5865 "org.gnu.gdb.arm.core");
5866 if (feature
== NULL
)
5869 tdesc_data
= tdesc_data_alloc ();
5872 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
5873 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5874 arm_register_names
[i
]);
5875 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5878 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5881 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5884 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5885 ARM_PS_REGNUM
, "cpsr");
5889 tdesc_data_cleanup (tdesc_data
);
5893 feature
= tdesc_find_feature (info
.target_desc
,
5894 "org.gnu.gdb.arm.fpa");
5895 if (feature
!= NULL
)
5898 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
5899 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5900 arm_register_names
[i
]);
5903 tdesc_data_cleanup (tdesc_data
);
5908 have_fpa_registers
= 0;
5910 feature
= tdesc_find_feature (info
.target_desc
,
5911 "org.gnu.gdb.xscale.iwmmxt");
5912 if (feature
!= NULL
)
5914 static const char *const iwmmxt_names
[] = {
5915 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
5916 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
5917 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
5918 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
5922 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
5924 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
5925 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5927 /* Check for the control registers, but do not fail if they
5929 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
5930 tdesc_numbered_register (feature
, tdesc_data
, i
,
5931 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5933 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
5935 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
5936 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
5940 tdesc_data_cleanup (tdesc_data
);
5945 /* If we have a VFP unit, check whether the single precision registers
5946 are present. If not, then we will synthesize them as pseudo
5948 feature
= tdesc_find_feature (info
.target_desc
,
5949 "org.gnu.gdb.arm.vfp");
5950 if (feature
!= NULL
)
5952 static const char *const vfp_double_names
[] = {
5953 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5954 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5955 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5956 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5959 /* Require the double precision registers. There must be either
5962 for (i
= 0; i
< 32; i
++)
5964 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5966 vfp_double_names
[i
]);
5971 if (!valid_p
&& i
!= 16)
5973 tdesc_data_cleanup (tdesc_data
);
5977 if (tdesc_unnumbered_register (feature
, "s0") == 0)
5978 have_vfp_pseudos
= 1;
5980 have_vfp_registers
= 1;
5982 /* If we have VFP, also check for NEON. The architecture allows
5983 NEON without VFP (integer vector operations only), but GDB
5984 does not support that. */
5985 feature
= tdesc_find_feature (info
.target_desc
,
5986 "org.gnu.gdb.arm.neon");
5987 if (feature
!= NULL
)
5989 /* NEON requires 32 double-precision registers. */
5992 tdesc_data_cleanup (tdesc_data
);
5996 /* If there are quad registers defined by the stub, use
5997 their type; otherwise (normally) provide them with
5998 the default type. */
5999 if (tdesc_unnumbered_register (feature
, "q0") == 0)
6000 have_neon_pseudos
= 1;
6007 /* If we have an object to base this architecture on, try to determine
6010 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
6012 int ei_osabi
, e_flags
;
6014 switch (bfd_get_flavour (info
.abfd
))
6016 case bfd_target_aout_flavour
:
6017 /* Assume it's an old APCS-style ABI. */
6018 arm_abi
= ARM_ABI_APCS
;
6021 case bfd_target_coff_flavour
:
6022 /* Assume it's an old APCS-style ABI. */
6024 arm_abi
= ARM_ABI_APCS
;
6027 case bfd_target_elf_flavour
:
6028 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
6029 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6031 if (ei_osabi
== ELFOSABI_ARM
)
6033 /* GNU tools used to use this value, but do not for EABI
6034 objects. There's nowhere to tag an EABI version
6035 anyway, so assume APCS. */
6036 arm_abi
= ARM_ABI_APCS
;
6038 else if (ei_osabi
== ELFOSABI_NONE
)
6040 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
6044 case EF_ARM_EABI_UNKNOWN
:
6045 /* Assume GNU tools. */
6046 arm_abi
= ARM_ABI_APCS
;
6049 case EF_ARM_EABI_VER4
:
6050 case EF_ARM_EABI_VER5
:
6051 arm_abi
= ARM_ABI_AAPCS
;
6052 /* EABI binaries default to VFP float ordering.
6053 They may also contain build attributes that can
6054 be used to identify if the VFP argument-passing
6056 if (fp_model
== ARM_FLOAT_AUTO
)
6059 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
6064 /* "The user intended FP parameter/result
6065 passing to conform to AAPCS, base
6067 fp_model
= ARM_FLOAT_SOFT_VFP
;
6070 /* "The user intended FP parameter/result
6071 passing to conform to AAPCS, VFP
6073 fp_model
= ARM_FLOAT_VFP
;
6076 /* "The user intended FP parameter/result
6077 passing to conform to tool chain-specific
6078 conventions" - we don't know any such
6079 conventions, so leave it as "auto". */
6082 /* Attribute value not mentioned in the
6083 October 2008 ABI, so leave it as
6088 fp_model
= ARM_FLOAT_SOFT_VFP
;
6094 /* Leave it as "auto". */
6095 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
6100 if (fp_model
== ARM_FLOAT_AUTO
)
6102 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6104 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
6107 /* Leave it as "auto". Strictly speaking this case
6108 means FPA, but almost nobody uses that now, and
6109 many toolchains fail to set the appropriate bits
6110 for the floating-point model they use. */
6112 case EF_ARM_SOFT_FLOAT
:
6113 fp_model
= ARM_FLOAT_SOFT_FPA
;
6115 case EF_ARM_VFP_FLOAT
:
6116 fp_model
= ARM_FLOAT_VFP
;
6118 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
6119 fp_model
= ARM_FLOAT_SOFT_VFP
;
6124 if (e_flags
& EF_ARM_BE8
)
6125 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
6130 /* Leave it as "auto". */
6135 /* If there is already a candidate, use it. */
6136 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
6138 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
6140 if (arm_abi
!= ARM_ABI_AUTO
6141 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
6144 if (fp_model
!= ARM_FLOAT_AUTO
6145 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
6148 /* There are various other properties in tdep that we do not
6149 need to check here: those derived from a target description,
6150 since gdbarches with a different target description are
6151 automatically disqualified. */
6153 /* Found a match. */
6157 if (best_arch
!= NULL
)
6159 if (tdesc_data
!= NULL
)
6160 tdesc_data_cleanup (tdesc_data
);
6161 return best_arch
->gdbarch
;
6164 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
6165 gdbarch
= gdbarch_alloc (&info
, tdep
);
6167 /* Record additional information about the architecture we are defining.
6168 These are gdbarch discriminators, like the OSABI. */
6169 tdep
->arm_abi
= arm_abi
;
6170 tdep
->fp_model
= fp_model
;
6171 tdep
->have_fpa_registers
= have_fpa_registers
;
6172 tdep
->have_vfp_registers
= have_vfp_registers
;
6173 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
6174 tdep
->have_neon_pseudos
= have_neon_pseudos
;
6175 tdep
->have_neon
= have_neon
;
6178 switch (info
.byte_order_for_code
)
6180 case BFD_ENDIAN_BIG
:
6181 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
6182 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
6183 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
6184 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
6188 case BFD_ENDIAN_LITTLE
:
6189 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
6190 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
6191 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
6192 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
6197 internal_error (__FILE__
, __LINE__
,
6198 _("arm_gdbarch_init: bad byte order for float format"));
6201 /* On ARM targets char defaults to unsigned. */
6202 set_gdbarch_char_signed (gdbarch
, 0);
6204 /* Note: for displaced stepping, this includes the breakpoint, and one word
6205 of additional scratch space. This setting isn't used for anything beside
6206 displaced stepping at present. */
6207 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
6209 /* This should be low enough for everything. */
6210 tdep
->lowest_pc
= 0x20;
6211 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
6213 /* The default, for both APCS and AAPCS, is to return small
6214 structures in registers. */
6215 tdep
->struct_return
= reg_struct_return
;
6217 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
6218 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
6220 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
6222 /* Frame handling. */
6223 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
6224 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
6225 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
6227 frame_base_set_default (gdbarch
, &arm_normal_base
);
6229 /* Address manipulation. */
6230 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
6231 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
6233 /* Advance PC across function entry code. */
6234 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
6236 /* Skip trampolines. */
6237 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
6239 /* The stack grows downward. */
6240 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6242 /* Breakpoint manipulation. */
6243 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
6244 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
6245 arm_remote_breakpoint_from_pc
);
6247 /* Information about registers, etc. */
6248 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
6249 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
6250 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
6251 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
6252 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6254 /* This "info float" is FPA-specific. Use the generic version if we
6256 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
6257 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
6259 /* Internal <-> external register number maps. */
6260 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
6261 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
6263 set_gdbarch_register_name (gdbarch
, arm_register_name
);
6265 /* Returning results. */
6266 set_gdbarch_return_value (gdbarch
, arm_return_value
);
6269 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
6271 /* Minsymbol frobbing. */
6272 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
6273 set_gdbarch_coff_make_msymbol_special (gdbarch
,
6274 arm_coff_make_msymbol_special
);
6275 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
6277 /* Virtual tables. */
6278 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6280 /* Hook in the ABI-specific overrides, if they have been registered. */
6281 gdbarch_init_osabi (info
, gdbarch
);
6283 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
6285 /* Add some default predicates. */
6286 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
6287 dwarf2_append_unwinders (gdbarch
);
6288 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
6290 /* Now we have tuned the configuration, set a few final things,
6291 based on what the OS ABI has told us. */
6293 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
6294 binaries are always marked. */
6295 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
6296 tdep
->arm_abi
= ARM_ABI_APCS
;
6298 /* We used to default to FPA for generic ARM, but almost nobody
6299 uses that now, and we now provide a way for the user to force
6300 the model. So default to the most useful variant. */
6301 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
6302 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
6304 if (tdep
->jb_pc
>= 0)
6305 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
6307 /* Floating point sizes and format. */
6308 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
6309 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
6311 set_gdbarch_double_format
6312 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6313 set_gdbarch_long_double_format
6314 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6318 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
6319 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
6322 if (have_vfp_pseudos
)
6324 /* NOTE: These are the only pseudo registers used by
6325 the ARM target at the moment. If more are added, a
6326 little more care in numbering will be needed. */
6328 int num_pseudos
= 32;
6329 if (have_neon_pseudos
)
6331 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
6332 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
6333 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
6338 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
6340 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6342 /* Override tdesc_register_type to adjust the types of VFP
6343 registers for NEON. */
6344 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6347 /* Add standard register aliases. We add aliases even for those
6348 nanes which are used by the current architecture - it's simpler,
6349 and does no harm, since nothing ever lists user registers. */
6350 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
6351 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
6352 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
6358 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6360 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6365 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
6366 (unsigned long) tdep
->lowest_pc
);
6369 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
6372 _initialize_arm_tdep (void)
6374 struct ui_file
*stb
;
6376 struct cmd_list_element
*new_set
, *new_show
;
6377 const char *setname
;
6378 const char *setdesc
;
6379 const char *const *regnames
;
6381 static char *helptext
;
6382 char regdesc
[1024], *rdptr
= regdesc
;
6383 size_t rest
= sizeof (regdesc
);
6385 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
6387 arm_objfile_data_key
6388 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
6390 /* Register an ELF OS ABI sniffer for ARM binaries. */
6391 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
6392 bfd_target_elf_flavour
,
6393 arm_elf_osabi_sniffer
);
6395 /* Get the number of possible sets of register names defined in opcodes. */
6396 num_disassembly_options
= get_arm_regname_num_options ();
6398 /* Add root prefix command for all "set arm"/"show arm" commands. */
6399 add_prefix_cmd ("arm", no_class
, set_arm_command
,
6400 _("Various ARM-specific commands."),
6401 &setarmcmdlist
, "set arm ", 0, &setlist
);
6403 add_prefix_cmd ("arm", no_class
, show_arm_command
,
6404 _("Various ARM-specific commands."),
6405 &showarmcmdlist
, "show arm ", 0, &showlist
);
6407 /* Sync the opcode insn printer with our register viewer. */
6408 parse_arm_disassembler_option ("reg-names-std");
6410 /* Initialize the array that will be passed to
6411 add_setshow_enum_cmd(). */
6412 valid_disassembly_styles
6413 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
6414 for (i
= 0; i
< num_disassembly_options
; i
++)
6416 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
6417 valid_disassembly_styles
[i
] = setname
;
6418 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
6421 /* When we find the default names, tell the disassembler to use
6423 if (!strcmp (setname
, "std"))
6425 disassembly_style
= setname
;
6426 set_arm_regname_option (i
);
6429 /* Mark the end of valid options. */
6430 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
6432 /* Create the help text. */
6433 stb
= mem_fileopen ();
6434 fprintf_unfiltered (stb
, "%s%s%s",
6435 _("The valid values are:\n"),
6437 _("The default is \"std\"."));
6438 helptext
= ui_file_xstrdup (stb
, NULL
);
6439 ui_file_delete (stb
);
6441 add_setshow_enum_cmd("disassembler", no_class
,
6442 valid_disassembly_styles
, &disassembly_style
,
6443 _("Set the disassembly style."),
6444 _("Show the disassembly style."),
6446 set_disassembly_style_sfunc
,
6447 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
6448 &setarmcmdlist
, &showarmcmdlist
);
6450 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
6451 _("Set usage of ARM 32-bit mode."),
6452 _("Show usage of ARM 32-bit mode."),
6453 _("When off, a 26-bit PC will be used."),
6455 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
6456 &setarmcmdlist
, &showarmcmdlist
);
6458 /* Add a command to allow the user to force the FPU model. */
6459 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
6460 _("Set the floating point type."),
6461 _("Show the floating point type."),
6462 _("auto - Determine the FP typefrom the OS-ABI.\n\
6463 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
6464 fpa - FPA co-processor (GCC compiled).\n\
6465 softvfp - Software FP with pure-endian doubles.\n\
6466 vfp - VFP co-processor."),
6467 set_fp_model_sfunc
, show_fp_model
,
6468 &setarmcmdlist
, &showarmcmdlist
);
6470 /* Add a command to allow the user to force the ABI. */
6471 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
6474 NULL
, arm_set_abi
, arm_show_abi
,
6475 &setarmcmdlist
, &showarmcmdlist
);
6477 /* Add two commands to allow the user to force the assumed
6479 add_setshow_enum_cmd ("fallback-mode", class_support
,
6480 arm_mode_strings
, &arm_fallback_mode_string
,
6481 _("Set the mode assumed when symbols are unavailable."),
6482 _("Show the mode assumed when symbols are unavailable."),
6483 NULL
, NULL
, arm_show_fallback_mode
,
6484 &setarmcmdlist
, &showarmcmdlist
);
6485 add_setshow_enum_cmd ("force-mode", class_support
,
6486 arm_mode_strings
, &arm_force_mode_string
,
6487 _("Set the mode assumed even when symbols are available."),
6488 _("Show the mode assumed even when symbols are available."),
6489 NULL
, NULL
, arm_show_force_mode
,
6490 &setarmcmdlist
, &showarmcmdlist
);
6492 /* Debugging flag. */
6493 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
6494 _("Set ARM debugging."),
6495 _("Show ARM debugging."),
6496 _("When on, arm-specific debugging is enabled."),
6498 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
6499 &setdebuglist
, &showdebuglist
);