1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
57 /* Macros for setting and testing a bit in a minimal symbol that marks
58 it as Thumb function. The MSB of the minimal symbol's "info" field
59 is used for this purpose.
61 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
62 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64 #define MSYMBOL_SET_SPECIAL(msym) \
65 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71 /* The list of available "set arm ..." and "show arm ..." commands. */
72 static struct cmd_list_element
*setarmcmdlist
= NULL
;
73 static struct cmd_list_element
*showarmcmdlist
= NULL
;
75 /* The type of floating-point to use. Keep this in sync with enum
76 arm_float_model, and the help string in _initialize_arm_tdep. */
77 static const char *fp_model_strings
[] =
87 /* A variable that can be configured by the user. */
88 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
89 static const char *current_fp_model
= "auto";
91 /* The ABI to use. Keep this in sync with arm_abi_kind. */
92 static const char *arm_abi_strings
[] =
100 /* A variable that can be configured by the user. */
101 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
102 static const char *arm_abi_string
= "auto";
104 /* The execution mode to assume. */
105 static const char *arm_mode_strings
[] =
112 static const char *arm_fallback_mode_string
= "auto";
113 static const char *arm_force_mode_string
= "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options
;
118 /* The standard register names, and all the valid aliases for them. */
123 } arm_register_aliases
[] = {
124 /* Basic register numbers. */
141 /* Synonyms (argument and variable registers). */
154 /* Other platform-specific names for r9. */
162 /* Names used by GCC (not listed in the ARM EABI). */
165 /* A special name from the older ATPCS. */
169 static const char *const arm_register_names
[] =
170 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
171 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
172 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
173 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
174 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
175 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
176 "fps", "cpsr" }; /* 24 25 */
178 /* Valid register name styles. */
179 static const char **valid_disassembly_styles
;
181 /* Disassembly style to use. Default to "std" register names. */
182 static const char *disassembly_style
;
184 /* This is used to keep the bfd arch_info in sync with the disassembly
186 static void set_disassembly_style_sfunc(char *, int,
187 struct cmd_list_element
*);
188 static void set_disassembly_style (void);
190 static void convert_from_extended (const struct floatformat
*, const void *,
192 static void convert_to_extended (const struct floatformat
*, void *,
195 struct arm_prologue_cache
197 /* The stack pointer at the time this frame was created; i.e. the
198 caller's stack pointer when this function was called. It is used
199 to identify this frame. */
202 /* The frame base for this frame is just prev_sp - frame size.
203 FRAMESIZE is the distance from the frame pointer to the
204 initial stack pointer. */
208 /* The register used to hold the frame pointer for this frame. */
211 /* Saved register offsets. */
212 struct trad_frame_saved_reg
*saved_regs
;
215 /* Addresses for calling Thumb functions have the bit 0 set.
216 Here are some macros to test, set, or clear bit 0 of addresses. */
217 #define IS_THUMB_ADDR(addr) ((addr) & 1)
218 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
219 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
221 /* Set to true if the 32-bit mode is in use. */
225 /* Determine if FRAME is executing in Thumb mode. */
228 arm_frame_is_thumb (struct frame_info
*frame
)
232 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
233 directly (from a signal frame or dummy frame) or by interpreting
234 the saved LR (from a prologue or DWARF frame). So consult it and
235 trust the unwinders. */
236 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
238 return (cpsr
& CPSR_T
) != 0;
241 /* Determine if the program counter specified in MEMADDR is in a Thumb
242 function. This function should be called for addresses unrelated to
243 any executing frame; otherwise, prefer arm_frame_is_thumb. */
246 arm_pc_is_thumb (CORE_ADDR memaddr
)
248 struct minimal_symbol
*sym
;
250 /* If bit 0 of the address is set, assume this is a Thumb address. */
251 if (IS_THUMB_ADDR (memaddr
))
254 /* If the user wants to override the symbol table, let him. */
255 if (strcmp (arm_force_mode_string
, "arm") == 0)
257 if (strcmp (arm_force_mode_string
, "thumb") == 0)
260 /* Thumb functions have a "special" bit set in minimal symbols. */
261 sym
= lookup_minimal_symbol_by_pc (memaddr
);
263 return (MSYMBOL_IS_SPECIAL (sym
));
265 /* If the user wants to override the fallback mode, let them. */
266 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
268 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
271 /* If we couldn't find any symbol, but we're talking to a running
272 target, then trust the current value of $cpsr. This lets
273 "display/i $pc" always show the correct mode (though if there is
274 a symbol table we will not reach here, so it still may not be
275 displayed in the mode it will be executed). */
276 if (target_has_registers
)
277 return arm_frame_is_thumb (get_current_frame ());
279 /* Otherwise we're out of luck; we assume ARM. */
283 /* Remove useless bits from addresses in a running program. */
285 arm_addr_bits_remove (CORE_ADDR val
)
288 return UNMAKE_THUMB_ADDR (val
);
290 return (val
& 0x03fffffc);
293 /* When reading symbols, we need to zap the low bit of the address,
294 which may be set to 1 for Thumb functions. */
296 arm_smash_text_address (CORE_ADDR val
)
301 /* Analyze a Thumb prologue, looking for a recognizable stack frame
302 and frame pointer. Scan until we encounter a store that could
303 clobber the stack frame unexpectedly, or an unknown instruction. */
306 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
307 CORE_ADDR start
, CORE_ADDR limit
,
308 struct arm_prologue_cache
*cache
)
312 struct pv_area
*stack
;
313 struct cleanup
*back_to
;
316 for (i
= 0; i
< 16; i
++)
317 regs
[i
] = pv_register (i
, 0);
318 stack
= make_pv_area (ARM_SP_REGNUM
);
319 back_to
= make_cleanup_free_pv_area (stack
);
321 while (start
< limit
)
325 insn
= read_memory_unsigned_integer (start
, 2);
327 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
332 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
335 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
336 whether to save LR (R14). */
337 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
339 /* Calculate offsets of saved R0-R7 and LR. */
340 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
341 if (mask
& (1 << regno
))
343 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
345 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
348 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
351 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
352 if (insn
& 0x80) /* Check for SUB. */
353 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
356 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
359 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
360 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
362 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
364 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
365 int src_reg
= (insn
& 0x78) >> 3;
366 regs
[dst_reg
] = regs
[src_reg
];
368 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
370 /* Handle stores to the stack. Normally pushes are used,
371 but with GCC -mtpcs-frame, there may be other stores
372 in the prologue to create the frame. */
373 int regno
= (insn
>> 8) & 0x7;
376 offset
= (insn
& 0xff) << 2;
377 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
379 if (pv_area_store_would_trash (stack
, addr
))
382 pv_area_store (stack
, addr
, 4, regs
[regno
]);
386 /* We don't know what this instruction is. We're finished
387 scanning. NOTE: Recognizing more safe-to-ignore
388 instructions here will improve support for optimized
398 do_cleanups (back_to
);
402 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
404 /* Frame pointer is fp. Frame size is constant. */
405 cache
->framereg
= ARM_FP_REGNUM
;
406 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
408 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
410 /* Frame pointer is r7. Frame size is constant. */
411 cache
->framereg
= THUMB_FP_REGNUM
;
412 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
414 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
416 /* Try the stack pointer... this is a bit desperate. */
417 cache
->framereg
= ARM_SP_REGNUM
;
418 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
422 /* We're just out of luck. We don't know where the frame is. */
423 cache
->framereg
= -1;
424 cache
->framesize
= 0;
427 for (i
= 0; i
< 16; i
++)
428 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
429 cache
->saved_regs
[i
].addr
= offset
;
431 do_cleanups (back_to
);
435 /* Advance the PC across any function entry prologue instructions to
436 reach some "real" code.
438 The APCS (ARM Procedure Call Standard) defines the following
442 [stmfd sp!, {a1,a2,a3,a4}]
443 stmfd sp!, {...,fp,ip,lr,pc}
444 [stfe f7, [sp, #-12]!]
445 [stfe f6, [sp, #-12]!]
446 [stfe f5, [sp, #-12]!]
447 [stfe f4, [sp, #-12]!]
448 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
451 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
455 CORE_ADDR func_addr
, func_end
= 0;
457 struct symtab_and_line sal
;
459 /* If we're in a dummy frame, don't even try to skip the prologue. */
460 if (deprecated_pc_in_call_dummy (pc
))
463 /* See what the symbol table says. */
465 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
469 /* Found a function. */
470 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
471 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
473 /* Don't use this trick for assembly source files. */
474 sal
= find_pc_line (func_addr
, 0);
475 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
480 /* Can't find the prologue end in the symbol table, try it the hard way
481 by disassembling the instructions. */
483 /* Like arm_scan_prologue, stop no later than pc + 64. */
484 if (func_end
== 0 || func_end
> pc
+ 64)
487 /* Check if this is Thumb code. */
488 if (arm_pc_is_thumb (pc
))
489 return thumb_analyze_prologue (gdbarch
, pc
, func_end
, NULL
);
491 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
493 inst
= read_memory_unsigned_integer (skip_pc
, 4);
495 /* "mov ip, sp" is no longer a required part of the prologue. */
496 if (inst
== 0xe1a0c00d) /* mov ip, sp */
499 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
502 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
505 /* Some prologues begin with "str lr, [sp, #-4]!". */
506 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
509 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
512 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
515 /* Any insns after this point may float into the code, if it makes
516 for better instruction scheduling, so we skip them only if we
517 find them, but still consider the function to be frame-ful. */
519 /* We may have either one sfmfd instruction here, or several stfe
520 insns, depending on the version of floating point code we
522 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
525 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
528 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
531 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
534 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
535 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
536 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
539 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
540 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
541 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
544 /* Un-recognized instruction; stop scanning. */
548 return skip_pc
; /* End of prologue */
552 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
553 This function decodes a Thumb function prologue to determine:
554 1) the size of the stack frame
555 2) which registers are saved on it
556 3) the offsets of saved regs
557 4) the offset from the stack pointer to the frame pointer
559 A typical Thumb function prologue would create this stack frame
560 (offsets relative to FP)
561 old SP -> 24 stack parameters
564 R7 -> 0 local variables (16 bytes)
565 SP -> -12 additional stack space (12 bytes)
566 The frame size would thus be 36 bytes, and the frame offset would be
567 12 bytes. The frame register is R7.
569 The comments for thumb_skip_prolog() describe the algorithm we use
570 to detect the end of the prolog. */
574 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
575 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
577 CORE_ADDR prologue_start
;
578 CORE_ADDR prologue_end
;
579 CORE_ADDR current_pc
;
581 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
584 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
586 if (sal
.line
== 0) /* no line info, use current PC */
587 prologue_end
= prev_pc
;
588 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
589 prologue_end
= sal
.end
; /* (probably means no prologue) */
592 /* We're in the boondocks: we have no idea where the start of the
596 prologue_end
= min (prologue_end
, prev_pc
);
598 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
601 /* This function decodes an ARM function prologue to determine:
602 1) the size of the stack frame
603 2) which registers are saved on it
604 3) the offsets of saved regs
605 4) the offset from the stack pointer to the frame pointer
606 This information is stored in the "extra" fields of the frame_info.
608 There are two basic forms for the ARM prologue. The fixed argument
609 function call will look like:
612 stmfd sp!, {fp, ip, lr, pc}
616 Which would create this stack frame (offsets relative to FP):
617 IP -> 4 (caller's stack)
618 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
619 -4 LR (return address in caller)
620 -8 IP (copy of caller's SP)
622 SP -> -28 Local variables
624 The frame size would thus be 32 bytes, and the frame offset would be
625 28 bytes. The stmfd call can also save any of the vN registers it
626 plans to use, which increases the frame size accordingly.
628 Note: The stored PC is 8 off of the STMFD instruction that stored it
629 because the ARM Store instructions always store PC + 8 when you read
632 A variable argument function call will look like:
635 stmfd sp!, {a1, a2, a3, a4}
636 stmfd sp!, {fp, ip, lr, pc}
639 Which would create this stack frame (offsets relative to FP):
640 IP -> 20 (caller's stack)
645 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
646 -4 LR (return address in caller)
647 -8 IP (copy of caller's SP)
649 SP -> -28 Local variables
651 The frame size would thus be 48 bytes, and the frame offset would be
654 There is another potential complication, which is that the optimizer
655 will try to separate the store of fp in the "stmfd" instruction from
656 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
657 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
659 Also, note, the original version of the ARM toolchain claimed that there
662 instruction at the end of the prologue. I have never seen GCC produce
663 this, and the ARM docs don't mention it. We still test for it below in
669 arm_scan_prologue (struct frame_info
*this_frame
,
670 struct arm_prologue_cache
*cache
)
672 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
674 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
675 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
676 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
677 pv_t regs
[ARM_FPS_REGNUM
];
678 struct pv_area
*stack
;
679 struct cleanup
*back_to
;
682 /* Assume there is no frame until proven otherwise. */
683 cache
->framereg
= ARM_SP_REGNUM
;
684 cache
->framesize
= 0;
686 /* Check for Thumb prologue. */
687 if (arm_frame_is_thumb (this_frame
))
689 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
693 /* Find the function prologue. If we can't find the function in
694 the symbol table, peek in the stack frame to find the PC. */
695 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
698 /* One way to find the end of the prologue (which works well
699 for unoptimized code) is to do the following:
701 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
704 prologue_end = prev_pc;
705 else if (sal.end < prologue_end)
706 prologue_end = sal.end;
708 This mechanism is very accurate so long as the optimizer
709 doesn't move any instructions from the function body into the
710 prologue. If this happens, sal.end will be the last
711 instruction in the first hunk of prologue code just before
712 the first instruction that the scheduler has moved from
713 the body to the prologue.
715 In order to make sure that we scan all of the prologue
716 instructions, we use a slightly less accurate mechanism which
717 may scan more than necessary. To help compensate for this
718 lack of accuracy, the prologue scanning loop below contains
719 several clauses which'll cause the loop to terminate early if
720 an implausible prologue instruction is encountered.
726 is a suitable endpoint since it accounts for the largest
727 possible prologue plus up to five instructions inserted by
730 if (prologue_end
> prologue_start
+ 64)
732 prologue_end
= prologue_start
+ 64; /* See above. */
737 /* We have no symbol information. Our only option is to assume this
738 function has a standard stack frame and the normal frame register.
739 Then, we can find the value of our frame pointer on entrance to
740 the callee (or at the present moment if this is the innermost frame).
741 The value stored there should be the address of the stmfd + 8. */
743 LONGEST return_value
;
745 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
746 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
750 prologue_start
= gdbarch_addr_bits_remove
751 (gdbarch
, return_value
) - 8;
752 prologue_end
= prologue_start
+ 64; /* See above. */
756 if (prev_pc
< prologue_end
)
757 prologue_end
= prev_pc
;
759 /* Now search the prologue looking for instructions that set up the
760 frame pointer, adjust the stack pointer, and save registers.
762 Be careful, however, and if it doesn't look like a prologue,
763 don't try to scan it. If, for instance, a frameless function
764 begins with stmfd sp!, then we will tell ourselves there is
765 a frame, which will confuse stack traceback, as well as "finish"
766 and other operations that rely on a knowledge of the stack
769 In the APCS, the prologue should start with "mov ip, sp" so
770 if we don't see this as the first insn, we will stop.
772 [Note: This doesn't seem to be true any longer, so it's now an
773 optional part of the prologue. - Kevin Buettner, 2001-11-20]
775 [Note further: The "mov ip,sp" only seems to be missing in
776 frameless functions at optimization level "-O2" or above,
777 in which case it is often (but not always) replaced by
778 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
780 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
781 regs
[regno
] = pv_register (regno
, 0);
782 stack
= make_pv_area (ARM_SP_REGNUM
);
783 back_to
= make_cleanup_free_pv_area (stack
);
785 for (current_pc
= prologue_start
;
786 current_pc
< prologue_end
;
789 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
791 if (insn
== 0xe1a0c00d) /* mov ip, sp */
793 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
796 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
798 unsigned imm
= insn
& 0xff; /* immediate value */
799 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
800 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
801 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
804 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
806 unsigned imm
= insn
& 0xff; /* immediate value */
807 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
808 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
809 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
812 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
814 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
816 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
817 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
820 else if ((insn
& 0xffff0000) == 0xe92d0000)
821 /* stmfd sp!, {..., fp, ip, lr, pc}
823 stmfd sp!, {a1, a2, a3, a4} */
825 int mask
= insn
& 0xffff;
827 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
830 /* Calculate offsets of saved registers. */
831 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
832 if (mask
& (1 << regno
))
834 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
835 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
838 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
839 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
840 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
842 /* No need to add this to saved_regs -- it's just an arg reg. */
845 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
846 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
847 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
849 /* No need to add this to saved_regs -- it's just an arg reg. */
852 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
854 unsigned imm
= insn
& 0xff; /* immediate value */
855 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
856 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
857 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
859 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
861 unsigned imm
= insn
& 0xff; /* immediate value */
862 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
863 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
864 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
866 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
867 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
869 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
872 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
873 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
874 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
876 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
877 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
880 unsigned int fp_start_reg
, fp_bound_reg
;
882 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
885 if ((insn
& 0x800) == 0x800) /* N0 is set */
887 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
894 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
900 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
901 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
902 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
904 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
905 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
906 regs
[fp_start_reg
++]);
909 else if ((insn
& 0xf0000000) != 0xe0000000)
910 break; /* Condition not true, exit early */
911 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
912 break; /* Don't scan past a block load */
914 /* The optimizer might shove anything into the prologue,
915 so we just skip what we don't recognize. */
919 /* The frame size is just the distance from the frame register
920 to the original stack pointer. */
921 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
923 /* Frame pointer is fp. */
924 cache
->framereg
= ARM_FP_REGNUM
;
925 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
927 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
929 /* Try the stack pointer... this is a bit desperate. */
930 cache
->framereg
= ARM_SP_REGNUM
;
931 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
935 /* We're just out of luck. We don't know where the frame is. */
936 cache
->framereg
= -1;
937 cache
->framesize
= 0;
940 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
941 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
942 cache
->saved_regs
[regno
].addr
= offset
;
944 do_cleanups (back_to
);
947 static struct arm_prologue_cache
*
948 arm_make_prologue_cache (struct frame_info
*this_frame
)
951 struct arm_prologue_cache
*cache
;
952 CORE_ADDR unwound_fp
;
954 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
955 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
957 arm_scan_prologue (this_frame
, cache
);
959 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
963 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
965 /* Calculate actual addresses of saved registers using offsets
966 determined by arm_scan_prologue. */
967 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
968 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
969 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
974 /* Our frame ID for a normal frame is the current function's starting PC
975 and the caller's SP when we were called. */
978 arm_prologue_this_id (struct frame_info
*this_frame
,
980 struct frame_id
*this_id
)
982 struct arm_prologue_cache
*cache
;
986 if (*this_cache
== NULL
)
987 *this_cache
= arm_make_prologue_cache (this_frame
);
990 /* This is meant to halt the backtrace at "_start". */
991 pc
= get_frame_pc (this_frame
);
992 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
995 /* If we've hit a wall, stop. */
996 if (cache
->prev_sp
== 0)
999 func
= get_frame_func (this_frame
);
1000 id
= frame_id_build (cache
->prev_sp
, func
);
1004 static struct value
*
1005 arm_prologue_prev_register (struct frame_info
*this_frame
,
1009 struct arm_prologue_cache
*cache
;
1011 if (*this_cache
== NULL
)
1012 *this_cache
= arm_make_prologue_cache (this_frame
);
1013 cache
= *this_cache
;
1015 /* If we are asked to unwind the PC, then we need to return the LR
1016 instead. The prologue may save PC, but it will point into this
1017 frame's prologue, not the next frame's resume location. Also
1018 strip the saved T bit. A valid LR may have the low bit set, but
1019 a valid PC never does. */
1020 if (prev_regnum
== ARM_PC_REGNUM
)
1024 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1025 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1026 arm_addr_bits_remove (lr
));
1029 /* SP is generally not saved to the stack, but this frame is
1030 identified by the next frame's stack pointer at the time of the call.
1031 The value was already reconstructed into PREV_SP. */
1032 if (prev_regnum
== ARM_SP_REGNUM
)
1033 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1035 /* The CPSR may have been changed by the call instruction and by the
1036 called function. The only bit we can reconstruct is the T bit,
1037 by checking the low bit of LR as of the call. This is a reliable
1038 indicator of Thumb-ness except for some ARM v4T pre-interworking
1039 Thumb code, which could get away with a clear low bit as long as
1040 the called function did not use bx. Guess that all other
1041 bits are unchanged; the condition flags are presumably lost,
1042 but the processor status is likely valid. */
1043 if (prev_regnum
== ARM_PS_REGNUM
)
1047 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1048 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1049 if (IS_THUMB_ADDR (lr
))
1053 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1056 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1060 struct frame_unwind arm_prologue_unwind
= {
1062 arm_prologue_this_id
,
1063 arm_prologue_prev_register
,
1065 default_frame_sniffer
1068 static struct arm_prologue_cache
*
1069 arm_make_stub_cache (struct frame_info
*this_frame
)
1072 struct arm_prologue_cache
*cache
;
1073 CORE_ADDR unwound_fp
;
1075 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1076 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1078 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1083 /* Our frame ID for a stub frame is the current SP and LR. */
1086 arm_stub_this_id (struct frame_info
*this_frame
,
1088 struct frame_id
*this_id
)
1090 struct arm_prologue_cache
*cache
;
1092 if (*this_cache
== NULL
)
1093 *this_cache
= arm_make_stub_cache (this_frame
);
1094 cache
= *this_cache
;
1096 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1100 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1101 struct frame_info
*this_frame
,
1102 void **this_prologue_cache
)
1104 CORE_ADDR addr_in_block
;
1107 addr_in_block
= get_frame_address_in_block (this_frame
);
1108 if (in_plt_section (addr_in_block
, NULL
)
1109 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1115 struct frame_unwind arm_stub_unwind
= {
1118 arm_prologue_prev_register
,
1120 arm_stub_unwind_sniffer
1124 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1126 struct arm_prologue_cache
*cache
;
1128 if (*this_cache
== NULL
)
1129 *this_cache
= arm_make_prologue_cache (this_frame
);
1130 cache
= *this_cache
;
1132 return cache
->prev_sp
- cache
->framesize
;
1135 struct frame_base arm_normal_base
= {
1136 &arm_prologue_unwind
,
1137 arm_normal_frame_base
,
1138 arm_normal_frame_base
,
1139 arm_normal_frame_base
1142 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1143 dummy frame. The frame ID's base needs to match the TOS value
1144 saved by save_dummy_frame_tos() and returned from
1145 arm_push_dummy_call, and the PC needs to match the dummy frame's
1148 static struct frame_id
1149 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1151 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1152 get_frame_pc (this_frame
));
1155 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1156 be used to construct the previous frame's ID, after looking up the
1157 containing function). */
1160 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1163 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1164 return arm_addr_bits_remove (pc
);
1168 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1170 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1173 static struct value
*
1174 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1182 /* The PC is normally copied from the return column, which
1183 describes saves of LR. However, that version may have an
1184 extra bit set to indicate Thumb state. The bit is not
1186 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1187 return frame_unwind_got_constant (this_frame
, regnum
,
1188 arm_addr_bits_remove (lr
));
1191 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1192 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1193 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1194 if (IS_THUMB_ADDR (lr
))
1198 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1201 internal_error (__FILE__
, __LINE__
,
1202 _("Unexpected register %d"), regnum
);
1207 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1208 struct dwarf2_frame_state_reg
*reg
,
1209 struct frame_info
*this_frame
)
1215 reg
->how
= DWARF2_FRAME_REG_FN
;
1216 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1219 reg
->how
= DWARF2_FRAME_REG_CFA
;
1224 /* When arguments must be pushed onto the stack, they go on in reverse
1225 order. The code below implements a FILO (stack) to do this. */
1230 struct stack_item
*prev
;
1234 static struct stack_item
*
1235 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1237 struct stack_item
*si
;
1238 si
= xmalloc (sizeof (struct stack_item
));
1239 si
->data
= xmalloc (len
);
1242 memcpy (si
->data
, contents
, len
);
1246 static struct stack_item
*
1247 pop_stack_item (struct stack_item
*si
)
1249 struct stack_item
*dead
= si
;
1257 /* Return the alignment (in bytes) of the given type. */
1260 arm_type_align (struct type
*t
)
1266 t
= check_typedef (t
);
1267 switch (TYPE_CODE (t
))
1270 /* Should never happen. */
1271 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1275 case TYPE_CODE_ENUM
:
1279 case TYPE_CODE_RANGE
:
1280 case TYPE_CODE_BITSTRING
:
1282 case TYPE_CODE_CHAR
:
1283 case TYPE_CODE_BOOL
:
1284 return TYPE_LENGTH (t
);
1286 case TYPE_CODE_ARRAY
:
1287 case TYPE_CODE_COMPLEX
:
1288 /* TODO: What about vector types? */
1289 return arm_type_align (TYPE_TARGET_TYPE (t
));
1291 case TYPE_CODE_STRUCT
:
1292 case TYPE_CODE_UNION
:
1294 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1296 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1304 /* We currently only support passing parameters in integer registers. This
1305 conforms with GCC's default model. Several other variants exist and
1306 we should probably support some of them based on the selected ABI. */
1309 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1310 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1311 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1312 CORE_ADDR struct_addr
)
1317 struct stack_item
*si
= NULL
;
1319 /* Set the return address. For the ARM, the return breakpoint is
1320 always at BP_ADDR. */
1321 /* XXX Fix for Thumb. */
1322 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1324 /* Walk through the list of args and determine how large a temporary
1325 stack is required. Need to take care here as structs may be
1326 passed on the stack, and we have to to push them. */
1329 argreg
= ARM_A1_REGNUM
;
1332 /* The struct_return pointer occupies the first parameter
1333 passing register. */
1337 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1338 gdbarch_register_name (gdbarch
, argreg
),
1339 paddr (struct_addr
));
1340 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1344 for (argnum
= 0; argnum
< nargs
; argnum
++)
1347 struct type
*arg_type
;
1348 struct type
*target_type
;
1349 enum type_code typecode
;
1353 arg_type
= check_typedef (value_type (args
[argnum
]));
1354 len
= TYPE_LENGTH (arg_type
);
1355 target_type
= TYPE_TARGET_TYPE (arg_type
);
1356 typecode
= TYPE_CODE (arg_type
);
1357 val
= value_contents_writeable (args
[argnum
]);
1359 align
= arm_type_align (arg_type
);
1360 /* Round alignment up to a whole number of words. */
1361 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1362 /* Different ABIs have different maximum alignments. */
1363 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1365 /* The APCS ABI only requires word alignment. */
1366 align
= INT_REGISTER_SIZE
;
1370 /* The AAPCS requires at most doubleword alignment. */
1371 if (align
> INT_REGISTER_SIZE
* 2)
1372 align
= INT_REGISTER_SIZE
* 2;
1375 /* Push stack padding for dowubleword alignment. */
1376 if (nstack
& (align
- 1))
1378 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1379 nstack
+= INT_REGISTER_SIZE
;
1382 /* Doubleword aligned quantities must go in even register pairs. */
1383 if (argreg
<= ARM_LAST_ARG_REGNUM
1384 && align
> INT_REGISTER_SIZE
1388 /* If the argument is a pointer to a function, and it is a
1389 Thumb function, create a LOCAL copy of the value and set
1390 the THUMB bit in it. */
1391 if (TYPE_CODE_PTR
== typecode
1392 && target_type
!= NULL
1393 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1395 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1396 if (arm_pc_is_thumb (regval
))
1399 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1403 /* Copy the argument to general registers or the stack in
1404 register-sized pieces. Large arguments are split between
1405 registers and stack. */
1408 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1410 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1412 /* The argument is being passed in a general purpose
1414 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1415 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1416 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1418 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1420 gdbarch_register_name
1422 phex (regval
, INT_REGISTER_SIZE
));
1423 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1428 /* Push the arguments onto the stack. */
1430 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1432 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1433 nstack
+= INT_REGISTER_SIZE
;
1440 /* If we have an odd number of words to push, then decrement the stack
1441 by one word now, so first stack argument will be dword aligned. */
1448 write_memory (sp
, si
->data
, si
->len
);
1449 si
= pop_stack_item (si
);
1452 /* Finally, update teh SP register. */
1453 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1459 /* Always align the frame to an 8-byte boundary. This is required on
1460 some platforms and harmless on the rest. */
1463 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1465 /* Align the stack to eight bytes. */
1466 return sp
& ~ (CORE_ADDR
) 7;
1470 print_fpu_flags (int flags
)
1472 if (flags
& (1 << 0))
1473 fputs ("IVO ", stdout
);
1474 if (flags
& (1 << 1))
1475 fputs ("DVZ ", stdout
);
1476 if (flags
& (1 << 2))
1477 fputs ("OFL ", stdout
);
1478 if (flags
& (1 << 3))
1479 fputs ("UFL ", stdout
);
1480 if (flags
& (1 << 4))
1481 fputs ("INX ", stdout
);
1485 /* Print interesting information about the floating point processor
1486 (if present) or emulator. */
1488 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1489 struct frame_info
*frame
, const char *args
)
1491 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1494 type
= (status
>> 24) & 127;
1495 if (status
& (1 << 31))
1496 printf (_("Hardware FPU type %d\n"), type
);
1498 printf (_("Software FPU type %d\n"), type
);
1499 /* i18n: [floating point unit] mask */
1500 fputs (_("mask: "), stdout
);
1501 print_fpu_flags (status
>> 16);
1502 /* i18n: [floating point unit] flags */
1503 fputs (_("flags: "), stdout
);
1504 print_fpu_flags (status
);
1507 /* Return the GDB type object for the "standard" data type of data in
1510 static struct type
*
1511 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1513 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1514 return builtin_type_arm_ext
;
1515 else if (regnum
== ARM_SP_REGNUM
)
1516 return builtin_type_void_data_ptr
;
1517 else if (regnum
== ARM_PC_REGNUM
)
1518 return builtin_type_void_func_ptr
;
1519 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1520 /* These registers are only supported on targets which supply
1521 an XML description. */
1522 return builtin_type_int0
;
1524 return builtin_type_uint32
;
1527 /* Map a DWARF register REGNUM onto the appropriate GDB register
1531 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1533 /* Core integer regs. */
1534 if (reg
>= 0 && reg
<= 15)
1537 /* Legacy FPA encoding. These were once used in a way which
1538 overlapped with VFP register numbering, so their use is
1539 discouraged, but GDB doesn't support the ARM toolchain
1540 which used them for VFP. */
1541 if (reg
>= 16 && reg
<= 23)
1542 return ARM_F0_REGNUM
+ reg
- 16;
1544 /* New assignments for the FPA registers. */
1545 if (reg
>= 96 && reg
<= 103)
1546 return ARM_F0_REGNUM
+ reg
- 96;
1548 /* WMMX register assignments. */
1549 if (reg
>= 104 && reg
<= 111)
1550 return ARM_WCGR0_REGNUM
+ reg
- 104;
1552 if (reg
>= 112 && reg
<= 127)
1553 return ARM_WR0_REGNUM
+ reg
- 112;
1555 if (reg
>= 192 && reg
<= 199)
1556 return ARM_WC0_REGNUM
+ reg
- 192;
1561 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1563 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1566 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1568 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1569 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1571 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1572 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1574 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1575 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1577 if (reg
< NUM_GREGS
)
1578 return SIM_ARM_R0_REGNUM
+ reg
;
1581 if (reg
< NUM_FREGS
)
1582 return SIM_ARM_FP0_REGNUM
+ reg
;
1585 if (reg
< NUM_SREGS
)
1586 return SIM_ARM_FPS_REGNUM
+ reg
;
1589 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1592 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1593 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1594 It is thought that this is is the floating-point register format on
1595 little-endian systems. */
1598 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1599 void *dbl
, int endianess
)
1603 if (endianess
== BFD_ENDIAN_BIG
)
1604 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1606 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1608 floatformat_from_doublest (fmt
, &d
, dbl
);
1612 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
1617 floatformat_to_doublest (fmt
, ptr
, &d
);
1618 if (endianess
== BFD_ENDIAN_BIG
)
1619 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1621 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1626 condition_true (unsigned long cond
, unsigned long status_reg
)
1628 if (cond
== INST_AL
|| cond
== INST_NV
)
1634 return ((status_reg
& FLAG_Z
) != 0);
1636 return ((status_reg
& FLAG_Z
) == 0);
1638 return ((status_reg
& FLAG_C
) != 0);
1640 return ((status_reg
& FLAG_C
) == 0);
1642 return ((status_reg
& FLAG_N
) != 0);
1644 return ((status_reg
& FLAG_N
) == 0);
1646 return ((status_reg
& FLAG_V
) != 0);
1648 return ((status_reg
& FLAG_V
) == 0);
1650 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1652 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1654 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1656 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1658 return (((status_reg
& FLAG_Z
) == 0) &&
1659 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1661 return (((status_reg
& FLAG_Z
) != 0) ||
1662 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1667 /* Support routines for single stepping. Calculate the next PC value. */
1668 #define submask(x) ((1L << ((x) + 1)) - 1)
1669 #define bit(obj,st) (((obj) >> (st)) & 1)
1670 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1671 #define sbits(obj,st,fn) \
1672 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1673 #define BranchDest(addr,instr) \
1674 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1677 static unsigned long
1678 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1679 unsigned long pc_val
, unsigned long status_reg
)
1681 unsigned long res
, shift
;
1682 int rm
= bits (inst
, 0, 3);
1683 unsigned long shifttype
= bits (inst
, 5, 6);
1687 int rs
= bits (inst
, 8, 11);
1688 shift
= (rs
== 15 ? pc_val
+ 8
1689 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1692 shift
= bits (inst
, 7, 11);
1695 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1696 + (bit (inst
, 4) ? 12 : 8))
1697 : get_frame_register_unsigned (frame
, rm
));
1702 res
= shift
>= 32 ? 0 : res
<< shift
;
1706 res
= shift
>= 32 ? 0 : res
>> shift
;
1712 res
= ((res
& 0x80000000L
)
1713 ? ~((~res
) >> shift
) : res
>> shift
);
1716 case 3: /* ROR/RRX */
1719 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1721 res
= (res
>> shift
) | (res
<< (32 - shift
));
1725 return res
& 0xffffffff;
1728 /* Return number of 1-bits in VAL. */
1731 bitcount (unsigned long val
)
1734 for (nbits
= 0; val
!= 0; nbits
++)
1735 val
&= val
- 1; /* delete rightmost 1-bit in val */
1740 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1742 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1743 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1744 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1745 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1746 unsigned long offset
;
1748 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1752 /* Fetch the saved PC from the stack. It's stored above
1753 all of the other registers. */
1754 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1755 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1756 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1757 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1759 error (_("Infinite loop detected"));
1761 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1763 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1764 unsigned long cond
= bits (inst1
, 8, 11);
1765 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1766 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1768 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1770 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1772 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1774 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1775 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1776 nextpc
= pc_val
+ offset
;
1777 /* For BLX make sure to clear the low bits. */
1778 if (bits (inst2
, 11, 12) == 1)
1779 nextpc
= nextpc
& 0xfffffffc;
1781 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1783 if (bits (inst1
, 3, 6) == 0x0f)
1786 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1788 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1790 error (_("Infinite loop detected"));
1797 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1799 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1800 unsigned long pc_val
;
1801 unsigned long this_instr
;
1802 unsigned long status
;
1805 if (arm_frame_is_thumb (frame
))
1806 return thumb_get_next_pc (frame
, pc
);
1808 pc_val
= (unsigned long) pc
;
1809 this_instr
= read_memory_unsigned_integer (pc
, 4);
1810 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1811 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1813 if (bits (this_instr
, 28, 31) == INST_NV
)
1814 switch (bits (this_instr
, 24, 27))
1819 /* Branch with Link and change to Thumb. */
1820 nextpc
= BranchDest (pc
, this_instr
);
1821 nextpc
|= bit (this_instr
, 24) << 1;
1823 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1825 error (_("Infinite loop detected"));
1831 /* Coprocessor register transfer. */
1832 if (bits (this_instr
, 12, 15) == 15)
1833 error (_("Invalid update to pc in instruction"));
1836 else if (condition_true (bits (this_instr
, 28, 31), status
))
1838 switch (bits (this_instr
, 24, 27))
1841 case 0x1: /* data processing */
1845 unsigned long operand1
, operand2
, result
= 0;
1849 if (bits (this_instr
, 12, 15) != 15)
1852 if (bits (this_instr
, 22, 25) == 0
1853 && bits (this_instr
, 4, 7) == 9) /* multiply */
1854 error (_("Invalid update to pc in instruction"));
1856 /* BX <reg>, BLX <reg> */
1857 if (bits (this_instr
, 4, 27) == 0x12fff1
1858 || bits (this_instr
, 4, 27) == 0x12fff3)
1860 rn
= bits (this_instr
, 0, 3);
1861 result
= (rn
== 15) ? pc_val
+ 8
1862 : get_frame_register_unsigned (frame
, rn
);
1863 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1867 error (_("Infinite loop detected"));
1872 /* Multiply into PC */
1873 c
= (status
& FLAG_C
) ? 1 : 0;
1874 rn
= bits (this_instr
, 16, 19);
1875 operand1
= (rn
== 15) ? pc_val
+ 8
1876 : get_frame_register_unsigned (frame
, rn
);
1878 if (bit (this_instr
, 25))
1880 unsigned long immval
= bits (this_instr
, 0, 7);
1881 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1882 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1885 else /* operand 2 is a shifted register */
1886 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1888 switch (bits (this_instr
, 21, 24))
1891 result
= operand1
& operand2
;
1895 result
= operand1
^ operand2
;
1899 result
= operand1
- operand2
;
1903 result
= operand2
- operand1
;
1907 result
= operand1
+ operand2
;
1911 result
= operand1
+ operand2
+ c
;
1915 result
= operand1
- operand2
+ c
;
1919 result
= operand2
- operand1
+ c
;
1925 case 0xb: /* tst, teq, cmp, cmn */
1926 result
= (unsigned long) nextpc
;
1930 result
= operand1
| operand2
;
1934 /* Always step into a function. */
1939 result
= operand1
& ~operand2
;
1946 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1950 error (_("Infinite loop detected"));
1955 case 0x5: /* data transfer */
1958 if (bit (this_instr
, 20))
1961 if (bits (this_instr
, 12, 15) == 15)
1967 if (bit (this_instr
, 22))
1968 error (_("Invalid update to pc in instruction"));
1970 /* byte write to PC */
1971 rn
= bits (this_instr
, 16, 19);
1972 base
= (rn
== 15) ? pc_val
+ 8
1973 : get_frame_register_unsigned (frame
, rn
);
1974 if (bit (this_instr
, 24))
1977 int c
= (status
& FLAG_C
) ? 1 : 0;
1978 unsigned long offset
=
1979 (bit (this_instr
, 25)
1980 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
1981 : bits (this_instr
, 0, 11));
1983 if (bit (this_instr
, 23))
1988 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1991 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1994 error (_("Infinite loop detected"));
2000 case 0x9: /* block transfer */
2001 if (bit (this_instr
, 20))
2004 if (bit (this_instr
, 15))
2009 if (bit (this_instr
, 23))
2012 unsigned long reglist
= bits (this_instr
, 0, 14);
2013 offset
= bitcount (reglist
) * 4;
2014 if (bit (this_instr
, 24)) /* pre */
2017 else if (bit (this_instr
, 24))
2021 unsigned long rn_val
=
2022 get_frame_register_unsigned (frame
,
2023 bits (this_instr
, 16, 19));
2025 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2029 nextpc
= gdbarch_addr_bits_remove
2032 error (_("Infinite loop detected"));
2037 case 0xb: /* branch & link */
2038 case 0xa: /* branch */
2040 nextpc
= BranchDest (pc
, this_instr
);
2042 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2044 error (_("Infinite loop detected"));
2050 case 0xe: /* coproc ops */
2055 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2063 /* single_step() is called just before we want to resume the inferior,
2064 if we want to single-step it but there is no hardware or kernel
2065 single-step support. We find the target of the coming instruction
2066 and breakpoint it. */
2069 arm_software_single_step (struct frame_info
*frame
)
2071 /* NOTE: This may insert the wrong breakpoint instruction when
2072 single-stepping over a mode-changing instruction, if the
2073 CPSR heuristics are used. */
2075 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2076 insert_single_step_breakpoint (next_pc
);
2081 #include "bfd-in2.h"
2082 #include "libcoff.h"
2085 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2087 if (arm_pc_is_thumb (memaddr
))
2089 static asymbol
*asym
;
2090 static combined_entry_type ce
;
2091 static struct coff_symbol_struct csym
;
2092 static struct bfd fake_bfd
;
2093 static bfd_target fake_target
;
2095 if (csym
.native
== NULL
)
2097 /* Create a fake symbol vector containing a Thumb symbol.
2098 This is solely so that the code in print_insn_little_arm()
2099 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2100 the presence of a Thumb symbol and switch to decoding
2101 Thumb instructions. */
2103 fake_target
.flavour
= bfd_target_coff_flavour
;
2104 fake_bfd
.xvec
= &fake_target
;
2105 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2107 csym
.symbol
.the_bfd
= &fake_bfd
;
2108 csym
.symbol
.name
= "fake";
2109 asym
= (asymbol
*) & csym
;
2112 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2113 info
->symbols
= &asym
;
2116 info
->symbols
= NULL
;
2118 if (info
->endian
== BFD_ENDIAN_BIG
)
2119 return print_insn_big_arm (memaddr
, info
);
2121 return print_insn_little_arm (memaddr
, info
);
2124 /* The following define instruction sequences that will cause ARM
2125 cpu's to take an undefined instruction trap. These are used to
2126 signal a breakpoint to GDB.
2128 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2129 modes. A different instruction is required for each mode. The ARM
2130 cpu's can also be big or little endian. Thus four different
2131 instructions are needed to support all cases.
2133 Note: ARMv4 defines several new instructions that will take the
2134 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2135 not in fact add the new instructions. The new undefined
2136 instructions in ARMv4 are all instructions that had no defined
2137 behaviour in earlier chips. There is no guarantee that they will
2138 raise an exception, but may be treated as NOP's. In practice, it
2139 may only safe to rely on instructions matching:
2141 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2142 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2143 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2145 Even this may only true if the condition predicate is true. The
2146 following use a condition predicate of ALWAYS so it is always TRUE.
2148 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2149 and NetBSD all use a software interrupt rather than an undefined
2150 instruction to force a trap. This can be handled by by the
2151 abi-specific code during establishment of the gdbarch vector. */
2153 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2154 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2155 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2156 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2158 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2159 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2160 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2161 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2163 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2164 the program counter value to determine whether a 16-bit or 32-bit
2165 breakpoint should be used. It returns a pointer to a string of
2166 bytes that encode a breakpoint instruction, stores the length of
2167 the string to *lenptr, and adjusts the program counter (if
2168 necessary) to point to the actual memory location where the
2169 breakpoint should be inserted. */
2171 static const unsigned char *
2172 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2176 if (arm_pc_is_thumb (*pcptr
))
2178 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2179 *lenptr
= tdep
->thumb_breakpoint_size
;
2180 return tdep
->thumb_breakpoint
;
2184 *lenptr
= tdep
->arm_breakpoint_size
;
2185 return tdep
->arm_breakpoint
;
2189 /* Extract from an array REGBUF containing the (raw) register state a
2190 function return value of type TYPE, and copy that, in virtual
2191 format, into VALBUF. */
2194 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2197 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2199 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2201 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2205 /* The value is in register F0 in internal format. We need to
2206 extract the raw value and then convert it to the desired
2208 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2210 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2211 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2212 valbuf
, gdbarch_byte_order (gdbarch
));
2216 case ARM_FLOAT_SOFT_FPA
:
2217 case ARM_FLOAT_SOFT_VFP
:
2218 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2219 if (TYPE_LENGTH (type
) > 4)
2220 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2221 valbuf
+ INT_REGISTER_SIZE
);
2226 (__FILE__
, __LINE__
,
2227 _("arm_extract_return_value: Floating point model not supported"));
2231 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2232 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2233 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2234 || TYPE_CODE (type
) == TYPE_CODE_PTR
2235 || TYPE_CODE (type
) == TYPE_CODE_REF
2236 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2238 /* If the the type is a plain integer, then the access is
2239 straight-forward. Otherwise we have to play around a bit more. */
2240 int len
= TYPE_LENGTH (type
);
2241 int regno
= ARM_A1_REGNUM
;
2246 /* By using store_unsigned_integer we avoid having to do
2247 anything special for small big-endian values. */
2248 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2249 store_unsigned_integer (valbuf
,
2250 (len
> INT_REGISTER_SIZE
2251 ? INT_REGISTER_SIZE
: len
),
2253 len
-= INT_REGISTER_SIZE
;
2254 valbuf
+= INT_REGISTER_SIZE
;
2259 /* For a structure or union the behaviour is as if the value had
2260 been stored to word-aligned memory and then loaded into
2261 registers with 32-bit load instruction(s). */
2262 int len
= TYPE_LENGTH (type
);
2263 int regno
= ARM_A1_REGNUM
;
2264 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2268 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2269 memcpy (valbuf
, tmpbuf
,
2270 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2271 len
-= INT_REGISTER_SIZE
;
2272 valbuf
+= INT_REGISTER_SIZE
;
2278 /* Will a function return an aggregate type in memory or in a
2279 register? Return 0 if an aggregate type can be returned in a
2280 register, 1 if it must be returned in memory. */
2283 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2286 enum type_code code
;
2288 CHECK_TYPEDEF (type
);
2290 /* In the ARM ABI, "integer" like aggregate types are returned in
2291 registers. For an aggregate type to be integer like, its size
2292 must be less than or equal to INT_REGISTER_SIZE and the
2293 offset of each addressable subfield must be zero. Note that bit
2294 fields are not addressable, and all addressable subfields of
2295 unions always start at offset zero.
2297 This function is based on the behaviour of GCC 2.95.1.
2298 See: gcc/arm.c: arm_return_in_memory() for details.
2300 Note: All versions of GCC before GCC 2.95.2 do not set up the
2301 parameters correctly for a function returning the following
2302 structure: struct { float f;}; This should be returned in memory,
2303 not a register. Richard Earnshaw sent me a patch, but I do not
2304 know of any way to detect if a function like the above has been
2305 compiled with the correct calling convention. */
2307 /* All aggregate types that won't fit in a register must be returned
2309 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2314 /* The AAPCS says all aggregates not larger than a word are returned
2316 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2319 /* The only aggregate types that can be returned in a register are
2320 structs and unions. Arrays must be returned in memory. */
2321 code
= TYPE_CODE (type
);
2322 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2327 /* Assume all other aggregate types can be returned in a register.
2328 Run a check for structures, unions and arrays. */
2331 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2334 /* Need to check if this struct/union is "integer" like. For
2335 this to be true, its size must be less than or equal to
2336 INT_REGISTER_SIZE and the offset of each addressable
2337 subfield must be zero. Note that bit fields are not
2338 addressable, and unions always start at offset zero. If any
2339 of the subfields is a floating point type, the struct/union
2340 cannot be an integer type. */
2342 /* For each field in the object, check:
2343 1) Is it FP? --> yes, nRc = 1;
2344 2) Is it addressable (bitpos != 0) and
2345 not packed (bitsize == 0)?
2349 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2351 enum type_code field_type_code
;
2352 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2354 /* Is it a floating point type field? */
2355 if (field_type_code
== TYPE_CODE_FLT
)
2361 /* If bitpos != 0, then we have to care about it. */
2362 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2364 /* Bitfields are not addressable. If the field bitsize is
2365 zero, then the field is not packed. Hence it cannot be
2366 a bitfield or any other packed type. */
2367 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2379 /* Write into appropriate registers a function return value of type
2380 TYPE, given in virtual format. */
2383 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2384 const gdb_byte
*valbuf
)
2386 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2388 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2390 char buf
[MAX_REGISTER_SIZE
];
2392 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2396 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
2397 gdbarch_byte_order (gdbarch
));
2398 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2401 case ARM_FLOAT_SOFT_FPA
:
2402 case ARM_FLOAT_SOFT_VFP
:
2403 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2404 if (TYPE_LENGTH (type
) > 4)
2405 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2406 valbuf
+ INT_REGISTER_SIZE
);
2411 (__FILE__
, __LINE__
,
2412 _("arm_store_return_value: Floating point model not supported"));
2416 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2417 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2418 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2419 || TYPE_CODE (type
) == TYPE_CODE_PTR
2420 || TYPE_CODE (type
) == TYPE_CODE_REF
2421 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2423 if (TYPE_LENGTH (type
) <= 4)
2425 /* Values of one word or less are zero/sign-extended and
2427 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2428 LONGEST val
= unpack_long (type
, valbuf
);
2430 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2431 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2435 /* Integral values greater than one word are stored in consecutive
2436 registers starting with r0. This will always be a multiple of
2437 the regiser size. */
2438 int len
= TYPE_LENGTH (type
);
2439 int regno
= ARM_A1_REGNUM
;
2443 regcache_cooked_write (regs
, regno
++, valbuf
);
2444 len
-= INT_REGISTER_SIZE
;
2445 valbuf
+= INT_REGISTER_SIZE
;
2451 /* For a structure or union the behaviour is as if the value had
2452 been stored to word-aligned memory and then loaded into
2453 registers with 32-bit load instruction(s). */
2454 int len
= TYPE_LENGTH (type
);
2455 int regno
= ARM_A1_REGNUM
;
2456 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2460 memcpy (tmpbuf
, valbuf
,
2461 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2462 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2463 len
-= INT_REGISTER_SIZE
;
2464 valbuf
+= INT_REGISTER_SIZE
;
2470 /* Handle function return values. */
2472 static enum return_value_convention
2473 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2474 struct type
*valtype
, struct regcache
*regcache
,
2475 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2477 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2479 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2480 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2481 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2483 if (tdep
->struct_return
== pcc_struct_return
2484 || arm_return_in_memory (gdbarch
, valtype
))
2485 return RETURN_VALUE_STRUCT_CONVENTION
;
2489 arm_store_return_value (valtype
, regcache
, writebuf
);
2492 arm_extract_return_value (valtype
, regcache
, readbuf
);
2494 return RETURN_VALUE_REGISTER_CONVENTION
;
2499 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2502 char buf
[INT_REGISTER_SIZE
];
2503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2505 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2507 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2511 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2515 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2516 return the target PC. Otherwise return 0. */
2519 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2523 CORE_ADDR start_addr
;
2525 /* Find the starting address and name of the function containing the PC. */
2526 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2529 /* If PC is in a Thumb call or return stub, return the address of the
2530 target PC, which is in a register. The thunk functions are called
2531 _call_via_xx, where x is the register name. The possible names
2532 are r0-r9, sl, fp, ip, sp, and lr. */
2533 if (strncmp (name
, "_call_via_", 10) == 0)
2535 /* Use the name suffix to determine which register contains the
2537 static char *table
[15] =
2538 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2539 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2542 int offset
= strlen (name
) - 2;
2544 for (regno
= 0; regno
<= 14; regno
++)
2545 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2546 return get_frame_register_unsigned (frame
, regno
);
2549 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2550 non-interworking calls to foo. We could decode the stubs
2551 to find the target but it's easier to use the symbol table. */
2552 namelen
= strlen (name
);
2553 if (name
[0] == '_' && name
[1] == '_'
2554 && ((namelen
> 2 + strlen ("_from_thumb")
2555 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2556 strlen ("_from_thumb")) == 0)
2557 || (namelen
> 2 + strlen ("_from_arm")
2558 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2559 strlen ("_from_arm")) == 0)))
2562 int target_len
= namelen
- 2;
2563 struct minimal_symbol
*minsym
;
2564 struct objfile
*objfile
;
2565 struct obj_section
*sec
;
2567 if (name
[namelen
- 1] == 'b')
2568 target_len
-= strlen ("_from_thumb");
2570 target_len
-= strlen ("_from_arm");
2572 target_name
= alloca (target_len
+ 1);
2573 memcpy (target_name
, name
+ 2, target_len
);
2574 target_name
[target_len
] = '\0';
2576 sec
= find_pc_section (pc
);
2577 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2578 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2580 return SYMBOL_VALUE_ADDRESS (minsym
);
2585 return 0; /* not a stub */
2589 set_arm_command (char *args
, int from_tty
)
2591 printf_unfiltered (_("\
2592 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2593 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2597 show_arm_command (char *args
, int from_tty
)
2599 cmd_show_list (showarmcmdlist
, from_tty
, "");
2603 arm_update_current_architecture (void)
2605 struct gdbarch_info info
;
2607 /* If the current architecture is not ARM, we have nothing to do. */
2608 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2611 /* Update the architecture. */
2612 gdbarch_info_init (&info
);
2614 if (!gdbarch_update_p (info
))
2615 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2619 set_fp_model_sfunc (char *args
, int from_tty
,
2620 struct cmd_list_element
*c
)
2622 enum arm_float_model fp_model
;
2624 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2625 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2627 arm_fp_model
= fp_model
;
2631 if (fp_model
== ARM_FLOAT_LAST
)
2632 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2635 arm_update_current_architecture ();
2639 show_fp_model (struct ui_file
*file
, int from_tty
,
2640 struct cmd_list_element
*c
, const char *value
)
2642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2644 if (arm_fp_model
== ARM_FLOAT_AUTO
2645 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2646 fprintf_filtered (file
, _("\
2647 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2648 fp_model_strings
[tdep
->fp_model
]);
2650 fprintf_filtered (file
, _("\
2651 The current ARM floating point model is \"%s\".\n"),
2652 fp_model_strings
[arm_fp_model
]);
2656 arm_set_abi (char *args
, int from_tty
,
2657 struct cmd_list_element
*c
)
2659 enum arm_abi_kind arm_abi
;
2661 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2662 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2664 arm_abi_global
= arm_abi
;
2668 if (arm_abi
== ARM_ABI_LAST
)
2669 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2672 arm_update_current_architecture ();
2676 arm_show_abi (struct ui_file
*file
, int from_tty
,
2677 struct cmd_list_element
*c
, const char *value
)
2679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2681 if (arm_abi_global
== ARM_ABI_AUTO
2682 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2683 fprintf_filtered (file
, _("\
2684 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2685 arm_abi_strings
[tdep
->arm_abi
]);
2687 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2692 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
2693 struct cmd_list_element
*c
, const char *value
)
2695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2697 fprintf_filtered (file
, _("\
2698 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2699 arm_fallback_mode_string
);
2703 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
2704 struct cmd_list_element
*c
, const char *value
)
2706 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2708 fprintf_filtered (file
, _("\
2709 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2710 arm_force_mode_string
);
2713 /* If the user changes the register disassembly style used for info
2714 register and other commands, we have to also switch the style used
2715 in opcodes for disassembly output. This function is run in the "set
2716 arm disassembly" command, and does that. */
2719 set_disassembly_style_sfunc (char *args
, int from_tty
,
2720 struct cmd_list_element
*c
)
2722 set_disassembly_style ();
2725 /* Return the ARM register name corresponding to register I. */
2727 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2729 if (i
>= ARRAY_SIZE (arm_register_names
))
2730 /* These registers are only supported on targets which supply
2731 an XML description. */
2734 return arm_register_names
[i
];
2738 set_disassembly_style (void)
2742 /* Find the style that the user wants. */
2743 for (current
= 0; current
< num_disassembly_options
; current
++)
2744 if (disassembly_style
== valid_disassembly_styles
[current
])
2746 gdb_assert (current
< num_disassembly_options
);
2748 /* Synchronize the disassembler. */
2749 set_arm_regname_option (current
);
2752 /* Test whether the coff symbol specific value corresponds to a Thumb
2756 coff_sym_is_thumb (int val
)
2758 return (val
== C_THUMBEXT
||
2759 val
== C_THUMBSTAT
||
2760 val
== C_THUMBEXTFUNC
||
2761 val
== C_THUMBSTATFUNC
||
2762 val
== C_THUMBLABEL
);
2765 /* arm_coff_make_msymbol_special()
2766 arm_elf_make_msymbol_special()
2768 These functions test whether the COFF or ELF symbol corresponds to
2769 an address in thumb code, and set a "special" bit in a minimal
2770 symbol to indicate that it does. */
2773 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2775 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2777 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2779 MSYMBOL_SET_SPECIAL (msym
);
2783 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2785 if (coff_sym_is_thumb (val
))
2786 MSYMBOL_SET_SPECIAL (msym
);
2790 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2792 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2794 /* If necessary, set the T bit. */
2798 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2799 if (arm_pc_is_thumb (pc
))
2800 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
2802 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2803 val
& ~(ULONGEST
) CPSR_T
);
2807 static struct value
*
2808 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2810 const int *reg_p
= baton
;
2811 return value_of_register (*reg_p
, frame
);
2814 static enum gdb_osabi
2815 arm_elf_osabi_sniffer (bfd
*abfd
)
2817 unsigned int elfosabi
;
2818 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2820 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2822 if (elfosabi
== ELFOSABI_ARM
)
2823 /* GNU tools use this value. Check note sections in this case,
2825 bfd_map_over_sections (abfd
,
2826 generic_elf_osabi_sniff_abi_tag_sections
,
2829 /* Anything else will be handled by the generic ELF sniffer. */
2834 /* Initialize the current architecture based on INFO. If possible,
2835 re-use an architecture from ARCHES, which is a list of
2836 architectures already created during this debugging session.
2838 Called e.g. at program startup, when reading a core file, and when
2839 reading a binary file. */
2841 static struct gdbarch
*
2842 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2844 struct gdbarch_tdep
*tdep
;
2845 struct gdbarch
*gdbarch
;
2846 struct gdbarch_list
*best_arch
;
2847 enum arm_abi_kind arm_abi
= arm_abi_global
;
2848 enum arm_float_model fp_model
= arm_fp_model
;
2849 struct tdesc_arch_data
*tdesc_data
= NULL
;
2851 int have_fpa_registers
= 1;
2853 /* Check any target description for validity. */
2854 if (tdesc_has_registers (info
.target_desc
))
2856 /* For most registers we require GDB's default names; but also allow
2857 the numeric names for sp / lr / pc, as a convenience. */
2858 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2859 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2860 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2862 const struct tdesc_feature
*feature
;
2865 feature
= tdesc_find_feature (info
.target_desc
,
2866 "org.gnu.gdb.arm.core");
2867 if (feature
== NULL
)
2870 tdesc_data
= tdesc_data_alloc ();
2873 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2874 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2875 arm_register_names
[i
]);
2876 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2879 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2882 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2885 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2886 ARM_PS_REGNUM
, "cpsr");
2890 tdesc_data_cleanup (tdesc_data
);
2894 feature
= tdesc_find_feature (info
.target_desc
,
2895 "org.gnu.gdb.arm.fpa");
2896 if (feature
!= NULL
)
2899 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2900 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2901 arm_register_names
[i
]);
2904 tdesc_data_cleanup (tdesc_data
);
2909 have_fpa_registers
= 0;
2911 feature
= tdesc_find_feature (info
.target_desc
,
2912 "org.gnu.gdb.xscale.iwmmxt");
2913 if (feature
!= NULL
)
2915 static const char *const iwmmxt_names
[] = {
2916 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2917 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2918 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2919 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2923 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2925 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2926 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2928 /* Check for the control registers, but do not fail if they
2930 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2931 tdesc_numbered_register (feature
, tdesc_data
, i
,
2932 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2934 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2936 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2937 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2941 tdesc_data_cleanup (tdesc_data
);
2947 /* If we have an object to base this architecture on, try to determine
2950 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2952 int ei_osabi
, e_flags
;
2954 switch (bfd_get_flavour (info
.abfd
))
2956 case bfd_target_aout_flavour
:
2957 /* Assume it's an old APCS-style ABI. */
2958 arm_abi
= ARM_ABI_APCS
;
2961 case bfd_target_coff_flavour
:
2962 /* Assume it's an old APCS-style ABI. */
2964 arm_abi
= ARM_ABI_APCS
;
2967 case bfd_target_elf_flavour
:
2968 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2969 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2971 if (ei_osabi
== ELFOSABI_ARM
)
2973 /* GNU tools used to use this value, but do not for EABI
2974 objects. There's nowhere to tag an EABI version
2975 anyway, so assume APCS. */
2976 arm_abi
= ARM_ABI_APCS
;
2978 else if (ei_osabi
== ELFOSABI_NONE
)
2980 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2984 case EF_ARM_EABI_UNKNOWN
:
2985 /* Assume GNU tools. */
2986 arm_abi
= ARM_ABI_APCS
;
2989 case EF_ARM_EABI_VER4
:
2990 case EF_ARM_EABI_VER5
:
2991 arm_abi
= ARM_ABI_AAPCS
;
2992 /* EABI binaries default to VFP float ordering. */
2993 if (fp_model
== ARM_FLOAT_AUTO
)
2994 fp_model
= ARM_FLOAT_SOFT_VFP
;
2998 /* Leave it as "auto". */
2999 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
3004 if (fp_model
== ARM_FLOAT_AUTO
)
3006 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3008 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
3011 /* Leave it as "auto". Strictly speaking this case
3012 means FPA, but almost nobody uses that now, and
3013 many toolchains fail to set the appropriate bits
3014 for the floating-point model they use. */
3016 case EF_ARM_SOFT_FLOAT
:
3017 fp_model
= ARM_FLOAT_SOFT_FPA
;
3019 case EF_ARM_VFP_FLOAT
:
3020 fp_model
= ARM_FLOAT_VFP
;
3022 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
3023 fp_model
= ARM_FLOAT_SOFT_VFP
;
3030 /* Leave it as "auto". */
3035 /* If there is already a candidate, use it. */
3036 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3038 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3040 if (arm_abi
!= ARM_ABI_AUTO
3041 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
3044 if (fp_model
!= ARM_FLOAT_AUTO
3045 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
3048 /* Found a match. */
3052 if (best_arch
!= NULL
)
3054 if (tdesc_data
!= NULL
)
3055 tdesc_data_cleanup (tdesc_data
);
3056 return best_arch
->gdbarch
;
3059 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
3060 gdbarch
= gdbarch_alloc (&info
, tdep
);
3062 /* Record additional information about the architecture we are defining.
3063 These are gdbarch discriminators, like the OSABI. */
3064 tdep
->arm_abi
= arm_abi
;
3065 tdep
->fp_model
= fp_model
;
3066 tdep
->have_fpa_registers
= have_fpa_registers
;
3069 switch (info
.byte_order
)
3071 case BFD_ENDIAN_BIG
:
3072 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
3073 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
3074 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
3075 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
3079 case BFD_ENDIAN_LITTLE
:
3080 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
3081 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
3082 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
3083 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
3088 internal_error (__FILE__
, __LINE__
,
3089 _("arm_gdbarch_init: bad byte order for float format"));
3092 /* On ARM targets char defaults to unsigned. */
3093 set_gdbarch_char_signed (gdbarch
, 0);
3095 /* This should be low enough for everything. */
3096 tdep
->lowest_pc
= 0x20;
3097 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3099 /* The default, for both APCS and AAPCS, is to return small
3100 structures in registers. */
3101 tdep
->struct_return
= reg_struct_return
;
3103 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
3104 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
3106 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
3108 /* Frame handling. */
3109 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
3110 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
3111 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
3113 frame_base_set_default (gdbarch
, &arm_normal_base
);
3115 /* Address manipulation. */
3116 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
3117 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
3119 /* Advance PC across function entry code. */
3120 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3122 /* Skip trampolines. */
3123 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
3125 /* The stack grows downward. */
3126 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3128 /* Breakpoint manipulation. */
3129 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3131 /* Information about registers, etc. */
3132 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3133 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3134 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3135 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3136 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3138 /* This "info float" is FPA-specific. Use the generic version if we
3140 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3141 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3143 /* Internal <-> external register number maps. */
3144 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3145 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3146 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3148 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3150 /* Returning results. */
3151 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3154 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3156 /* Minsymbol frobbing. */
3157 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3158 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3159 arm_coff_make_msymbol_special
);
3161 /* Virtual tables. */
3162 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3164 /* Hook in the ABI-specific overrides, if they have been registered. */
3165 gdbarch_init_osabi (info
, gdbarch
);
3167 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
3169 /* Add some default predicates. */
3170 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
3171 dwarf2_append_unwinders (gdbarch
);
3172 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
3174 /* Now we have tuned the configuration, set a few final things,
3175 based on what the OS ABI has told us. */
3177 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3178 binaries are always marked. */
3179 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3180 tdep
->arm_abi
= ARM_ABI_APCS
;
3182 /* We used to default to FPA for generic ARM, but almost nobody
3183 uses that now, and we now provide a way for the user to force
3184 the model. So default to the most useful variant. */
3185 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3186 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3188 if (tdep
->jb_pc
>= 0)
3189 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3191 /* Floating point sizes and format. */
3192 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3193 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3195 set_gdbarch_double_format
3196 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3197 set_gdbarch_long_double_format
3198 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3202 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3203 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3207 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3209 /* Add standard register aliases. We add aliases even for those
3210 nanes which are used by the current architecture - it's simpler,
3211 and does no harm, since nothing ever lists user registers. */
3212 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3213 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3214 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3220 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3227 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3228 (unsigned long) tdep
->lowest_pc
);
3231 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3234 _initialize_arm_tdep (void)
3236 struct ui_file
*stb
;
3238 struct cmd_list_element
*new_set
, *new_show
;
3239 const char *setname
;
3240 const char *setdesc
;
3241 const char *const *regnames
;
3243 static char *helptext
;
3244 char regdesc
[1024], *rdptr
= regdesc
;
3245 size_t rest
= sizeof (regdesc
);
3247 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3249 /* Register an ELF OS ABI sniffer for ARM binaries. */
3250 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3251 bfd_target_elf_flavour
,
3252 arm_elf_osabi_sniffer
);
3254 /* Get the number of possible sets of register names defined in opcodes. */
3255 num_disassembly_options
= get_arm_regname_num_options ();
3257 /* Add root prefix command for all "set arm"/"show arm" commands. */
3258 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3259 _("Various ARM-specific commands."),
3260 &setarmcmdlist
, "set arm ", 0, &setlist
);
3262 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3263 _("Various ARM-specific commands."),
3264 &showarmcmdlist
, "show arm ", 0, &showlist
);
3266 /* Sync the opcode insn printer with our register viewer. */
3267 parse_arm_disassembler_option ("reg-names-std");
3269 /* Initialize the array that will be passed to
3270 add_setshow_enum_cmd(). */
3271 valid_disassembly_styles
3272 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3273 for (i
= 0; i
< num_disassembly_options
; i
++)
3275 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3276 valid_disassembly_styles
[i
] = setname
;
3277 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3280 /* When we find the default names, tell the disassembler to use
3282 if (!strcmp (setname
, "std"))
3284 disassembly_style
= setname
;
3285 set_arm_regname_option (i
);
3288 /* Mark the end of valid options. */
3289 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3291 /* Create the help text. */
3292 stb
= mem_fileopen ();
3293 fprintf_unfiltered (stb
, "%s%s%s",
3294 _("The valid values are:\n"),
3296 _("The default is \"std\"."));
3297 helptext
= ui_file_xstrdup (stb
, &length
);
3298 ui_file_delete (stb
);
3300 add_setshow_enum_cmd("disassembler", no_class
,
3301 valid_disassembly_styles
, &disassembly_style
,
3302 _("Set the disassembly style."),
3303 _("Show the disassembly style."),
3305 set_disassembly_style_sfunc
,
3306 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3307 &setarmcmdlist
, &showarmcmdlist
);
3309 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3310 _("Set usage of ARM 32-bit mode."),
3311 _("Show usage of ARM 32-bit mode."),
3312 _("When off, a 26-bit PC will be used."),
3314 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3315 &setarmcmdlist
, &showarmcmdlist
);
3317 /* Add a command to allow the user to force the FPU model. */
3318 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3319 _("Set the floating point type."),
3320 _("Show the floating point type."),
3321 _("auto - Determine the FP typefrom the OS-ABI.\n\
3322 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3323 fpa - FPA co-processor (GCC compiled).\n\
3324 softvfp - Software FP with pure-endian doubles.\n\
3325 vfp - VFP co-processor."),
3326 set_fp_model_sfunc
, show_fp_model
,
3327 &setarmcmdlist
, &showarmcmdlist
);
3329 /* Add a command to allow the user to force the ABI. */
3330 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3333 NULL
, arm_set_abi
, arm_show_abi
,
3334 &setarmcmdlist
, &showarmcmdlist
);
3336 /* Add two commands to allow the user to force the assumed
3338 add_setshow_enum_cmd ("fallback-mode", class_support
,
3339 arm_mode_strings
, &arm_fallback_mode_string
,
3340 _("Set the mode assumed when symbols are unavailable."),
3341 _("Show the mode assumed when symbols are unavailable."),
3342 NULL
, NULL
, arm_show_fallback_mode
,
3343 &setarmcmdlist
, &showarmcmdlist
);
3344 add_setshow_enum_cmd ("force-mode", class_support
,
3345 arm_mode_strings
, &arm_force_mode_string
,
3346 _("Set the mode assumed even when symbols are available."),
3347 _("Show the mode assumed even when symbols are available."),
3348 NULL
, NULL
, arm_show_force_mode
,
3349 &setarmcmdlist
, &showarmcmdlist
);
3351 /* Debugging flag. */
3352 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3353 _("Set ARM debugging."),
3354 _("Show ARM debugging."),
3355 _("When on, arm-specific debugging is enabled."),
3357 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3358 &setdebuglist
, &showdebuglist
);