1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
63 #include "features/arm/arm-with-m.c"
64 #include "features/arm/arm-with-m-fpa-layout.c"
65 #include "features/arm/arm-with-m-vfp-d16.c"
66 #include "features/arm/arm-with-iwmmxt.c"
67 #include "features/arm/arm-with-vfpv2.c"
68 #include "features/arm/arm-with-vfpv3.c"
69 #include "features/arm/arm-with-neon.c"
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose.
77 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
78 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
80 #define MSYMBOL_SET_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym) = 1
83 #define MSYMBOL_IS_SPECIAL(msym) \
84 MSYMBOL_TARGET_FLAG_1 (msym)
86 /* Per-objfile data used for mapping symbols. */
87 static const struct objfile_data
*arm_objfile_data_key
;
89 struct arm_mapping_symbol
94 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
95 DEF_VEC_O(arm_mapping_symbol_s
);
97 struct arm_per_objfile
99 VEC(arm_mapping_symbol_s
) **section_maps
;
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element
*setarmcmdlist
= NULL
;
104 static struct cmd_list_element
*showarmcmdlist
= NULL
;
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *const fp_model_strings
[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
120 static const char *current_fp_model
= "auto";
122 /* The ABI to use. Keep this in sync with arm_abi_kind. */
123 static const char *const arm_abi_strings
[] =
131 /* A variable that can be configured by the user. */
132 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
133 static const char *arm_abi_string
= "auto";
135 /* The execution mode to assume. */
136 static const char *const arm_mode_strings
[] =
144 static const char *arm_fallback_mode_string
= "auto";
145 static const char *arm_force_mode_string
= "auto";
147 /* Internal override of the execution mode. -1 means no override,
148 0 means override to ARM mode, 1 means override to Thumb mode.
149 The effect is the same as if arm_force_mode has been set by the
150 user (except the internal override has precedence over a user's
151 arm_force_mode override). */
152 static int arm_override_mode
= -1;
154 /* Number of different reg name sets (options). */
155 static int num_disassembly_options
;
157 /* The standard register names, and all the valid aliases for them. Note
158 that `fp', `sp' and `pc' are not added in this alias list, because they
159 have been added as builtin user registers in
160 std-regs.c:_initialize_frame_reg. */
165 } arm_register_aliases
[] = {
166 /* Basic register numbers. */
183 /* Synonyms (argument and variable registers). */
196 /* Other platform-specific names for r9. */
202 /* Names used by GCC (not listed in the ARM EABI). */
204 /* A special name from the older ATPCS. */
208 static const char *const arm_register_names
[] =
209 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
210 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
211 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
212 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
213 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
214 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
215 "fps", "cpsr" }; /* 24 25 */
217 /* Valid register name styles. */
218 static const char **valid_disassembly_styles
;
220 /* Disassembly style to use. Default to "std" register names. */
221 static const char *disassembly_style
;
223 /* This is used to keep the bfd arch_info in sync with the disassembly
225 static void set_disassembly_style_sfunc(char *, int,
226 struct cmd_list_element
*);
227 static void set_disassembly_style (void);
229 static void convert_from_extended (const struct floatformat
*, const void *,
231 static void convert_to_extended (const struct floatformat
*, void *,
234 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, gdb_byte
*buf
);
237 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
238 struct regcache
*regcache
,
239 int regnum
, const gdb_byte
*buf
);
242 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
245 /* get_next_pcs operations. */
246 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
247 arm_get_next_pcs_read_memory_unsigned_integer
,
248 arm_get_next_pcs_syscall_next_pc
,
249 arm_get_next_pcs_addr_bits_remove
,
250 arm_get_next_pcs_is_thumb
,
254 struct arm_prologue_cache
256 /* The stack pointer at the time this frame was created; i.e. the
257 caller's stack pointer when this function was called. It is used
258 to identify this frame. */
261 /* The frame base for this frame is just prev_sp - frame size.
262 FRAMESIZE is the distance from the frame pointer to the
263 initial stack pointer. */
267 /* The register used to hold the frame pointer for this frame. */
270 /* Saved register offsets. */
271 struct trad_frame_saved_reg
*saved_regs
;
274 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
275 CORE_ADDR prologue_start
,
276 CORE_ADDR prologue_end
,
277 struct arm_prologue_cache
*cache
);
279 /* Architecture version for displaced stepping. This effects the behaviour of
280 certain instructions, and really should not be hard-wired. */
282 #define DISPLACED_STEPPING_ARCH_VERSION 5
284 /* Set to true if the 32-bit mode is in use. */
288 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
291 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
293 if (gdbarch_tdep (gdbarch
)->is_m
)
299 /* Determine if the processor is currently executing in Thumb mode. */
302 arm_is_thumb (struct regcache
*regcache
)
305 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
307 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
309 return (cpsr
& t_bit
) != 0;
312 /* Determine if FRAME is executing in Thumb mode. */
315 arm_frame_is_thumb (struct frame_info
*frame
)
318 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
320 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
321 directly (from a signal frame or dummy frame) or by interpreting
322 the saved LR (from a prologue or DWARF frame). So consult it and
323 trust the unwinders. */
324 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
326 return (cpsr
& t_bit
) != 0;
329 /* Callback for VEC_lower_bound. */
332 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
333 const struct arm_mapping_symbol
*rhs
)
335 return lhs
->value
< rhs
->value
;
338 /* Search for the mapping symbol covering MEMADDR. If one is found,
339 return its type. Otherwise, return 0. If START is non-NULL,
340 set *START to the location of the mapping symbol. */
343 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
345 struct obj_section
*sec
;
347 /* If there are mapping symbols, consult them. */
348 sec
= find_pc_section (memaddr
);
351 struct arm_per_objfile
*data
;
352 VEC(arm_mapping_symbol_s
) *map
;
353 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
357 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
358 arm_objfile_data_key
);
361 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
362 if (!VEC_empty (arm_mapping_symbol_s
, map
))
364 struct arm_mapping_symbol
*map_sym
;
366 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
367 arm_compare_mapping_symbols
);
369 /* VEC_lower_bound finds the earliest ordered insertion
370 point. If the following symbol starts at this exact
371 address, we use that; otherwise, the preceding
372 mapping symbol covers this address. */
373 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
375 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
376 if (map_sym
->value
== map_key
.value
)
379 *start
= map_sym
->value
+ obj_section_addr (sec
);
380 return map_sym
->type
;
386 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
388 *start
= map_sym
->value
+ obj_section_addr (sec
);
389 return map_sym
->type
;
398 /* Determine if the program counter specified in MEMADDR is in a Thumb
399 function. This function should be called for addresses unrelated to
400 any executing frame; otherwise, prefer arm_frame_is_thumb. */
403 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
405 struct bound_minimal_symbol sym
;
407 struct displaced_step_closure
* dsc
408 = get_displaced_step_closure_by_addr(memaddr
);
410 /* If checking the mode of displaced instruction in copy area, the mode
411 should be determined by instruction on the original address. */
415 fprintf_unfiltered (gdb_stdlog
,
416 "displaced: check mode of %.8lx instead of %.8lx\n",
417 (unsigned long) dsc
->insn_addr
,
418 (unsigned long) memaddr
);
419 memaddr
= dsc
->insn_addr
;
422 /* If bit 0 of the address is set, assume this is a Thumb address. */
423 if (IS_THUMB_ADDR (memaddr
))
426 /* Respect internal mode override if active. */
427 if (arm_override_mode
!= -1)
428 return arm_override_mode
;
430 /* If the user wants to override the symbol table, let him. */
431 if (strcmp (arm_force_mode_string
, "arm") == 0)
433 if (strcmp (arm_force_mode_string
, "thumb") == 0)
436 /* ARM v6-M and v7-M are always in Thumb mode. */
437 if (gdbarch_tdep (gdbarch
)->is_m
)
440 /* If there are mapping symbols, consult them. */
441 type
= arm_find_mapping_symbol (memaddr
, NULL
);
445 /* Thumb functions have a "special" bit set in minimal symbols. */
446 sym
= lookup_minimal_symbol_by_pc (memaddr
);
448 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
450 /* If the user wants to override the fallback mode, let them. */
451 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
453 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
456 /* If we couldn't find any symbol, but we're talking to a running
457 target, then trust the current value of $cpsr. This lets
458 "display/i $pc" always show the correct mode (though if there is
459 a symbol table we will not reach here, so it still may not be
460 displayed in the mode it will be executed). */
461 if (target_has_registers
)
462 return arm_frame_is_thumb (get_current_frame ());
464 /* Otherwise we're out of luck; we assume ARM. */
468 /* Determine if the address specified equals any of these magic return
469 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
472 From ARMv6-M Reference Manual B1.5.8
473 Table B1-5 Exception return behavior
475 EXC_RETURN Return To Return Stack
476 0xFFFFFFF1 Handler mode Main
477 0xFFFFFFF9 Thread mode Main
478 0xFFFFFFFD Thread mode Process
480 From ARMv7-M Reference Manual B1.5.8
481 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
483 EXC_RETURN Return To Return Stack
484 0xFFFFFFF1 Handler mode Main
485 0xFFFFFFF9 Thread mode Main
486 0xFFFFFFFD Thread mode Process
488 Table B1-9 EXC_RETURN definition of exception return behavior, with
491 EXC_RETURN Return To Return Stack Frame Type
492 0xFFFFFFE1 Handler mode Main Extended
493 0xFFFFFFE9 Thread mode Main Extended
494 0xFFFFFFED Thread mode Process Extended
495 0xFFFFFFF1 Handler mode Main Basic
496 0xFFFFFFF9 Thread mode Main Basic
497 0xFFFFFFFD Thread mode Process Basic
499 For more details see "B1.5.8 Exception return behavior"
500 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
503 arm_m_addr_is_magic (CORE_ADDR addr
)
507 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
508 the exception return behavior. */
515 /* Address is magic. */
519 /* Address is not magic. */
524 /* Remove useless bits from addresses in a running program. */
526 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
528 /* On M-profile devices, do not strip the low bit from EXC_RETURN
529 (the magic exception return address). */
530 if (gdbarch_tdep (gdbarch
)->is_m
531 && arm_m_addr_is_magic (val
))
535 return UNMAKE_THUMB_ADDR (val
);
537 return (val
& 0x03fffffc);
540 /* Return 1 if PC is the start of a compiler helper function which
541 can be safely ignored during prologue skipping. IS_THUMB is true
542 if the function is known to be a Thumb function due to the way it
545 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
547 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
548 struct bound_minimal_symbol msym
;
550 msym
= lookup_minimal_symbol_by_pc (pc
);
551 if (msym
.minsym
!= NULL
552 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
553 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
555 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
557 /* The GNU linker's Thumb call stub to foo is named
559 if (strstr (name
, "_from_thumb") != NULL
)
562 /* On soft-float targets, __truncdfsf2 is called to convert promoted
563 arguments to their argument types in non-prototyped
565 if (startswith (name
, "__truncdfsf2"))
567 if (startswith (name
, "__aeabi_d2f"))
570 /* Internal functions related to thread-local storage. */
571 if (startswith (name
, "__tls_get_addr"))
573 if (startswith (name
, "__aeabi_read_tp"))
578 /* If we run against a stripped glibc, we may be unable to identify
579 special functions by name. Check for one important case,
580 __aeabi_read_tp, by comparing the *code* against the default
581 implementation (this is hand-written ARM assembler in glibc). */
584 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
585 == 0xe3e00a0f /* mov r0, #0xffff0fff */
586 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
587 == 0xe240f01f) /* sub pc, r0, #31 */
594 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
595 the first 16-bit of instruction, and INSN2 is the second 16-bit of
597 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
598 ((bits ((insn1), 0, 3) << 12) \
599 | (bits ((insn1), 10, 10) << 11) \
600 | (bits ((insn2), 12, 14) << 8) \
601 | bits ((insn2), 0, 7))
603 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
604 the 32-bit instruction. */
605 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
606 ((bits ((insn), 16, 19) << 12) \
607 | bits ((insn), 0, 11))
609 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
612 thumb_expand_immediate (unsigned int imm
)
614 unsigned int count
= imm
>> 7;
622 return (imm
& 0xff) | ((imm
& 0xff) << 16);
624 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
626 return (imm
& 0xff) | ((imm
& 0xff) << 8)
627 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
630 return (0x80 | (imm
& 0x7f)) << (32 - count
);
633 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
634 epilogue, 0 otherwise. */
637 thumb_instruction_restores_sp (unsigned short insn
)
639 return (insn
== 0x46bd /* mov sp, r7 */
640 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
641 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
644 /* Analyze a Thumb prologue, looking for a recognizable stack frame
645 and frame pointer. Scan until we encounter a store that could
646 clobber the stack frame unexpectedly, or an unknown instruction.
647 Return the last address which is definitely safe to skip for an
648 initial breakpoint. */
651 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
652 CORE_ADDR start
, CORE_ADDR limit
,
653 struct arm_prologue_cache
*cache
)
655 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
656 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
659 struct pv_area
*stack
;
660 struct cleanup
*back_to
;
662 CORE_ADDR unrecognized_pc
= 0;
664 for (i
= 0; i
< 16; i
++)
665 regs
[i
] = pv_register (i
, 0);
666 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
667 back_to
= make_cleanup_free_pv_area (stack
);
669 while (start
< limit
)
673 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
675 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
680 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
683 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
684 whether to save LR (R14). */
685 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
687 /* Calculate offsets of saved R0-R7 and LR. */
688 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
689 if (mask
& (1 << regno
))
691 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
693 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
696 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
698 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
699 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
702 else if (thumb_instruction_restores_sp (insn
))
704 /* Don't scan past the epilogue. */
707 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
708 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
710 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
711 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
712 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
714 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
715 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
716 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
718 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
719 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
720 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
721 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
722 regs
[bits (insn
, 6, 8)]);
723 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
724 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
726 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
727 int rm
= bits (insn
, 3, 6);
728 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
730 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
732 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
733 int src_reg
= (insn
& 0x78) >> 3;
734 regs
[dst_reg
] = regs
[src_reg
];
736 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
738 /* Handle stores to the stack. Normally pushes are used,
739 but with GCC -mtpcs-frame, there may be other stores
740 in the prologue to create the frame. */
741 int regno
= (insn
>> 8) & 0x7;
744 offset
= (insn
& 0xff) << 2;
745 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
747 if (pv_area_store_would_trash (stack
, addr
))
750 pv_area_store (stack
, addr
, 4, regs
[regno
]);
752 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
754 int rd
= bits (insn
, 0, 2);
755 int rn
= bits (insn
, 3, 5);
758 offset
= bits (insn
, 6, 10) << 2;
759 addr
= pv_add_constant (regs
[rn
], offset
);
761 if (pv_area_store_would_trash (stack
, addr
))
764 pv_area_store (stack
, addr
, 4, regs
[rd
]);
766 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
767 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
768 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
769 /* Ignore stores of argument registers to the stack. */
771 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
772 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
773 /* Ignore block loads from the stack, potentially copying
774 parameters from memory. */
776 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
777 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
778 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
779 /* Similarly ignore single loads from the stack. */
781 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
782 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
783 /* Skip register copies, i.e. saves to another register
784 instead of the stack. */
786 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
787 /* Recognize constant loads; even with small stacks these are necessary
789 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
790 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
792 /* Constant pool loads, for the same reason. */
793 unsigned int constant
;
796 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
797 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
798 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
800 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
802 unsigned short inst2
;
804 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
805 byte_order_for_code
);
807 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
809 /* BL, BLX. Allow some special function calls when
810 skipping the prologue; GCC generates these before
811 storing arguments to the stack. */
813 int j1
, j2
, imm1
, imm2
;
815 imm1
= sbits (insn
, 0, 10);
816 imm2
= bits (inst2
, 0, 10);
817 j1
= bit (inst2
, 13);
818 j2
= bit (inst2
, 11);
820 offset
= ((imm1
<< 12) + (imm2
<< 1));
821 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
823 nextpc
= start
+ 4 + offset
;
824 /* For BLX make sure to clear the low bits. */
825 if (bit (inst2
, 12) == 0)
826 nextpc
= nextpc
& 0xfffffffc;
828 if (!skip_prologue_function (gdbarch
, nextpc
,
829 bit (inst2
, 12) != 0))
833 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
835 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
837 pv_t addr
= regs
[bits (insn
, 0, 3)];
840 if (pv_area_store_would_trash (stack
, addr
))
843 /* Calculate offsets of saved registers. */
844 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
845 if (inst2
& (1 << regno
))
847 addr
= pv_add_constant (addr
, -4);
848 pv_area_store (stack
, addr
, 4, regs
[regno
]);
852 regs
[bits (insn
, 0, 3)] = addr
;
855 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
857 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
859 int regno1
= bits (inst2
, 12, 15);
860 int regno2
= bits (inst2
, 8, 11);
861 pv_t addr
= regs
[bits (insn
, 0, 3)];
863 offset
= inst2
& 0xff;
865 addr
= pv_add_constant (addr
, offset
);
867 addr
= pv_add_constant (addr
, -offset
);
869 if (pv_area_store_would_trash (stack
, addr
))
872 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
873 pv_area_store (stack
, pv_add_constant (addr
, 4),
877 regs
[bits (insn
, 0, 3)] = addr
;
880 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
881 && (inst2
& 0x0c00) == 0x0c00
882 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
884 int regno
= bits (inst2
, 12, 15);
885 pv_t addr
= regs
[bits (insn
, 0, 3)];
887 offset
= inst2
& 0xff;
889 addr
= pv_add_constant (addr
, offset
);
891 addr
= pv_add_constant (addr
, -offset
);
893 if (pv_area_store_would_trash (stack
, addr
))
896 pv_area_store (stack
, addr
, 4, regs
[regno
]);
899 regs
[bits (insn
, 0, 3)] = addr
;
902 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
903 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
905 int regno
= bits (inst2
, 12, 15);
908 offset
= inst2
& 0xfff;
909 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
911 if (pv_area_store_would_trash (stack
, addr
))
914 pv_area_store (stack
, addr
, 4, regs
[regno
]);
917 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
918 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
919 /* Ignore stores of argument registers to the stack. */
922 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
923 && (inst2
& 0x0d00) == 0x0c00
924 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
925 /* Ignore stores of argument registers to the stack. */
928 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
930 && (inst2
& 0x8000) == 0x0000
931 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
932 /* Ignore block loads from the stack, potentially copying
933 parameters from memory. */
936 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
938 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
939 /* Similarly ignore dual loads from the stack. */
942 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
943 && (inst2
& 0x0d00) == 0x0c00
944 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
945 /* Similarly ignore single loads from the stack. */
948 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
949 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
950 /* Similarly ignore single loads from the stack. */
953 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
954 && (inst2
& 0x8000) == 0x0000)
956 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
957 | (bits (inst2
, 12, 14) << 8)
958 | bits (inst2
, 0, 7));
960 regs
[bits (inst2
, 8, 11)]
961 = pv_add_constant (regs
[bits (insn
, 0, 3)],
962 thumb_expand_immediate (imm
));
965 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
966 && (inst2
& 0x8000) == 0x0000)
968 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
969 | (bits (inst2
, 12, 14) << 8)
970 | bits (inst2
, 0, 7));
972 regs
[bits (inst2
, 8, 11)]
973 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
976 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
977 && (inst2
& 0x8000) == 0x0000)
979 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
980 | (bits (inst2
, 12, 14) << 8)
981 | bits (inst2
, 0, 7));
983 regs
[bits (inst2
, 8, 11)]
984 = pv_add_constant (regs
[bits (insn
, 0, 3)],
985 - (CORE_ADDR
) thumb_expand_immediate (imm
));
988 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
989 && (inst2
& 0x8000) == 0x0000)
991 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
992 | (bits (inst2
, 12, 14) << 8)
993 | bits (inst2
, 0, 7));
995 regs
[bits (inst2
, 8, 11)]
996 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
999 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1001 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1002 | (bits (inst2
, 12, 14) << 8)
1003 | bits (inst2
, 0, 7));
1005 regs
[bits (inst2
, 8, 11)]
1006 = pv_constant (thumb_expand_immediate (imm
));
1009 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1012 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1014 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1017 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1018 && (inst2
& 0xf0f0) == 0)
1020 int dst_reg
= (inst2
& 0x0f00) >> 8;
1021 int src_reg
= inst2
& 0xf;
1022 regs
[dst_reg
] = regs
[src_reg
];
1025 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1027 /* Constant pool loads. */
1028 unsigned int constant
;
1031 offset
= bits (inst2
, 0, 11);
1033 loc
= start
+ 4 + offset
;
1035 loc
= start
+ 4 - offset
;
1037 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1038 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1041 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1043 /* Constant pool loads. */
1044 unsigned int constant
;
1047 offset
= bits (inst2
, 0, 7) << 2;
1049 loc
= start
+ 4 + offset
;
1051 loc
= start
+ 4 - offset
;
1053 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1054 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1056 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1057 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1060 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1062 /* Don't scan past anything that might change control flow. */
1067 /* The optimizer might shove anything into the prologue,
1068 so we just skip what we don't recognize. */
1069 unrecognized_pc
= start
;
1074 else if (thumb_instruction_changes_pc (insn
))
1076 /* Don't scan past anything that might change control flow. */
1081 /* The optimizer might shove anything into the prologue,
1082 so we just skip what we don't recognize. */
1083 unrecognized_pc
= start
;
1090 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1091 paddress (gdbarch
, start
));
1093 if (unrecognized_pc
== 0)
1094 unrecognized_pc
= start
;
1098 do_cleanups (back_to
);
1099 return unrecognized_pc
;
1102 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1104 /* Frame pointer is fp. Frame size is constant. */
1105 cache
->framereg
= ARM_FP_REGNUM
;
1106 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1108 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1110 /* Frame pointer is r7. Frame size is constant. */
1111 cache
->framereg
= THUMB_FP_REGNUM
;
1112 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1116 /* Try the stack pointer... this is a bit desperate. */
1117 cache
->framereg
= ARM_SP_REGNUM
;
1118 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1121 for (i
= 0; i
< 16; i
++)
1122 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1123 cache
->saved_regs
[i
].addr
= offset
;
1125 do_cleanups (back_to
);
1126 return unrecognized_pc
;
1130 /* Try to analyze the instructions starting from PC, which load symbol
1131 __stack_chk_guard. Return the address of instruction after loading this
1132 symbol, set the dest register number to *BASEREG, and set the size of
1133 instructions for loading symbol in OFFSET. Return 0 if instructions are
1137 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1138 unsigned int *destreg
, int *offset
)
1140 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1141 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1142 unsigned int low
, high
, address
;
1147 unsigned short insn1
1148 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1150 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1152 *destreg
= bits (insn1
, 8, 10);
1154 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1155 address
= read_memory_unsigned_integer (address
, 4,
1156 byte_order_for_code
);
1158 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1160 unsigned short insn2
1161 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1163 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1166 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1168 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1170 /* movt Rd, #const */
1171 if ((insn1
& 0xfbc0) == 0xf2c0)
1173 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1174 *destreg
= bits (insn2
, 8, 11);
1176 address
= (high
<< 16 | low
);
1183 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1185 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1187 address
= bits (insn
, 0, 11) + pc
+ 8;
1188 address
= read_memory_unsigned_integer (address
, 4,
1189 byte_order_for_code
);
1191 *destreg
= bits (insn
, 12, 15);
1194 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1196 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1199 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1201 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1203 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1204 *destreg
= bits (insn
, 12, 15);
1206 address
= (high
<< 16 | low
);
1214 /* Try to skip a sequence of instructions used for stack protector. If PC
1215 points to the first instruction of this sequence, return the address of
1216 first instruction after this sequence, otherwise, return original PC.
1218 On arm, this sequence of instructions is composed of mainly three steps,
1219 Step 1: load symbol __stack_chk_guard,
1220 Step 2: load from address of __stack_chk_guard,
1221 Step 3: store it to somewhere else.
1223 Usually, instructions on step 2 and step 3 are the same on various ARM
1224 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1225 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1226 instructions in step 1 vary from different ARM architectures. On ARMv7,
1229 movw Rn, #:lower16:__stack_chk_guard
1230 movt Rn, #:upper16:__stack_chk_guard
1237 .word __stack_chk_guard
1239 Since ldr/str is a very popular instruction, we can't use them as
1240 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1241 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1242 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1245 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1247 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1248 unsigned int basereg
;
1249 struct bound_minimal_symbol stack_chk_guard
;
1251 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1254 /* Try to parse the instructions in Step 1. */
1255 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1260 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1261 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1262 Otherwise, this sequence cannot be for stack protector. */
1263 if (stack_chk_guard
.minsym
== NULL
1264 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1269 unsigned int destreg
;
1271 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1273 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1274 if ((insn
& 0xf800) != 0x6800)
1276 if (bits (insn
, 3, 5) != basereg
)
1278 destreg
= bits (insn
, 0, 2);
1280 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1281 byte_order_for_code
);
1282 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1283 if ((insn
& 0xf800) != 0x6000)
1285 if (destreg
!= bits (insn
, 0, 2))
1290 unsigned int destreg
;
1292 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1294 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1295 if ((insn
& 0x0e500000) != 0x04100000)
1297 if (bits (insn
, 16, 19) != basereg
)
1299 destreg
= bits (insn
, 12, 15);
1300 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1301 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1302 4, byte_order_for_code
);
1303 if ((insn
& 0x0e500000) != 0x04000000)
1305 if (bits (insn
, 12, 15) != destreg
)
1308 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1311 return pc
+ offset
+ 4;
1313 return pc
+ offset
+ 8;
1316 /* Advance the PC across any function entry prologue instructions to
1317 reach some "real" code.
1319 The APCS (ARM Procedure Call Standard) defines the following
1323 [stmfd sp!, {a1,a2,a3,a4}]
1324 stmfd sp!, {...,fp,ip,lr,pc}
1325 [stfe f7, [sp, #-12]!]
1326 [stfe f6, [sp, #-12]!]
1327 [stfe f5, [sp, #-12]!]
1328 [stfe f4, [sp, #-12]!]
1329 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1332 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1334 CORE_ADDR func_addr
, limit_pc
;
1336 /* See if we can determine the end of the prologue via the symbol table.
1337 If so, then return either PC, or the PC after the prologue, whichever
1339 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1341 CORE_ADDR post_prologue_pc
1342 = skip_prologue_using_sal (gdbarch
, func_addr
);
1343 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1345 if (post_prologue_pc
)
1347 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1350 /* GCC always emits a line note before the prologue and another
1351 one after, even if the two are at the same address or on the
1352 same line. Take advantage of this so that we do not need to
1353 know every instruction that might appear in the prologue. We
1354 will have producer information for most binaries; if it is
1355 missing (e.g. for -gstabs), assuming the GNU tools. */
1356 if (post_prologue_pc
1358 || COMPUNIT_PRODUCER (cust
) == NULL
1359 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1360 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1361 return post_prologue_pc
;
1363 if (post_prologue_pc
!= 0)
1365 CORE_ADDR analyzed_limit
;
1367 /* For non-GCC compilers, make sure the entire line is an
1368 acceptable prologue; GDB will round this function's
1369 return value up to the end of the following line so we
1370 can not skip just part of a line (and we do not want to).
1372 RealView does not treat the prologue specially, but does
1373 associate prologue code with the opening brace; so this
1374 lets us skip the first line if we think it is the opening
1376 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1377 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1378 post_prologue_pc
, NULL
);
1380 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1381 post_prologue_pc
, NULL
);
1383 if (analyzed_limit
!= post_prologue_pc
)
1386 return post_prologue_pc
;
1390 /* Can't determine prologue from the symbol table, need to examine
1393 /* Find an upper limit on the function prologue using the debug
1394 information. If the debug information could not be used to provide
1395 that bound, then use an arbitrary large number as the upper bound. */
1396 /* Like arm_scan_prologue, stop no later than pc + 64. */
1397 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1399 limit_pc
= pc
+ 64; /* Magic. */
1402 /* Check if this is Thumb code. */
1403 if (arm_pc_is_thumb (gdbarch
, pc
))
1404 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1406 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1410 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1411 This function decodes a Thumb function prologue to determine:
1412 1) the size of the stack frame
1413 2) which registers are saved on it
1414 3) the offsets of saved regs
1415 4) the offset from the stack pointer to the frame pointer
1417 A typical Thumb function prologue would create this stack frame
1418 (offsets relative to FP)
1419 old SP -> 24 stack parameters
1422 R7 -> 0 local variables (16 bytes)
1423 SP -> -12 additional stack space (12 bytes)
1424 The frame size would thus be 36 bytes, and the frame offset would be
1425 12 bytes. The frame register is R7.
1427 The comments for thumb_skip_prolog() describe the algorithm we use
1428 to detect the end of the prolog. */
1432 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1433 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1435 CORE_ADDR prologue_start
;
1436 CORE_ADDR prologue_end
;
1438 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1441 /* See comment in arm_scan_prologue for an explanation of
1443 if (prologue_end
> prologue_start
+ 64)
1445 prologue_end
= prologue_start
+ 64;
1449 /* We're in the boondocks: we have no idea where the start of the
1453 prologue_end
= std::min (prologue_end
, prev_pc
);
1455 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1458 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1462 arm_instruction_restores_sp (unsigned int insn
)
1464 if (bits (insn
, 28, 31) != INST_NV
)
1466 if ((insn
& 0x0df0f000) == 0x0080d000
1467 /* ADD SP (register or immediate). */
1468 || (insn
& 0x0df0f000) == 0x0040d000
1469 /* SUB SP (register or immediate). */
1470 || (insn
& 0x0ffffff0) == 0x01a0d000
1472 || (insn
& 0x0fff0000) == 0x08bd0000
1474 || (insn
& 0x0fff0000) == 0x049d0000)
1475 /* POP of a single register. */
1482 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1483 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1484 fill it in. Return the first address not recognized as a prologue
1487 We recognize all the instructions typically found in ARM prologues,
1488 plus harmless instructions which can be skipped (either for analysis
1489 purposes, or a more restrictive set that can be skipped when finding
1490 the end of the prologue). */
1493 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1494 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1495 struct arm_prologue_cache
*cache
)
1497 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1499 CORE_ADDR offset
, current_pc
;
1500 pv_t regs
[ARM_FPS_REGNUM
];
1501 struct pv_area
*stack
;
1502 struct cleanup
*back_to
;
1503 CORE_ADDR unrecognized_pc
= 0;
1505 /* Search the prologue looking for instructions that set up the
1506 frame pointer, adjust the stack pointer, and save registers.
1508 Be careful, however, and if it doesn't look like a prologue,
1509 don't try to scan it. If, for instance, a frameless function
1510 begins with stmfd sp!, then we will tell ourselves there is
1511 a frame, which will confuse stack traceback, as well as "finish"
1512 and other operations that rely on a knowledge of the stack
1515 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1516 regs
[regno
] = pv_register (regno
, 0);
1517 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1518 back_to
= make_cleanup_free_pv_area (stack
);
1520 for (current_pc
= prologue_start
;
1521 current_pc
< prologue_end
;
1525 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1527 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1529 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1532 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1533 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1535 unsigned imm
= insn
& 0xff; /* immediate value */
1536 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1537 int rd
= bits (insn
, 12, 15);
1538 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1539 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1542 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1543 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1545 unsigned imm
= insn
& 0xff; /* immediate value */
1546 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1547 int rd
= bits (insn
, 12, 15);
1548 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1549 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1552 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1555 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1557 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1558 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1559 regs
[bits (insn
, 12, 15)]);
1562 else if ((insn
& 0xffff0000) == 0xe92d0000)
1563 /* stmfd sp!, {..., fp, ip, lr, pc}
1565 stmfd sp!, {a1, a2, a3, a4} */
1567 int mask
= insn
& 0xffff;
1569 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1572 /* Calculate offsets of saved registers. */
1573 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1574 if (mask
& (1 << regno
))
1577 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1578 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1581 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1582 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1583 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1585 /* No need to add this to saved_regs -- it's just an arg reg. */
1588 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1589 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1590 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1592 /* No need to add this to saved_regs -- it's just an arg reg. */
1595 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1597 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1599 /* No need to add this to saved_regs -- it's just arg regs. */
1602 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1604 unsigned imm
= insn
& 0xff; /* immediate value */
1605 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1606 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1607 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1609 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1611 unsigned imm
= insn
& 0xff; /* immediate value */
1612 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1613 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1614 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1616 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1618 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1620 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1623 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1624 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1625 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1627 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1629 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1631 int n_saved_fp_regs
;
1632 unsigned int fp_start_reg
, fp_bound_reg
;
1634 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1637 if ((insn
& 0x800) == 0x800) /* N0 is set */
1639 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1640 n_saved_fp_regs
= 3;
1642 n_saved_fp_regs
= 1;
1646 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1647 n_saved_fp_regs
= 2;
1649 n_saved_fp_regs
= 4;
1652 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1653 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1654 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1656 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1657 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1658 regs
[fp_start_reg
++]);
1661 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1663 /* Allow some special function calls when skipping the
1664 prologue; GCC generates these before storing arguments to
1666 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1668 if (skip_prologue_function (gdbarch
, dest
, 0))
1673 else if ((insn
& 0xf0000000) != 0xe0000000)
1674 break; /* Condition not true, exit early. */
1675 else if (arm_instruction_changes_pc (insn
))
1676 /* Don't scan past anything that might change control flow. */
1678 else if (arm_instruction_restores_sp (insn
))
1680 /* Don't scan past the epilogue. */
1683 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1684 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1685 /* Ignore block loads from the stack, potentially copying
1686 parameters from memory. */
1688 else if ((insn
& 0xfc500000) == 0xe4100000
1689 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1690 /* Similarly ignore single loads from the stack. */
1692 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1693 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1694 register instead of the stack. */
1698 /* The optimizer might shove anything into the prologue, if
1699 we build up cache (cache != NULL) from scanning prologue,
1700 we just skip what we don't recognize and scan further to
1701 make cache as complete as possible. However, if we skip
1702 prologue, we'll stop immediately on unrecognized
1704 unrecognized_pc
= current_pc
;
1712 if (unrecognized_pc
== 0)
1713 unrecognized_pc
= current_pc
;
1717 int framereg
, framesize
;
1719 /* The frame size is just the distance from the frame register
1720 to the original stack pointer. */
1721 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1723 /* Frame pointer is fp. */
1724 framereg
= ARM_FP_REGNUM
;
1725 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1729 /* Try the stack pointer... this is a bit desperate. */
1730 framereg
= ARM_SP_REGNUM
;
1731 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1734 cache
->framereg
= framereg
;
1735 cache
->framesize
= framesize
;
1737 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1738 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1739 cache
->saved_regs
[regno
].addr
= offset
;
1743 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1744 paddress (gdbarch
, unrecognized_pc
));
1746 do_cleanups (back_to
);
1747 return unrecognized_pc
;
1751 arm_scan_prologue (struct frame_info
*this_frame
,
1752 struct arm_prologue_cache
*cache
)
1754 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1755 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1756 CORE_ADDR prologue_start
, prologue_end
;
1757 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1758 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1760 /* Assume there is no frame until proven otherwise. */
1761 cache
->framereg
= ARM_SP_REGNUM
;
1762 cache
->framesize
= 0;
1764 /* Check for Thumb prologue. */
1765 if (arm_frame_is_thumb (this_frame
))
1767 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1771 /* Find the function prologue. If we can't find the function in
1772 the symbol table, peek in the stack frame to find the PC. */
1773 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1776 /* One way to find the end of the prologue (which works well
1777 for unoptimized code) is to do the following:
1779 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1782 prologue_end = prev_pc;
1783 else if (sal.end < prologue_end)
1784 prologue_end = sal.end;
1786 This mechanism is very accurate so long as the optimizer
1787 doesn't move any instructions from the function body into the
1788 prologue. If this happens, sal.end will be the last
1789 instruction in the first hunk of prologue code just before
1790 the first instruction that the scheduler has moved from
1791 the body to the prologue.
1793 In order to make sure that we scan all of the prologue
1794 instructions, we use a slightly less accurate mechanism which
1795 may scan more than necessary. To help compensate for this
1796 lack of accuracy, the prologue scanning loop below contains
1797 several clauses which'll cause the loop to terminate early if
1798 an implausible prologue instruction is encountered.
1804 is a suitable endpoint since it accounts for the largest
1805 possible prologue plus up to five instructions inserted by
1808 if (prologue_end
> prologue_start
+ 64)
1810 prologue_end
= prologue_start
+ 64; /* See above. */
1815 /* We have no symbol information. Our only option is to assume this
1816 function has a standard stack frame and the normal frame register.
1817 Then, we can find the value of our frame pointer on entrance to
1818 the callee (or at the present moment if this is the innermost frame).
1819 The value stored there should be the address of the stmfd + 8. */
1820 CORE_ADDR frame_loc
;
1821 LONGEST return_value
;
1823 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1824 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1828 prologue_start
= gdbarch_addr_bits_remove
1829 (gdbarch
, return_value
) - 8;
1830 prologue_end
= prologue_start
+ 64; /* See above. */
1834 if (prev_pc
< prologue_end
)
1835 prologue_end
= prev_pc
;
1837 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1840 static struct arm_prologue_cache
*
1841 arm_make_prologue_cache (struct frame_info
*this_frame
)
1844 struct arm_prologue_cache
*cache
;
1845 CORE_ADDR unwound_fp
;
1847 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1848 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1850 arm_scan_prologue (this_frame
, cache
);
1852 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1853 if (unwound_fp
== 0)
1856 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1858 /* Calculate actual addresses of saved registers using offsets
1859 determined by arm_scan_prologue. */
1860 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1861 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1862 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1867 /* Implementation of the stop_reason hook for arm_prologue frames. */
1869 static enum unwind_stop_reason
1870 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1873 struct arm_prologue_cache
*cache
;
1876 if (*this_cache
== NULL
)
1877 *this_cache
= arm_make_prologue_cache (this_frame
);
1878 cache
= (struct arm_prologue_cache
*) *this_cache
;
1880 /* This is meant to halt the backtrace at "_start". */
1881 pc
= get_frame_pc (this_frame
);
1882 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1883 return UNWIND_OUTERMOST
;
1885 /* If we've hit a wall, stop. */
1886 if (cache
->prev_sp
== 0)
1887 return UNWIND_OUTERMOST
;
1889 return UNWIND_NO_REASON
;
1892 /* Our frame ID for a normal frame is the current function's starting PC
1893 and the caller's SP when we were called. */
1896 arm_prologue_this_id (struct frame_info
*this_frame
,
1898 struct frame_id
*this_id
)
1900 struct arm_prologue_cache
*cache
;
1904 if (*this_cache
== NULL
)
1905 *this_cache
= arm_make_prologue_cache (this_frame
);
1906 cache
= (struct arm_prologue_cache
*) *this_cache
;
1908 /* Use function start address as part of the frame ID. If we cannot
1909 identify the start address (due to missing symbol information),
1910 fall back to just using the current PC. */
1911 pc
= get_frame_pc (this_frame
);
1912 func
= get_frame_func (this_frame
);
1916 id
= frame_id_build (cache
->prev_sp
, func
);
1920 static struct value
*
1921 arm_prologue_prev_register (struct frame_info
*this_frame
,
1925 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1926 struct arm_prologue_cache
*cache
;
1928 if (*this_cache
== NULL
)
1929 *this_cache
= arm_make_prologue_cache (this_frame
);
1930 cache
= (struct arm_prologue_cache
*) *this_cache
;
1932 /* If we are asked to unwind the PC, then we need to return the LR
1933 instead. The prologue may save PC, but it will point into this
1934 frame's prologue, not the next frame's resume location. Also
1935 strip the saved T bit. A valid LR may have the low bit set, but
1936 a valid PC never does. */
1937 if (prev_regnum
== ARM_PC_REGNUM
)
1941 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1942 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1943 arm_addr_bits_remove (gdbarch
, lr
));
1946 /* SP is generally not saved to the stack, but this frame is
1947 identified by the next frame's stack pointer at the time of the call.
1948 The value was already reconstructed into PREV_SP. */
1949 if (prev_regnum
== ARM_SP_REGNUM
)
1950 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1952 /* The CPSR may have been changed by the call instruction and by the
1953 called function. The only bit we can reconstruct is the T bit,
1954 by checking the low bit of LR as of the call. This is a reliable
1955 indicator of Thumb-ness except for some ARM v4T pre-interworking
1956 Thumb code, which could get away with a clear low bit as long as
1957 the called function did not use bx. Guess that all other
1958 bits are unchanged; the condition flags are presumably lost,
1959 but the processor status is likely valid. */
1960 if (prev_regnum
== ARM_PS_REGNUM
)
1963 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1965 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1966 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1967 if (IS_THUMB_ADDR (lr
))
1971 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1974 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1978 struct frame_unwind arm_prologue_unwind
= {
1980 arm_prologue_unwind_stop_reason
,
1981 arm_prologue_this_id
,
1982 arm_prologue_prev_register
,
1984 default_frame_sniffer
1987 /* Maintain a list of ARM exception table entries per objfile, similar to the
1988 list of mapping symbols. We only cache entries for standard ARM-defined
1989 personality routines; the cache will contain only the frame unwinding
1990 instructions associated with the entry (not the descriptors). */
1992 static const struct objfile_data
*arm_exidx_data_key
;
1994 struct arm_exidx_entry
1999 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2000 DEF_VEC_O(arm_exidx_entry_s
);
2002 struct arm_exidx_data
2004 VEC(arm_exidx_entry_s
) **section_maps
;
2008 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2010 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2013 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2014 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2018 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2019 const struct arm_exidx_entry
*rhs
)
2021 return lhs
->addr
< rhs
->addr
;
2024 static struct obj_section
*
2025 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2027 struct obj_section
*osect
;
2029 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2030 if (bfd_get_section_flags (objfile
->obfd
,
2031 osect
->the_bfd_section
) & SEC_ALLOC
)
2033 bfd_vma start
, size
;
2034 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2035 size
= bfd_get_section_size (osect
->the_bfd_section
);
2037 if (start
<= vma
&& vma
< start
+ size
)
2044 /* Parse contents of exception table and exception index sections
2045 of OBJFILE, and fill in the exception table entry cache.
2047 For each entry that refers to a standard ARM-defined personality
2048 routine, extract the frame unwinding instructions (from either
2049 the index or the table section). The unwinding instructions
2051 - extracting them from the rest of the table data
2052 - converting to host endianness
2053 - appending the implicit 0xb0 ("Finish") code
2055 The extracted and normalized instructions are stored for later
2056 retrieval by the arm_find_exidx_entry routine. */
2059 arm_exidx_new_objfile (struct objfile
*objfile
)
2061 struct cleanup
*cleanups
;
2062 struct arm_exidx_data
*data
;
2063 asection
*exidx
, *extab
;
2064 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2065 bfd_size_type exidx_size
= 0, extab_size
= 0;
2066 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2069 /* If we've already touched this file, do nothing. */
2070 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2072 cleanups
= make_cleanup (null_cleanup
, NULL
);
2074 /* Read contents of exception table and index. */
2075 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2078 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2079 exidx_size
= bfd_get_section_size (exidx
);
2080 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2081 make_cleanup (xfree
, exidx_data
);
2083 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2084 exidx_data
, 0, exidx_size
))
2086 do_cleanups (cleanups
);
2091 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2094 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2095 extab_size
= bfd_get_section_size (extab
);
2096 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2097 make_cleanup (xfree
, extab_data
);
2099 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2100 extab_data
, 0, extab_size
))
2102 do_cleanups (cleanups
);
2107 /* Allocate exception table data structure. */
2108 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2109 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2110 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2111 objfile
->obfd
->section_count
,
2112 VEC(arm_exidx_entry_s
) *);
2114 /* Fill in exception table. */
2115 for (i
= 0; i
< exidx_size
/ 8; i
++)
2117 struct arm_exidx_entry new_exidx_entry
;
2118 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2119 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2120 bfd_vma addr
= 0, word
= 0;
2121 int n_bytes
= 0, n_words
= 0;
2122 struct obj_section
*sec
;
2123 gdb_byte
*entry
= NULL
;
2125 /* Extract address of start of function. */
2126 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2127 idx
+= exidx_vma
+ i
* 8;
2129 /* Find section containing function and compute section offset. */
2130 sec
= arm_obj_section_from_vma (objfile
, idx
);
2133 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2135 /* Determine address of exception table entry. */
2138 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2140 else if ((val
& 0xff000000) == 0x80000000)
2142 /* Exception table entry embedded in .ARM.exidx
2143 -- must be short form. */
2147 else if (!(val
& 0x80000000))
2149 /* Exception table entry in .ARM.extab. */
2150 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2151 addr
+= exidx_vma
+ i
* 8 + 4;
2153 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2155 word
= bfd_h_get_32 (objfile
->obfd
,
2156 extab_data
+ addr
- extab_vma
);
2159 if ((word
& 0xff000000) == 0x80000000)
2164 else if ((word
& 0xff000000) == 0x81000000
2165 || (word
& 0xff000000) == 0x82000000)
2169 n_words
= ((word
>> 16) & 0xff);
2171 else if (!(word
& 0x80000000))
2174 struct obj_section
*pers_sec
;
2175 int gnu_personality
= 0;
2177 /* Custom personality routine. */
2178 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2179 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2181 /* Check whether we've got one of the variants of the
2182 GNU personality routines. */
2183 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2186 static const char *personality
[] =
2188 "__gcc_personality_v0",
2189 "__gxx_personality_v0",
2190 "__gcj_personality_v0",
2191 "__gnu_objc_personality_v0",
2195 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2198 for (k
= 0; personality
[k
]; k
++)
2199 if (lookup_minimal_symbol_by_pc_name
2200 (pc
, personality
[k
], objfile
))
2202 gnu_personality
= 1;
2207 /* If so, the next word contains a word count in the high
2208 byte, followed by the same unwind instructions as the
2209 pre-defined forms. */
2211 && addr
+ 4 <= extab_vma
+ extab_size
)
2213 word
= bfd_h_get_32 (objfile
->obfd
,
2214 extab_data
+ addr
- extab_vma
);
2217 n_words
= ((word
>> 24) & 0xff);
2223 /* Sanity check address. */
2225 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2226 n_words
= n_bytes
= 0;
2228 /* The unwind instructions reside in WORD (only the N_BYTES least
2229 significant bytes are valid), followed by N_WORDS words in the
2230 extab section starting at ADDR. */
2231 if (n_bytes
|| n_words
)
2234 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2235 n_bytes
+ n_words
* 4 + 1);
2238 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2242 word
= bfd_h_get_32 (objfile
->obfd
,
2243 extab_data
+ addr
- extab_vma
);
2246 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2247 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2248 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2249 *p
++ = (gdb_byte
) (word
& 0xff);
2252 /* Implied "Finish" to terminate the list. */
2256 /* Push entry onto vector. They are guaranteed to always
2257 appear in order of increasing addresses. */
2258 new_exidx_entry
.addr
= idx
;
2259 new_exidx_entry
.entry
= entry
;
2260 VEC_safe_push (arm_exidx_entry_s
,
2261 data
->section_maps
[sec
->the_bfd_section
->index
],
2265 do_cleanups (cleanups
);
2268 /* Search for the exception table entry covering MEMADDR. If one is found,
2269 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2270 set *START to the start of the region covered by this entry. */
2273 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2275 struct obj_section
*sec
;
2277 sec
= find_pc_section (memaddr
);
2280 struct arm_exidx_data
*data
;
2281 VEC(arm_exidx_entry_s
) *map
;
2282 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2285 data
= ((struct arm_exidx_data
*)
2286 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2289 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2290 if (!VEC_empty (arm_exidx_entry_s
, map
))
2292 struct arm_exidx_entry
*map_sym
;
2294 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2295 arm_compare_exidx_entries
);
2297 /* VEC_lower_bound finds the earliest ordered insertion
2298 point. If the following symbol starts at this exact
2299 address, we use that; otherwise, the preceding
2300 exception table entry covers this address. */
2301 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2303 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2304 if (map_sym
->addr
== map_key
.addr
)
2307 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2308 return map_sym
->entry
;
2314 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2316 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2317 return map_sym
->entry
;
2326 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2327 instruction list from the ARM exception table entry ENTRY, allocate and
2328 return a prologue cache structure describing how to unwind this frame.
2330 Return NULL if the unwinding instruction list contains a "spare",
2331 "reserved" or "refuse to unwind" instruction as defined in section
2332 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2333 for the ARM Architecture" document. */
2335 static struct arm_prologue_cache
*
2336 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2341 struct arm_prologue_cache
*cache
;
2342 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2343 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2349 /* Whenever we reload SP, we actually have to retrieve its
2350 actual value in the current frame. */
2353 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2355 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2356 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2360 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2361 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2367 /* Decode next unwind instruction. */
2370 if ((insn
& 0xc0) == 0)
2372 int offset
= insn
& 0x3f;
2373 vsp
+= (offset
<< 2) + 4;
2375 else if ((insn
& 0xc0) == 0x40)
2377 int offset
= insn
& 0x3f;
2378 vsp
-= (offset
<< 2) + 4;
2380 else if ((insn
& 0xf0) == 0x80)
2382 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2385 /* The special case of an all-zero mask identifies
2386 "Refuse to unwind". We return NULL to fall back
2387 to the prologue analyzer. */
2391 /* Pop registers r4..r15 under mask. */
2392 for (i
= 0; i
< 12; i
++)
2393 if (mask
& (1 << i
))
2395 cache
->saved_regs
[4 + i
].addr
= vsp
;
2399 /* Special-case popping SP -- we need to reload vsp. */
2400 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2403 else if ((insn
& 0xf0) == 0x90)
2405 int reg
= insn
& 0xf;
2407 /* Reserved cases. */
2408 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2411 /* Set SP from another register and mark VSP for reload. */
2412 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2415 else if ((insn
& 0xf0) == 0xa0)
2417 int count
= insn
& 0x7;
2418 int pop_lr
= (insn
& 0x8) != 0;
2421 /* Pop r4..r[4+count]. */
2422 for (i
= 0; i
<= count
; i
++)
2424 cache
->saved_regs
[4 + i
].addr
= vsp
;
2428 /* If indicated by flag, pop LR as well. */
2431 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2435 else if (insn
== 0xb0)
2437 /* We could only have updated PC by popping into it; if so, it
2438 will show up as address. Otherwise, copy LR into PC. */
2439 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2440 cache
->saved_regs
[ARM_PC_REGNUM
]
2441 = cache
->saved_regs
[ARM_LR_REGNUM
];
2446 else if (insn
== 0xb1)
2448 int mask
= *entry
++;
2451 /* All-zero mask and mask >= 16 is "spare". */
2452 if (mask
== 0 || mask
>= 16)
2455 /* Pop r0..r3 under mask. */
2456 for (i
= 0; i
< 4; i
++)
2457 if (mask
& (1 << i
))
2459 cache
->saved_regs
[i
].addr
= vsp
;
2463 else if (insn
== 0xb2)
2465 ULONGEST offset
= 0;
2470 offset
|= (*entry
& 0x7f) << shift
;
2473 while (*entry
++ & 0x80);
2475 vsp
+= 0x204 + (offset
<< 2);
2477 else if (insn
== 0xb3)
2479 int start
= *entry
>> 4;
2480 int count
= (*entry
++) & 0xf;
2483 /* Only registers D0..D15 are valid here. */
2484 if (start
+ count
>= 16)
2487 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2488 for (i
= 0; i
<= count
; i
++)
2490 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2494 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2497 else if ((insn
& 0xf8) == 0xb8)
2499 int count
= insn
& 0x7;
2502 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2503 for (i
= 0; i
<= count
; i
++)
2505 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2509 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2512 else if (insn
== 0xc6)
2514 int start
= *entry
>> 4;
2515 int count
= (*entry
++) & 0xf;
2518 /* Only registers WR0..WR15 are valid. */
2519 if (start
+ count
>= 16)
2522 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2523 for (i
= 0; i
<= count
; i
++)
2525 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2529 else if (insn
== 0xc7)
2531 int mask
= *entry
++;
2534 /* All-zero mask and mask >= 16 is "spare". */
2535 if (mask
== 0 || mask
>= 16)
2538 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2539 for (i
= 0; i
< 4; i
++)
2540 if (mask
& (1 << i
))
2542 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2546 else if ((insn
& 0xf8) == 0xc0)
2548 int count
= insn
& 0x7;
2551 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2552 for (i
= 0; i
<= count
; i
++)
2554 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2558 else if (insn
== 0xc8)
2560 int start
= *entry
>> 4;
2561 int count
= (*entry
++) & 0xf;
2564 /* Only registers D0..D31 are valid. */
2565 if (start
+ count
>= 16)
2568 /* Pop VFP double-precision registers
2569 D[16+start]..D[16+start+count]. */
2570 for (i
= 0; i
<= count
; i
++)
2572 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2576 else if (insn
== 0xc9)
2578 int start
= *entry
>> 4;
2579 int count
= (*entry
++) & 0xf;
2582 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2583 for (i
= 0; i
<= count
; i
++)
2585 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2589 else if ((insn
& 0xf8) == 0xd0)
2591 int count
= insn
& 0x7;
2594 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2595 for (i
= 0; i
<= count
; i
++)
2597 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2603 /* Everything else is "spare". */
2608 /* If we restore SP from a register, assume this was the frame register.
2609 Otherwise just fall back to SP as frame register. */
2610 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2611 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2613 cache
->framereg
= ARM_SP_REGNUM
;
2615 /* Determine offset to previous frame. */
2617 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2619 /* We already got the previous SP. */
2620 cache
->prev_sp
= vsp
;
2625 /* Unwinding via ARM exception table entries. Note that the sniffer
2626 already computes a filled-in prologue cache, which is then used
2627 with the same arm_prologue_this_id and arm_prologue_prev_register
2628 routines also used for prologue-parsing based unwinding. */
2631 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2632 struct frame_info
*this_frame
,
2633 void **this_prologue_cache
)
2635 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2636 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2637 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2638 struct arm_prologue_cache
*cache
;
2641 /* See if we have an ARM exception table entry covering this address. */
2642 addr_in_block
= get_frame_address_in_block (this_frame
);
2643 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2647 /* The ARM exception table does not describe unwind information
2648 for arbitrary PC values, but is guaranteed to be correct only
2649 at call sites. We have to decide here whether we want to use
2650 ARM exception table information for this frame, or fall back
2651 to using prologue parsing. (Note that if we have DWARF CFI,
2652 this sniffer isn't even called -- CFI is always preferred.)
2654 Before we make this decision, however, we check whether we
2655 actually have *symbol* information for the current frame.
2656 If not, prologue parsing would not work anyway, so we might
2657 as well use the exception table and hope for the best. */
2658 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2662 /* If the next frame is "normal", we are at a call site in this
2663 frame, so exception information is guaranteed to be valid. */
2664 if (get_next_frame (this_frame
)
2665 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2668 /* We also assume exception information is valid if we're currently
2669 blocked in a system call. The system library is supposed to
2670 ensure this, so that e.g. pthread cancellation works. */
2671 if (arm_frame_is_thumb (this_frame
))
2675 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2676 byte_order_for_code
, &insn
)
2677 && (insn
& 0xff00) == 0xdf00 /* svc */)
2684 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2685 byte_order_for_code
, &insn
)
2686 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2690 /* Bail out if we don't know that exception information is valid. */
2694 /* The ARM exception index does not mark the *end* of the region
2695 covered by the entry, and some functions will not have any entry.
2696 To correctly recognize the end of the covered region, the linker
2697 should have inserted dummy records with a CANTUNWIND marker.
2699 Unfortunately, current versions of GNU ld do not reliably do
2700 this, and thus we may have found an incorrect entry above.
2701 As a (temporary) sanity check, we only use the entry if it
2702 lies *within* the bounds of the function. Note that this check
2703 might reject perfectly valid entries that just happen to cover
2704 multiple functions; therefore this check ought to be removed
2705 once the linker is fixed. */
2706 if (func_start
> exidx_region
)
2710 /* Decode the list of unwinding instructions into a prologue cache.
2711 Note that this may fail due to e.g. a "refuse to unwind" code. */
2712 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2716 *this_prologue_cache
= cache
;
2720 struct frame_unwind arm_exidx_unwind
= {
2722 default_frame_unwind_stop_reason
,
2723 arm_prologue_this_id
,
2724 arm_prologue_prev_register
,
2726 arm_exidx_unwind_sniffer
2729 static struct arm_prologue_cache
*
2730 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2732 struct arm_prologue_cache
*cache
;
2735 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2736 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2738 /* Still rely on the offset calculated from prologue. */
2739 arm_scan_prologue (this_frame
, cache
);
2741 /* Since we are in epilogue, the SP has been restored. */
2742 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2744 /* Calculate actual addresses of saved registers using offsets
2745 determined by arm_scan_prologue. */
2746 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2747 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2748 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2753 /* Implementation of function hook 'this_id' in
2754 'struct frame_uwnind' for epilogue unwinder. */
2757 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2759 struct frame_id
*this_id
)
2761 struct arm_prologue_cache
*cache
;
2764 if (*this_cache
== NULL
)
2765 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2766 cache
= (struct arm_prologue_cache
*) *this_cache
;
2768 /* Use function start address as part of the frame ID. If we cannot
2769 identify the start address (due to missing symbol information),
2770 fall back to just using the current PC. */
2771 pc
= get_frame_pc (this_frame
);
2772 func
= get_frame_func (this_frame
);
2776 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2779 /* Implementation of function hook 'prev_register' in
2780 'struct frame_uwnind' for epilogue unwinder. */
2782 static struct value
*
2783 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2784 void **this_cache
, int regnum
)
2786 if (*this_cache
== NULL
)
2787 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2789 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2792 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2794 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2797 /* Implementation of function hook 'sniffer' in
2798 'struct frame_uwnind' for epilogue unwinder. */
2801 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2802 struct frame_info
*this_frame
,
2803 void **this_prologue_cache
)
2805 if (frame_relative_level (this_frame
) == 0)
2807 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2808 CORE_ADDR pc
= get_frame_pc (this_frame
);
2810 if (arm_frame_is_thumb (this_frame
))
2811 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2813 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2819 /* Frame unwinder from epilogue. */
2821 static const struct frame_unwind arm_epilogue_frame_unwind
=
2824 default_frame_unwind_stop_reason
,
2825 arm_epilogue_frame_this_id
,
2826 arm_epilogue_frame_prev_register
,
2828 arm_epilogue_frame_sniffer
,
2831 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2832 trampoline, return the target PC. Otherwise return 0.
2834 void call0a (char c, short s, int i, long l) {}
2838 (*pointer_to_call0a) (c, s, i, l);
2841 Instead of calling a stub library function _call_via_xx (xx is
2842 the register name), GCC may inline the trampoline in the object
2843 file as below (register r2 has the address of call0a).
2846 .type main, %function
2855 The trampoline 'bx r2' doesn't belong to main. */
2858 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2860 /* The heuristics of recognizing such trampoline is that FRAME is
2861 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2862 if (arm_frame_is_thumb (frame
))
2866 if (target_read_memory (pc
, buf
, 2) == 0)
2868 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2869 enum bfd_endian byte_order_for_code
2870 = gdbarch_byte_order_for_code (gdbarch
);
2872 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2874 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2877 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2879 /* Clear the LSB so that gdb core sets step-resume
2880 breakpoint at the right address. */
2881 return UNMAKE_THUMB_ADDR (dest
);
2889 static struct arm_prologue_cache
*
2890 arm_make_stub_cache (struct frame_info
*this_frame
)
2892 struct arm_prologue_cache
*cache
;
2894 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2895 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2897 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2902 /* Our frame ID for a stub frame is the current SP and LR. */
2905 arm_stub_this_id (struct frame_info
*this_frame
,
2907 struct frame_id
*this_id
)
2909 struct arm_prologue_cache
*cache
;
2911 if (*this_cache
== NULL
)
2912 *this_cache
= arm_make_stub_cache (this_frame
);
2913 cache
= (struct arm_prologue_cache
*) *this_cache
;
2915 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2919 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2920 struct frame_info
*this_frame
,
2921 void **this_prologue_cache
)
2923 CORE_ADDR addr_in_block
;
2925 CORE_ADDR pc
, start_addr
;
2928 addr_in_block
= get_frame_address_in_block (this_frame
);
2929 pc
= get_frame_pc (this_frame
);
2930 if (in_plt_section (addr_in_block
)
2931 /* We also use the stub winder if the target memory is unreadable
2932 to avoid having the prologue unwinder trying to read it. */
2933 || target_read_memory (pc
, dummy
, 4) != 0)
2936 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2937 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2943 struct frame_unwind arm_stub_unwind
= {
2945 default_frame_unwind_stop_reason
,
2947 arm_prologue_prev_register
,
2949 arm_stub_unwind_sniffer
2952 /* Put here the code to store, into CACHE->saved_regs, the addresses
2953 of the saved registers of frame described by THIS_FRAME. CACHE is
2956 static struct arm_prologue_cache
*
2957 arm_m_exception_cache (struct frame_info
*this_frame
)
2959 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2960 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2961 struct arm_prologue_cache
*cache
;
2962 CORE_ADDR unwound_sp
;
2965 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2966 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2968 unwound_sp
= get_frame_register_unsigned (this_frame
,
2971 /* The hardware saves eight 32-bit words, comprising xPSR,
2972 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2973 "B1.5.6 Exception entry behavior" in
2974 "ARMv7-M Architecture Reference Manual". */
2975 cache
->saved_regs
[0].addr
= unwound_sp
;
2976 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2977 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2978 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2979 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2980 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2981 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2982 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2984 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2985 aligner between the top of the 32-byte stack frame and the
2986 previous context's stack pointer. */
2987 cache
->prev_sp
= unwound_sp
+ 32;
2988 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2989 && (xpsr
& (1 << 9)) != 0)
2990 cache
->prev_sp
+= 4;
2995 /* Implementation of function hook 'this_id' in
2996 'struct frame_uwnind'. */
2999 arm_m_exception_this_id (struct frame_info
*this_frame
,
3001 struct frame_id
*this_id
)
3003 struct arm_prologue_cache
*cache
;
3005 if (*this_cache
== NULL
)
3006 *this_cache
= arm_m_exception_cache (this_frame
);
3007 cache
= (struct arm_prologue_cache
*) *this_cache
;
3009 /* Our frame ID for a stub frame is the current SP and LR. */
3010 *this_id
= frame_id_build (cache
->prev_sp
,
3011 get_frame_pc (this_frame
));
3014 /* Implementation of function hook 'prev_register' in
3015 'struct frame_uwnind'. */
3017 static struct value
*
3018 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3022 struct arm_prologue_cache
*cache
;
3024 if (*this_cache
== NULL
)
3025 *this_cache
= arm_m_exception_cache (this_frame
);
3026 cache
= (struct arm_prologue_cache
*) *this_cache
;
3028 /* The value was already reconstructed into PREV_SP. */
3029 if (prev_regnum
== ARM_SP_REGNUM
)
3030 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3033 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3037 /* Implementation of function hook 'sniffer' in
3038 'struct frame_uwnind'. */
3041 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3042 struct frame_info
*this_frame
,
3043 void **this_prologue_cache
)
3045 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3047 /* No need to check is_m; this sniffer is only registered for
3048 M-profile architectures. */
3050 /* Check if exception frame returns to a magic PC value. */
3051 return arm_m_addr_is_magic (this_pc
);
3054 /* Frame unwinder for M-profile exceptions. */
3056 struct frame_unwind arm_m_exception_unwind
=
3059 default_frame_unwind_stop_reason
,
3060 arm_m_exception_this_id
,
3061 arm_m_exception_prev_register
,
3063 arm_m_exception_unwind_sniffer
3067 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3069 struct arm_prologue_cache
*cache
;
3071 if (*this_cache
== NULL
)
3072 *this_cache
= arm_make_prologue_cache (this_frame
);
3073 cache
= (struct arm_prologue_cache
*) *this_cache
;
3075 return cache
->prev_sp
- cache
->framesize
;
3078 struct frame_base arm_normal_base
= {
3079 &arm_prologue_unwind
,
3080 arm_normal_frame_base
,
3081 arm_normal_frame_base
,
3082 arm_normal_frame_base
3085 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3086 dummy frame. The frame ID's base needs to match the TOS value
3087 saved by save_dummy_frame_tos() and returned from
3088 arm_push_dummy_call, and the PC needs to match the dummy frame's
3091 static struct frame_id
3092 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3094 return frame_id_build (get_frame_register_unsigned (this_frame
,
3096 get_frame_pc (this_frame
));
3099 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3100 be used to construct the previous frame's ID, after looking up the
3101 containing function). */
3104 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3107 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3108 return arm_addr_bits_remove (gdbarch
, pc
);
3112 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3114 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3117 static struct value
*
3118 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3121 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3123 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3128 /* The PC is normally copied from the return column, which
3129 describes saves of LR. However, that version may have an
3130 extra bit set to indicate Thumb state. The bit is not
3132 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3133 return frame_unwind_got_constant (this_frame
, regnum
,
3134 arm_addr_bits_remove (gdbarch
, lr
));
3137 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3138 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3139 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3140 if (IS_THUMB_ADDR (lr
))
3144 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3147 internal_error (__FILE__
, __LINE__
,
3148 _("Unexpected register %d"), regnum
);
3153 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3154 struct dwarf2_frame_state_reg
*reg
,
3155 struct frame_info
*this_frame
)
3161 reg
->how
= DWARF2_FRAME_REG_FN
;
3162 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3165 reg
->how
= DWARF2_FRAME_REG_CFA
;
3170 /* Implement the stack_frame_destroyed_p gdbarch method. */
3173 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3175 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3176 unsigned int insn
, insn2
;
3177 int found_return
= 0, found_stack_adjust
= 0;
3178 CORE_ADDR func_start
, func_end
;
3182 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3185 /* The epilogue is a sequence of instructions along the following lines:
3187 - add stack frame size to SP or FP
3188 - [if frame pointer used] restore SP from FP
3189 - restore registers from SP [may include PC]
3190 - a return-type instruction [if PC wasn't already restored]
3192 In a first pass, we scan forward from the current PC and verify the
3193 instructions we find as compatible with this sequence, ending in a
3196 However, this is not sufficient to distinguish indirect function calls
3197 within a function from indirect tail calls in the epilogue in some cases.
3198 Therefore, if we didn't already find any SP-changing instruction during
3199 forward scan, we add a backward scanning heuristic to ensure we actually
3200 are in the epilogue. */
3203 while (scan_pc
< func_end
&& !found_return
)
3205 if (target_read_memory (scan_pc
, buf
, 2))
3209 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3211 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3213 else if (insn
== 0x46f7) /* mov pc, lr */
3215 else if (thumb_instruction_restores_sp (insn
))
3217 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3220 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3222 if (target_read_memory (scan_pc
, buf
, 2))
3226 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3228 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3230 if (insn2
& 0x8000) /* <registers> include PC. */
3233 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3234 && (insn2
& 0x0fff) == 0x0b04)
3236 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3239 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3240 && (insn2
& 0x0e00) == 0x0a00)
3252 /* Since any instruction in the epilogue sequence, with the possible
3253 exception of return itself, updates the stack pointer, we need to
3254 scan backwards for at most one instruction. Try either a 16-bit or
3255 a 32-bit instruction. This is just a heuristic, so we do not worry
3256 too much about false positives. */
3258 if (pc
- 4 < func_start
)
3260 if (target_read_memory (pc
- 4, buf
, 4))
3263 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3264 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3266 if (thumb_instruction_restores_sp (insn2
))
3267 found_stack_adjust
= 1;
3268 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3269 found_stack_adjust
= 1;
3270 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3271 && (insn2
& 0x0fff) == 0x0b04)
3272 found_stack_adjust
= 1;
3273 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3274 && (insn2
& 0x0e00) == 0x0a00)
3275 found_stack_adjust
= 1;
3277 return found_stack_adjust
;
3281 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3283 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3286 CORE_ADDR func_start
, func_end
;
3288 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3291 /* We are in the epilogue if the previous instruction was a stack
3292 adjustment and the next instruction is a possible return (bx, mov
3293 pc, or pop). We could have to scan backwards to find the stack
3294 adjustment, or forwards to find the return, but this is a decent
3295 approximation. First scan forwards. */
3298 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3299 if (bits (insn
, 28, 31) != INST_NV
)
3301 if ((insn
& 0x0ffffff0) == 0x012fff10)
3304 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3307 else if ((insn
& 0x0fff0000) == 0x08bd0000
3308 && (insn
& 0x0000c000) != 0)
3309 /* POP (LDMIA), including PC or LR. */
3316 /* Scan backwards. This is just a heuristic, so do not worry about
3317 false positives from mode changes. */
3319 if (pc
< func_start
+ 4)
3322 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3323 if (arm_instruction_restores_sp (insn
))
3329 /* Implement the stack_frame_destroyed_p gdbarch method. */
3332 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3334 if (arm_pc_is_thumb (gdbarch
, pc
))
3335 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3337 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3340 /* When arguments must be pushed onto the stack, they go on in reverse
3341 order. The code below implements a FILO (stack) to do this. */
3346 struct stack_item
*prev
;
3350 static struct stack_item
*
3351 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3353 struct stack_item
*si
;
3354 si
= XNEW (struct stack_item
);
3355 si
->data
= (gdb_byte
*) xmalloc (len
);
3358 memcpy (si
->data
, contents
, len
);
3362 static struct stack_item
*
3363 pop_stack_item (struct stack_item
*si
)
3365 struct stack_item
*dead
= si
;
3373 /* Return the alignment (in bytes) of the given type. */
3376 arm_type_align (struct type
*t
)
3382 t
= check_typedef (t
);
3383 switch (TYPE_CODE (t
))
3386 /* Should never happen. */
3387 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3391 case TYPE_CODE_ENUM
:
3395 case TYPE_CODE_RANGE
:
3397 case TYPE_CODE_CHAR
:
3398 case TYPE_CODE_BOOL
:
3399 return TYPE_LENGTH (t
);
3401 case TYPE_CODE_ARRAY
:
3402 if (TYPE_VECTOR (t
))
3404 /* Use the natural alignment for vector types (the same for
3405 scalar type), but the maximum alignment is 64-bit. */
3406 if (TYPE_LENGTH (t
) > 8)
3409 return TYPE_LENGTH (t
);
3412 return arm_type_align (TYPE_TARGET_TYPE (t
));
3413 case TYPE_CODE_COMPLEX
:
3414 return arm_type_align (TYPE_TARGET_TYPE (t
));
3416 case TYPE_CODE_STRUCT
:
3417 case TYPE_CODE_UNION
:
3419 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3421 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3429 /* Possible base types for a candidate for passing and returning in
3432 enum arm_vfp_cprc_base_type
3441 /* The length of one element of base type B. */
3444 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3448 case VFP_CPRC_SINGLE
:
3450 case VFP_CPRC_DOUBLE
:
3452 case VFP_CPRC_VEC64
:
3454 case VFP_CPRC_VEC128
:
3457 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3462 /* The character ('s', 'd' or 'q') for the type of VFP register used
3463 for passing base type B. */
3466 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3470 case VFP_CPRC_SINGLE
:
3472 case VFP_CPRC_DOUBLE
:
3474 case VFP_CPRC_VEC64
:
3476 case VFP_CPRC_VEC128
:
3479 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3484 /* Determine whether T may be part of a candidate for passing and
3485 returning in VFP registers, ignoring the limit on the total number
3486 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3487 classification of the first valid component found; if it is not
3488 VFP_CPRC_UNKNOWN, all components must have the same classification
3489 as *BASE_TYPE. If it is found that T contains a type not permitted
3490 for passing and returning in VFP registers, a type differently
3491 classified from *BASE_TYPE, or two types differently classified
3492 from each other, return -1, otherwise return the total number of
3493 base-type elements found (possibly 0 in an empty structure or
3494 array). Vector types are not currently supported, matching the
3495 generic AAPCS support. */
3498 arm_vfp_cprc_sub_candidate (struct type
*t
,
3499 enum arm_vfp_cprc_base_type
*base_type
)
3501 t
= check_typedef (t
);
3502 switch (TYPE_CODE (t
))
3505 switch (TYPE_LENGTH (t
))
3508 if (*base_type
== VFP_CPRC_UNKNOWN
)
3509 *base_type
= VFP_CPRC_SINGLE
;
3510 else if (*base_type
!= VFP_CPRC_SINGLE
)
3515 if (*base_type
== VFP_CPRC_UNKNOWN
)
3516 *base_type
= VFP_CPRC_DOUBLE
;
3517 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3526 case TYPE_CODE_COMPLEX
:
3527 /* Arguments of complex T where T is one of the types float or
3528 double get treated as if they are implemented as:
3537 switch (TYPE_LENGTH (t
))
3540 if (*base_type
== VFP_CPRC_UNKNOWN
)
3541 *base_type
= VFP_CPRC_SINGLE
;
3542 else if (*base_type
!= VFP_CPRC_SINGLE
)
3547 if (*base_type
== VFP_CPRC_UNKNOWN
)
3548 *base_type
= VFP_CPRC_DOUBLE
;
3549 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3558 case TYPE_CODE_ARRAY
:
3560 if (TYPE_VECTOR (t
))
3562 /* A 64-bit or 128-bit containerized vector type are VFP
3564 switch (TYPE_LENGTH (t
))
3567 if (*base_type
== VFP_CPRC_UNKNOWN
)
3568 *base_type
= VFP_CPRC_VEC64
;
3571 if (*base_type
== VFP_CPRC_UNKNOWN
)
3572 *base_type
= VFP_CPRC_VEC128
;
3583 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3587 if (TYPE_LENGTH (t
) == 0)
3589 gdb_assert (count
== 0);
3592 else if (count
== 0)
3594 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3595 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3596 return TYPE_LENGTH (t
) / unitlen
;
3601 case TYPE_CODE_STRUCT
:
3606 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3610 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3611 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3613 if (sub_count
== -1)
3617 if (TYPE_LENGTH (t
) == 0)
3619 gdb_assert (count
== 0);
3622 else if (count
== 0)
3624 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3625 if (TYPE_LENGTH (t
) != unitlen
* count
)
3630 case TYPE_CODE_UNION
:
3635 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3637 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3639 if (sub_count
== -1)
3641 count
= (count
> sub_count
? count
: sub_count
);
3643 if (TYPE_LENGTH (t
) == 0)
3645 gdb_assert (count
== 0);
3648 else if (count
== 0)
3650 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3651 if (TYPE_LENGTH (t
) != unitlen
* count
)
3663 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3664 if passed to or returned from a non-variadic function with the VFP
3665 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3666 *BASE_TYPE to the base type for T and *COUNT to the number of
3667 elements of that base type before returning. */
3670 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3673 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3674 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3675 if (c
<= 0 || c
> 4)
3682 /* Return 1 if the VFP ABI should be used for passing arguments to and
3683 returning values from a function of type FUNC_TYPE, 0
3687 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3689 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3690 /* Variadic functions always use the base ABI. Assume that functions
3691 without debug info are not variadic. */
3692 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3694 /* The VFP ABI is only supported as a variant of AAPCS. */
3695 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3697 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3700 /* We currently only support passing parameters in integer registers, which
3701 conforms with GCC's default model, and VFP argument passing following
3702 the VFP variant of AAPCS. Several other variants exist and
3703 we should probably support some of them based on the selected ABI. */
3706 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3707 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3708 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3709 CORE_ADDR struct_addr
)
3711 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3715 struct stack_item
*si
= NULL
;
3718 unsigned vfp_regs_free
= (1 << 16) - 1;
3720 /* Determine the type of this function and whether the VFP ABI
3722 ftype
= check_typedef (value_type (function
));
3723 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3724 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3725 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3727 /* Set the return address. For the ARM, the return breakpoint is
3728 always at BP_ADDR. */
3729 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3731 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3733 /* Walk through the list of args and determine how large a temporary
3734 stack is required. Need to take care here as structs may be
3735 passed on the stack, and we have to push them. */
3738 argreg
= ARM_A1_REGNUM
;
3741 /* The struct_return pointer occupies the first parameter
3742 passing register. */
3746 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3747 gdbarch_register_name (gdbarch
, argreg
),
3748 paddress (gdbarch
, struct_addr
));
3749 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3753 for (argnum
= 0; argnum
< nargs
; argnum
++)
3756 struct type
*arg_type
;
3757 struct type
*target_type
;
3758 enum type_code typecode
;
3759 const bfd_byte
*val
;
3761 enum arm_vfp_cprc_base_type vfp_base_type
;
3763 int may_use_core_reg
= 1;
3765 arg_type
= check_typedef (value_type (args
[argnum
]));
3766 len
= TYPE_LENGTH (arg_type
);
3767 target_type
= TYPE_TARGET_TYPE (arg_type
);
3768 typecode
= TYPE_CODE (arg_type
);
3769 val
= value_contents (args
[argnum
]);
3771 align
= arm_type_align (arg_type
);
3772 /* Round alignment up to a whole number of words. */
3773 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3774 /* Different ABIs have different maximum alignments. */
3775 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3777 /* The APCS ABI only requires word alignment. */
3778 align
= INT_REGISTER_SIZE
;
3782 /* The AAPCS requires at most doubleword alignment. */
3783 if (align
> INT_REGISTER_SIZE
* 2)
3784 align
= INT_REGISTER_SIZE
* 2;
3788 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3796 /* Because this is a CPRC it cannot go in a core register or
3797 cause a core register to be skipped for alignment.
3798 Either it goes in VFP registers and the rest of this loop
3799 iteration is skipped for this argument, or it goes on the
3800 stack (and the stack alignment code is correct for this
3802 may_use_core_reg
= 0;
3804 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3805 shift
= unit_length
/ 4;
3806 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3807 for (regno
= 0; regno
< 16; regno
+= shift
)
3808 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3817 vfp_regs_free
&= ~(mask
<< regno
);
3818 reg_scaled
= regno
/ shift
;
3819 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3820 for (i
= 0; i
< vfp_base_count
; i
++)
3824 if (reg_char
== 'q')
3825 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3826 val
+ i
* unit_length
);
3829 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3830 reg_char
, reg_scaled
+ i
);
3831 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3833 regcache_cooked_write (regcache
, regnum
,
3834 val
+ i
* unit_length
);
3841 /* This CPRC could not go in VFP registers, so all VFP
3842 registers are now marked as used. */
3847 /* Push stack padding for dowubleword alignment. */
3848 if (nstack
& (align
- 1))
3850 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3851 nstack
+= INT_REGISTER_SIZE
;
3854 /* Doubleword aligned quantities must go in even register pairs. */
3855 if (may_use_core_reg
3856 && argreg
<= ARM_LAST_ARG_REGNUM
3857 && align
> INT_REGISTER_SIZE
3861 /* If the argument is a pointer to a function, and it is a
3862 Thumb function, create a LOCAL copy of the value and set
3863 the THUMB bit in it. */
3864 if (TYPE_CODE_PTR
== typecode
3865 && target_type
!= NULL
3866 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3868 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3869 if (arm_pc_is_thumb (gdbarch
, regval
))
3871 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3872 store_unsigned_integer (copy
, len
, byte_order
,
3873 MAKE_THUMB_ADDR (regval
));
3878 /* Copy the argument to general registers or the stack in
3879 register-sized pieces. Large arguments are split between
3880 registers and stack. */
3883 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3885 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3887 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3889 /* The argument is being passed in a general purpose
3891 if (byte_order
== BFD_ENDIAN_BIG
)
3892 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3894 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3896 gdbarch_register_name
3898 phex (regval
, INT_REGISTER_SIZE
));
3899 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3904 gdb_byte buf
[INT_REGISTER_SIZE
];
3906 memset (buf
, 0, sizeof (buf
));
3907 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3909 /* Push the arguments onto the stack. */
3911 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3913 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3914 nstack
+= INT_REGISTER_SIZE
;
3921 /* If we have an odd number of words to push, then decrement the stack
3922 by one word now, so first stack argument will be dword aligned. */
3929 write_memory (sp
, si
->data
, si
->len
);
3930 si
= pop_stack_item (si
);
3933 /* Finally, update teh SP register. */
3934 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3940 /* Always align the frame to an 8-byte boundary. This is required on
3941 some platforms and harmless on the rest. */
3944 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3946 /* Align the stack to eight bytes. */
3947 return sp
& ~ (CORE_ADDR
) 7;
3951 print_fpu_flags (struct ui_file
*file
, int flags
)
3953 if (flags
& (1 << 0))
3954 fputs_filtered ("IVO ", file
);
3955 if (flags
& (1 << 1))
3956 fputs_filtered ("DVZ ", file
);
3957 if (flags
& (1 << 2))
3958 fputs_filtered ("OFL ", file
);
3959 if (flags
& (1 << 3))
3960 fputs_filtered ("UFL ", file
);
3961 if (flags
& (1 << 4))
3962 fputs_filtered ("INX ", file
);
3963 fputc_filtered ('\n', file
);
3966 /* Print interesting information about the floating point processor
3967 (if present) or emulator. */
3969 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3970 struct frame_info
*frame
, const char *args
)
3972 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3975 type
= (status
>> 24) & 127;
3976 if (status
& (1 << 31))
3977 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3979 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3980 /* i18n: [floating point unit] mask */
3981 fputs_filtered (_("mask: "), file
);
3982 print_fpu_flags (file
, status
>> 16);
3983 /* i18n: [floating point unit] flags */
3984 fputs_filtered (_("flags: "), file
);
3985 print_fpu_flags (file
, status
);
3988 /* Construct the ARM extended floating point type. */
3989 static struct type
*
3990 arm_ext_type (struct gdbarch
*gdbarch
)
3992 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3994 if (!tdep
->arm_ext_type
)
3996 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3997 floatformats_arm_ext
);
3999 return tdep
->arm_ext_type
;
4002 static struct type
*
4003 arm_neon_double_type (struct gdbarch
*gdbarch
)
4005 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4007 if (tdep
->neon_double_type
== NULL
)
4009 struct type
*t
, *elem
;
4011 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4013 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4014 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4015 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4016 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4017 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4018 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4019 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4020 append_composite_type_field (t
, "u64", elem
);
4021 elem
= builtin_type (gdbarch
)->builtin_float
;
4022 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4023 elem
= builtin_type (gdbarch
)->builtin_double
;
4024 append_composite_type_field (t
, "f64", elem
);
4026 TYPE_VECTOR (t
) = 1;
4027 TYPE_NAME (t
) = "neon_d";
4028 tdep
->neon_double_type
= t
;
4031 return tdep
->neon_double_type
;
4034 /* FIXME: The vector types are not correctly ordered on big-endian
4035 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4036 bits of d0 - regardless of what unit size is being held in d0. So
4037 the offset of the first uint8 in d0 is 7, but the offset of the
4038 first float is 4. This code works as-is for little-endian
4041 static struct type
*
4042 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4046 if (tdep
->neon_quad_type
== NULL
)
4048 struct type
*t
, *elem
;
4050 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4052 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4053 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4054 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4055 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4056 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4057 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4058 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4059 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4060 elem
= builtin_type (gdbarch
)->builtin_float
;
4061 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4062 elem
= builtin_type (gdbarch
)->builtin_double
;
4063 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4065 TYPE_VECTOR (t
) = 1;
4066 TYPE_NAME (t
) = "neon_q";
4067 tdep
->neon_quad_type
= t
;
4070 return tdep
->neon_quad_type
;
4073 /* Return the GDB type object for the "standard" data type of data in
4076 static struct type
*
4077 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4079 int num_regs
= gdbarch_num_regs (gdbarch
);
4081 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4082 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4083 return builtin_type (gdbarch
)->builtin_float
;
4085 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4086 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4087 return arm_neon_quad_type (gdbarch
);
4089 /* If the target description has register information, we are only
4090 in this function so that we can override the types of
4091 double-precision registers for NEON. */
4092 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4094 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4096 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4097 && TYPE_CODE (t
) == TYPE_CODE_FLT
4098 && gdbarch_tdep (gdbarch
)->have_neon
)
4099 return arm_neon_double_type (gdbarch
);
4104 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4106 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4107 return builtin_type (gdbarch
)->builtin_void
;
4109 return arm_ext_type (gdbarch
);
4111 else if (regnum
== ARM_SP_REGNUM
)
4112 return builtin_type (gdbarch
)->builtin_data_ptr
;
4113 else if (regnum
== ARM_PC_REGNUM
)
4114 return builtin_type (gdbarch
)->builtin_func_ptr
;
4115 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4116 /* These registers are only supported on targets which supply
4117 an XML description. */
4118 return builtin_type (gdbarch
)->builtin_int0
;
4120 return builtin_type (gdbarch
)->builtin_uint32
;
4123 /* Map a DWARF register REGNUM onto the appropriate GDB register
4127 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4129 /* Core integer regs. */
4130 if (reg
>= 0 && reg
<= 15)
4133 /* Legacy FPA encoding. These were once used in a way which
4134 overlapped with VFP register numbering, so their use is
4135 discouraged, but GDB doesn't support the ARM toolchain
4136 which used them for VFP. */
4137 if (reg
>= 16 && reg
<= 23)
4138 return ARM_F0_REGNUM
+ reg
- 16;
4140 /* New assignments for the FPA registers. */
4141 if (reg
>= 96 && reg
<= 103)
4142 return ARM_F0_REGNUM
+ reg
- 96;
4144 /* WMMX register assignments. */
4145 if (reg
>= 104 && reg
<= 111)
4146 return ARM_WCGR0_REGNUM
+ reg
- 104;
4148 if (reg
>= 112 && reg
<= 127)
4149 return ARM_WR0_REGNUM
+ reg
- 112;
4151 if (reg
>= 192 && reg
<= 199)
4152 return ARM_WC0_REGNUM
+ reg
- 192;
4154 /* VFP v2 registers. A double precision value is actually
4155 in d1 rather than s2, but the ABI only defines numbering
4156 for the single precision registers. This will "just work"
4157 in GDB for little endian targets (we'll read eight bytes,
4158 starting in s0 and then progressing to s1), but will be
4159 reversed on big endian targets with VFP. This won't
4160 be a problem for the new Neon quad registers; you're supposed
4161 to use DW_OP_piece for those. */
4162 if (reg
>= 64 && reg
<= 95)
4166 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4167 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4171 /* VFP v3 / Neon registers. This range is also used for VFP v2
4172 registers, except that it now describes d0 instead of s0. */
4173 if (reg
>= 256 && reg
<= 287)
4177 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4178 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4185 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4187 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4190 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4192 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4193 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4195 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4196 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4198 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4199 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4201 if (reg
< NUM_GREGS
)
4202 return SIM_ARM_R0_REGNUM
+ reg
;
4205 if (reg
< NUM_FREGS
)
4206 return SIM_ARM_FP0_REGNUM
+ reg
;
4209 if (reg
< NUM_SREGS
)
4210 return SIM_ARM_FPS_REGNUM
+ reg
;
4213 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4216 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4217 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4218 It is thought that this is is the floating-point register format on
4219 little-endian systems. */
4222 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4223 void *dbl
, int endianess
)
4227 if (endianess
== BFD_ENDIAN_BIG
)
4228 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4230 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4232 floatformat_from_doublest (fmt
, &d
, dbl
);
4236 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4241 floatformat_to_doublest (fmt
, ptr
, &d
);
4242 if (endianess
== BFD_ENDIAN_BIG
)
4243 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4245 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4249 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4250 of the appropriate mode (as encoded in the PC value), even if this
4251 differs from what would be expected according to the symbol tables. */
4254 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4255 struct address_space
*aspace
,
4258 scoped_restore save_override_mode
4259 = make_scoped_restore (&arm_override_mode
,
4260 (int) IS_THUMB_ADDR (pc
));
4261 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4263 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4266 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4267 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4268 NULL if an error occurs. BUF is freed. */
4271 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4272 int old_len
, int new_len
)
4275 int bytes_to_read
= new_len
- old_len
;
4277 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4278 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4280 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4288 /* An IT block is at most the 2-byte IT instruction followed by
4289 four 4-byte instructions. The furthest back we must search to
4290 find an IT block that affects the current instruction is thus
4291 2 + 3 * 4 == 14 bytes. */
4292 #define MAX_IT_BLOCK_PREFIX 14
4294 /* Use a quick scan if there are more than this many bytes of
4296 #define IT_SCAN_THRESHOLD 32
4298 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4299 A breakpoint in an IT block may not be hit, depending on the
4302 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4306 CORE_ADDR boundary
, func_start
;
4308 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4309 int i
, any
, last_it
, last_it_count
;
4311 /* If we are using BKPT breakpoints, none of this is necessary. */
4312 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4315 /* ARM mode does not have this problem. */
4316 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4319 /* We are setting a breakpoint in Thumb code that could potentially
4320 contain an IT block. The first step is to find how much Thumb
4321 code there is; we do not need to read outside of known Thumb
4323 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4325 /* Thumb-2 code must have mapping symbols to have a chance. */
4328 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4330 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4331 && func_start
> boundary
)
4332 boundary
= func_start
;
4334 /* Search for a candidate IT instruction. We have to do some fancy
4335 footwork to distinguish a real IT instruction from the second
4336 half of a 32-bit instruction, but there is no need for that if
4337 there's no candidate. */
4338 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4340 /* No room for an IT instruction. */
4343 buf
= (gdb_byte
*) xmalloc (buf_len
);
4344 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4347 for (i
= 0; i
< buf_len
; i
+= 2)
4349 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4350 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4363 /* OK, the code bytes before this instruction contain at least one
4364 halfword which resembles an IT instruction. We know that it's
4365 Thumb code, but there are still two possibilities. Either the
4366 halfword really is an IT instruction, or it is the second half of
4367 a 32-bit Thumb instruction. The only way we can tell is to
4368 scan forwards from a known instruction boundary. */
4369 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4373 /* There's a lot of code before this instruction. Start with an
4374 optimistic search; it's easy to recognize halfwords that can
4375 not be the start of a 32-bit instruction, and use that to
4376 lock on to the instruction boundaries. */
4377 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4380 buf_len
= IT_SCAN_THRESHOLD
;
4383 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4385 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4386 if (thumb_insn_size (inst1
) == 2)
4393 /* At this point, if DEFINITE, BUF[I] is the first place we
4394 are sure that we know the instruction boundaries, and it is far
4395 enough from BPADDR that we could not miss an IT instruction
4396 affecting BPADDR. If ! DEFINITE, give up - start from a
4400 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4404 buf_len
= bpaddr
- boundary
;
4410 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4413 buf_len
= bpaddr
- boundary
;
4417 /* Scan forwards. Find the last IT instruction before BPADDR. */
4422 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4424 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4429 else if (inst1
& 0x0002)
4431 else if (inst1
& 0x0004)
4436 i
+= thumb_insn_size (inst1
);
4442 /* There wasn't really an IT instruction after all. */
4445 if (last_it_count
< 1)
4446 /* It was too far away. */
4449 /* This really is a trouble spot. Move the breakpoint to the IT
4451 return bpaddr
- buf_len
+ last_it
;
4454 /* ARM displaced stepping support.
4456 Generally ARM displaced stepping works as follows:
4458 1. When an instruction is to be single-stepped, it is first decoded by
4459 arm_process_displaced_insn. Depending on the type of instruction, it is
4460 then copied to a scratch location, possibly in a modified form. The
4461 copy_* set of functions performs such modification, as necessary. A
4462 breakpoint is placed after the modified instruction in the scratch space
4463 to return control to GDB. Note in particular that instructions which
4464 modify the PC will no longer do so after modification.
4466 2. The instruction is single-stepped, by setting the PC to the scratch
4467 location address, and resuming. Control returns to GDB when the
4470 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4471 function used for the current instruction. This function's job is to
4472 put the CPU/memory state back to what it would have been if the
4473 instruction had been executed unmodified in its original location. */
4475 /* NOP instruction (mov r0, r0). */
4476 #define ARM_NOP 0xe1a00000
4477 #define THUMB_NOP 0x4600
4479 /* Helper for register reads for displaced stepping. In particular, this
4480 returns the PC as it would be seen by the instruction at its original
4484 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4488 CORE_ADDR from
= dsc
->insn_addr
;
4490 if (regno
== ARM_PC_REGNUM
)
4492 /* Compute pipeline offset:
4493 - When executing an ARM instruction, PC reads as the address of the
4494 current instruction plus 8.
4495 - When executing a Thumb instruction, PC reads as the address of the
4496 current instruction plus 4. */
4503 if (debug_displaced
)
4504 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4505 (unsigned long) from
);
4506 return (ULONGEST
) from
;
4510 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4511 if (debug_displaced
)
4512 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4513 regno
, (unsigned long) ret
);
4519 displaced_in_arm_mode (struct regcache
*regs
)
4522 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4524 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4526 return (ps
& t_bit
) == 0;
4529 /* Write to the PC as from a branch instruction. */
4532 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4536 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4537 architecture versions < 6. */
4538 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4539 val
& ~(ULONGEST
) 0x3);
4541 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4542 val
& ~(ULONGEST
) 0x1);
4545 /* Write to the PC as from a branch-exchange instruction. */
4548 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4551 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4553 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4557 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4558 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4560 else if ((val
& 2) == 0)
4562 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4563 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4567 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4568 mode, align dest to 4 bytes). */
4569 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4570 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4571 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4575 /* Write to the PC as if from a load instruction. */
4578 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4581 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4582 bx_write_pc (regs
, val
);
4584 branch_write_pc (regs
, dsc
, val
);
4587 /* Write to the PC as if from an ALU instruction. */
4590 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4593 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4594 bx_write_pc (regs
, val
);
4596 branch_write_pc (regs
, dsc
, val
);
4599 /* Helper for writing to registers for displaced stepping. Writing to the PC
4600 has a varying effects depending on the instruction which does the write:
4601 this is controlled by the WRITE_PC argument. */
4604 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4605 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4607 if (regno
== ARM_PC_REGNUM
)
4609 if (debug_displaced
)
4610 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4611 (unsigned long) val
);
4614 case BRANCH_WRITE_PC
:
4615 branch_write_pc (regs
, dsc
, val
);
4619 bx_write_pc (regs
, val
);
4623 load_write_pc (regs
, dsc
, val
);
4627 alu_write_pc (regs
, dsc
, val
);
4630 case CANNOT_WRITE_PC
:
4631 warning (_("Instruction wrote to PC in an unexpected way when "
4632 "single-stepping"));
4636 internal_error (__FILE__
, __LINE__
,
4637 _("Invalid argument to displaced_write_reg"));
4640 dsc
->wrote_to_pc
= 1;
4644 if (debug_displaced
)
4645 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4646 regno
, (unsigned long) val
);
4647 regcache_cooked_write_unsigned (regs
, regno
, val
);
4651 /* This function is used to concisely determine if an instruction INSN
4652 references PC. Register fields of interest in INSN should have the
4653 corresponding fields of BITMASK set to 0b1111. The function
4654 returns return 1 if any of these fields in INSN reference the PC
4655 (also 0b1111, r15), else it returns 0. */
4658 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4660 uint32_t lowbit
= 1;
4662 while (bitmask
!= 0)
4666 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4672 mask
= lowbit
* 0xf;
4674 if ((insn
& mask
) == mask
)
4683 /* The simplest copy function. Many instructions have the same effect no
4684 matter what address they are executed at: in those cases, use this. */
4687 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4688 const char *iname
, struct displaced_step_closure
*dsc
)
4690 if (debug_displaced
)
4691 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4692 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4695 dsc
->modinsn
[0] = insn
;
4701 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4702 uint16_t insn2
, const char *iname
,
4703 struct displaced_step_closure
*dsc
)
4705 if (debug_displaced
)
4706 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4707 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4710 dsc
->modinsn
[0] = insn1
;
4711 dsc
->modinsn
[1] = insn2
;
4717 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4720 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4722 struct displaced_step_closure
*dsc
)
4724 if (debug_displaced
)
4725 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4726 "opcode/class '%s' unmodified\n", insn
,
4729 dsc
->modinsn
[0] = insn
;
4734 /* Preload instructions with immediate offset. */
4737 cleanup_preload (struct gdbarch
*gdbarch
,
4738 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4740 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4741 if (!dsc
->u
.preload
.immed
)
4742 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4746 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4747 struct displaced_step_closure
*dsc
, unsigned int rn
)
4750 /* Preload instructions:
4752 {pli/pld} [rn, #+/-imm]
4754 {pli/pld} [r0, #+/-imm]. */
4756 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4757 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4758 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4759 dsc
->u
.preload
.immed
= 1;
4761 dsc
->cleanup
= &cleanup_preload
;
4765 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4766 struct displaced_step_closure
*dsc
)
4768 unsigned int rn
= bits (insn
, 16, 19);
4770 if (!insn_references_pc (insn
, 0x000f0000ul
))
4771 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4773 if (debug_displaced
)
4774 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4775 (unsigned long) insn
);
4777 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4779 install_preload (gdbarch
, regs
, dsc
, rn
);
4785 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4786 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4788 unsigned int rn
= bits (insn1
, 0, 3);
4789 unsigned int u_bit
= bit (insn1
, 7);
4790 int imm12
= bits (insn2
, 0, 11);
4793 if (rn
!= ARM_PC_REGNUM
)
4794 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4796 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4797 PLD (literal) Encoding T1. */
4798 if (debug_displaced
)
4799 fprintf_unfiltered (gdb_stdlog
,
4800 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4801 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4807 /* Rewrite instruction {pli/pld} PC imm12 into:
4808 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4812 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4814 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4815 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4817 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4819 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4820 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4821 dsc
->u
.preload
.immed
= 0;
4823 /* {pli/pld} [r0, r1] */
4824 dsc
->modinsn
[0] = insn1
& 0xfff0;
4825 dsc
->modinsn
[1] = 0xf001;
4828 dsc
->cleanup
= &cleanup_preload
;
4832 /* Preload instructions with register offset. */
4835 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4836 struct displaced_step_closure
*dsc
, unsigned int rn
,
4839 ULONGEST rn_val
, rm_val
;
4841 /* Preload register-offset instructions:
4843 {pli/pld} [rn, rm {, shift}]
4845 {pli/pld} [r0, r1 {, shift}]. */
4847 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4848 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4849 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4850 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4851 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4852 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4853 dsc
->u
.preload
.immed
= 0;
4855 dsc
->cleanup
= &cleanup_preload
;
4859 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4860 struct regcache
*regs
,
4861 struct displaced_step_closure
*dsc
)
4863 unsigned int rn
= bits (insn
, 16, 19);
4864 unsigned int rm
= bits (insn
, 0, 3);
4867 if (!insn_references_pc (insn
, 0x000f000ful
))
4868 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4870 if (debug_displaced
)
4871 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4872 (unsigned long) insn
);
4874 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4876 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4880 /* Copy/cleanup coprocessor load and store instructions. */
4883 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4884 struct regcache
*regs
,
4885 struct displaced_step_closure
*dsc
)
4887 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4889 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4891 if (dsc
->u
.ldst
.writeback
)
4892 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4896 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4897 struct displaced_step_closure
*dsc
,
4898 int writeback
, unsigned int rn
)
4902 /* Coprocessor load/store instructions:
4904 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4906 {stc/stc2} [r0, #+/-imm].
4908 ldc/ldc2 are handled identically. */
4910 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4911 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4912 /* PC should be 4-byte aligned. */
4913 rn_val
= rn_val
& 0xfffffffc;
4914 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4916 dsc
->u
.ldst
.writeback
= writeback
;
4917 dsc
->u
.ldst
.rn
= rn
;
4919 dsc
->cleanup
= &cleanup_copro_load_store
;
4923 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4924 struct regcache
*regs
,
4925 struct displaced_step_closure
*dsc
)
4927 unsigned int rn
= bits (insn
, 16, 19);
4929 if (!insn_references_pc (insn
, 0x000f0000ul
))
4930 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4932 if (debug_displaced
)
4933 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4934 "load/store insn %.8lx\n", (unsigned long) insn
);
4936 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4938 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4944 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4945 uint16_t insn2
, struct regcache
*regs
,
4946 struct displaced_step_closure
*dsc
)
4948 unsigned int rn
= bits (insn1
, 0, 3);
4950 if (rn
!= ARM_PC_REGNUM
)
4951 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4952 "copro load/store", dsc
);
4954 if (debug_displaced
)
4955 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4956 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4958 dsc
->modinsn
[0] = insn1
& 0xfff0;
4959 dsc
->modinsn
[1] = insn2
;
4962 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4963 doesn't support writeback, so pass 0. */
4964 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4969 /* Clean up branch instructions (actually perform the branch, by setting
4973 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4974 struct displaced_step_closure
*dsc
)
4976 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4977 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4978 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4979 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4984 if (dsc
->u
.branch
.link
)
4986 /* The value of LR should be the next insn of current one. In order
4987 not to confuse logic hanlding later insn `bx lr', if current insn mode
4988 is Thumb, the bit 0 of LR value should be set to 1. */
4989 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4992 next_insn_addr
|= 0x1;
4994 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4998 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
5001 /* Copy B/BL/BLX instructions with immediate destinations. */
5004 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5005 struct displaced_step_closure
*dsc
,
5006 unsigned int cond
, int exchange
, int link
, long offset
)
5008 /* Implement "BL<cond> <label>" as:
5010 Preparation: cond <- instruction condition
5011 Insn: mov r0, r0 (nop)
5012 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5014 B<cond> similar, but don't set r14 in cleanup. */
5016 dsc
->u
.branch
.cond
= cond
;
5017 dsc
->u
.branch
.link
= link
;
5018 dsc
->u
.branch
.exchange
= exchange
;
5020 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5021 if (link
&& exchange
)
5022 /* For BLX, offset is computed from the Align (PC, 4). */
5023 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5026 dsc
->u
.branch
.dest
+= 4 + offset
;
5028 dsc
->u
.branch
.dest
+= 8 + offset
;
5030 dsc
->cleanup
= &cleanup_branch
;
5033 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5034 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5036 unsigned int cond
= bits (insn
, 28, 31);
5037 int exchange
= (cond
== 0xf);
5038 int link
= exchange
|| bit (insn
, 24);
5041 if (debug_displaced
)
5042 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5043 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5044 (unsigned long) insn
);
5046 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5047 then arrange the switch into Thumb mode. */
5048 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5050 offset
= bits (insn
, 0, 23) << 2;
5052 if (bit (offset
, 25))
5053 offset
= offset
| ~0x3ffffff;
5055 dsc
->modinsn
[0] = ARM_NOP
;
5057 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5062 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5063 uint16_t insn2
, struct regcache
*regs
,
5064 struct displaced_step_closure
*dsc
)
5066 int link
= bit (insn2
, 14);
5067 int exchange
= link
&& !bit (insn2
, 12);
5070 int j1
= bit (insn2
, 13);
5071 int j2
= bit (insn2
, 11);
5072 int s
= sbits (insn1
, 10, 10);
5073 int i1
= !(j1
^ bit (insn1
, 10));
5074 int i2
= !(j2
^ bit (insn1
, 10));
5076 if (!link
&& !exchange
) /* B */
5078 offset
= (bits (insn2
, 0, 10) << 1);
5079 if (bit (insn2
, 12)) /* Encoding T4 */
5081 offset
|= (bits (insn1
, 0, 9) << 12)
5087 else /* Encoding T3 */
5089 offset
|= (bits (insn1
, 0, 5) << 12)
5093 cond
= bits (insn1
, 6, 9);
5098 offset
= (bits (insn1
, 0, 9) << 12);
5099 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5100 offset
|= exchange
?
5101 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5104 if (debug_displaced
)
5105 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5106 "%.4x %.4x with offset %.8lx\n",
5107 link
? (exchange
) ? "blx" : "bl" : "b",
5108 insn1
, insn2
, offset
);
5110 dsc
->modinsn
[0] = THUMB_NOP
;
5112 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5116 /* Copy B Thumb instructions. */
5118 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5119 struct displaced_step_closure
*dsc
)
5121 unsigned int cond
= 0;
5123 unsigned short bit_12_15
= bits (insn
, 12, 15);
5124 CORE_ADDR from
= dsc
->insn_addr
;
5126 if (bit_12_15
== 0xd)
5128 /* offset = SignExtend (imm8:0, 32) */
5129 offset
= sbits ((insn
<< 1), 0, 8);
5130 cond
= bits (insn
, 8, 11);
5132 else if (bit_12_15
== 0xe) /* Encoding T2 */
5134 offset
= sbits ((insn
<< 1), 0, 11);
5138 if (debug_displaced
)
5139 fprintf_unfiltered (gdb_stdlog
,
5140 "displaced: copying b immediate insn %.4x "
5141 "with offset %d\n", insn
, offset
);
5143 dsc
->u
.branch
.cond
= cond
;
5144 dsc
->u
.branch
.link
= 0;
5145 dsc
->u
.branch
.exchange
= 0;
5146 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5148 dsc
->modinsn
[0] = THUMB_NOP
;
5150 dsc
->cleanup
= &cleanup_branch
;
5155 /* Copy BX/BLX with register-specified destinations. */
5158 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5159 struct displaced_step_closure
*dsc
, int link
,
5160 unsigned int cond
, unsigned int rm
)
5162 /* Implement {BX,BLX}<cond> <reg>" as:
5164 Preparation: cond <- instruction condition
5165 Insn: mov r0, r0 (nop)
5166 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5168 Don't set r14 in cleanup for BX. */
5170 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5172 dsc
->u
.branch
.cond
= cond
;
5173 dsc
->u
.branch
.link
= link
;
5175 dsc
->u
.branch
.exchange
= 1;
5177 dsc
->cleanup
= &cleanup_branch
;
5181 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5182 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5184 unsigned int cond
= bits (insn
, 28, 31);
5187 int link
= bit (insn
, 5);
5188 unsigned int rm
= bits (insn
, 0, 3);
5190 if (debug_displaced
)
5191 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5192 (unsigned long) insn
);
5194 dsc
->modinsn
[0] = ARM_NOP
;
5196 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5201 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5202 struct regcache
*regs
,
5203 struct displaced_step_closure
*dsc
)
5205 int link
= bit (insn
, 7);
5206 unsigned int rm
= bits (insn
, 3, 6);
5208 if (debug_displaced
)
5209 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5210 (unsigned short) insn
);
5212 dsc
->modinsn
[0] = THUMB_NOP
;
5214 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5220 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5223 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5224 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5226 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5227 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5228 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5229 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5233 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5234 struct displaced_step_closure
*dsc
)
5236 unsigned int rn
= bits (insn
, 16, 19);
5237 unsigned int rd
= bits (insn
, 12, 15);
5238 unsigned int op
= bits (insn
, 21, 24);
5239 int is_mov
= (op
== 0xd);
5240 ULONGEST rd_val
, rn_val
;
5242 if (!insn_references_pc (insn
, 0x000ff000ul
))
5243 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5245 if (debug_displaced
)
5246 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5247 "%.8lx\n", is_mov
? "move" : "ALU",
5248 (unsigned long) insn
);
5250 /* Instruction is of form:
5252 <op><cond> rd, [rn,] #imm
5256 Preparation: tmp1, tmp2 <- r0, r1;
5258 Insn: <op><cond> r0, r1, #imm
5259 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5262 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5263 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5264 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5265 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5266 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5267 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5271 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5273 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5275 dsc
->cleanup
= &cleanup_alu_imm
;
5281 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5282 uint16_t insn2
, struct regcache
*regs
,
5283 struct displaced_step_closure
*dsc
)
5285 unsigned int op
= bits (insn1
, 5, 8);
5286 unsigned int rn
, rm
, rd
;
5287 ULONGEST rd_val
, rn_val
;
5289 rn
= bits (insn1
, 0, 3); /* Rn */
5290 rm
= bits (insn2
, 0, 3); /* Rm */
5291 rd
= bits (insn2
, 8, 11); /* Rd */
5293 /* This routine is only called for instruction MOV. */
5294 gdb_assert (op
== 0x2 && rn
== 0xf);
5296 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5297 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5299 if (debug_displaced
)
5300 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5301 "ALU", insn1
, insn2
);
5303 /* Instruction is of form:
5305 <op><cond> rd, [rn,] #imm
5309 Preparation: tmp1, tmp2 <- r0, r1;
5311 Insn: <op><cond> r0, r1, #imm
5312 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5315 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5316 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5317 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5318 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5319 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5320 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5323 dsc
->modinsn
[0] = insn1
;
5324 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5327 dsc
->cleanup
= &cleanup_alu_imm
;
5332 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5335 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5336 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5341 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5343 for (i
= 0; i
< 3; i
++)
5344 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5346 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5350 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5351 struct displaced_step_closure
*dsc
,
5352 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5354 ULONGEST rd_val
, rn_val
, rm_val
;
5356 /* Instruction is of form:
5358 <op><cond> rd, [rn,] rm [, <shift>]
5362 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5363 r0, r1, r2 <- rd, rn, rm
5364 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5365 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5368 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5369 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5370 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5371 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5372 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5373 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5374 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5375 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5376 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5379 dsc
->cleanup
= &cleanup_alu_reg
;
5383 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5384 struct displaced_step_closure
*dsc
)
5386 unsigned int op
= bits (insn
, 21, 24);
5387 int is_mov
= (op
== 0xd);
5389 if (!insn_references_pc (insn
, 0x000ff00ful
))
5390 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5392 if (debug_displaced
)
5393 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5394 is_mov
? "move" : "ALU", (unsigned long) insn
);
5397 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5399 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5401 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5407 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5408 struct regcache
*regs
,
5409 struct displaced_step_closure
*dsc
)
5413 rm
= bits (insn
, 3, 6);
5414 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5416 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5417 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5419 if (debug_displaced
)
5420 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5421 (unsigned short) insn
);
5423 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5425 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5430 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5433 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5434 struct regcache
*regs
,
5435 struct displaced_step_closure
*dsc
)
5437 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5440 for (i
= 0; i
< 4; i
++)
5441 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5443 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5447 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5448 struct displaced_step_closure
*dsc
,
5449 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5453 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5455 /* Instruction is of form:
5457 <op><cond> rd, [rn,] rm, <shift> rs
5461 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5462 r0, r1, r2, r3 <- rd, rn, rm, rs
5463 Insn: <op><cond> r0, r1, r2, <shift> r3
5465 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5469 for (i
= 0; i
< 4; i
++)
5470 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5472 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5473 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5474 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5475 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5476 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5477 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5478 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5479 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5481 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5485 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5486 struct regcache
*regs
,
5487 struct displaced_step_closure
*dsc
)
5489 unsigned int op
= bits (insn
, 21, 24);
5490 int is_mov
= (op
== 0xd);
5491 unsigned int rd
, rn
, rm
, rs
;
5493 if (!insn_references_pc (insn
, 0x000fff0ful
))
5494 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5496 if (debug_displaced
)
5497 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5498 "%.8lx\n", is_mov
? "move" : "ALU",
5499 (unsigned long) insn
);
5501 rn
= bits (insn
, 16, 19);
5502 rm
= bits (insn
, 0, 3);
5503 rs
= bits (insn
, 8, 11);
5504 rd
= bits (insn
, 12, 15);
5507 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5509 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5511 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5516 /* Clean up load instructions. */
5519 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5520 struct displaced_step_closure
*dsc
)
5522 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5524 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5525 if (dsc
->u
.ldst
.xfersize
== 8)
5526 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5527 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5529 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5530 if (dsc
->u
.ldst
.xfersize
> 4)
5531 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5532 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5533 if (!dsc
->u
.ldst
.immed
)
5534 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5536 /* Handle register writeback. */
5537 if (dsc
->u
.ldst
.writeback
)
5538 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5539 /* Put result in right place. */
5540 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5541 if (dsc
->u
.ldst
.xfersize
== 8)
5542 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5545 /* Clean up store instructions. */
5548 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5549 struct displaced_step_closure
*dsc
)
5551 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5553 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5554 if (dsc
->u
.ldst
.xfersize
> 4)
5555 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5556 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5557 if (!dsc
->u
.ldst
.immed
)
5558 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5559 if (!dsc
->u
.ldst
.restore_r4
)
5560 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5563 if (dsc
->u
.ldst
.writeback
)
5564 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5567 /* Copy "extra" load/store instructions. These are halfword/doubleword
5568 transfers, which have a different encoding to byte/word transfers. */
5571 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5572 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5574 unsigned int op1
= bits (insn
, 20, 24);
5575 unsigned int op2
= bits (insn
, 5, 6);
5576 unsigned int rt
= bits (insn
, 12, 15);
5577 unsigned int rn
= bits (insn
, 16, 19);
5578 unsigned int rm
= bits (insn
, 0, 3);
5579 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5580 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5581 int immed
= (op1
& 0x4) != 0;
5583 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5585 if (!insn_references_pc (insn
, 0x000ff00ful
))
5586 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5588 if (debug_displaced
)
5589 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5590 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5591 (unsigned long) insn
);
5593 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5596 internal_error (__FILE__
, __LINE__
,
5597 _("copy_extra_ld_st: instruction decode error"));
5599 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5600 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5601 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5603 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5605 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5606 if (bytesize
[opcode
] == 8)
5607 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5608 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5610 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5612 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5613 if (bytesize
[opcode
] == 8)
5614 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5615 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5617 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5620 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5621 dsc
->u
.ldst
.rn
= rn
;
5622 dsc
->u
.ldst
.immed
= immed
;
5623 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5624 dsc
->u
.ldst
.restore_r4
= 0;
5627 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5629 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5630 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5632 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5634 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5635 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5637 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5642 /* Copy byte/half word/word loads and stores. */
5645 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5646 struct displaced_step_closure
*dsc
, int load
,
5647 int immed
, int writeback
, int size
, int usermode
,
5648 int rt
, int rm
, int rn
)
5650 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5652 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5653 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5655 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5657 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5659 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5660 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5662 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5664 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5665 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5667 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5669 dsc
->u
.ldst
.xfersize
= size
;
5670 dsc
->u
.ldst
.rn
= rn
;
5671 dsc
->u
.ldst
.immed
= immed
;
5672 dsc
->u
.ldst
.writeback
= writeback
;
5674 /* To write PC we can do:
5676 Before this sequence of instructions:
5677 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5678 r2 is the Rn value got from dispalced_read_reg.
5680 Insn1: push {pc} Write address of STR instruction + offset on stack
5681 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5682 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5683 = addr(Insn1) + offset - addr(Insn3) - 8
5685 Insn4: add r4, r4, #8 r4 = offset - 8
5686 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5688 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5690 Otherwise we don't know what value to write for PC, since the offset is
5691 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5692 of this can be found in Section "Saving from r15" in
5693 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5695 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5700 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5701 uint16_t insn2
, struct regcache
*regs
,
5702 struct displaced_step_closure
*dsc
, int size
)
5704 unsigned int u_bit
= bit (insn1
, 7);
5705 unsigned int rt
= bits (insn2
, 12, 15);
5706 int imm12
= bits (insn2
, 0, 11);
5709 if (debug_displaced
)
5710 fprintf_unfiltered (gdb_stdlog
,
5711 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5712 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5718 /* Rewrite instruction LDR Rt imm12 into:
5720 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5724 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5727 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5728 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5729 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5731 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5733 pc_val
= pc_val
& 0xfffffffc;
5735 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5736 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5740 dsc
->u
.ldst
.xfersize
= size
;
5741 dsc
->u
.ldst
.immed
= 0;
5742 dsc
->u
.ldst
.writeback
= 0;
5743 dsc
->u
.ldst
.restore_r4
= 0;
5745 /* LDR R0, R2, R3 */
5746 dsc
->modinsn
[0] = 0xf852;
5747 dsc
->modinsn
[1] = 0x3;
5750 dsc
->cleanup
= &cleanup_load
;
5756 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5757 uint16_t insn2
, struct regcache
*regs
,
5758 struct displaced_step_closure
*dsc
,
5759 int writeback
, int immed
)
5761 unsigned int rt
= bits (insn2
, 12, 15);
5762 unsigned int rn
= bits (insn1
, 0, 3);
5763 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5764 /* In LDR (register), there is also a register Rm, which is not allowed to
5765 be PC, so we don't have to check it. */
5767 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5768 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5771 if (debug_displaced
)
5772 fprintf_unfiltered (gdb_stdlog
,
5773 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5774 rt
, rn
, insn1
, insn2
);
5776 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5779 dsc
->u
.ldst
.restore_r4
= 0;
5782 /* ldr[b]<cond> rt, [rn, #imm], etc.
5784 ldr[b]<cond> r0, [r2, #imm]. */
5786 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5787 dsc
->modinsn
[1] = insn2
& 0x0fff;
5790 /* ldr[b]<cond> rt, [rn, rm], etc.
5792 ldr[b]<cond> r0, [r2, r3]. */
5794 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5795 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5805 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5806 struct regcache
*regs
,
5807 struct displaced_step_closure
*dsc
,
5808 int load
, int size
, int usermode
)
5810 int immed
= !bit (insn
, 25);
5811 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5812 unsigned int rt
= bits (insn
, 12, 15);
5813 unsigned int rn
= bits (insn
, 16, 19);
5814 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5816 if (!insn_references_pc (insn
, 0x000ff00ful
))
5817 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5819 if (debug_displaced
)
5820 fprintf_unfiltered (gdb_stdlog
,
5821 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5822 load
? (size
== 1 ? "ldrb" : "ldr")
5823 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5825 (unsigned long) insn
);
5827 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5828 usermode
, rt
, rm
, rn
);
5830 if (load
|| rt
!= ARM_PC_REGNUM
)
5832 dsc
->u
.ldst
.restore_r4
= 0;
5835 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5837 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5838 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5840 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5842 {ldr,str}[b]<cond> r0, [r2, r3]. */
5843 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5847 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5848 dsc
->u
.ldst
.restore_r4
= 1;
5849 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5850 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5851 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5852 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5853 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5857 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5859 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5864 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5869 /* Cleanup LDM instructions with fully-populated register list. This is an
5870 unfortunate corner case: it's impossible to implement correctly by modifying
5871 the instruction. The issue is as follows: we have an instruction,
5875 which we must rewrite to avoid loading PC. A possible solution would be to
5876 do the load in two halves, something like (with suitable cleanup
5880 ldm[id][ab] r8!, {r0-r7}
5882 ldm[id][ab] r8, {r7-r14}
5885 but at present there's no suitable place for <temp>, since the scratch space
5886 is overwritten before the cleanup routine is called. For now, we simply
5887 emulate the instruction. */
5890 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5891 struct displaced_step_closure
*dsc
)
5893 int inc
= dsc
->u
.block
.increment
;
5894 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5895 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5896 uint32_t regmask
= dsc
->u
.block
.regmask
;
5897 int regno
= inc
? 0 : 15;
5898 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5899 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5900 && (regmask
& 0x8000) != 0;
5901 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5902 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5903 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5908 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5909 sensible we can do here. Complain loudly. */
5910 if (exception_return
)
5911 error (_("Cannot single-step exception return"));
5913 /* We don't handle any stores here for now. */
5914 gdb_assert (dsc
->u
.block
.load
!= 0);
5916 if (debug_displaced
)
5917 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5918 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5919 dsc
->u
.block
.increment
? "inc" : "dec",
5920 dsc
->u
.block
.before
? "before" : "after");
5927 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5930 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5933 xfer_addr
+= bump_before
;
5935 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5936 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5938 xfer_addr
+= bump_after
;
5940 regmask
&= ~(1 << regno
);
5943 if (dsc
->u
.block
.writeback
)
5944 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5948 /* Clean up an STM which included the PC in the register list. */
5951 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5952 struct displaced_step_closure
*dsc
)
5954 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5955 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5956 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5957 CORE_ADDR stm_insn_addr
;
5960 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5962 /* If condition code fails, there's nothing else to do. */
5963 if (!store_executed
)
5966 if (dsc
->u
.block
.increment
)
5968 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5970 if (dsc
->u
.block
.before
)
5975 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5977 if (dsc
->u
.block
.before
)
5981 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5982 stm_insn_addr
= dsc
->scratch_base
;
5983 offset
= pc_val
- stm_insn_addr
;
5985 if (debug_displaced
)
5986 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5987 "STM instruction\n", offset
);
5989 /* Rewrite the stored PC to the proper value for the non-displaced original
5991 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5992 dsc
->insn_addr
+ offset
);
5995 /* Clean up an LDM which includes the PC in the register list. We clumped all
5996 the registers in the transferred list into a contiguous range r0...rX (to
5997 avoid loading PC directly and losing control of the debugged program), so we
5998 must undo that here. */
6001 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6002 struct regcache
*regs
,
6003 struct displaced_step_closure
*dsc
)
6005 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6006 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6007 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
6008 unsigned int regs_loaded
= bitcount (mask
);
6009 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6011 /* The method employed here will fail if the register list is fully populated
6012 (we need to avoid loading PC directly). */
6013 gdb_assert (num_to_shuffle
< 16);
6018 clobbered
= (1 << num_to_shuffle
) - 1;
6020 while (num_to_shuffle
> 0)
6022 if ((mask
& (1 << write_reg
)) != 0)
6024 unsigned int read_reg
= num_to_shuffle
- 1;
6026 if (read_reg
!= write_reg
)
6028 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6029 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6030 if (debug_displaced
)
6031 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6032 "loaded register r%d to r%d\n"), read_reg
,
6035 else if (debug_displaced
)
6036 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6037 "r%d already in the right place\n"),
6040 clobbered
&= ~(1 << write_reg
);
6048 /* Restore any registers we scribbled over. */
6049 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6051 if ((clobbered
& (1 << write_reg
)) != 0)
6053 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6055 if (debug_displaced
)
6056 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6057 "clobbered register r%d\n"), write_reg
);
6058 clobbered
&= ~(1 << write_reg
);
6062 /* Perform register writeback manually. */
6063 if (dsc
->u
.block
.writeback
)
6065 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6067 if (dsc
->u
.block
.increment
)
6068 new_rn_val
+= regs_loaded
* 4;
6070 new_rn_val
-= regs_loaded
* 4;
6072 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6077 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6078 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6081 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6082 struct regcache
*regs
,
6083 struct displaced_step_closure
*dsc
)
6085 int load
= bit (insn
, 20);
6086 int user
= bit (insn
, 22);
6087 int increment
= bit (insn
, 23);
6088 int before
= bit (insn
, 24);
6089 int writeback
= bit (insn
, 21);
6090 int rn
= bits (insn
, 16, 19);
6092 /* Block transfers which don't mention PC can be run directly
6094 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6095 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6097 if (rn
== ARM_PC_REGNUM
)
6099 warning (_("displaced: Unpredictable LDM or STM with "
6100 "base register r15"));
6101 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6104 if (debug_displaced
)
6105 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6106 "%.8lx\n", (unsigned long) insn
);
6108 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6109 dsc
->u
.block
.rn
= rn
;
6111 dsc
->u
.block
.load
= load
;
6112 dsc
->u
.block
.user
= user
;
6113 dsc
->u
.block
.increment
= increment
;
6114 dsc
->u
.block
.before
= before
;
6115 dsc
->u
.block
.writeback
= writeback
;
6116 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6118 dsc
->u
.block
.regmask
= insn
& 0xffff;
6122 if ((insn
& 0xffff) == 0xffff)
6124 /* LDM with a fully-populated register list. This case is
6125 particularly tricky. Implement for now by fully emulating the
6126 instruction (which might not behave perfectly in all cases, but
6127 these instructions should be rare enough for that not to matter
6129 dsc
->modinsn
[0] = ARM_NOP
;
6131 dsc
->cleanup
= &cleanup_block_load_all
;
6135 /* LDM of a list of registers which includes PC. Implement by
6136 rewriting the list of registers to be transferred into a
6137 contiguous chunk r0...rX before doing the transfer, then shuffling
6138 registers into the correct places in the cleanup routine. */
6139 unsigned int regmask
= insn
& 0xffff;
6140 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6143 for (i
= 0; i
< num_in_list
; i
++)
6144 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6146 /* Writeback makes things complicated. We need to avoid clobbering
6147 the base register with one of the registers in our modified
6148 register list, but just using a different register can't work in
6151 ldm r14!, {r0-r13,pc}
6153 which would need to be rewritten as:
6157 but that can't work, because there's no free register for N.
6159 Solve this by turning off the writeback bit, and emulating
6160 writeback manually in the cleanup routine. */
6165 new_regmask
= (1 << num_in_list
) - 1;
6167 if (debug_displaced
)
6168 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6169 "{..., pc}: original reg list %.4x, modified "
6170 "list %.4x\n"), rn
, writeback
? "!" : "",
6171 (int) insn
& 0xffff, new_regmask
);
6173 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6175 dsc
->cleanup
= &cleanup_block_load_pc
;
6180 /* STM of a list of registers which includes PC. Run the instruction
6181 as-is, but out of line: this will store the wrong value for the PC,
6182 so we must manually fix up the memory in the cleanup routine.
6183 Doing things this way has the advantage that we can auto-detect
6184 the offset of the PC write (which is architecture-dependent) in
6185 the cleanup routine. */
6186 dsc
->modinsn
[0] = insn
;
6188 dsc
->cleanup
= &cleanup_block_store_pc
;
6195 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6196 struct regcache
*regs
,
6197 struct displaced_step_closure
*dsc
)
6199 int rn
= bits (insn1
, 0, 3);
6200 int load
= bit (insn1
, 4);
6201 int writeback
= bit (insn1
, 5);
6203 /* Block transfers which don't mention PC can be run directly
6205 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6206 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6208 if (rn
== ARM_PC_REGNUM
)
6210 warning (_("displaced: Unpredictable LDM or STM with "
6211 "base register r15"));
6212 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6213 "unpredictable ldm/stm", dsc
);
6216 if (debug_displaced
)
6217 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6218 "%.4x%.4x\n", insn1
, insn2
);
6220 /* Clear bit 13, since it should be always zero. */
6221 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6222 dsc
->u
.block
.rn
= rn
;
6224 dsc
->u
.block
.load
= load
;
6225 dsc
->u
.block
.user
= 0;
6226 dsc
->u
.block
.increment
= bit (insn1
, 7);
6227 dsc
->u
.block
.before
= bit (insn1
, 8);
6228 dsc
->u
.block
.writeback
= writeback
;
6229 dsc
->u
.block
.cond
= INST_AL
;
6230 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6234 if (dsc
->u
.block
.regmask
== 0xffff)
6236 /* This branch is impossible to happen. */
6241 unsigned int regmask
= dsc
->u
.block
.regmask
;
6242 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6245 for (i
= 0; i
< num_in_list
; i
++)
6246 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6251 new_regmask
= (1 << num_in_list
) - 1;
6253 if (debug_displaced
)
6254 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6255 "{..., pc}: original reg list %.4x, modified "
6256 "list %.4x\n"), rn
, writeback
? "!" : "",
6257 (int) dsc
->u
.block
.regmask
, new_regmask
);
6259 dsc
->modinsn
[0] = insn1
;
6260 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6263 dsc
->cleanup
= &cleanup_block_load_pc
;
6268 dsc
->modinsn
[0] = insn1
;
6269 dsc
->modinsn
[1] = insn2
;
6271 dsc
->cleanup
= &cleanup_block_store_pc
;
6276 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6277 This is used to avoid a dependency on BFD's bfd_endian enum. */
6280 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6283 return read_memory_unsigned_integer (memaddr
, len
,
6284 (enum bfd_endian
) byte_order
);
6287 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6290 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6293 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6296 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6299 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6304 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6307 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6309 return arm_is_thumb (self
->regcache
);
6312 /* single_step() is called just before we want to resume the inferior,
6313 if we want to single-step it but there is no hardware or kernel
6314 single-step support. We find the target of the coming instructions
6315 and breakpoint them. */
6318 arm_software_single_step (struct frame_info
*frame
)
6320 struct regcache
*regcache
= get_current_regcache ();
6321 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6322 struct address_space
*aspace
= get_regcache_aspace (regcache
);
6323 struct arm_get_next_pcs next_pcs_ctx
;
6326 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6327 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6329 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6330 &arm_get_next_pcs_ops
,
6331 gdbarch_byte_order (gdbarch
),
6332 gdbarch_byte_order_for_code (gdbarch
),
6336 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6338 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6339 arm_insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
6341 do_cleanups (old_chain
);
6346 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6347 for Linux, where some SVC instructions must be treated specially. */
6350 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6351 struct displaced_step_closure
*dsc
)
6353 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6355 if (debug_displaced
)
6356 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6357 "%.8lx\n", (unsigned long) resume_addr
);
6359 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6363 /* Common copy routine for svc instruciton. */
6366 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6367 struct displaced_step_closure
*dsc
)
6369 /* Preparation: none.
6370 Insn: unmodified svc.
6371 Cleanup: pc <- insn_addr + insn_size. */
6373 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6375 dsc
->wrote_to_pc
= 1;
6377 /* Allow OS-specific code to override SVC handling. */
6378 if (dsc
->u
.svc
.copy_svc_os
)
6379 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6382 dsc
->cleanup
= &cleanup_svc
;
6388 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6389 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6392 if (debug_displaced
)
6393 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6394 (unsigned long) insn
);
6396 dsc
->modinsn
[0] = insn
;
6398 return install_svc (gdbarch
, regs
, dsc
);
6402 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6403 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6406 if (debug_displaced
)
6407 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6410 dsc
->modinsn
[0] = insn
;
6412 return install_svc (gdbarch
, regs
, dsc
);
6415 /* Copy undefined instructions. */
6418 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6419 struct displaced_step_closure
*dsc
)
6421 if (debug_displaced
)
6422 fprintf_unfiltered (gdb_stdlog
,
6423 "displaced: copying undefined insn %.8lx\n",
6424 (unsigned long) insn
);
6426 dsc
->modinsn
[0] = insn
;
6432 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6433 struct displaced_step_closure
*dsc
)
6436 if (debug_displaced
)
6437 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6438 "%.4x %.4x\n", (unsigned short) insn1
,
6439 (unsigned short) insn2
);
6441 dsc
->modinsn
[0] = insn1
;
6442 dsc
->modinsn
[1] = insn2
;
6448 /* Copy unpredictable instructions. */
6451 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6452 struct displaced_step_closure
*dsc
)
6454 if (debug_displaced
)
6455 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6456 "%.8lx\n", (unsigned long) insn
);
6458 dsc
->modinsn
[0] = insn
;
6463 /* The decode_* functions are instruction decoding helpers. They mostly follow
6464 the presentation in the ARM ARM. */
6467 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6468 struct regcache
*regs
,
6469 struct displaced_step_closure
*dsc
)
6471 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6472 unsigned int rn
= bits (insn
, 16, 19);
6474 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6475 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6476 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6477 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6478 else if ((op1
& 0x60) == 0x20)
6479 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6480 else if ((op1
& 0x71) == 0x40)
6481 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6483 else if ((op1
& 0x77) == 0x41)
6484 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6485 else if ((op1
& 0x77) == 0x45)
6486 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6487 else if ((op1
& 0x77) == 0x51)
6490 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6492 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6494 else if ((op1
& 0x77) == 0x55)
6495 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6496 else if (op1
== 0x57)
6499 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6500 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6501 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6502 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6503 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6505 else if ((op1
& 0x63) == 0x43)
6506 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6507 else if ((op2
& 0x1) == 0x0)
6508 switch (op1
& ~0x80)
6511 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6513 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6514 case 0x71: case 0x75:
6516 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6517 case 0x63: case 0x67: case 0x73: case 0x77:
6518 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6520 return arm_copy_undef (gdbarch
, insn
, dsc
);
6523 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6527 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6528 struct regcache
*regs
,
6529 struct displaced_step_closure
*dsc
)
6531 if (bit (insn
, 27) == 0)
6532 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6533 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6534 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6537 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6540 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6542 case 0x4: case 0x5: case 0x6: case 0x7:
6543 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6546 switch ((insn
& 0xe00000) >> 21)
6548 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6550 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6553 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6556 return arm_copy_undef (gdbarch
, insn
, dsc
);
6561 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6562 switch ((insn
& 0xe00000) >> 21)
6565 /* ldc/ldc2 imm (undefined for rn == pc). */
6566 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6567 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6570 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6572 case 0x4: case 0x5: case 0x6: case 0x7:
6573 /* ldc/ldc2 lit (undefined for rn != pc). */
6574 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6575 : arm_copy_undef (gdbarch
, insn
, dsc
);
6578 return arm_copy_undef (gdbarch
, insn
, dsc
);
6583 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6586 if (bits (insn
, 16, 19) == 0xf)
6588 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6590 return arm_copy_undef (gdbarch
, insn
, dsc
);
6594 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6596 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6600 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6602 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6605 return arm_copy_undef (gdbarch
, insn
, dsc
);
6609 /* Decode miscellaneous instructions in dp/misc encoding space. */
6612 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6613 struct regcache
*regs
,
6614 struct displaced_step_closure
*dsc
)
6616 unsigned int op2
= bits (insn
, 4, 6);
6617 unsigned int op
= bits (insn
, 21, 22);
6622 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6625 if (op
== 0x1) /* bx. */
6626 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6628 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6630 return arm_copy_undef (gdbarch
, insn
, dsc
);
6634 /* Not really supported. */
6635 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6637 return arm_copy_undef (gdbarch
, insn
, dsc
);
6641 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6642 regs
, dsc
); /* blx register. */
6644 return arm_copy_undef (gdbarch
, insn
, dsc
);
6647 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6651 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6653 /* Not really supported. */
6654 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6657 return arm_copy_undef (gdbarch
, insn
, dsc
);
6662 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6663 struct regcache
*regs
,
6664 struct displaced_step_closure
*dsc
)
6667 switch (bits (insn
, 20, 24))
6670 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6673 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6675 case 0x12: case 0x16:
6676 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6679 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6683 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6685 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6686 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6687 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6688 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6689 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6690 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6691 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6692 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6693 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6694 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6695 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6696 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6697 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6698 /* 2nd arg means "unprivileged". */
6699 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6703 /* Should be unreachable. */
6708 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6709 struct regcache
*regs
,
6710 struct displaced_step_closure
*dsc
)
6712 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6713 uint32_t op1
= bits (insn
, 20, 24);
6715 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6716 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6717 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6718 else if ((!a
&& (op1
& 0x17) == 0x02)
6719 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6720 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6721 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6722 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6723 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6724 else if ((!a
&& (op1
& 0x17) == 0x03)
6725 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6726 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6727 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6728 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6729 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6730 else if ((!a
&& (op1
& 0x17) == 0x06)
6731 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6732 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6733 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6734 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6735 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6736 else if ((!a
&& (op1
& 0x17) == 0x07)
6737 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6738 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6740 /* Should be unreachable. */
6745 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6746 struct displaced_step_closure
*dsc
)
6748 switch (bits (insn
, 20, 24))
6750 case 0x00: case 0x01: case 0x02: case 0x03:
6751 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6753 case 0x04: case 0x05: case 0x06: case 0x07:
6754 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6756 case 0x08: case 0x09: case 0x0a: case 0x0b:
6757 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6758 return arm_copy_unmodified (gdbarch
, insn
,
6759 "decode/pack/unpack/saturate/reverse", dsc
);
6762 if (bits (insn
, 5, 7) == 0) /* op2. */
6764 if (bits (insn
, 12, 15) == 0xf)
6765 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6767 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6770 return arm_copy_undef (gdbarch
, insn
, dsc
);
6772 case 0x1a: case 0x1b:
6773 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6774 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6776 return arm_copy_undef (gdbarch
, insn
, dsc
);
6778 case 0x1c: case 0x1d:
6779 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6781 if (bits (insn
, 0, 3) == 0xf)
6782 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6784 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6787 return arm_copy_undef (gdbarch
, insn
, dsc
);
6789 case 0x1e: case 0x1f:
6790 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6791 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6793 return arm_copy_undef (gdbarch
, insn
, dsc
);
6796 /* Should be unreachable. */
6801 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6802 struct regcache
*regs
,
6803 struct displaced_step_closure
*dsc
)
6806 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6808 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6812 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6813 struct regcache
*regs
,
6814 struct displaced_step_closure
*dsc
)
6816 unsigned int opcode
= bits (insn
, 20, 24);
6820 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6821 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6823 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6824 case 0x12: case 0x16:
6825 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6827 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6828 case 0x13: case 0x17:
6829 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6831 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6832 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6833 /* Note: no writeback for these instructions. Bit 25 will always be
6834 zero though (via caller), so the following works OK. */
6835 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6838 /* Should be unreachable. */
6842 /* Decode shifted register instructions. */
6845 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6846 uint16_t insn2
, struct regcache
*regs
,
6847 struct displaced_step_closure
*dsc
)
6849 /* PC is only allowed to be used in instruction MOV. */
6851 unsigned int op
= bits (insn1
, 5, 8);
6852 unsigned int rn
= bits (insn1
, 0, 3);
6854 if (op
== 0x2 && rn
== 0xf) /* MOV */
6855 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6857 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6858 "dp (shift reg)", dsc
);
6862 /* Decode extension register load/store. Exactly the same as
6863 arm_decode_ext_reg_ld_st. */
6866 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6867 uint16_t insn2
, struct regcache
*regs
,
6868 struct displaced_step_closure
*dsc
)
6870 unsigned int opcode
= bits (insn1
, 4, 8);
6874 case 0x04: case 0x05:
6875 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6876 "vfp/neon vmov", dsc
);
6878 case 0x08: case 0x0c: /* 01x00 */
6879 case 0x0a: case 0x0e: /* 01x10 */
6880 case 0x12: case 0x16: /* 10x10 */
6881 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6882 "vfp/neon vstm/vpush", dsc
);
6884 case 0x09: case 0x0d: /* 01x01 */
6885 case 0x0b: case 0x0f: /* 01x11 */
6886 case 0x13: case 0x17: /* 10x11 */
6887 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6888 "vfp/neon vldm/vpop", dsc
);
6890 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6891 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6893 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6894 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6897 /* Should be unreachable. */
6902 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6903 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6905 unsigned int op1
= bits (insn
, 20, 25);
6906 int op
= bit (insn
, 4);
6907 unsigned int coproc
= bits (insn
, 8, 11);
6909 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6910 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6911 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6912 && (coproc
& 0xe) != 0xa)
6914 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6915 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6916 && (coproc
& 0xe) != 0xa)
6917 /* ldc/ldc2 imm/lit. */
6918 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6919 else if ((op1
& 0x3e) == 0x00)
6920 return arm_copy_undef (gdbarch
, insn
, dsc
);
6921 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6922 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6923 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6924 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6925 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6926 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6927 else if ((op1
& 0x30) == 0x20 && !op
)
6929 if ((coproc
& 0xe) == 0xa)
6930 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6932 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6934 else if ((op1
& 0x30) == 0x20 && op
)
6935 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6936 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6937 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6938 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6939 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6940 else if ((op1
& 0x30) == 0x30)
6941 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6943 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6947 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6948 uint16_t insn2
, struct regcache
*regs
,
6949 struct displaced_step_closure
*dsc
)
6951 unsigned int coproc
= bits (insn2
, 8, 11);
6952 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6953 unsigned int bit_9
= bit (insn1
, 9);
6954 unsigned int bit_4
= bit (insn1
, 4);
6959 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6960 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6962 else if (bit_5_8
== 0) /* UNDEFINED. */
6963 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6966 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6967 if ((coproc
& 0xe) == 0xa)
6968 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6970 else /* coproc is not 101x. */
6972 if (bit_4
== 0) /* STC/STC2. */
6973 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6975 else /* LDC/LDC2 {literal, immeidate}. */
6976 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6982 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6988 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6989 struct displaced_step_closure
*dsc
, int rd
)
6995 Preparation: Rd <- PC
7001 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7002 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7006 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7007 struct displaced_step_closure
*dsc
,
7008 int rd
, unsigned int imm
)
7011 /* Encoding T2: ADDS Rd, #imm */
7012 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7014 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7020 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7021 struct regcache
*regs
,
7022 struct displaced_step_closure
*dsc
)
7024 unsigned int rd
= bits (insn
, 8, 10);
7025 unsigned int imm8
= bits (insn
, 0, 7);
7027 if (debug_displaced
)
7028 fprintf_unfiltered (gdb_stdlog
,
7029 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7032 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7036 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7037 uint16_t insn2
, struct regcache
*regs
,
7038 struct displaced_step_closure
*dsc
)
7040 unsigned int rd
= bits (insn2
, 8, 11);
7041 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7042 extract raw immediate encoding rather than computing immediate. When
7043 generating ADD or SUB instruction, we can simply perform OR operation to
7044 set immediate into ADD. */
7045 unsigned int imm_3_8
= insn2
& 0x70ff;
7046 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7048 if (debug_displaced
)
7049 fprintf_unfiltered (gdb_stdlog
,
7050 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7051 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7053 if (bit (insn1
, 7)) /* Encoding T2 */
7055 /* Encoding T3: SUB Rd, Rd, #imm */
7056 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7057 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7059 else /* Encoding T3 */
7061 /* Encoding T3: ADD Rd, Rd, #imm */
7062 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7063 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7067 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7073 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7074 struct regcache
*regs
,
7075 struct displaced_step_closure
*dsc
)
7077 unsigned int rt
= bits (insn1
, 8, 10);
7079 int imm8
= (bits (insn1
, 0, 7) << 2);
7085 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7087 Insn: LDR R0, [R2, R3];
7088 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7090 if (debug_displaced
)
7091 fprintf_unfiltered (gdb_stdlog
,
7092 "displaced: copying thumb ldr r%d [pc #%d]\n"
7095 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7096 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7097 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7098 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7099 /* The assembler calculates the required value of the offset from the
7100 Align(PC,4) value of this instruction to the label. */
7101 pc
= pc
& 0xfffffffc;
7103 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7104 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7107 dsc
->u
.ldst
.xfersize
= 4;
7109 dsc
->u
.ldst
.immed
= 0;
7110 dsc
->u
.ldst
.writeback
= 0;
7111 dsc
->u
.ldst
.restore_r4
= 0;
7113 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7115 dsc
->cleanup
= &cleanup_load
;
7120 /* Copy Thumb cbnz/cbz insruction. */
7123 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7124 struct regcache
*regs
,
7125 struct displaced_step_closure
*dsc
)
7127 int non_zero
= bit (insn1
, 11);
7128 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7129 CORE_ADDR from
= dsc
->insn_addr
;
7130 int rn
= bits (insn1
, 0, 2);
7131 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7133 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7134 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7135 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7136 condition is false, let it be, cleanup_branch will do nothing. */
7137 if (dsc
->u
.branch
.cond
)
7139 dsc
->u
.branch
.cond
= INST_AL
;
7140 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7143 dsc
->u
.branch
.dest
= from
+ 2;
7145 dsc
->u
.branch
.link
= 0;
7146 dsc
->u
.branch
.exchange
= 0;
7148 if (debug_displaced
)
7149 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7150 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7151 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7153 dsc
->modinsn
[0] = THUMB_NOP
;
7155 dsc
->cleanup
= &cleanup_branch
;
7159 /* Copy Table Branch Byte/Halfword */
7161 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7162 uint16_t insn2
, struct regcache
*regs
,
7163 struct displaced_step_closure
*dsc
)
7165 ULONGEST rn_val
, rm_val
;
7166 int is_tbh
= bit (insn2
, 4);
7167 CORE_ADDR halfwords
= 0;
7168 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7170 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7171 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7177 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7178 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7184 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7185 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7188 if (debug_displaced
)
7189 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7190 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7191 (unsigned int) rn_val
, (unsigned int) rm_val
,
7192 (unsigned int) halfwords
);
7194 dsc
->u
.branch
.cond
= INST_AL
;
7195 dsc
->u
.branch
.link
= 0;
7196 dsc
->u
.branch
.exchange
= 0;
7197 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7199 dsc
->cleanup
= &cleanup_branch
;
7205 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7206 struct displaced_step_closure
*dsc
)
7209 int val
= displaced_read_reg (regs
, dsc
, 7);
7210 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7213 val
= displaced_read_reg (regs
, dsc
, 8);
7214 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7217 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7222 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7223 struct regcache
*regs
,
7224 struct displaced_step_closure
*dsc
)
7226 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7228 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7231 (1) register list is full, that is, r0-r7 are used.
7232 Prepare: tmp[0] <- r8
7234 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7235 MOV r8, r7; Move value of r7 to r8;
7236 POP {r7}; Store PC value into r7.
7238 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7240 (2) register list is not full, supposing there are N registers in
7241 register list (except PC, 0 <= N <= 7).
7242 Prepare: for each i, 0 - N, tmp[i] <- ri.
7244 POP {r0, r1, ...., rN};
7246 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7247 from tmp[] properly.
7249 if (debug_displaced
)
7250 fprintf_unfiltered (gdb_stdlog
,
7251 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7252 dsc
->u
.block
.regmask
, insn1
);
7254 if (dsc
->u
.block
.regmask
== 0xff)
7256 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7258 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7259 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7260 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7263 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7267 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7269 unsigned int new_regmask
;
7271 for (i
= 0; i
< num_in_list
+ 1; i
++)
7272 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7274 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7276 if (debug_displaced
)
7277 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7278 "{..., pc}: original reg list %.4x,"
7279 " modified list %.4x\n"),
7280 (int) dsc
->u
.block
.regmask
, new_regmask
);
7282 dsc
->u
.block
.regmask
|= 0x8000;
7283 dsc
->u
.block
.writeback
= 0;
7284 dsc
->u
.block
.cond
= INST_AL
;
7286 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7288 dsc
->cleanup
= &cleanup_block_load_pc
;
7295 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7296 struct regcache
*regs
,
7297 struct displaced_step_closure
*dsc
)
7299 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7300 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7303 /* 16-bit thumb instructions. */
7304 switch (op_bit_12_15
)
7306 /* Shift (imme), add, subtract, move and compare. */
7307 case 0: case 1: case 2: case 3:
7308 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7309 "shift/add/sub/mov/cmp",
7313 switch (op_bit_10_11
)
7315 case 0: /* Data-processing */
7316 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7320 case 1: /* Special data instructions and branch and exchange. */
7322 unsigned short op
= bits (insn1
, 7, 9);
7323 if (op
== 6 || op
== 7) /* BX or BLX */
7324 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7325 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7326 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7328 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7332 default: /* LDR (literal) */
7333 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7336 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7337 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7340 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7341 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7342 else /* Generate SP-relative address */
7343 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7345 case 11: /* Misc 16-bit instructions */
7347 switch (bits (insn1
, 8, 11))
7349 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7350 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7352 case 12: case 13: /* POP */
7353 if (bit (insn1
, 8)) /* PC is in register list. */
7354 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7356 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7358 case 15: /* If-Then, and hints */
7359 if (bits (insn1
, 0, 3))
7360 /* If-Then makes up to four following instructions conditional.
7361 IT instruction itself is not conditional, so handle it as a
7362 common unmodified instruction. */
7363 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7366 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7369 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7374 if (op_bit_10_11
< 2) /* Store multiple registers */
7375 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7376 else /* Load multiple registers */
7377 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7379 case 13: /* Conditional branch and supervisor call */
7380 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7381 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7383 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7385 case 14: /* Unconditional branch */
7386 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7393 internal_error (__FILE__
, __LINE__
,
7394 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7398 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7399 uint16_t insn1
, uint16_t insn2
,
7400 struct regcache
*regs
,
7401 struct displaced_step_closure
*dsc
)
7403 int rt
= bits (insn2
, 12, 15);
7404 int rn
= bits (insn1
, 0, 3);
7405 int op1
= bits (insn1
, 7, 8);
7407 switch (bits (insn1
, 5, 6))
7409 case 0: /* Load byte and memory hints */
7410 if (rt
== 0xf) /* PLD/PLI */
7413 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7414 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7416 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7421 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7422 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7425 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7426 "ldrb{reg, immediate}/ldrbt",
7431 case 1: /* Load halfword and memory hints. */
7432 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7433 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7434 "pld/unalloc memhint", dsc
);
7438 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7441 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7445 case 2: /* Load word */
7447 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7450 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7451 else if (op1
== 0x1) /* Encoding T3 */
7452 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7454 else /* op1 == 0x0 */
7456 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7457 /* LDR (immediate) */
7458 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7459 dsc
, bit (insn2
, 8), 1);
7460 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7461 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7464 /* LDR (register) */
7465 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7471 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7478 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7479 uint16_t insn2
, struct regcache
*regs
,
7480 struct displaced_step_closure
*dsc
)
7483 unsigned short op
= bit (insn2
, 15);
7484 unsigned int op1
= bits (insn1
, 11, 12);
7490 switch (bits (insn1
, 9, 10))
7495 /* Load/store {dual, execlusive}, table branch. */
7496 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7497 && bits (insn2
, 5, 7) == 0)
7498 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7501 /* PC is not allowed to use in load/store {dual, exclusive}
7503 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7504 "load/store dual/ex", dsc
);
7506 else /* load/store multiple */
7508 switch (bits (insn1
, 7, 8))
7510 case 0: case 3: /* SRS, RFE */
7511 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7514 case 1: case 2: /* LDM/STM/PUSH/POP */
7515 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7522 /* Data-processing (shift register). */
7523 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7526 default: /* Coprocessor instructions. */
7527 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7532 case 2: /* op1 = 2 */
7533 if (op
) /* Branch and misc control. */
7535 if (bit (insn2
, 14) /* BLX/BL */
7536 || bit (insn2
, 12) /* Unconditional branch */
7537 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7538 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7540 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7545 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7547 int op
= bits (insn1
, 4, 8);
7548 int rn
= bits (insn1
, 0, 3);
7549 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7550 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7553 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7556 else /* Data processing (modified immeidate) */
7557 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7561 case 3: /* op1 = 3 */
7562 switch (bits (insn1
, 9, 10))
7566 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7568 else /* NEON Load/Store and Store single data item */
7569 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7570 "neon elt/struct load/store",
7573 case 1: /* op1 = 3, bits (9, 10) == 1 */
7574 switch (bits (insn1
, 7, 8))
7576 case 0: case 1: /* Data processing (register) */
7577 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7580 case 2: /* Multiply and absolute difference */
7581 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7582 "mul/mua/diff", dsc
);
7584 case 3: /* Long multiply and divide */
7585 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7590 default: /* Coprocessor instructions */
7591 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7600 internal_error (__FILE__
, __LINE__
,
7601 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7606 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7607 struct regcache
*regs
,
7608 struct displaced_step_closure
*dsc
)
7610 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7612 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7614 if (debug_displaced
)
7615 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7616 "at %.8lx\n", insn1
, (unsigned long) from
);
7619 dsc
->insn_size
= thumb_insn_size (insn1
);
7620 if (thumb_insn_size (insn1
) == 4)
7623 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7624 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7627 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7631 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7632 CORE_ADDR to
, struct regcache
*regs
,
7633 struct displaced_step_closure
*dsc
)
7636 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7639 /* Most displaced instructions use a 1-instruction scratch space, so set this
7640 here and override below if/when necessary. */
7642 dsc
->insn_addr
= from
;
7643 dsc
->scratch_base
= to
;
7644 dsc
->cleanup
= NULL
;
7645 dsc
->wrote_to_pc
= 0;
7647 if (!displaced_in_arm_mode (regs
))
7648 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7652 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7653 if (debug_displaced
)
7654 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7655 "at %.8lx\n", (unsigned long) insn
,
7656 (unsigned long) from
);
7658 if ((insn
& 0xf0000000) == 0xf0000000)
7659 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7660 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7662 case 0x0: case 0x1: case 0x2: case 0x3:
7663 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7666 case 0x4: case 0x5: case 0x6:
7667 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7671 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7674 case 0x8: case 0x9: case 0xa: case 0xb:
7675 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7678 case 0xc: case 0xd: case 0xe: case 0xf:
7679 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7684 internal_error (__FILE__
, __LINE__
,
7685 _("arm_process_displaced_insn: Instruction decode error"));
7688 /* Actually set up the scratch space for a displaced instruction. */
7691 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7692 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7694 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7695 unsigned int i
, len
, offset
;
7696 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7697 int size
= dsc
->is_thumb
? 2 : 4;
7698 const gdb_byte
*bkp_insn
;
7701 /* Poke modified instruction(s). */
7702 for (i
= 0; i
< dsc
->numinsns
; i
++)
7704 if (debug_displaced
)
7706 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7708 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7711 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7712 (unsigned short)dsc
->modinsn
[i
]);
7714 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7715 (unsigned long) to
+ offset
);
7718 write_memory_unsigned_integer (to
+ offset
, size
,
7719 byte_order_for_code
,
7724 /* Choose the correct breakpoint instruction. */
7727 bkp_insn
= tdep
->thumb_breakpoint
;
7728 len
= tdep
->thumb_breakpoint_size
;
7732 bkp_insn
= tdep
->arm_breakpoint
;
7733 len
= tdep
->arm_breakpoint_size
;
7736 /* Put breakpoint afterwards. */
7737 write_memory (to
+ offset
, bkp_insn
, len
);
7739 if (debug_displaced
)
7740 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7741 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7744 /* Entry point for cleaning things up after a displaced instruction has been
7748 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7749 struct displaced_step_closure
*dsc
,
7750 CORE_ADDR from
, CORE_ADDR to
,
7751 struct regcache
*regs
)
7754 dsc
->cleanup (gdbarch
, regs
, dsc
);
7756 if (!dsc
->wrote_to_pc
)
7757 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7758 dsc
->insn_addr
+ dsc
->insn_size
);
7762 #include "bfd-in2.h"
7763 #include "libcoff.h"
7766 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7768 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7770 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7772 static asymbol
*asym
;
7773 static combined_entry_type ce
;
7774 static struct coff_symbol_struct csym
;
7775 static struct bfd fake_bfd
;
7776 static bfd_target fake_target
;
7778 if (csym
.native
== NULL
)
7780 /* Create a fake symbol vector containing a Thumb symbol.
7781 This is solely so that the code in print_insn_little_arm()
7782 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7783 the presence of a Thumb symbol and switch to decoding
7784 Thumb instructions. */
7786 fake_target
.flavour
= bfd_target_coff_flavour
;
7787 fake_bfd
.xvec
= &fake_target
;
7788 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7790 csym
.symbol
.the_bfd
= &fake_bfd
;
7791 csym
.symbol
.name
= "fake";
7792 asym
= (asymbol
*) & csym
;
7795 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7796 info
->symbols
= &asym
;
7799 info
->symbols
= NULL
;
7801 if (info
->endian
== BFD_ENDIAN_BIG
)
7802 return print_insn_big_arm (memaddr
, info
);
7804 return print_insn_little_arm (memaddr
, info
);
7807 /* The following define instruction sequences that will cause ARM
7808 cpu's to take an undefined instruction trap. These are used to
7809 signal a breakpoint to GDB.
7811 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7812 modes. A different instruction is required for each mode. The ARM
7813 cpu's can also be big or little endian. Thus four different
7814 instructions are needed to support all cases.
7816 Note: ARMv4 defines several new instructions that will take the
7817 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7818 not in fact add the new instructions. The new undefined
7819 instructions in ARMv4 are all instructions that had no defined
7820 behaviour in earlier chips. There is no guarantee that they will
7821 raise an exception, but may be treated as NOP's. In practice, it
7822 may only safe to rely on instructions matching:
7824 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7825 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7826 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7828 Even this may only true if the condition predicate is true. The
7829 following use a condition predicate of ALWAYS so it is always TRUE.
7831 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7832 and NetBSD all use a software interrupt rather than an undefined
7833 instruction to force a trap. This can be handled by by the
7834 abi-specific code during establishment of the gdbarch vector. */
7836 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7837 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7838 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7839 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7841 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7842 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7843 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7844 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7846 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7849 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7852 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7854 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7856 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7858 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7859 check whether we are replacing a 32-bit instruction. */
7860 if (tdep
->thumb2_breakpoint
!= NULL
)
7864 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7866 unsigned short inst1
;
7868 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7869 if (thumb_insn_size (inst1
) == 4)
7870 return ARM_BP_KIND_THUMB2
;
7874 return ARM_BP_KIND_THUMB
;
7877 return ARM_BP_KIND_ARM
;
7881 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7883 static const gdb_byte
*
7884 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7886 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7890 case ARM_BP_KIND_ARM
:
7891 *size
= tdep
->arm_breakpoint_size
;
7892 return tdep
->arm_breakpoint
;
7893 case ARM_BP_KIND_THUMB
:
7894 *size
= tdep
->thumb_breakpoint_size
;
7895 return tdep
->thumb_breakpoint
;
7896 case ARM_BP_KIND_THUMB2
:
7897 *size
= tdep
->thumb2_breakpoint_size
;
7898 return tdep
->thumb2_breakpoint
;
7900 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7904 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7905 the program counter value to determine whether a 16-bit or 32-bit
7906 breakpoint should be used. It returns a pointer to a string of
7907 bytes that encode a breakpoint instruction, stores the length of
7908 the string to *lenptr, and adjusts the program counter (if
7909 necessary) to point to the actual memory location where the
7910 breakpoint should be inserted. */
7912 GDBARCH_BREAKPOINT_FROM_PC (arm
)
7914 /* Extract from an array REGBUF containing the (raw) register state a
7915 function return value of type TYPE, and copy that, in virtual
7916 format, into VALBUF. */
7919 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7922 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7925 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7927 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7931 /* The value is in register F0 in internal format. We need to
7932 extract the raw value and then convert it to the desired
7934 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7936 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7937 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7938 valbuf
, gdbarch_byte_order (gdbarch
));
7942 case ARM_FLOAT_SOFT_FPA
:
7943 case ARM_FLOAT_SOFT_VFP
:
7944 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7945 not using the VFP ABI code. */
7947 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7948 if (TYPE_LENGTH (type
) > 4)
7949 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7950 valbuf
+ INT_REGISTER_SIZE
);
7954 internal_error (__FILE__
, __LINE__
,
7955 _("arm_extract_return_value: "
7956 "Floating point model not supported"));
7960 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7961 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7962 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7963 || TYPE_CODE (type
) == TYPE_CODE_PTR
7964 || TYPE_CODE (type
) == TYPE_CODE_REF
7965 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7967 /* If the type is a plain integer, then the access is
7968 straight-forward. Otherwise we have to play around a bit
7970 int len
= TYPE_LENGTH (type
);
7971 int regno
= ARM_A1_REGNUM
;
7976 /* By using store_unsigned_integer we avoid having to do
7977 anything special for small big-endian values. */
7978 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7979 store_unsigned_integer (valbuf
,
7980 (len
> INT_REGISTER_SIZE
7981 ? INT_REGISTER_SIZE
: len
),
7983 len
-= INT_REGISTER_SIZE
;
7984 valbuf
+= INT_REGISTER_SIZE
;
7989 /* For a structure or union the behaviour is as if the value had
7990 been stored to word-aligned memory and then loaded into
7991 registers with 32-bit load instruction(s). */
7992 int len
= TYPE_LENGTH (type
);
7993 int regno
= ARM_A1_REGNUM
;
7994 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7998 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7999 memcpy (valbuf
, tmpbuf
,
8000 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8001 len
-= INT_REGISTER_SIZE
;
8002 valbuf
+= INT_REGISTER_SIZE
;
8008 /* Will a function return an aggregate type in memory or in a
8009 register? Return 0 if an aggregate type can be returned in a
8010 register, 1 if it must be returned in memory. */
8013 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8015 enum type_code code
;
8017 type
= check_typedef (type
);
8019 /* Simple, non-aggregate types (ie not including vectors and
8020 complex) are always returned in a register (or registers). */
8021 code
= TYPE_CODE (type
);
8022 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8023 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8026 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8028 /* Vector values should be returned using ARM registers if they
8029 are not over 16 bytes. */
8030 return (TYPE_LENGTH (type
) > 16);
8033 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8035 /* The AAPCS says all aggregates not larger than a word are returned
8037 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8046 /* All aggregate types that won't fit in a register must be returned
8048 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8051 /* In the ARM ABI, "integer" like aggregate types are returned in
8052 registers. For an aggregate type to be integer like, its size
8053 must be less than or equal to INT_REGISTER_SIZE and the
8054 offset of each addressable subfield must be zero. Note that bit
8055 fields are not addressable, and all addressable subfields of
8056 unions always start at offset zero.
8058 This function is based on the behaviour of GCC 2.95.1.
8059 See: gcc/arm.c: arm_return_in_memory() for details.
8061 Note: All versions of GCC before GCC 2.95.2 do not set up the
8062 parameters correctly for a function returning the following
8063 structure: struct { float f;}; This should be returned in memory,
8064 not a register. Richard Earnshaw sent me a patch, but I do not
8065 know of any way to detect if a function like the above has been
8066 compiled with the correct calling convention. */
8068 /* Assume all other aggregate types can be returned in a register.
8069 Run a check for structures, unions and arrays. */
8072 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8075 /* Need to check if this struct/union is "integer" like. For
8076 this to be true, its size must be less than or equal to
8077 INT_REGISTER_SIZE and the offset of each addressable
8078 subfield must be zero. Note that bit fields are not
8079 addressable, and unions always start at offset zero. If any
8080 of the subfields is a floating point type, the struct/union
8081 cannot be an integer type. */
8083 /* For each field in the object, check:
8084 1) Is it FP? --> yes, nRc = 1;
8085 2) Is it addressable (bitpos != 0) and
8086 not packed (bitsize == 0)?
8090 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8092 enum type_code field_type_code
;
8095 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8098 /* Is it a floating point type field? */
8099 if (field_type_code
== TYPE_CODE_FLT
)
8105 /* If bitpos != 0, then we have to care about it. */
8106 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8108 /* Bitfields are not addressable. If the field bitsize is
8109 zero, then the field is not packed. Hence it cannot be
8110 a bitfield or any other packed type. */
8111 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8124 /* Write into appropriate registers a function return value of type
8125 TYPE, given in virtual format. */
8128 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8129 const gdb_byte
*valbuf
)
8131 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8132 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8134 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8136 gdb_byte buf
[MAX_REGISTER_SIZE
];
8138 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8142 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8143 gdbarch_byte_order (gdbarch
));
8144 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8147 case ARM_FLOAT_SOFT_FPA
:
8148 case ARM_FLOAT_SOFT_VFP
:
8149 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8150 not using the VFP ABI code. */
8152 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8153 if (TYPE_LENGTH (type
) > 4)
8154 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8155 valbuf
+ INT_REGISTER_SIZE
);
8159 internal_error (__FILE__
, __LINE__
,
8160 _("arm_store_return_value: Floating "
8161 "point model not supported"));
8165 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8166 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8167 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8168 || TYPE_CODE (type
) == TYPE_CODE_PTR
8169 || TYPE_CODE (type
) == TYPE_CODE_REF
8170 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8172 if (TYPE_LENGTH (type
) <= 4)
8174 /* Values of one word or less are zero/sign-extended and
8176 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8177 LONGEST val
= unpack_long (type
, valbuf
);
8179 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8180 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8184 /* Integral values greater than one word are stored in consecutive
8185 registers starting with r0. This will always be a multiple of
8186 the regiser size. */
8187 int len
= TYPE_LENGTH (type
);
8188 int regno
= ARM_A1_REGNUM
;
8192 regcache_cooked_write (regs
, regno
++, valbuf
);
8193 len
-= INT_REGISTER_SIZE
;
8194 valbuf
+= INT_REGISTER_SIZE
;
8200 /* For a structure or union the behaviour is as if the value had
8201 been stored to word-aligned memory and then loaded into
8202 registers with 32-bit load instruction(s). */
8203 int len
= TYPE_LENGTH (type
);
8204 int regno
= ARM_A1_REGNUM
;
8205 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8209 memcpy (tmpbuf
, valbuf
,
8210 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8211 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8212 len
-= INT_REGISTER_SIZE
;
8213 valbuf
+= INT_REGISTER_SIZE
;
8219 /* Handle function return values. */
8221 static enum return_value_convention
8222 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8223 struct type
*valtype
, struct regcache
*regcache
,
8224 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8227 struct type
*func_type
= function
? value_type (function
) : NULL
;
8228 enum arm_vfp_cprc_base_type vfp_base_type
;
8231 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8232 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8234 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8235 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8237 for (i
= 0; i
< vfp_base_count
; i
++)
8239 if (reg_char
== 'q')
8242 arm_neon_quad_write (gdbarch
, regcache
, i
,
8243 writebuf
+ i
* unit_length
);
8246 arm_neon_quad_read (gdbarch
, regcache
, i
,
8247 readbuf
+ i
* unit_length
);
8254 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8255 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8258 regcache_cooked_write (regcache
, regnum
,
8259 writebuf
+ i
* unit_length
);
8261 regcache_cooked_read (regcache
, regnum
,
8262 readbuf
+ i
* unit_length
);
8265 return RETURN_VALUE_REGISTER_CONVENTION
;
8268 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8269 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8270 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8272 if (tdep
->struct_return
== pcc_struct_return
8273 || arm_return_in_memory (gdbarch
, valtype
))
8274 return RETURN_VALUE_STRUCT_CONVENTION
;
8276 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8278 if (arm_return_in_memory (gdbarch
, valtype
))
8279 return RETURN_VALUE_STRUCT_CONVENTION
;
8283 arm_store_return_value (valtype
, regcache
, writebuf
);
8286 arm_extract_return_value (valtype
, regcache
, readbuf
);
8288 return RETURN_VALUE_REGISTER_CONVENTION
;
8293 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8299 gdb_byte buf
[INT_REGISTER_SIZE
];
8301 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8303 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8307 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8311 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8312 return the target PC. Otherwise return 0. */
8315 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8319 CORE_ADDR start_addr
;
8321 /* Find the starting address and name of the function containing the PC. */
8322 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8324 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8326 start_addr
= arm_skip_bx_reg (frame
, pc
);
8327 if (start_addr
!= 0)
8333 /* If PC is in a Thumb call or return stub, return the address of the
8334 target PC, which is in a register. The thunk functions are called
8335 _call_via_xx, where x is the register name. The possible names
8336 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8337 functions, named __ARM_call_via_r[0-7]. */
8338 if (startswith (name
, "_call_via_")
8339 || startswith (name
, "__ARM_call_via_"))
8341 /* Use the name suffix to determine which register contains the
8343 static char *table
[15] =
8344 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8345 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8348 int offset
= strlen (name
) - 2;
8350 for (regno
= 0; regno
<= 14; regno
++)
8351 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8352 return get_frame_register_unsigned (frame
, regno
);
8355 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8356 non-interworking calls to foo. We could decode the stubs
8357 to find the target but it's easier to use the symbol table. */
8358 namelen
= strlen (name
);
8359 if (name
[0] == '_' && name
[1] == '_'
8360 && ((namelen
> 2 + strlen ("_from_thumb")
8361 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8362 || (namelen
> 2 + strlen ("_from_arm")
8363 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8366 int target_len
= namelen
- 2;
8367 struct bound_minimal_symbol minsym
;
8368 struct objfile
*objfile
;
8369 struct obj_section
*sec
;
8371 if (name
[namelen
- 1] == 'b')
8372 target_len
-= strlen ("_from_thumb");
8374 target_len
-= strlen ("_from_arm");
8376 target_name
= (char *) alloca (target_len
+ 1);
8377 memcpy (target_name
, name
+ 2, target_len
);
8378 target_name
[target_len
] = '\0';
8380 sec
= find_pc_section (pc
);
8381 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8382 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8383 if (minsym
.minsym
!= NULL
)
8384 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8389 return 0; /* not a stub */
8393 set_arm_command (char *args
, int from_tty
)
8395 printf_unfiltered (_("\
8396 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8397 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8401 show_arm_command (char *args
, int from_tty
)
8403 cmd_show_list (showarmcmdlist
, from_tty
, "");
8407 arm_update_current_architecture (void)
8409 struct gdbarch_info info
;
8411 /* If the current architecture is not ARM, we have nothing to do. */
8412 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8415 /* Update the architecture. */
8416 gdbarch_info_init (&info
);
8418 if (!gdbarch_update_p (info
))
8419 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8423 set_fp_model_sfunc (char *args
, int from_tty
,
8424 struct cmd_list_element
*c
)
8428 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8429 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8431 arm_fp_model
= (enum arm_float_model
) fp_model
;
8435 if (fp_model
== ARM_FLOAT_LAST
)
8436 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8439 arm_update_current_architecture ();
8443 show_fp_model (struct ui_file
*file
, int from_tty
,
8444 struct cmd_list_element
*c
, const char *value
)
8446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8448 if (arm_fp_model
== ARM_FLOAT_AUTO
8449 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8450 fprintf_filtered (file
, _("\
8451 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8452 fp_model_strings
[tdep
->fp_model
]);
8454 fprintf_filtered (file
, _("\
8455 The current ARM floating point model is \"%s\".\n"),
8456 fp_model_strings
[arm_fp_model
]);
8460 arm_set_abi (char *args
, int from_tty
,
8461 struct cmd_list_element
*c
)
8465 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8466 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8468 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8472 if (arm_abi
== ARM_ABI_LAST
)
8473 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8476 arm_update_current_architecture ();
8480 arm_show_abi (struct ui_file
*file
, int from_tty
,
8481 struct cmd_list_element
*c
, const char *value
)
8483 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8485 if (arm_abi_global
== ARM_ABI_AUTO
8486 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8487 fprintf_filtered (file
, _("\
8488 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8489 arm_abi_strings
[tdep
->arm_abi
]);
8491 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8496 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8497 struct cmd_list_element
*c
, const char *value
)
8499 fprintf_filtered (file
,
8500 _("The current execution mode assumed "
8501 "(when symbols are unavailable) is \"%s\".\n"),
8502 arm_fallback_mode_string
);
8506 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8507 struct cmd_list_element
*c
, const char *value
)
8509 fprintf_filtered (file
,
8510 _("The current execution mode assumed "
8511 "(even when symbols are available) is \"%s\".\n"),
8512 arm_force_mode_string
);
8515 /* If the user changes the register disassembly style used for info
8516 register and other commands, we have to also switch the style used
8517 in opcodes for disassembly output. This function is run in the "set
8518 arm disassembly" command, and does that. */
8521 set_disassembly_style_sfunc (char *args
, int from_tty
,
8522 struct cmd_list_element
*c
)
8524 set_disassembly_style ();
8527 /* Return the ARM register name corresponding to register I. */
8529 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8531 const int num_regs
= gdbarch_num_regs (gdbarch
);
8533 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8534 && i
>= num_regs
&& i
< num_regs
+ 32)
8536 static const char *const vfp_pseudo_names
[] = {
8537 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8538 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8539 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8540 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8543 return vfp_pseudo_names
[i
- num_regs
];
8546 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8547 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8549 static const char *const neon_pseudo_names
[] = {
8550 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8551 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8554 return neon_pseudo_names
[i
- num_regs
- 32];
8557 if (i
>= ARRAY_SIZE (arm_register_names
))
8558 /* These registers are only supported on targets which supply
8559 an XML description. */
8562 return arm_register_names
[i
];
8566 set_disassembly_style (void)
8570 /* Find the style that the user wants. */
8571 for (current
= 0; current
< num_disassembly_options
; current
++)
8572 if (disassembly_style
== valid_disassembly_styles
[current
])
8574 gdb_assert (current
< num_disassembly_options
);
8576 /* Synchronize the disassembler. */
8577 set_arm_regname_option (current
);
8580 /* Test whether the coff symbol specific value corresponds to a Thumb
8584 coff_sym_is_thumb (int val
)
8586 return (val
== C_THUMBEXT
8587 || val
== C_THUMBSTAT
8588 || val
== C_THUMBEXTFUNC
8589 || val
== C_THUMBSTATFUNC
8590 || val
== C_THUMBLABEL
);
8593 /* arm_coff_make_msymbol_special()
8594 arm_elf_make_msymbol_special()
8596 These functions test whether the COFF or ELF symbol corresponds to
8597 an address in thumb code, and set a "special" bit in a minimal
8598 symbol to indicate that it does. */
8601 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8603 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8605 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8606 == ST_BRANCH_TO_THUMB
)
8607 MSYMBOL_SET_SPECIAL (msym
);
8611 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8613 if (coff_sym_is_thumb (val
))
8614 MSYMBOL_SET_SPECIAL (msym
);
8618 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8620 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8623 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8624 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8628 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8631 const char *name
= bfd_asymbol_name (sym
);
8632 struct arm_per_objfile
*data
;
8633 VEC(arm_mapping_symbol_s
) **map_p
;
8634 struct arm_mapping_symbol new_map_sym
;
8636 gdb_assert (name
[0] == '$');
8637 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8640 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8641 arm_objfile_data_key
);
8644 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8645 struct arm_per_objfile
);
8646 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8647 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8648 objfile
->obfd
->section_count
,
8649 VEC(arm_mapping_symbol_s
) *);
8651 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8653 new_map_sym
.value
= sym
->value
;
8654 new_map_sym
.type
= name
[1];
8656 /* Assume that most mapping symbols appear in order of increasing
8657 value. If they were randomly distributed, it would be faster to
8658 always push here and then sort at first use. */
8659 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8661 struct arm_mapping_symbol
*prev_map_sym
;
8663 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8664 if (prev_map_sym
->value
>= sym
->value
)
8667 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8668 arm_compare_mapping_symbols
);
8669 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8674 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8678 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8680 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8681 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8683 /* If necessary, set the T bit. */
8686 ULONGEST val
, t_bit
;
8687 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8688 t_bit
= arm_psr_thumb_bit (gdbarch
);
8689 if (arm_pc_is_thumb (gdbarch
, pc
))
8690 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8693 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8698 /* Read the contents of a NEON quad register, by reading from two
8699 double registers. This is used to implement the quad pseudo
8700 registers, and for argument passing in case the quad registers are
8701 missing; vectors are passed in quad registers when using the VFP
8702 ABI, even if a NEON unit is not present. REGNUM is the index of
8703 the quad register, in [0, 15]. */
8705 static enum register_status
8706 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8707 int regnum
, gdb_byte
*buf
)
8710 gdb_byte reg_buf
[8];
8711 int offset
, double_regnum
;
8712 enum register_status status
;
8714 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8715 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8718 /* d0 is always the least significant half of q0. */
8719 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8724 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8725 if (status
!= REG_VALID
)
8727 memcpy (buf
+ offset
, reg_buf
, 8);
8729 offset
= 8 - offset
;
8730 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8731 if (status
!= REG_VALID
)
8733 memcpy (buf
+ offset
, reg_buf
, 8);
8738 static enum register_status
8739 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8740 int regnum
, gdb_byte
*buf
)
8742 const int num_regs
= gdbarch_num_regs (gdbarch
);
8744 gdb_byte reg_buf
[8];
8745 int offset
, double_regnum
;
8747 gdb_assert (regnum
>= num_regs
);
8750 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8751 /* Quad-precision register. */
8752 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8755 enum register_status status
;
8757 /* Single-precision register. */
8758 gdb_assert (regnum
< 32);
8760 /* s0 is always the least significant half of d0. */
8761 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8762 offset
= (regnum
& 1) ? 0 : 4;
8764 offset
= (regnum
& 1) ? 4 : 0;
8766 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8767 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8770 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8771 if (status
== REG_VALID
)
8772 memcpy (buf
, reg_buf
+ offset
, 4);
8777 /* Store the contents of BUF to a NEON quad register, by writing to
8778 two double registers. This is used to implement the quad pseudo
8779 registers, and for argument passing in case the quad registers are
8780 missing; vectors are passed in quad registers when using the VFP
8781 ABI, even if a NEON unit is not present. REGNUM is the index
8782 of the quad register, in [0, 15]. */
8785 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8786 int regnum
, const gdb_byte
*buf
)
8789 int offset
, double_regnum
;
8791 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8792 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8795 /* d0 is always the least significant half of q0. */
8796 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8801 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8802 offset
= 8 - offset
;
8803 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8807 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8808 int regnum
, const gdb_byte
*buf
)
8810 const int num_regs
= gdbarch_num_regs (gdbarch
);
8812 gdb_byte reg_buf
[8];
8813 int offset
, double_regnum
;
8815 gdb_assert (regnum
>= num_regs
);
8818 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8819 /* Quad-precision register. */
8820 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8823 /* Single-precision register. */
8824 gdb_assert (regnum
< 32);
8826 /* s0 is always the least significant half of d0. */
8827 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8828 offset
= (regnum
& 1) ? 0 : 4;
8830 offset
= (regnum
& 1) ? 4 : 0;
8832 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8833 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8836 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8837 memcpy (reg_buf
+ offset
, buf
, 4);
8838 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8842 static struct value
*
8843 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8845 const int *reg_p
= (const int *) baton
;
8846 return value_of_register (*reg_p
, frame
);
8849 static enum gdb_osabi
8850 arm_elf_osabi_sniffer (bfd
*abfd
)
8852 unsigned int elfosabi
;
8853 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8855 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8857 if (elfosabi
== ELFOSABI_ARM
)
8858 /* GNU tools use this value. Check note sections in this case,
8860 bfd_map_over_sections (abfd
,
8861 generic_elf_osabi_sniff_abi_tag_sections
,
8864 /* Anything else will be handled by the generic ELF sniffer. */
8869 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8870 struct reggroup
*group
)
8872 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8873 this, FPS register belongs to save_regroup, restore_reggroup, and
8874 all_reggroup, of course. */
8875 if (regnum
== ARM_FPS_REGNUM
)
8876 return (group
== float_reggroup
8877 || group
== save_reggroup
8878 || group
== restore_reggroup
8879 || group
== all_reggroup
);
8881 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8885 /* For backward-compatibility we allow two 'g' packet lengths with
8886 the remote protocol depending on whether FPA registers are
8887 supplied. M-profile targets do not have FPA registers, but some
8888 stubs already exist in the wild which use a 'g' packet which
8889 supplies them albeit with dummy values. The packet format which
8890 includes FPA registers should be considered deprecated for
8891 M-profile targets. */
8894 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8896 if (gdbarch_tdep (gdbarch
)->is_m
)
8898 /* If we know from the executable this is an M-profile target,
8899 cater for remote targets whose register set layout is the
8900 same as the FPA layout. */
8901 register_remote_g_packet_guess (gdbarch
,
8902 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8903 (16 * INT_REGISTER_SIZE
)
8904 + (8 * FP_REGISTER_SIZE
)
8905 + (2 * INT_REGISTER_SIZE
),
8906 tdesc_arm_with_m_fpa_layout
);
8908 /* The regular M-profile layout. */
8909 register_remote_g_packet_guess (gdbarch
,
8910 /* r0-r12,sp,lr,pc; xpsr */
8911 (16 * INT_REGISTER_SIZE
)
8912 + INT_REGISTER_SIZE
,
8915 /* M-profile plus M4F VFP. */
8916 register_remote_g_packet_guess (gdbarch
,
8917 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8918 (16 * INT_REGISTER_SIZE
)
8919 + (16 * VFP_REGISTER_SIZE
)
8920 + (2 * INT_REGISTER_SIZE
),
8921 tdesc_arm_with_m_vfp_d16
);
8924 /* Otherwise we don't have a useful guess. */
8927 /* Implement the code_of_frame_writable gdbarch method. */
8930 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8932 if (gdbarch_tdep (gdbarch
)->is_m
8933 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8935 /* M-profile exception frames return to some magic PCs, where
8936 isn't writable at all. */
8944 /* Initialize the current architecture based on INFO. If possible,
8945 re-use an architecture from ARCHES, which is a list of
8946 architectures already created during this debugging session.
8948 Called e.g. at program startup, when reading a core file, and when
8949 reading a binary file. */
8951 static struct gdbarch
*
8952 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8954 struct gdbarch_tdep
*tdep
;
8955 struct gdbarch
*gdbarch
;
8956 struct gdbarch_list
*best_arch
;
8957 enum arm_abi_kind arm_abi
= arm_abi_global
;
8958 enum arm_float_model fp_model
= arm_fp_model
;
8959 struct tdesc_arch_data
*tdesc_data
= NULL
;
8961 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8962 int have_wmmx_registers
= 0;
8964 int have_fpa_registers
= 1;
8965 const struct target_desc
*tdesc
= info
.target_desc
;
8967 /* If we have an object to base this architecture on, try to determine
8970 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8972 int ei_osabi
, e_flags
;
8974 switch (bfd_get_flavour (info
.abfd
))
8976 case bfd_target_aout_flavour
:
8977 /* Assume it's an old APCS-style ABI. */
8978 arm_abi
= ARM_ABI_APCS
;
8981 case bfd_target_coff_flavour
:
8982 /* Assume it's an old APCS-style ABI. */
8984 arm_abi
= ARM_ABI_APCS
;
8987 case bfd_target_elf_flavour
:
8988 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8989 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8991 if (ei_osabi
== ELFOSABI_ARM
)
8993 /* GNU tools used to use this value, but do not for EABI
8994 objects. There's nowhere to tag an EABI version
8995 anyway, so assume APCS. */
8996 arm_abi
= ARM_ABI_APCS
;
8998 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9000 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9001 int attr_arch
, attr_profile
;
9005 case EF_ARM_EABI_UNKNOWN
:
9006 /* Assume GNU tools. */
9007 arm_abi
= ARM_ABI_APCS
;
9010 case EF_ARM_EABI_VER4
:
9011 case EF_ARM_EABI_VER5
:
9012 arm_abi
= ARM_ABI_AAPCS
;
9013 /* EABI binaries default to VFP float ordering.
9014 They may also contain build attributes that can
9015 be used to identify if the VFP argument-passing
9017 if (fp_model
== ARM_FLOAT_AUTO
)
9020 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9024 case AEABI_VFP_args_base
:
9025 /* "The user intended FP parameter/result
9026 passing to conform to AAPCS, base
9028 fp_model
= ARM_FLOAT_SOFT_VFP
;
9030 case AEABI_VFP_args_vfp
:
9031 /* "The user intended FP parameter/result
9032 passing to conform to AAPCS, VFP
9034 fp_model
= ARM_FLOAT_VFP
;
9036 case AEABI_VFP_args_toolchain
:
9037 /* "The user intended FP parameter/result
9038 passing to conform to tool chain-specific
9039 conventions" - we don't know any such
9040 conventions, so leave it as "auto". */
9042 case AEABI_VFP_args_compatible
:
9043 /* "Code is compatible with both the base
9044 and VFP variants; the user did not permit
9045 non-variadic functions to pass FP
9046 parameters/results" - leave it as
9050 /* Attribute value not mentioned in the
9051 November 2012 ABI, so leave it as
9056 fp_model
= ARM_FLOAT_SOFT_VFP
;
9062 /* Leave it as "auto". */
9063 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9068 /* Detect M-profile programs. This only works if the
9069 executable file includes build attributes; GCC does
9070 copy them to the executable, but e.g. RealView does
9072 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9074 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9076 Tag_CPU_arch_profile
);
9077 /* GCC specifies the profile for v6-M; RealView only
9078 specifies the profile for architectures starting with
9079 V7 (as opposed to architectures with a tag
9080 numerically greater than TAG_CPU_ARCH_V7). */
9081 if (!tdesc_has_registers (tdesc
)
9082 && (attr_arch
== TAG_CPU_ARCH_V6_M
9083 || attr_arch
== TAG_CPU_ARCH_V6S_M
9084 || attr_profile
== 'M'))
9089 if (fp_model
== ARM_FLOAT_AUTO
)
9091 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9093 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9096 /* Leave it as "auto". Strictly speaking this case
9097 means FPA, but almost nobody uses that now, and
9098 many toolchains fail to set the appropriate bits
9099 for the floating-point model they use. */
9101 case EF_ARM_SOFT_FLOAT
:
9102 fp_model
= ARM_FLOAT_SOFT_FPA
;
9104 case EF_ARM_VFP_FLOAT
:
9105 fp_model
= ARM_FLOAT_VFP
;
9107 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9108 fp_model
= ARM_FLOAT_SOFT_VFP
;
9113 if (e_flags
& EF_ARM_BE8
)
9114 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9119 /* Leave it as "auto". */
9124 /* Check any target description for validity. */
9125 if (tdesc_has_registers (tdesc
))
9127 /* For most registers we require GDB's default names; but also allow
9128 the numeric names for sp / lr / pc, as a convenience. */
9129 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9130 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9131 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9133 const struct tdesc_feature
*feature
;
9136 feature
= tdesc_find_feature (tdesc
,
9137 "org.gnu.gdb.arm.core");
9138 if (feature
== NULL
)
9140 feature
= tdesc_find_feature (tdesc
,
9141 "org.gnu.gdb.arm.m-profile");
9142 if (feature
== NULL
)
9148 tdesc_data
= tdesc_data_alloc ();
9151 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9152 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9153 arm_register_names
[i
]);
9154 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9157 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9160 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9164 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9165 ARM_PS_REGNUM
, "xpsr");
9167 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9168 ARM_PS_REGNUM
, "cpsr");
9172 tdesc_data_cleanup (tdesc_data
);
9176 feature
= tdesc_find_feature (tdesc
,
9177 "org.gnu.gdb.arm.fpa");
9178 if (feature
!= NULL
)
9181 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9182 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9183 arm_register_names
[i
]);
9186 tdesc_data_cleanup (tdesc_data
);
9191 have_fpa_registers
= 0;
9193 feature
= tdesc_find_feature (tdesc
,
9194 "org.gnu.gdb.xscale.iwmmxt");
9195 if (feature
!= NULL
)
9197 static const char *const iwmmxt_names
[] = {
9198 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9199 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9200 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9201 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9205 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9207 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9208 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9210 /* Check for the control registers, but do not fail if they
9212 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9213 tdesc_numbered_register (feature
, tdesc_data
, i
,
9214 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9216 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9218 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9219 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9223 tdesc_data_cleanup (tdesc_data
);
9227 have_wmmx_registers
= 1;
9230 /* If we have a VFP unit, check whether the single precision registers
9231 are present. If not, then we will synthesize them as pseudo
9233 feature
= tdesc_find_feature (tdesc
,
9234 "org.gnu.gdb.arm.vfp");
9235 if (feature
!= NULL
)
9237 static const char *const vfp_double_names
[] = {
9238 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9239 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9240 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9241 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9244 /* Require the double precision registers. There must be either
9247 for (i
= 0; i
< 32; i
++)
9249 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9251 vfp_double_names
[i
]);
9255 if (!valid_p
&& i
== 16)
9258 /* Also require FPSCR. */
9259 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9260 ARM_FPSCR_REGNUM
, "fpscr");
9263 tdesc_data_cleanup (tdesc_data
);
9267 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9268 have_vfp_pseudos
= 1;
9270 vfp_register_count
= i
;
9272 /* If we have VFP, also check for NEON. The architecture allows
9273 NEON without VFP (integer vector operations only), but GDB
9274 does not support that. */
9275 feature
= tdesc_find_feature (tdesc
,
9276 "org.gnu.gdb.arm.neon");
9277 if (feature
!= NULL
)
9279 /* NEON requires 32 double-precision registers. */
9282 tdesc_data_cleanup (tdesc_data
);
9286 /* If there are quad registers defined by the stub, use
9287 their type; otherwise (normally) provide them with
9288 the default type. */
9289 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9290 have_neon_pseudos
= 1;
9297 /* If there is already a candidate, use it. */
9298 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9300 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9302 if (arm_abi
!= ARM_ABI_AUTO
9303 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9306 if (fp_model
!= ARM_FLOAT_AUTO
9307 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9310 /* There are various other properties in tdep that we do not
9311 need to check here: those derived from a target description,
9312 since gdbarches with a different target description are
9313 automatically disqualified. */
9315 /* Do check is_m, though, since it might come from the binary. */
9316 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9319 /* Found a match. */
9323 if (best_arch
!= NULL
)
9325 if (tdesc_data
!= NULL
)
9326 tdesc_data_cleanup (tdesc_data
);
9327 return best_arch
->gdbarch
;
9330 tdep
= XCNEW (struct gdbarch_tdep
);
9331 gdbarch
= gdbarch_alloc (&info
, tdep
);
9333 /* Record additional information about the architecture we are defining.
9334 These are gdbarch discriminators, like the OSABI. */
9335 tdep
->arm_abi
= arm_abi
;
9336 tdep
->fp_model
= fp_model
;
9338 tdep
->have_fpa_registers
= have_fpa_registers
;
9339 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9340 gdb_assert (vfp_register_count
== 0
9341 || vfp_register_count
== 16
9342 || vfp_register_count
== 32);
9343 tdep
->vfp_register_count
= vfp_register_count
;
9344 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9345 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9346 tdep
->have_neon
= have_neon
;
9348 arm_register_g_packet_guesses (gdbarch
);
9351 switch (info
.byte_order_for_code
)
9353 case BFD_ENDIAN_BIG
:
9354 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9355 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9356 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9357 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9361 case BFD_ENDIAN_LITTLE
:
9362 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9363 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9364 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9365 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9370 internal_error (__FILE__
, __LINE__
,
9371 _("arm_gdbarch_init: bad byte order for float format"));
9374 /* On ARM targets char defaults to unsigned. */
9375 set_gdbarch_char_signed (gdbarch
, 0);
9377 /* Note: for displaced stepping, this includes the breakpoint, and one word
9378 of additional scratch space. This setting isn't used for anything beside
9379 displaced stepping at present. */
9380 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9382 /* This should be low enough for everything. */
9383 tdep
->lowest_pc
= 0x20;
9384 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9386 /* The default, for both APCS and AAPCS, is to return small
9387 structures in registers. */
9388 tdep
->struct_return
= reg_struct_return
;
9390 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9391 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9394 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9396 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9398 /* Frame handling. */
9399 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9400 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9401 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9403 frame_base_set_default (gdbarch
, &arm_normal_base
);
9405 /* Address manipulation. */
9406 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9408 /* Advance PC across function entry code. */
9409 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9411 /* Detect whether PC is at a point where the stack has been destroyed. */
9412 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9414 /* Skip trampolines. */
9415 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9417 /* The stack grows downward. */
9418 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9420 /* Breakpoint manipulation. */
9421 SET_GDBARCH_BREAKPOINT_MANIPULATION (arm
);
9423 /* Information about registers, etc. */
9424 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9425 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9426 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9427 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9428 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9430 /* This "info float" is FPA-specific. Use the generic version if we
9432 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9433 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9435 /* Internal <-> external register number maps. */
9436 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9437 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9439 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9441 /* Returning results. */
9442 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9445 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9447 /* Minsymbol frobbing. */
9448 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9449 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9450 arm_coff_make_msymbol_special
);
9451 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9453 /* Thumb-2 IT block support. */
9454 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9455 arm_adjust_breakpoint_address
);
9457 /* Virtual tables. */
9458 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9460 /* Hook in the ABI-specific overrides, if they have been registered. */
9461 gdbarch_init_osabi (info
, gdbarch
);
9463 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9465 /* Add some default predicates. */
9467 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9468 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9469 dwarf2_append_unwinders (gdbarch
);
9470 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9471 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9472 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9474 /* Now we have tuned the configuration, set a few final things,
9475 based on what the OS ABI has told us. */
9477 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9478 binaries are always marked. */
9479 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9480 tdep
->arm_abi
= ARM_ABI_APCS
;
9482 /* Watchpoints are not steppable. */
9483 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9485 /* We used to default to FPA for generic ARM, but almost nobody
9486 uses that now, and we now provide a way for the user to force
9487 the model. So default to the most useful variant. */
9488 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9489 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9491 if (tdep
->jb_pc
>= 0)
9492 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9494 /* Floating point sizes and format. */
9495 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9496 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9498 set_gdbarch_double_format
9499 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9500 set_gdbarch_long_double_format
9501 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9505 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9506 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9509 if (have_vfp_pseudos
)
9511 /* NOTE: These are the only pseudo registers used by
9512 the ARM target at the moment. If more are added, a
9513 little more care in numbering will be needed. */
9515 int num_pseudos
= 32;
9516 if (have_neon_pseudos
)
9518 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9519 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9520 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9525 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9527 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9529 /* Override tdesc_register_type to adjust the types of VFP
9530 registers for NEON. */
9531 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9534 /* Add standard register aliases. We add aliases even for those
9535 nanes which are used by the current architecture - it's simpler,
9536 and does no harm, since nothing ever lists user registers. */
9537 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9538 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9539 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9545 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9547 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9552 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9553 (unsigned long) tdep
->lowest_pc
);
9556 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9559 _initialize_arm_tdep (void)
9561 struct ui_file
*stb
;
9563 const char *setname
;
9564 const char *setdesc
;
9565 const char *const *regnames
;
9567 static char *helptext
;
9568 char regdesc
[1024], *rdptr
= regdesc
;
9569 size_t rest
= sizeof (regdesc
);
9571 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9573 arm_objfile_data_key
9574 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9576 /* Add ourselves to objfile event chain. */
9577 observer_attach_new_objfile (arm_exidx_new_objfile
);
9579 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9581 /* Register an ELF OS ABI sniffer for ARM binaries. */
9582 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9583 bfd_target_elf_flavour
,
9584 arm_elf_osabi_sniffer
);
9586 /* Initialize the standard target descriptions. */
9587 initialize_tdesc_arm_with_m ();
9588 initialize_tdesc_arm_with_m_fpa_layout ();
9589 initialize_tdesc_arm_with_m_vfp_d16 ();
9590 initialize_tdesc_arm_with_iwmmxt ();
9591 initialize_tdesc_arm_with_vfpv2 ();
9592 initialize_tdesc_arm_with_vfpv3 ();
9593 initialize_tdesc_arm_with_neon ();
9595 /* Get the number of possible sets of register names defined in opcodes. */
9596 num_disassembly_options
= get_arm_regname_num_options ();
9598 /* Add root prefix command for all "set arm"/"show arm" commands. */
9599 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9600 _("Various ARM-specific commands."),
9601 &setarmcmdlist
, "set arm ", 0, &setlist
);
9603 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9604 _("Various ARM-specific commands."),
9605 &showarmcmdlist
, "show arm ", 0, &showlist
);
9607 /* Sync the opcode insn printer with our register viewer. */
9608 parse_arm_disassembler_option ("reg-names-std");
9610 /* Initialize the array that will be passed to
9611 add_setshow_enum_cmd(). */
9612 valid_disassembly_styles
= XNEWVEC (const char *,
9613 num_disassembly_options
+ 1);
9614 for (i
= 0; i
< num_disassembly_options
; i
++)
9616 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9617 valid_disassembly_styles
[i
] = setname
;
9618 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9621 /* When we find the default names, tell the disassembler to use
9623 if (!strcmp (setname
, "std"))
9625 disassembly_style
= setname
;
9626 set_arm_regname_option (i
);
9629 /* Mark the end of valid options. */
9630 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9632 /* Create the help text. */
9633 stb
= mem_fileopen ();
9634 fprintf_unfiltered (stb
, "%s%s%s",
9635 _("The valid values are:\n"),
9637 _("The default is \"std\"."));
9638 helptext
= ui_file_xstrdup (stb
, NULL
);
9639 ui_file_delete (stb
);
9641 add_setshow_enum_cmd("disassembler", no_class
,
9642 valid_disassembly_styles
, &disassembly_style
,
9643 _("Set the disassembly style."),
9644 _("Show the disassembly style."),
9646 set_disassembly_style_sfunc
,
9647 NULL
, /* FIXME: i18n: The disassembly style is
9649 &setarmcmdlist
, &showarmcmdlist
);
9651 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9652 _("Set usage of ARM 32-bit mode."),
9653 _("Show usage of ARM 32-bit mode."),
9654 _("When off, a 26-bit PC will be used."),
9656 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9658 &setarmcmdlist
, &showarmcmdlist
);
9660 /* Add a command to allow the user to force the FPU model. */
9661 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9662 _("Set the floating point type."),
9663 _("Show the floating point type."),
9664 _("auto - Determine the FP typefrom the OS-ABI.\n\
9665 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9666 fpa - FPA co-processor (GCC compiled).\n\
9667 softvfp - Software FP with pure-endian doubles.\n\
9668 vfp - VFP co-processor."),
9669 set_fp_model_sfunc
, show_fp_model
,
9670 &setarmcmdlist
, &showarmcmdlist
);
9672 /* Add a command to allow the user to force the ABI. */
9673 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9676 NULL
, arm_set_abi
, arm_show_abi
,
9677 &setarmcmdlist
, &showarmcmdlist
);
9679 /* Add two commands to allow the user to force the assumed
9681 add_setshow_enum_cmd ("fallback-mode", class_support
,
9682 arm_mode_strings
, &arm_fallback_mode_string
,
9683 _("Set the mode assumed when symbols are unavailable."),
9684 _("Show the mode assumed when symbols are unavailable."),
9685 NULL
, NULL
, arm_show_fallback_mode
,
9686 &setarmcmdlist
, &showarmcmdlist
);
9687 add_setshow_enum_cmd ("force-mode", class_support
,
9688 arm_mode_strings
, &arm_force_mode_string
,
9689 _("Set the mode assumed even when symbols are available."),
9690 _("Show the mode assumed even when symbols are available."),
9691 NULL
, NULL
, arm_show_force_mode
,
9692 &setarmcmdlist
, &showarmcmdlist
);
9694 /* Debugging flag. */
9695 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9696 _("Set ARM debugging."),
9697 _("Show ARM debugging."),
9698 _("When on, arm-specific debugging is enabled."),
9700 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9701 &setdebuglist
, &showdebuglist
);
9704 /* ARM-reversible process record data structures. */
9706 #define ARM_INSN_SIZE_BYTES 4
9707 #define THUMB_INSN_SIZE_BYTES 2
9708 #define THUMB2_INSN_SIZE_BYTES 4
9711 /* Position of the bit within a 32-bit ARM instruction
9712 that defines whether the instruction is a load or store. */
9713 #define INSN_S_L_BIT_NUM 20
9715 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9718 unsigned int reg_len = LENGTH; \
9721 REGS = XNEWVEC (uint32_t, reg_len); \
9722 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9727 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9730 unsigned int mem_len = LENGTH; \
9733 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9734 memcpy(&MEMS->len, &RECORD_BUF[0], \
9735 sizeof(struct arm_mem_r) * LENGTH); \
9740 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9741 #define INSN_RECORDED(ARM_RECORD) \
9742 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9744 /* ARM memory record structure. */
9747 uint32_t len
; /* Record length. */
9748 uint32_t addr
; /* Memory address. */
9751 /* ARM instruction record contains opcode of current insn
9752 and execution state (before entry to decode_insn()),
9753 contains list of to-be-modified registers and
9754 memory blocks (on return from decode_insn()). */
9756 typedef struct insn_decode_record_t
9758 struct gdbarch
*gdbarch
;
9759 struct regcache
*regcache
;
9760 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9761 uint32_t arm_insn
; /* Should accommodate thumb. */
9762 uint32_t cond
; /* Condition code. */
9763 uint32_t opcode
; /* Insn opcode. */
9764 uint32_t decode
; /* Insn decode bits. */
9765 uint32_t mem_rec_count
; /* No of mem records. */
9766 uint32_t reg_rec_count
; /* No of reg records. */
9767 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9768 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9769 } insn_decode_record
;
9772 /* Checks ARM SBZ and SBO mandatory fields. */
9775 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9777 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9796 enum arm_record_result
9798 ARM_RECORD_SUCCESS
= 0,
9799 ARM_RECORD_FAILURE
= 1
9806 } arm_record_strx_t
;
9817 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9818 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9821 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9822 ULONGEST u_regval
[2]= {0};
9824 uint32_t reg_src1
= 0, reg_src2
= 0;
9825 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9827 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9828 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9830 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9832 /* 1) Handle misc store, immediate offset. */
9833 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9834 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9835 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9836 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9838 if (ARM_PC_REGNUM
== reg_src1
)
9840 /* If R15 was used as Rn, hence current PC+8. */
9841 u_regval
[0] = u_regval
[0] + 8;
9843 offset_8
= (immed_high
<< 4) | immed_low
;
9844 /* Calculate target store address. */
9845 if (14 == arm_insn_r
->opcode
)
9847 tgt_mem_addr
= u_regval
[0] + offset_8
;
9851 tgt_mem_addr
= u_regval
[0] - offset_8
;
9853 if (ARM_RECORD_STRH
== str_type
)
9855 record_buf_mem
[0] = 2;
9856 record_buf_mem
[1] = tgt_mem_addr
;
9857 arm_insn_r
->mem_rec_count
= 1;
9859 else if (ARM_RECORD_STRD
== str_type
)
9861 record_buf_mem
[0] = 4;
9862 record_buf_mem
[1] = tgt_mem_addr
;
9863 record_buf_mem
[2] = 4;
9864 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9865 arm_insn_r
->mem_rec_count
= 2;
9868 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9870 /* 2) Store, register offset. */
9872 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9874 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9875 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9876 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9879 /* If R15 was used as Rn, hence current PC+8. */
9880 u_regval
[0] = u_regval
[0] + 8;
9882 /* Calculate target store address, Rn +/- Rm, register offset. */
9883 if (12 == arm_insn_r
->opcode
)
9885 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9889 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9891 if (ARM_RECORD_STRH
== str_type
)
9893 record_buf_mem
[0] = 2;
9894 record_buf_mem
[1] = tgt_mem_addr
;
9895 arm_insn_r
->mem_rec_count
= 1;
9897 else if (ARM_RECORD_STRD
== str_type
)
9899 record_buf_mem
[0] = 4;
9900 record_buf_mem
[1] = tgt_mem_addr
;
9901 record_buf_mem
[2] = 4;
9902 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9903 arm_insn_r
->mem_rec_count
= 2;
9906 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9907 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9909 /* 3) Store, immediate pre-indexed. */
9910 /* 5) Store, immediate post-indexed. */
9911 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9912 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9913 offset_8
= (immed_high
<< 4) | immed_low
;
9914 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9915 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9916 /* Calculate target store address, Rn +/- Rm, register offset. */
9917 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9919 tgt_mem_addr
= u_regval
[0] + offset_8
;
9923 tgt_mem_addr
= u_regval
[0] - offset_8
;
9925 if (ARM_RECORD_STRH
== str_type
)
9927 record_buf_mem
[0] = 2;
9928 record_buf_mem
[1] = tgt_mem_addr
;
9929 arm_insn_r
->mem_rec_count
= 1;
9931 else if (ARM_RECORD_STRD
== str_type
)
9933 record_buf_mem
[0] = 4;
9934 record_buf_mem
[1] = tgt_mem_addr
;
9935 record_buf_mem
[2] = 4;
9936 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9937 arm_insn_r
->mem_rec_count
= 2;
9939 /* Record Rn also as it changes. */
9940 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9941 arm_insn_r
->reg_rec_count
= 1;
9943 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9944 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9946 /* 4) Store, register pre-indexed. */
9947 /* 6) Store, register post -indexed. */
9948 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9949 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9950 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9951 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9952 /* Calculate target store address, Rn +/- Rm, register offset. */
9953 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9955 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9959 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9961 if (ARM_RECORD_STRH
== str_type
)
9963 record_buf_mem
[0] = 2;
9964 record_buf_mem
[1] = tgt_mem_addr
;
9965 arm_insn_r
->mem_rec_count
= 1;
9967 else if (ARM_RECORD_STRD
== str_type
)
9969 record_buf_mem
[0] = 4;
9970 record_buf_mem
[1] = tgt_mem_addr
;
9971 record_buf_mem
[2] = 4;
9972 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9973 arm_insn_r
->mem_rec_count
= 2;
9975 /* Record Rn also as it changes. */
9976 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9977 arm_insn_r
->reg_rec_count
= 1;
9982 /* Handling ARM extension space insns. */
9985 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9987 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
9988 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9989 uint32_t record_buf
[8], record_buf_mem
[8];
9990 uint32_t reg_src1
= 0;
9991 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9992 ULONGEST u_regval
= 0;
9994 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9995 /* Handle unconditional insn extension space. */
9997 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9998 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9999 if (arm_insn_r
->cond
)
10001 /* PLD has no affect on architectural state, it just affects
10003 if (5 == ((opcode1
& 0xE0) >> 5))
10006 record_buf
[0] = ARM_PS_REGNUM
;
10007 record_buf
[1] = ARM_LR_REGNUM
;
10008 arm_insn_r
->reg_rec_count
= 2;
10010 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10014 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10015 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10018 /* Undefined instruction on ARM V5; need to handle if later
10019 versions define it. */
10022 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10023 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10024 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10026 /* Handle arithmetic insn extension space. */
10027 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10028 && !INSN_RECORDED(arm_insn_r
))
10030 /* Handle MLA(S) and MUL(S). */
10031 if (0 <= insn_op1
&& 3 >= insn_op1
)
10033 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10034 record_buf
[1] = ARM_PS_REGNUM
;
10035 arm_insn_r
->reg_rec_count
= 2;
10037 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10039 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10040 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10041 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10042 record_buf
[2] = ARM_PS_REGNUM
;
10043 arm_insn_r
->reg_rec_count
= 3;
10047 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10048 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10049 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10051 /* Handle control insn extension space. */
10053 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10054 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10056 if (!bit (arm_insn_r
->arm_insn
,25))
10058 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10060 if ((0 == insn_op1
) || (2 == insn_op1
))
10063 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10064 arm_insn_r
->reg_rec_count
= 1;
10066 else if (1 == insn_op1
)
10068 /* CSPR is going to be changed. */
10069 record_buf
[0] = ARM_PS_REGNUM
;
10070 arm_insn_r
->reg_rec_count
= 1;
10072 else if (3 == insn_op1
)
10074 /* SPSR is going to be changed. */
10075 /* We need to get SPSR value, which is yet to be done. */
10079 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10084 record_buf
[0] = ARM_PS_REGNUM
;
10085 arm_insn_r
->reg_rec_count
= 1;
10087 else if (3 == insn_op1
)
10090 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10091 arm_insn_r
->reg_rec_count
= 1;
10094 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10097 record_buf
[0] = ARM_PS_REGNUM
;
10098 record_buf
[1] = ARM_LR_REGNUM
;
10099 arm_insn_r
->reg_rec_count
= 2;
10101 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10103 /* QADD, QSUB, QDADD, QDSUB */
10104 record_buf
[0] = ARM_PS_REGNUM
;
10105 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10106 arm_insn_r
->reg_rec_count
= 2;
10108 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10111 record_buf
[0] = ARM_PS_REGNUM
;
10112 record_buf
[1] = ARM_LR_REGNUM
;
10113 arm_insn_r
->reg_rec_count
= 2;
10115 /* Save SPSR also;how? */
10118 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10119 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10120 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10121 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10124 if (0 == insn_op1
|| 1 == insn_op1
)
10126 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10127 /* We dont do optimization for SMULW<y> where we
10129 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10130 record_buf
[1] = ARM_PS_REGNUM
;
10131 arm_insn_r
->reg_rec_count
= 2;
10133 else if (2 == insn_op1
)
10136 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10137 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10138 arm_insn_r
->reg_rec_count
= 2;
10140 else if (3 == insn_op1
)
10143 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10144 arm_insn_r
->reg_rec_count
= 1;
10150 /* MSR : immediate form. */
10153 /* CSPR is going to be changed. */
10154 record_buf
[0] = ARM_PS_REGNUM
;
10155 arm_insn_r
->reg_rec_count
= 1;
10157 else if (3 == insn_op1
)
10159 /* SPSR is going to be changed. */
10160 /* we need to get SPSR value, which is yet to be done */
10166 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10167 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10168 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10170 /* Handle load/store insn extension space. */
10172 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10173 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10174 && !INSN_RECORDED(arm_insn_r
))
10179 /* These insn, changes register and memory as well. */
10180 /* SWP or SWPB insn. */
10181 /* Get memory address given by Rn. */
10182 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10183 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10184 /* SWP insn ?, swaps word. */
10185 if (8 == arm_insn_r
->opcode
)
10187 record_buf_mem
[0] = 4;
10191 /* SWPB insn, swaps only byte. */
10192 record_buf_mem
[0] = 1;
10194 record_buf_mem
[1] = u_regval
;
10195 arm_insn_r
->mem_rec_count
= 1;
10196 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10197 arm_insn_r
->reg_rec_count
= 1;
10199 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10202 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10205 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10208 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10209 record_buf
[1] = record_buf
[0] + 1;
10210 arm_insn_r
->reg_rec_count
= 2;
10212 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10215 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10218 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10220 /* LDRH, LDRSB, LDRSH. */
10221 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10222 arm_insn_r
->reg_rec_count
= 1;
10227 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10228 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10229 && !INSN_RECORDED(arm_insn_r
))
10232 /* Handle coprocessor insn extension space. */
10235 /* To be done for ARMv5 and later; as of now we return -1. */
10239 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10240 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10245 /* Handling opcode 000 insns. */
10248 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10250 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10251 uint32_t record_buf
[8], record_buf_mem
[8];
10252 ULONGEST u_regval
[2] = {0};
10254 uint32_t reg_src1
= 0, reg_dest
= 0;
10255 uint32_t opcode1
= 0;
10257 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10258 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10259 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10261 /* Data processing insn /multiply insn. */
10262 if (9 == arm_insn_r
->decode
10263 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10264 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10266 /* Handle multiply instructions. */
10267 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10268 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10270 /* Handle MLA and MUL. */
10271 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10272 record_buf
[1] = ARM_PS_REGNUM
;
10273 arm_insn_r
->reg_rec_count
= 2;
10275 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10277 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10278 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10279 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10280 record_buf
[2] = ARM_PS_REGNUM
;
10281 arm_insn_r
->reg_rec_count
= 3;
10284 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10285 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10287 /* Handle misc load insns, as 20th bit (L = 1). */
10288 /* LDR insn has a capability to do branching, if
10289 MOV LR, PC is precceded by LDR insn having Rn as R15
10290 in that case, it emulates branch and link insn, and hence we
10291 need to save CSPR and PC as well. I am not sure this is right
10292 place; as opcode = 010 LDR insn make this happen, if R15 was
10294 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10295 if (15 != reg_dest
)
10297 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10298 arm_insn_r
->reg_rec_count
= 1;
10302 record_buf
[0] = reg_dest
;
10303 record_buf
[1] = ARM_PS_REGNUM
;
10304 arm_insn_r
->reg_rec_count
= 2;
10307 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10308 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10309 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10310 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10312 /* Handle MSR insn. */
10313 if (9 == arm_insn_r
->opcode
)
10315 /* CSPR is going to be changed. */
10316 record_buf
[0] = ARM_PS_REGNUM
;
10317 arm_insn_r
->reg_rec_count
= 1;
10321 /* SPSR is going to be changed. */
10322 /* How to read SPSR value? */
10326 else if (9 == arm_insn_r
->decode
10327 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10328 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10330 /* Handling SWP, SWPB. */
10331 /* These insn, changes register and memory as well. */
10332 /* SWP or SWPB insn. */
10334 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10335 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10336 /* SWP insn ?, swaps word. */
10337 if (8 == arm_insn_r
->opcode
)
10339 record_buf_mem
[0] = 4;
10343 /* SWPB insn, swaps only byte. */
10344 record_buf_mem
[0] = 1;
10346 record_buf_mem
[1] = u_regval
[0];
10347 arm_insn_r
->mem_rec_count
= 1;
10348 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10349 arm_insn_r
->reg_rec_count
= 1;
10351 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10352 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10354 /* Handle BLX, branch and link/exchange. */
10355 if (9 == arm_insn_r
->opcode
)
10357 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10358 and R14 stores the return address. */
10359 record_buf
[0] = ARM_PS_REGNUM
;
10360 record_buf
[1] = ARM_LR_REGNUM
;
10361 arm_insn_r
->reg_rec_count
= 2;
10364 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10366 /* Handle enhanced software breakpoint insn, BKPT. */
10367 /* CPSR is changed to be executed in ARM state, disabling normal
10368 interrupts, entering abort mode. */
10369 /* According to high vector configuration PC is set. */
10370 /* user hit breakpoint and type reverse, in
10371 that case, we need to go back with previous CPSR and
10372 Program Counter. */
10373 record_buf
[0] = ARM_PS_REGNUM
;
10374 record_buf
[1] = ARM_LR_REGNUM
;
10375 arm_insn_r
->reg_rec_count
= 2;
10377 /* Save SPSR also; how? */
10380 else if (11 == arm_insn_r
->decode
10381 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10383 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10385 /* Handle str(x) insn */
10386 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10389 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10390 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10392 /* Handle BX, branch and link/exchange. */
10393 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10394 record_buf
[0] = ARM_PS_REGNUM
;
10395 arm_insn_r
->reg_rec_count
= 1;
10397 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10398 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10399 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10401 /* Count leading zeros: CLZ. */
10402 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10403 arm_insn_r
->reg_rec_count
= 1;
10405 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10406 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10407 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10408 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10411 /* Handle MRS insn. */
10412 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10413 arm_insn_r
->reg_rec_count
= 1;
10415 else if (arm_insn_r
->opcode
<= 15)
10417 /* Normal data processing insns. */
10418 /* Out of 11 shifter operands mode, all the insn modifies destination
10419 register, which is specified by 13-16 decode. */
10420 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10421 record_buf
[1] = ARM_PS_REGNUM
;
10422 arm_insn_r
->reg_rec_count
= 2;
10429 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10430 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10434 /* Handling opcode 001 insns. */
10437 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10439 uint32_t record_buf
[8], record_buf_mem
[8];
10441 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10442 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10444 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10445 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10446 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10449 /* Handle MSR insn. */
10450 if (9 == arm_insn_r
->opcode
)
10452 /* CSPR is going to be changed. */
10453 record_buf
[0] = ARM_PS_REGNUM
;
10454 arm_insn_r
->reg_rec_count
= 1;
10458 /* SPSR is going to be changed. */
10461 else if (arm_insn_r
->opcode
<= 15)
10463 /* Normal data processing insns. */
10464 /* Out of 11 shifter operands mode, all the insn modifies destination
10465 register, which is specified by 13-16 decode. */
10466 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10467 record_buf
[1] = ARM_PS_REGNUM
;
10468 arm_insn_r
->reg_rec_count
= 2;
10475 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10476 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10481 arm_record_media (insn_decode_record
*arm_insn_r
)
10483 uint32_t record_buf
[8];
10485 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10488 /* Parallel addition and subtraction, signed */
10490 /* Parallel addition and subtraction, unsigned */
10493 /* Packing, unpacking, saturation and reversal */
10495 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10497 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10503 /* Signed multiplies */
10505 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10506 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10508 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10510 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10511 else if (op1
== 0x4)
10512 record_buf
[arm_insn_r
->reg_rec_count
++]
10513 = bits (arm_insn_r
->arm_insn
, 12, 15);
10519 if (bit (arm_insn_r
->arm_insn
, 21)
10520 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10523 record_buf
[arm_insn_r
->reg_rec_count
++]
10524 = bits (arm_insn_r
->arm_insn
, 12, 15);
10526 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10527 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10529 /* USAD8 and USADA8 */
10530 record_buf
[arm_insn_r
->reg_rec_count
++]
10531 = bits (arm_insn_r
->arm_insn
, 16, 19);
10538 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10539 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10541 /* Permanently UNDEFINED */
10546 /* BFC, BFI and UBFX */
10547 record_buf
[arm_insn_r
->reg_rec_count
++]
10548 = bits (arm_insn_r
->arm_insn
, 12, 15);
10557 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10562 /* Handle ARM mode instructions with opcode 010. */
10565 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10567 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10569 uint32_t reg_base
, reg_dest
;
10570 uint32_t offset_12
, tgt_mem_addr
;
10571 uint32_t record_buf
[8], record_buf_mem
[8];
10572 unsigned char wback
;
10575 /* Calculate wback. */
10576 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10577 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10579 arm_insn_r
->reg_rec_count
= 0;
10580 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10582 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10584 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10587 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10588 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10590 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10591 preceeds a LDR instruction having R15 as reg_base, it
10592 emulates a branch and link instruction, and hence we need to save
10593 CPSR and PC as well. */
10594 if (ARM_PC_REGNUM
== reg_dest
)
10595 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10597 /* If wback is true, also save the base register, which is going to be
10600 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10604 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10606 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10607 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10609 /* Handle bit U. */
10610 if (bit (arm_insn_r
->arm_insn
, 23))
10612 /* U == 1: Add the offset. */
10613 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10617 /* U == 0: subtract the offset. */
10618 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10621 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10623 if (bit (arm_insn_r
->arm_insn
, 22))
10625 /* STRB and STRBT: 1 byte. */
10626 record_buf_mem
[0] = 1;
10630 /* STR and STRT: 4 bytes. */
10631 record_buf_mem
[0] = 4;
10634 /* Handle bit P. */
10635 if (bit (arm_insn_r
->arm_insn
, 24))
10636 record_buf_mem
[1] = tgt_mem_addr
;
10638 record_buf_mem
[1] = (uint32_t) u_regval
;
10640 arm_insn_r
->mem_rec_count
= 1;
10642 /* If wback is true, also save the base register, which is going to be
10645 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10648 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10649 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10653 /* Handling opcode 011 insns. */
10656 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10658 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10660 uint32_t shift_imm
= 0;
10661 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10662 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10663 uint32_t record_buf
[8], record_buf_mem
[8];
10666 ULONGEST u_regval
[2];
10668 if (bit (arm_insn_r
->arm_insn
, 4))
10669 return arm_record_media (arm_insn_r
);
10671 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10672 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10674 /* Handle enhanced store insns and LDRD DSP insn,
10675 order begins according to addressing modes for store insns
10679 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10681 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10682 /* LDR insn has a capability to do branching, if
10683 MOV LR, PC is precedded by LDR insn having Rn as R15
10684 in that case, it emulates branch and link insn, and hence we
10685 need to save CSPR and PC as well. */
10686 if (15 != reg_dest
)
10688 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10689 arm_insn_r
->reg_rec_count
= 1;
10693 record_buf
[0] = reg_dest
;
10694 record_buf
[1] = ARM_PS_REGNUM
;
10695 arm_insn_r
->reg_rec_count
= 2;
10700 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10702 /* Store insn, register offset and register pre-indexed,
10703 register post-indexed. */
10705 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10707 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10708 regcache_raw_read_unsigned (reg_cache
, reg_src1
10710 regcache_raw_read_unsigned (reg_cache
, reg_src2
10712 if (15 == reg_src2
)
10714 /* If R15 was used as Rn, hence current PC+8. */
10715 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10716 u_regval
[0] = u_regval
[0] + 8;
10718 /* Calculate target store address, Rn +/- Rm, register offset. */
10720 if (bit (arm_insn_r
->arm_insn
, 23))
10722 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10726 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10729 switch (arm_insn_r
->opcode
)
10743 record_buf_mem
[0] = 4;
10758 record_buf_mem
[0] = 1;
10762 gdb_assert_not_reached ("no decoding pattern found");
10765 record_buf_mem
[1] = tgt_mem_addr
;
10766 arm_insn_r
->mem_rec_count
= 1;
10768 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10769 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10770 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10771 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10772 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10773 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10776 /* Rn is going to be changed in pre-indexed mode and
10777 post-indexed mode as well. */
10778 record_buf
[0] = reg_src2
;
10779 arm_insn_r
->reg_rec_count
= 1;
10784 /* Store insn, scaled register offset; scaled pre-indexed. */
10785 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10787 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10789 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10790 /* Get shift_imm. */
10791 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10792 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10793 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10794 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10795 /* Offset_12 used as shift. */
10799 /* Offset_12 used as index. */
10800 offset_12
= u_regval
[0] << shift_imm
;
10804 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10810 if (bit (u_regval
[0], 31))
10812 offset_12
= 0xFFFFFFFF;
10821 /* This is arithmetic shift. */
10822 offset_12
= s_word
>> shift_imm
;
10829 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10831 /* Get C flag value and shift it by 31. */
10832 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10833 | (u_regval
[0]) >> 1);
10837 offset_12
= (u_regval
[0] >> shift_imm
) \
10839 (sizeof(uint32_t) - shift_imm
));
10844 gdb_assert_not_reached ("no decoding pattern found");
10848 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10850 if (bit (arm_insn_r
->arm_insn
, 23))
10852 tgt_mem_addr
= u_regval
[1] + offset_12
;
10856 tgt_mem_addr
= u_regval
[1] - offset_12
;
10859 switch (arm_insn_r
->opcode
)
10873 record_buf_mem
[0] = 4;
10888 record_buf_mem
[0] = 1;
10892 gdb_assert_not_reached ("no decoding pattern found");
10895 record_buf_mem
[1] = tgt_mem_addr
;
10896 arm_insn_r
->mem_rec_count
= 1;
10898 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10899 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10900 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10901 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10902 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10903 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10906 /* Rn is going to be changed in register scaled pre-indexed
10907 mode,and scaled post indexed mode. */
10908 record_buf
[0] = reg_src2
;
10909 arm_insn_r
->reg_rec_count
= 1;
10914 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10915 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10919 /* Handle ARM mode instructions with opcode 100. */
10922 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10924 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10925 uint32_t register_count
= 0, register_bits
;
10926 uint32_t reg_base
, addr_mode
;
10927 uint32_t record_buf
[24], record_buf_mem
[48];
10931 /* Fetch the list of registers. */
10932 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10933 arm_insn_r
->reg_rec_count
= 0;
10935 /* Fetch the base register that contains the address we are loading data
10937 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10939 /* Calculate wback. */
10940 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10942 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10944 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10946 /* Find out which registers are going to be loaded from memory. */
10947 while (register_bits
)
10949 if (register_bits
& 0x00000001)
10950 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10951 register_bits
= register_bits
>> 1;
10956 /* If wback is true, also save the base register, which is going to be
10959 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10961 /* Save the CPSR register. */
10962 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10966 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10968 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10970 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10972 /* Find out how many registers are going to be stored to memory. */
10973 while (register_bits
)
10975 if (register_bits
& 0x00000001)
10977 register_bits
= register_bits
>> 1;
10982 /* STMDA (STMED): Decrement after. */
10984 record_buf_mem
[1] = (uint32_t) u_regval
10985 - register_count
* INT_REGISTER_SIZE
+ 4;
10987 /* STM (STMIA, STMEA): Increment after. */
10989 record_buf_mem
[1] = (uint32_t) u_regval
;
10991 /* STMDB (STMFD): Decrement before. */
10993 record_buf_mem
[1] = (uint32_t) u_regval
10994 - register_count
* INT_REGISTER_SIZE
;
10996 /* STMIB (STMFA): Increment before. */
10998 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11001 gdb_assert_not_reached ("no decoding pattern found");
11005 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11006 arm_insn_r
->mem_rec_count
= 1;
11008 /* If wback is true, also save the base register, which is going to be
11011 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11014 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11015 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11019 /* Handling opcode 101 insns. */
11022 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11024 uint32_t record_buf
[8];
11026 /* Handle B, BL, BLX(1) insns. */
11027 /* B simply branches so we do nothing here. */
11028 /* Note: BLX(1) doesnt fall here but instead it falls into
11029 extension space. */
11030 if (bit (arm_insn_r
->arm_insn
, 24))
11032 record_buf
[0] = ARM_LR_REGNUM
;
11033 arm_insn_r
->reg_rec_count
= 1;
11036 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11042 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11044 printf_unfiltered (_("Process record does not support instruction "
11045 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11046 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11051 /* Record handler for vector data transfer instructions. */
11054 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11056 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11057 uint32_t record_buf
[4];
11059 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11060 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11061 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11062 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11063 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11065 /* Handle VMOV instruction. */
11066 if (bit_l
&& bit_c
)
11068 record_buf
[0] = reg_t
;
11069 arm_insn_r
->reg_rec_count
= 1;
11071 else if (bit_l
&& !bit_c
)
11073 /* Handle VMOV instruction. */
11074 if (bits_a
== 0x00)
11076 record_buf
[0] = reg_t
;
11077 arm_insn_r
->reg_rec_count
= 1;
11079 /* Handle VMRS instruction. */
11080 else if (bits_a
== 0x07)
11083 reg_t
= ARM_PS_REGNUM
;
11085 record_buf
[0] = reg_t
;
11086 arm_insn_r
->reg_rec_count
= 1;
11089 else if (!bit_l
&& !bit_c
)
11091 /* Handle VMOV instruction. */
11092 if (bits_a
== 0x00)
11094 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11096 arm_insn_r
->reg_rec_count
= 1;
11098 /* Handle VMSR instruction. */
11099 else if (bits_a
== 0x07)
11101 record_buf
[0] = ARM_FPSCR_REGNUM
;
11102 arm_insn_r
->reg_rec_count
= 1;
11105 else if (!bit_l
&& bit_c
)
11107 /* Handle VMOV instruction. */
11108 if (!(bits_a
& 0x04))
11110 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11112 arm_insn_r
->reg_rec_count
= 1;
11114 /* Handle VDUP instruction. */
11117 if (bit (arm_insn_r
->arm_insn
, 21))
11119 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11120 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11121 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11122 arm_insn_r
->reg_rec_count
= 2;
11126 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11127 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11128 arm_insn_r
->reg_rec_count
= 1;
11133 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11137 /* Record handler for extension register load/store instructions. */
11140 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11142 uint32_t opcode
, single_reg
;
11143 uint8_t op_vldm_vstm
;
11144 uint32_t record_buf
[8], record_buf_mem
[128];
11145 ULONGEST u_regval
= 0;
11147 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11149 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11150 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11151 op_vldm_vstm
= opcode
& 0x1b;
11153 /* Handle VMOV instructions. */
11154 if ((opcode
& 0x1e) == 0x04)
11156 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11158 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11159 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11160 arm_insn_r
->reg_rec_count
= 2;
11164 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11165 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11169 /* The first S register number m is REG_M:M (M is bit 5),
11170 the corresponding D register number is REG_M:M / 2, which
11172 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11173 /* The second S register number is REG_M:M + 1, the
11174 corresponding D register number is (REG_M:M + 1) / 2.
11175 IOW, if bit M is 1, the first and second S registers
11176 are mapped to different D registers, otherwise, they are
11177 in the same D register. */
11180 record_buf
[arm_insn_r
->reg_rec_count
++]
11181 = ARM_D0_REGNUM
+ reg_m
+ 1;
11186 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11187 arm_insn_r
->reg_rec_count
= 1;
11191 /* Handle VSTM and VPUSH instructions. */
11192 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11193 || op_vldm_vstm
== 0x12)
11195 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11196 uint32_t memory_index
= 0;
11198 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11199 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11200 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11201 imm_off32
= imm_off8
<< 2;
11202 memory_count
= imm_off8
;
11204 if (bit (arm_insn_r
->arm_insn
, 23))
11205 start_address
= u_regval
;
11207 start_address
= u_regval
- imm_off32
;
11209 if (bit (arm_insn_r
->arm_insn
, 21))
11211 record_buf
[0] = reg_rn
;
11212 arm_insn_r
->reg_rec_count
= 1;
11215 while (memory_count
> 0)
11219 record_buf_mem
[memory_index
] = 4;
11220 record_buf_mem
[memory_index
+ 1] = start_address
;
11221 start_address
= start_address
+ 4;
11222 memory_index
= memory_index
+ 2;
11226 record_buf_mem
[memory_index
] = 4;
11227 record_buf_mem
[memory_index
+ 1] = start_address
;
11228 record_buf_mem
[memory_index
+ 2] = 4;
11229 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11230 start_address
= start_address
+ 8;
11231 memory_index
= memory_index
+ 4;
11235 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11237 /* Handle VLDM instructions. */
11238 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11239 || op_vldm_vstm
== 0x13)
11241 uint32_t reg_count
, reg_vd
;
11242 uint32_t reg_index
= 0;
11243 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11245 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11246 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11248 /* REG_VD is the first D register number. If the instruction
11249 loads memory to S registers (SINGLE_REG is TRUE), the register
11250 number is (REG_VD << 1 | bit D), so the corresponding D
11251 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11253 reg_vd
= reg_vd
| (bit_d
<< 4);
11255 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11256 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11258 /* If the instruction loads memory to D register, REG_COUNT should
11259 be divided by 2, according to the ARM Architecture Reference
11260 Manual. If the instruction loads memory to S register, divide by
11261 2 as well because two S registers are mapped to D register. */
11262 reg_count
= reg_count
/ 2;
11263 if (single_reg
&& bit_d
)
11265 /* Increase the register count if S register list starts from
11266 an odd number (bit d is one). */
11270 while (reg_count
> 0)
11272 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11275 arm_insn_r
->reg_rec_count
= reg_index
;
11277 /* VSTR Vector store register. */
11278 else if ((opcode
& 0x13) == 0x10)
11280 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11281 uint32_t memory_index
= 0;
11283 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11284 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11285 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11286 imm_off32
= imm_off8
<< 2;
11288 if (bit (arm_insn_r
->arm_insn
, 23))
11289 start_address
= u_regval
+ imm_off32
;
11291 start_address
= u_regval
- imm_off32
;
11295 record_buf_mem
[memory_index
] = 4;
11296 record_buf_mem
[memory_index
+ 1] = start_address
;
11297 arm_insn_r
->mem_rec_count
= 1;
11301 record_buf_mem
[memory_index
] = 4;
11302 record_buf_mem
[memory_index
+ 1] = start_address
;
11303 record_buf_mem
[memory_index
+ 2] = 4;
11304 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11305 arm_insn_r
->mem_rec_count
= 2;
11308 /* VLDR Vector load register. */
11309 else if ((opcode
& 0x13) == 0x11)
11311 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11315 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11316 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11320 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11321 /* Record register D rather than pseudo register S. */
11322 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11324 arm_insn_r
->reg_rec_count
= 1;
11327 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11328 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11332 /* Record handler for arm/thumb mode VFP data processing instructions. */
11335 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11337 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11338 uint32_t record_buf
[4];
11339 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11340 enum insn_types curr_insn_type
= INSN_INV
;
11342 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11343 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11344 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11345 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11346 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11347 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11348 opc1
= opc1
& 0x04;
11350 /* Handle VMLA, VMLS. */
11353 if (bit (arm_insn_r
->arm_insn
, 10))
11355 if (bit (arm_insn_r
->arm_insn
, 6))
11356 curr_insn_type
= INSN_T0
;
11358 curr_insn_type
= INSN_T1
;
11363 curr_insn_type
= INSN_T1
;
11365 curr_insn_type
= INSN_T2
;
11368 /* Handle VNMLA, VNMLS, VNMUL. */
11369 else if (opc1
== 0x01)
11372 curr_insn_type
= INSN_T1
;
11374 curr_insn_type
= INSN_T2
;
11377 else if (opc1
== 0x02 && !(opc3
& 0x01))
11379 if (bit (arm_insn_r
->arm_insn
, 10))
11381 if (bit (arm_insn_r
->arm_insn
, 6))
11382 curr_insn_type
= INSN_T0
;
11384 curr_insn_type
= INSN_T1
;
11389 curr_insn_type
= INSN_T1
;
11391 curr_insn_type
= INSN_T2
;
11394 /* Handle VADD, VSUB. */
11395 else if (opc1
== 0x03)
11397 if (!bit (arm_insn_r
->arm_insn
, 9))
11399 if (bit (arm_insn_r
->arm_insn
, 6))
11400 curr_insn_type
= INSN_T0
;
11402 curr_insn_type
= INSN_T1
;
11407 curr_insn_type
= INSN_T1
;
11409 curr_insn_type
= INSN_T2
;
11413 else if (opc1
== 0x0b)
11416 curr_insn_type
= INSN_T1
;
11418 curr_insn_type
= INSN_T2
;
11420 /* Handle all other vfp data processing instructions. */
11421 else if (opc1
== 0x0b)
11424 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11426 if (bit (arm_insn_r
->arm_insn
, 4))
11428 if (bit (arm_insn_r
->arm_insn
, 6))
11429 curr_insn_type
= INSN_T0
;
11431 curr_insn_type
= INSN_T1
;
11436 curr_insn_type
= INSN_T1
;
11438 curr_insn_type
= INSN_T2
;
11441 /* Handle VNEG and VABS. */
11442 else if ((opc2
== 0x01 && opc3
== 0x01)
11443 || (opc2
== 0x00 && opc3
== 0x03))
11445 if (!bit (arm_insn_r
->arm_insn
, 11))
11447 if (bit (arm_insn_r
->arm_insn
, 6))
11448 curr_insn_type
= INSN_T0
;
11450 curr_insn_type
= INSN_T1
;
11455 curr_insn_type
= INSN_T1
;
11457 curr_insn_type
= INSN_T2
;
11460 /* Handle VSQRT. */
11461 else if (opc2
== 0x01 && opc3
== 0x03)
11464 curr_insn_type
= INSN_T1
;
11466 curr_insn_type
= INSN_T2
;
11469 else if (opc2
== 0x07 && opc3
== 0x03)
11472 curr_insn_type
= INSN_T1
;
11474 curr_insn_type
= INSN_T2
;
11476 else if (opc3
& 0x01)
11479 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11481 if (!bit (arm_insn_r
->arm_insn
, 18))
11482 curr_insn_type
= INSN_T2
;
11486 curr_insn_type
= INSN_T1
;
11488 curr_insn_type
= INSN_T2
;
11492 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11495 curr_insn_type
= INSN_T1
;
11497 curr_insn_type
= INSN_T2
;
11499 /* Handle VCVTB, VCVTT. */
11500 else if ((opc2
& 0x0e) == 0x02)
11501 curr_insn_type
= INSN_T2
;
11502 /* Handle VCMP, VCMPE. */
11503 else if ((opc2
& 0x0e) == 0x04)
11504 curr_insn_type
= INSN_T3
;
11508 switch (curr_insn_type
)
11511 reg_vd
= reg_vd
| (bit_d
<< 4);
11512 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11513 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11514 arm_insn_r
->reg_rec_count
= 2;
11518 reg_vd
= reg_vd
| (bit_d
<< 4);
11519 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11520 arm_insn_r
->reg_rec_count
= 1;
11524 reg_vd
= (reg_vd
<< 1) | bit_d
;
11525 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11526 arm_insn_r
->reg_rec_count
= 1;
11530 record_buf
[0] = ARM_FPSCR_REGNUM
;
11531 arm_insn_r
->reg_rec_count
= 1;
11535 gdb_assert_not_reached ("no decoding pattern found");
11539 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11543 /* Handling opcode 110 insns. */
11546 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11548 uint32_t op1
, op1_ebit
, coproc
;
11550 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11551 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11552 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11554 if ((coproc
& 0x0e) == 0x0a)
11556 /* Handle extension register ld/st instructions. */
11558 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11560 /* 64-bit transfers between arm core and extension registers. */
11561 if ((op1
& 0x3e) == 0x04)
11562 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11566 /* Handle coprocessor ld/st instructions. */
11571 return arm_record_unsupported_insn (arm_insn_r
);
11574 return arm_record_unsupported_insn (arm_insn_r
);
11577 /* Move to coprocessor from two arm core registers. */
11579 return arm_record_unsupported_insn (arm_insn_r
);
11581 /* Move to two arm core registers from coprocessor. */
11586 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11587 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11588 arm_insn_r
->reg_rec_count
= 2;
11590 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11594 return arm_record_unsupported_insn (arm_insn_r
);
11597 /* Handling opcode 111 insns. */
11600 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11602 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11603 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11604 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11606 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11607 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11608 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11609 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11610 op
= bit (arm_insn_r
->arm_insn
, 4);
11612 /* Handle arm SWI/SVC system call instructions. */
11615 if (tdep
->arm_syscall_record
!= NULL
)
11617 ULONGEST svc_operand
, svc_number
;
11619 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11621 if (svc_operand
) /* OABI. */
11622 svc_number
= svc_operand
- 0x900000;
11624 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11626 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11630 printf_unfiltered (_("no syscall record support\n"));
11635 if ((coproc
& 0x0e) == 0x0a)
11637 /* VFP data-processing instructions. */
11638 if (!op1_sbit
&& !op
)
11639 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11641 /* Advanced SIMD, VFP instructions. */
11642 if (!op1_sbit
&& op
)
11643 return arm_record_vdata_transfer_insn (arm_insn_r
);
11647 /* Coprocessor data operations. */
11648 if (!op1_sbit
&& !op
)
11649 return arm_record_unsupported_insn (arm_insn_r
);
11651 /* Move to Coprocessor from ARM core register. */
11652 if (!op1_sbit
&& !op1_ebit
&& op
)
11653 return arm_record_unsupported_insn (arm_insn_r
);
11655 /* Move to arm core register from coprocessor. */
11656 if (!op1_sbit
&& op1_ebit
&& op
)
11658 uint32_t record_buf
[1];
11660 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11661 if (record_buf
[0] == 15)
11662 record_buf
[0] = ARM_PS_REGNUM
;
11664 arm_insn_r
->reg_rec_count
= 1;
11665 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11671 return arm_record_unsupported_insn (arm_insn_r
);
11674 /* Handling opcode 000 insns. */
11677 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11679 uint32_t record_buf
[8];
11680 uint32_t reg_src1
= 0;
11682 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11684 record_buf
[0] = ARM_PS_REGNUM
;
11685 record_buf
[1] = reg_src1
;
11686 thumb_insn_r
->reg_rec_count
= 2;
11688 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11694 /* Handling opcode 001 insns. */
11697 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11699 uint32_t record_buf
[8];
11700 uint32_t reg_src1
= 0;
11702 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11704 record_buf
[0] = ARM_PS_REGNUM
;
11705 record_buf
[1] = reg_src1
;
11706 thumb_insn_r
->reg_rec_count
= 2;
11708 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11713 /* Handling opcode 010 insns. */
11716 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11718 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11719 uint32_t record_buf
[8], record_buf_mem
[8];
11721 uint32_t reg_src1
= 0, reg_src2
= 0;
11722 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11724 ULONGEST u_regval
[2] = {0};
11726 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11728 if (bit (thumb_insn_r
->arm_insn
, 12))
11730 /* Handle load/store register offset. */
11731 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11732 if (opcode2
>= 12 && opcode2
<= 15)
11734 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11735 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11736 record_buf
[0] = reg_src1
;
11737 thumb_insn_r
->reg_rec_count
= 1;
11739 else if (opcode2
>= 8 && opcode2
<= 10)
11741 /* STR(2), STRB(2), STRH(2) . */
11742 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11743 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11744 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11745 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11747 record_buf_mem
[0] = 4; /* STR (2). */
11748 else if (10 == opcode2
)
11749 record_buf_mem
[0] = 1; /* STRB (2). */
11750 else if (9 == opcode2
)
11751 record_buf_mem
[0] = 2; /* STRH (2). */
11752 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11753 thumb_insn_r
->mem_rec_count
= 1;
11756 else if (bit (thumb_insn_r
->arm_insn
, 11))
11758 /* Handle load from literal pool. */
11760 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11761 record_buf
[0] = reg_src1
;
11762 thumb_insn_r
->reg_rec_count
= 1;
11766 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11767 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11768 if ((3 == opcode2
) && (!opcode3
))
11770 /* Branch with exchange. */
11771 record_buf
[0] = ARM_PS_REGNUM
;
11772 thumb_insn_r
->reg_rec_count
= 1;
11776 /* Format 8; special data processing insns. */
11777 record_buf
[0] = ARM_PS_REGNUM
;
11778 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11779 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11780 thumb_insn_r
->reg_rec_count
= 2;
11785 /* Format 5; data processing insns. */
11786 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11787 if (bit (thumb_insn_r
->arm_insn
, 7))
11789 reg_src1
= reg_src1
+ 8;
11791 record_buf
[0] = ARM_PS_REGNUM
;
11792 record_buf
[1] = reg_src1
;
11793 thumb_insn_r
->reg_rec_count
= 2;
11796 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11797 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11803 /* Handling opcode 001 insns. */
11806 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11808 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11809 uint32_t record_buf
[8], record_buf_mem
[8];
11811 uint32_t reg_src1
= 0;
11812 uint32_t opcode
= 0, immed_5
= 0;
11814 ULONGEST u_regval
= 0;
11816 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11821 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11822 record_buf
[0] = reg_src1
;
11823 thumb_insn_r
->reg_rec_count
= 1;
11828 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11829 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11830 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11831 record_buf_mem
[0] = 4;
11832 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11833 thumb_insn_r
->mem_rec_count
= 1;
11836 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11837 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11843 /* Handling opcode 100 insns. */
11846 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11848 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11849 uint32_t record_buf
[8], record_buf_mem
[8];
11851 uint32_t reg_src1
= 0;
11852 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11854 ULONGEST u_regval
= 0;
11856 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11861 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11862 record_buf
[0] = reg_src1
;
11863 thumb_insn_r
->reg_rec_count
= 1;
11865 else if (1 == opcode
)
11868 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11869 record_buf
[0] = reg_src1
;
11870 thumb_insn_r
->reg_rec_count
= 1;
11872 else if (2 == opcode
)
11875 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11876 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11877 record_buf_mem
[0] = 4;
11878 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11879 thumb_insn_r
->mem_rec_count
= 1;
11881 else if (0 == opcode
)
11884 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11885 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11886 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11887 record_buf_mem
[0] = 2;
11888 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11889 thumb_insn_r
->mem_rec_count
= 1;
11892 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11893 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11899 /* Handling opcode 101 insns. */
11902 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11904 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11906 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11907 uint32_t register_bits
= 0, register_count
= 0;
11908 uint32_t index
= 0, start_address
= 0;
11909 uint32_t record_buf
[24], record_buf_mem
[48];
11912 ULONGEST u_regval
= 0;
11914 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11915 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11916 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11921 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11922 while (register_bits
)
11924 if (register_bits
& 0x00000001)
11925 record_buf
[index
++] = register_count
;
11926 register_bits
= register_bits
>> 1;
11929 record_buf
[index
++] = ARM_PS_REGNUM
;
11930 record_buf
[index
++] = ARM_SP_REGNUM
;
11931 thumb_insn_r
->reg_rec_count
= index
;
11933 else if (10 == opcode2
)
11936 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11937 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11938 while (register_bits
)
11940 if (register_bits
& 0x00000001)
11942 register_bits
= register_bits
>> 1;
11944 start_address
= u_regval
- \
11945 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11946 thumb_insn_r
->mem_rec_count
= register_count
;
11947 while (register_count
)
11949 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11950 record_buf_mem
[(register_count
* 2) - 2] = 4;
11951 start_address
= start_address
+ 4;
11954 record_buf
[0] = ARM_SP_REGNUM
;
11955 thumb_insn_r
->reg_rec_count
= 1;
11957 else if (0x1E == opcode1
)
11960 /* Handle enhanced software breakpoint insn, BKPT. */
11961 /* CPSR is changed to be executed in ARM state, disabling normal
11962 interrupts, entering abort mode. */
11963 /* According to high vector configuration PC is set. */
11964 /* User hits breakpoint and type reverse, in that case, we need to go back with
11965 previous CPSR and Program Counter. */
11966 record_buf
[0] = ARM_PS_REGNUM
;
11967 record_buf
[1] = ARM_LR_REGNUM
;
11968 thumb_insn_r
->reg_rec_count
= 2;
11969 /* We need to save SPSR value, which is not yet done. */
11970 printf_unfiltered (_("Process record does not support instruction "
11971 "0x%0x at address %s.\n"),
11972 thumb_insn_r
->arm_insn
,
11973 paddress (thumb_insn_r
->gdbarch
,
11974 thumb_insn_r
->this_addr
));
11977 else if ((0 == opcode
) || (1 == opcode
))
11979 /* ADD(5), ADD(6). */
11980 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11981 record_buf
[0] = reg_src1
;
11982 thumb_insn_r
->reg_rec_count
= 1;
11984 else if (2 == opcode
)
11986 /* ADD(7), SUB(4). */
11987 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11988 record_buf
[0] = ARM_SP_REGNUM
;
11989 thumb_insn_r
->reg_rec_count
= 1;
11992 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11993 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11999 /* Handling opcode 110 insns. */
12002 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12004 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12005 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12007 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12008 uint32_t reg_src1
= 0;
12009 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12010 uint32_t index
= 0, start_address
= 0;
12011 uint32_t record_buf
[24], record_buf_mem
[48];
12013 ULONGEST u_regval
= 0;
12015 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12016 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12022 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12024 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12025 while (register_bits
)
12027 if (register_bits
& 0x00000001)
12028 record_buf
[index
++] = register_count
;
12029 register_bits
= register_bits
>> 1;
12032 record_buf
[index
++] = reg_src1
;
12033 thumb_insn_r
->reg_rec_count
= index
;
12035 else if (0 == opcode2
)
12037 /* It handles both STMIA. */
12038 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12040 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12041 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12042 while (register_bits
)
12044 if (register_bits
& 0x00000001)
12046 register_bits
= register_bits
>> 1;
12048 start_address
= u_regval
;
12049 thumb_insn_r
->mem_rec_count
= register_count
;
12050 while (register_count
)
12052 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12053 record_buf_mem
[(register_count
* 2) - 2] = 4;
12054 start_address
= start_address
+ 4;
12058 else if (0x1F == opcode1
)
12060 /* Handle arm syscall insn. */
12061 if (tdep
->arm_syscall_record
!= NULL
)
12063 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12064 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12068 printf_unfiltered (_("no syscall record support\n"));
12073 /* B (1), conditional branch is automatically taken care in process_record,
12074 as PC is saved there. */
12076 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12077 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12083 /* Handling opcode 111 insns. */
12086 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12088 uint32_t record_buf
[8];
12089 uint32_t bits_h
= 0;
12091 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12093 if (2 == bits_h
|| 3 == bits_h
)
12096 record_buf
[0] = ARM_LR_REGNUM
;
12097 thumb_insn_r
->reg_rec_count
= 1;
12099 else if (1 == bits_h
)
12102 record_buf
[0] = ARM_PS_REGNUM
;
12103 record_buf
[1] = ARM_LR_REGNUM
;
12104 thumb_insn_r
->reg_rec_count
= 2;
12107 /* B(2) is automatically taken care in process_record, as PC is
12110 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12115 /* Handler for thumb2 load/store multiple instructions. */
12118 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12120 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12122 uint32_t reg_rn
, op
;
12123 uint32_t register_bits
= 0, register_count
= 0;
12124 uint32_t index
= 0, start_address
= 0;
12125 uint32_t record_buf
[24], record_buf_mem
[48];
12127 ULONGEST u_regval
= 0;
12129 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12130 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12132 if (0 == op
|| 3 == op
)
12134 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12136 /* Handle RFE instruction. */
12137 record_buf
[0] = ARM_PS_REGNUM
;
12138 thumb2_insn_r
->reg_rec_count
= 1;
12142 /* Handle SRS instruction after reading banked SP. */
12143 return arm_record_unsupported_insn (thumb2_insn_r
);
12146 else if (1 == op
|| 2 == op
)
12148 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12150 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12151 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12152 while (register_bits
)
12154 if (register_bits
& 0x00000001)
12155 record_buf
[index
++] = register_count
;
12158 register_bits
= register_bits
>> 1;
12160 record_buf
[index
++] = reg_rn
;
12161 record_buf
[index
++] = ARM_PS_REGNUM
;
12162 thumb2_insn_r
->reg_rec_count
= index
;
12166 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12167 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12168 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12169 while (register_bits
)
12171 if (register_bits
& 0x00000001)
12174 register_bits
= register_bits
>> 1;
12179 /* Start address calculation for LDMDB/LDMEA. */
12180 start_address
= u_regval
;
12184 /* Start address calculation for LDMDB/LDMEA. */
12185 start_address
= u_regval
- register_count
* 4;
12188 thumb2_insn_r
->mem_rec_count
= register_count
;
12189 while (register_count
)
12191 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12192 record_buf_mem
[register_count
* 2 - 2] = 4;
12193 start_address
= start_address
+ 4;
12196 record_buf
[0] = reg_rn
;
12197 record_buf
[1] = ARM_PS_REGNUM
;
12198 thumb2_insn_r
->reg_rec_count
= 2;
12202 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12204 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12206 return ARM_RECORD_SUCCESS
;
12209 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12213 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12215 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12217 uint32_t reg_rd
, reg_rn
, offset_imm
;
12218 uint32_t reg_dest1
, reg_dest2
;
12219 uint32_t address
, offset_addr
;
12220 uint32_t record_buf
[8], record_buf_mem
[8];
12221 uint32_t op1
, op2
, op3
;
12223 ULONGEST u_regval
[2];
12225 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12226 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12227 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12229 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12231 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12233 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12234 record_buf
[0] = reg_dest1
;
12235 record_buf
[1] = ARM_PS_REGNUM
;
12236 thumb2_insn_r
->reg_rec_count
= 2;
12239 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12241 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12242 record_buf
[2] = reg_dest2
;
12243 thumb2_insn_r
->reg_rec_count
= 3;
12248 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12249 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12251 if (0 == op1
&& 0 == op2
)
12253 /* Handle STREX. */
12254 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12255 address
= u_regval
[0] + (offset_imm
* 4);
12256 record_buf_mem
[0] = 4;
12257 record_buf_mem
[1] = address
;
12258 thumb2_insn_r
->mem_rec_count
= 1;
12259 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12260 record_buf
[0] = reg_rd
;
12261 thumb2_insn_r
->reg_rec_count
= 1;
12263 else if (1 == op1
&& 0 == op2
)
12265 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12266 record_buf
[0] = reg_rd
;
12267 thumb2_insn_r
->reg_rec_count
= 1;
12268 address
= u_regval
[0];
12269 record_buf_mem
[1] = address
;
12273 /* Handle STREXB. */
12274 record_buf_mem
[0] = 1;
12275 thumb2_insn_r
->mem_rec_count
= 1;
12279 /* Handle STREXH. */
12280 record_buf_mem
[0] = 2 ;
12281 thumb2_insn_r
->mem_rec_count
= 1;
12285 /* Handle STREXD. */
12286 address
= u_regval
[0];
12287 record_buf_mem
[0] = 4;
12288 record_buf_mem
[2] = 4;
12289 record_buf_mem
[3] = address
+ 4;
12290 thumb2_insn_r
->mem_rec_count
= 2;
12295 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12297 if (bit (thumb2_insn_r
->arm_insn
, 24))
12299 if (bit (thumb2_insn_r
->arm_insn
, 23))
12300 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12302 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12304 address
= offset_addr
;
12307 address
= u_regval
[0];
12309 record_buf_mem
[0] = 4;
12310 record_buf_mem
[1] = address
;
12311 record_buf_mem
[2] = 4;
12312 record_buf_mem
[3] = address
+ 4;
12313 thumb2_insn_r
->mem_rec_count
= 2;
12314 record_buf
[0] = reg_rn
;
12315 thumb2_insn_r
->reg_rec_count
= 1;
12319 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12321 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12323 return ARM_RECORD_SUCCESS
;
12326 /* Handler for thumb2 data processing (shift register and modified immediate)
12330 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12332 uint32_t reg_rd
, op
;
12333 uint32_t record_buf
[8];
12335 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12336 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12338 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12340 record_buf
[0] = ARM_PS_REGNUM
;
12341 thumb2_insn_r
->reg_rec_count
= 1;
12345 record_buf
[0] = reg_rd
;
12346 record_buf
[1] = ARM_PS_REGNUM
;
12347 thumb2_insn_r
->reg_rec_count
= 2;
12350 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12352 return ARM_RECORD_SUCCESS
;
12355 /* Generic handler for thumb2 instructions which effect destination and PS
12359 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12362 uint32_t record_buf
[8];
12364 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12366 record_buf
[0] = reg_rd
;
12367 record_buf
[1] = ARM_PS_REGNUM
;
12368 thumb2_insn_r
->reg_rec_count
= 2;
12370 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12372 return ARM_RECORD_SUCCESS
;
12375 /* Handler for thumb2 branch and miscellaneous control instructions. */
12378 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12380 uint32_t op
, op1
, op2
;
12381 uint32_t record_buf
[8];
12383 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12384 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12385 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12387 /* Handle MSR insn. */
12388 if (!(op1
& 0x2) && 0x38 == op
)
12392 /* CPSR is going to be changed. */
12393 record_buf
[0] = ARM_PS_REGNUM
;
12394 thumb2_insn_r
->reg_rec_count
= 1;
12398 arm_record_unsupported_insn(thumb2_insn_r
);
12402 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12405 record_buf
[0] = ARM_PS_REGNUM
;
12406 record_buf
[1] = ARM_LR_REGNUM
;
12407 thumb2_insn_r
->reg_rec_count
= 2;
12410 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12412 return ARM_RECORD_SUCCESS
;
12415 /* Handler for thumb2 store single data item instructions. */
12418 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12420 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12422 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12423 uint32_t address
, offset_addr
;
12424 uint32_t record_buf
[8], record_buf_mem
[8];
12427 ULONGEST u_regval
[2];
12429 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12430 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12431 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12432 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12434 if (bit (thumb2_insn_r
->arm_insn
, 23))
12437 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12438 offset_addr
= u_regval
[0] + offset_imm
;
12439 address
= offset_addr
;
12444 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12446 /* Handle STRB (register). */
12447 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12448 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12449 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12450 offset_addr
= u_regval
[1] << shift_imm
;
12451 address
= u_regval
[0] + offset_addr
;
12455 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12456 if (bit (thumb2_insn_r
->arm_insn
, 10))
12458 if (bit (thumb2_insn_r
->arm_insn
, 9))
12459 offset_addr
= u_regval
[0] + offset_imm
;
12461 offset_addr
= u_regval
[0] - offset_imm
;
12463 address
= offset_addr
;
12466 address
= u_regval
[0];
12472 /* Store byte instructions. */
12475 record_buf_mem
[0] = 1;
12477 /* Store half word instructions. */
12480 record_buf_mem
[0] = 2;
12482 /* Store word instructions. */
12485 record_buf_mem
[0] = 4;
12489 gdb_assert_not_reached ("no decoding pattern found");
12493 record_buf_mem
[1] = address
;
12494 thumb2_insn_r
->mem_rec_count
= 1;
12495 record_buf
[0] = reg_rn
;
12496 thumb2_insn_r
->reg_rec_count
= 1;
12498 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12500 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12502 return ARM_RECORD_SUCCESS
;
12505 /* Handler for thumb2 load memory hints instructions. */
12508 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12510 uint32_t record_buf
[8];
12511 uint32_t reg_rt
, reg_rn
;
12513 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12514 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12516 if (ARM_PC_REGNUM
!= reg_rt
)
12518 record_buf
[0] = reg_rt
;
12519 record_buf
[1] = reg_rn
;
12520 record_buf
[2] = ARM_PS_REGNUM
;
12521 thumb2_insn_r
->reg_rec_count
= 3;
12523 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12525 return ARM_RECORD_SUCCESS
;
12528 return ARM_RECORD_FAILURE
;
12531 /* Handler for thumb2 load word instructions. */
12534 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12536 uint32_t record_buf
[8];
12538 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12539 record_buf
[1] = ARM_PS_REGNUM
;
12540 thumb2_insn_r
->reg_rec_count
= 2;
12542 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12544 return ARM_RECORD_SUCCESS
;
12547 /* Handler for thumb2 long multiply, long multiply accumulate, and
12548 divide instructions. */
12551 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12553 uint32_t opcode1
= 0, opcode2
= 0;
12554 uint32_t record_buf
[8];
12556 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12557 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12559 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12561 /* Handle SMULL, UMULL, SMULAL. */
12562 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12563 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12564 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12565 record_buf
[2] = ARM_PS_REGNUM
;
12566 thumb2_insn_r
->reg_rec_count
= 3;
12568 else if (1 == opcode1
|| 3 == opcode2
)
12570 /* Handle SDIV and UDIV. */
12571 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12572 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12573 record_buf
[2] = ARM_PS_REGNUM
;
12574 thumb2_insn_r
->reg_rec_count
= 3;
12577 return ARM_RECORD_FAILURE
;
12579 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12581 return ARM_RECORD_SUCCESS
;
12584 /* Record handler for thumb32 coprocessor instructions. */
12587 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12589 if (bit (thumb2_insn_r
->arm_insn
, 25))
12590 return arm_record_coproc_data_proc (thumb2_insn_r
);
12592 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12595 /* Record handler for advance SIMD structure load/store instructions. */
12598 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12600 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12601 uint32_t l_bit
, a_bit
, b_bits
;
12602 uint32_t record_buf
[128], record_buf_mem
[128];
12603 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12604 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12607 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12608 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12609 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12610 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12611 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12612 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12613 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12614 f_elem
= 8 / f_ebytes
;
12618 ULONGEST u_regval
= 0;
12619 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12620 address
= u_regval
;
12625 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12627 if (b_bits
== 0x07)
12629 else if (b_bits
== 0x0a)
12631 else if (b_bits
== 0x06)
12633 else if (b_bits
== 0x02)
12638 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12640 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12642 record_buf_mem
[index_m
++] = f_ebytes
;
12643 record_buf_mem
[index_m
++] = address
;
12644 address
= address
+ f_ebytes
;
12645 thumb2_insn_r
->mem_rec_count
+= 1;
12650 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12652 if (b_bits
== 0x09 || b_bits
== 0x08)
12654 else if (b_bits
== 0x03)
12659 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12660 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12662 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12664 record_buf_mem
[index_m
++] = f_ebytes
;
12665 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12666 thumb2_insn_r
->mem_rec_count
+= 1;
12668 address
= address
+ (2 * f_ebytes
);
12672 else if ((b_bits
& 0x0e) == 0x04)
12674 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12676 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12678 record_buf_mem
[index_m
++] = f_ebytes
;
12679 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12680 thumb2_insn_r
->mem_rec_count
+= 1;
12682 address
= address
+ (3 * f_ebytes
);
12686 else if (!(b_bits
& 0x0e))
12688 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12690 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12692 record_buf_mem
[index_m
++] = f_ebytes
;
12693 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12694 thumb2_insn_r
->mem_rec_count
+= 1;
12696 address
= address
+ (4 * f_ebytes
);
12702 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12704 if (bft_size
== 0x00)
12706 else if (bft_size
== 0x01)
12708 else if (bft_size
== 0x02)
12714 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12715 thumb2_insn_r
->mem_rec_count
= 1;
12717 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12718 thumb2_insn_r
->mem_rec_count
= 2;
12720 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12721 thumb2_insn_r
->mem_rec_count
= 3;
12723 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12724 thumb2_insn_r
->mem_rec_count
= 4;
12726 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12728 record_buf_mem
[index_m
] = f_ebytes
;
12729 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12738 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12739 thumb2_insn_r
->reg_rec_count
= 1;
12741 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12742 thumb2_insn_r
->reg_rec_count
= 2;
12744 else if ((b_bits
& 0x0e) == 0x04)
12745 thumb2_insn_r
->reg_rec_count
= 3;
12747 else if (!(b_bits
& 0x0e))
12748 thumb2_insn_r
->reg_rec_count
= 4;
12753 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12754 thumb2_insn_r
->reg_rec_count
= 1;
12756 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12757 thumb2_insn_r
->reg_rec_count
= 2;
12759 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12760 thumb2_insn_r
->reg_rec_count
= 3;
12762 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12763 thumb2_insn_r
->reg_rec_count
= 4;
12765 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12766 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12770 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12772 record_buf
[index_r
] = reg_rn
;
12773 thumb2_insn_r
->reg_rec_count
+= 1;
12776 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12778 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12783 /* Decodes thumb2 instruction type and invokes its record handler. */
12785 static unsigned int
12786 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12788 uint32_t op
, op1
, op2
;
12790 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12791 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12792 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12796 if (!(op2
& 0x64 ))
12798 /* Load/store multiple instruction. */
12799 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12801 else if (!((op2
& 0x64) ^ 0x04))
12803 /* Load/store (dual/exclusive) and table branch instruction. */
12804 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12806 else if (!((op2
& 0x20) ^ 0x20))
12808 /* Data-processing (shifted register). */
12809 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12811 else if (op2
& 0x40)
12813 /* Co-processor instructions. */
12814 return thumb2_record_coproc_insn (thumb2_insn_r
);
12817 else if (op1
== 0x02)
12821 /* Branches and miscellaneous control instructions. */
12822 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12824 else if (op2
& 0x20)
12826 /* Data-processing (plain binary immediate) instruction. */
12827 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12831 /* Data-processing (modified immediate). */
12832 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12835 else if (op1
== 0x03)
12837 if (!(op2
& 0x71 ))
12839 /* Store single data item. */
12840 return thumb2_record_str_single_data (thumb2_insn_r
);
12842 else if (!((op2
& 0x71) ^ 0x10))
12844 /* Advanced SIMD or structure load/store instructions. */
12845 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12847 else if (!((op2
& 0x67) ^ 0x01))
12849 /* Load byte, memory hints instruction. */
12850 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12852 else if (!((op2
& 0x67) ^ 0x03))
12854 /* Load halfword, memory hints instruction. */
12855 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12857 else if (!((op2
& 0x67) ^ 0x05))
12859 /* Load word instruction. */
12860 return thumb2_record_ld_word (thumb2_insn_r
);
12862 else if (!((op2
& 0x70) ^ 0x20))
12864 /* Data-processing (register) instruction. */
12865 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12867 else if (!((op2
& 0x78) ^ 0x30))
12869 /* Multiply, multiply accumulate, abs diff instruction. */
12870 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12872 else if (!((op2
& 0x78) ^ 0x38))
12874 /* Long multiply, long multiply accumulate, and divide. */
12875 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12877 else if (op2
& 0x40)
12879 /* Co-processor instructions. */
12880 return thumb2_record_coproc_insn (thumb2_insn_r
);
12887 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12888 and positive val on fauilure. */
12891 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12893 gdb_byte buf
[insn_size
];
12895 memset (&buf
[0], 0, insn_size
);
12897 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12899 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12901 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12905 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12907 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12911 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12912 uint32_t insn_size
)
12915 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12917 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12919 arm_record_data_proc_misc_ld_str
, /* 000. */
12920 arm_record_data_proc_imm
, /* 001. */
12921 arm_record_ld_st_imm_offset
, /* 010. */
12922 arm_record_ld_st_reg_offset
, /* 011. */
12923 arm_record_ld_st_multiple
, /* 100. */
12924 arm_record_b_bl
, /* 101. */
12925 arm_record_asimd_vfp_coproc
, /* 110. */
12926 arm_record_coproc_data_proc
/* 111. */
12929 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12931 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12933 thumb_record_shift_add_sub
, /* 000. */
12934 thumb_record_add_sub_cmp_mov
, /* 001. */
12935 thumb_record_ld_st_reg_offset
, /* 010. */
12936 thumb_record_ld_st_imm_offset
, /* 011. */
12937 thumb_record_ld_st_stack
, /* 100. */
12938 thumb_record_misc
, /* 101. */
12939 thumb_record_ldm_stm_swi
, /* 110. */
12940 thumb_record_branch
/* 111. */
12943 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12944 uint32_t insn_id
= 0;
12946 if (extract_arm_insn (arm_record
, insn_size
))
12950 printf_unfiltered (_("Process record: error reading memory at "
12951 "addr %s len = %d.\n"),
12952 paddress (arm_record
->gdbarch
,
12953 arm_record
->this_addr
), insn_size
);
12957 else if (ARM_RECORD
== record_type
)
12959 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12960 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12962 if (arm_record
->cond
== 0xf)
12963 ret
= arm_record_extension_space (arm_record
);
12966 /* If this insn has fallen into extension space
12967 then we need not decode it anymore. */
12968 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12970 if (ret
!= ARM_RECORD_SUCCESS
)
12972 arm_record_unsupported_insn (arm_record
);
12976 else if (THUMB_RECORD
== record_type
)
12978 /* As thumb does not have condition codes, we set negative. */
12979 arm_record
->cond
= -1;
12980 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12981 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12982 if (ret
!= ARM_RECORD_SUCCESS
)
12984 arm_record_unsupported_insn (arm_record
);
12988 else if (THUMB2_RECORD
== record_type
)
12990 /* As thumb does not have condition codes, we set negative. */
12991 arm_record
->cond
= -1;
12993 /* Swap first half of 32bit thumb instruction with second half. */
12994 arm_record
->arm_insn
12995 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
12997 ret
= thumb2_record_decode_insn_handler (arm_record
);
12999 if (ret
!= ARM_RECORD_SUCCESS
)
13001 arm_record_unsupported_insn (arm_record
);
13007 /* Throw assertion. */
13008 gdb_assert_not_reached ("not a valid instruction, could not decode");
13015 /* Cleans up local record registers and memory allocations. */
13018 deallocate_reg_mem (insn_decode_record
*record
)
13020 xfree (record
->arm_regs
);
13021 xfree (record
->arm_mems
);
13025 /* Parse the current instruction and record the values of the registers and
13026 memory that will be changed in current instruction to record_arch_list".
13027 Return -1 if something is wrong. */
13030 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13031 CORE_ADDR insn_addr
)
13034 uint32_t no_of_rec
= 0;
13035 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13036 ULONGEST t_bit
= 0, insn_id
= 0;
13038 ULONGEST u_regval
= 0;
13040 insn_decode_record arm_record
;
13042 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13043 arm_record
.regcache
= regcache
;
13044 arm_record
.this_addr
= insn_addr
;
13045 arm_record
.gdbarch
= gdbarch
;
13048 if (record_debug
> 1)
13050 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13052 paddress (gdbarch
, arm_record
.this_addr
));
13055 if (extract_arm_insn (&arm_record
, 2))
13059 printf_unfiltered (_("Process record: error reading memory at "
13060 "addr %s len = %d.\n"),
13061 paddress (arm_record
.gdbarch
,
13062 arm_record
.this_addr
), 2);
13067 /* Check the insn, whether it is thumb or arm one. */
13069 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13070 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13073 if (!(u_regval
& t_bit
))
13075 /* We are decoding arm insn. */
13076 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13080 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13081 /* is it thumb2 insn? */
13082 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13084 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13085 THUMB2_INSN_SIZE_BYTES
);
13089 /* We are decoding thumb insn. */
13090 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13096 /* Record registers. */
13097 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13098 if (arm_record
.arm_regs
)
13100 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13102 if (record_full_arch_list_add_reg
13103 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13107 /* Record memories. */
13108 if (arm_record
.arm_mems
)
13110 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13112 if (record_full_arch_list_add_mem
13113 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13114 arm_record
.arm_mems
[no_of_rec
].len
))
13119 if (record_full_arch_list_add_end ())
13124 deallocate_reg_mem (&arm_record
);