gdb/arm-tdep.h

   1 /* Common target dependent code for GDB on ARM systems.
   2    Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef ARM_TDEP_H
  21 #define ARM_TDEP_H
  22
  23 /* Forward declarations.  */
  24 struct gdbarch;
  25 struct regset;
  26
  27 /* Register numbers of various important registers.  */
  28
  29 enum gdb_regnum {
  30   ARM_A1_REGNUM = 0,            /* first integer-like argument */
  31   ARM_A4_REGNUM = 3,            /* last integer-like argument */
  32   ARM_AP_REGNUM = 11,
  33   ARM_IP_REGNUM = 12,
  34   ARM_SP_REGNUM = 13,           /* Contains address of top of stack */
  35   ARM_LR_REGNUM = 14,           /* address to return to from a function call */
  36   ARM_PC_REGNUM = 15,           /* Contains program counter */
  37   ARM_F0_REGNUM = 16,           /* first floating point register */
  38   ARM_F3_REGNUM = 19,           /* last floating point argument register */
  39   ARM_F7_REGNUM = 23,           /* last floating point register */
  40   ARM_FPS_REGNUM = 24,          /* floating point status register */
  41   ARM_PS_REGNUM = 25,           /* Contains processor status */
  42   ARM_WR0_REGNUM,               /* WMMX data registers.  */
  43   ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
  44   ARM_WC0_REGNUM,               /* WMMX control registers.  */
  45   ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
  46   ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
  47   ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
  48   ARM_WCGR0_REGNUM,             /* WMMX general purpose registers.  */
  49   ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
  50   ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
  51   ARM_D0_REGNUM,                /* VFP double-precision registers.  */
  52   ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
  53
  54   ARM_NUM_REGS,
  55
  56   /* Other useful registers.  */
  57   ARM_FP_REGNUM = 11,           /* Frame register in ARM code, if used.  */
  58   THUMB_FP_REGNUM = 7,          /* Frame register in Thumb code, if used.  */
  59   ARM_NUM_ARG_REGS = 4,
  60   ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
  61   ARM_NUM_FP_ARG_REGS = 4,
  62   ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
  63 };
  64
  65 /* Size of integer registers.  */
  66 #define INT_REGISTER_SIZE               4
  67
  68 /* Say how long FP registers are.  Used for documentation purposes and
  69    code readability in this header.  IEEE extended doubles are 80
  70    bits.  DWORD aligned they use 96 bits.  */
  71 #define FP_REGISTER_SIZE        12
  72
  73 /* Number of machine registers.  The only define actually required
  74    is gdbarch_num_regs.  The other definitions are used for documentation
  75    purposes and code readability.  */
  76 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
  77    (and called PS for processor status) so the status bits can be cleared
  78    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
  79    in PS.  */
  80 #define NUM_FREGS       8       /* Number of floating point registers.  */
  81 #define NUM_SREGS       2       /* Number of status registers.  */
  82 #define NUM_GREGS       16      /* Number of general purpose registers.  */
  83
  84
  85 /* Instruction condition field values.  */
  86 #define INST_EQ         0x0
  87 #define INST_NE         0x1
  88 #define INST_CS         0x2
  89 #define INST_CC         0x3
  90 #define INST_MI         0x4
  91 #define INST_PL         0x5
  92 #define INST_VS         0x6
  93 #define INST_VC         0x7
  94 #define INST_HI         0x8
  95 #define INST_LS         0x9
  96 #define INST_GE         0xa
  97 #define INST_LT         0xb
  98 #define INST_GT         0xc
  99 #define INST_LE         0xd
 100 #define INST_AL         0xe
 101 #define INST_NV         0xf
 102
 103 #define FLAG_N          0x80000000
 104 #define FLAG_Z          0x40000000
 105 #define FLAG_C          0x20000000
 106 #define FLAG_V          0x10000000
 107
 108 #define CPSR_T          0x20
 109
 110 /* Type of floating-point code in use by inferior.  There are really 3 models
 111    that are traditionally supported (plus the endianness issue), but gcc can
 112    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 113    functions are passed in floating-point registers.
 114
 115    In addition to the traditional models, VFP adds two more.
 116
 117    If you update this enum, don't forget to update fp_model_strings in
 118    arm-tdep.c.  */
 119
 120 enum arm_float_model
 121 {
 122   ARM_FLOAT_AUTO,       /* Automatic detection.  Do not set in tdep.  */
 123   ARM_FLOAT_SOFT_FPA,   /* Traditional soft-float (mixed-endian on LE ARM).  */
 124   ARM_FLOAT_FPA,        /* FPA co-processor.  GCC calling convention.  */
 125   ARM_FLOAT_SOFT_VFP,   /* Soft-float with pure-endian doubles.  */
 126   ARM_FLOAT_VFP,        /* Full VFP calling convention.  */
 127   ARM_FLOAT_LAST        /* Keep at end.  */
 128 };
 129
 130 /* ABI used by the inferior.  */
 131 enum arm_abi_kind
 132 {
 133   ARM_ABI_AUTO,
 134   ARM_ABI_APCS,
 135   ARM_ABI_AAPCS,
 136   ARM_ABI_LAST
 137 };
 138
 139 /* Convention for returning structures.  */
 140
 141 enum struct_return
 142 {
 143   pcc_struct_return,            /* Return "short" structures in memory.  */
 144   reg_struct_return             /* Return "short" structures in registers.  */
 145 };
 146
 147 /* Target-dependent structure in gdbarch.  */
 148 struct gdbarch_tdep
 149 {
 150   /* The ABI for this architecture.  It should never be set to
 151      ARM_ABI_AUTO.  */
 152   enum arm_abi_kind arm_abi;
 153
 154   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 155
 156   int have_fpa_registers;       /* Does the target report the FPA registers?  */
 157   int have_vfp_registers;       /* Does the target report the VFP registers?  */
 158   int have_vfp_pseudos;         /* Are we synthesizing the single precision
 159                                    VFP registers?  */
 160   int have_neon_pseudos;        /* Are we synthesizing the quad precision
 161                                    NEON registers?  Requires
 162                                    have_vfp_pseudos.  */
 163   int have_neon;                /* Do we have a NEON unit?  */
 164
 165   CORE_ADDR lowest_pc;          /* Lowest address at which instructions
 166                                    will appear.  */
 167
 168   const char *arm_breakpoint;   /* Breakpoint pattern for an ARM insn.  */
 169   int arm_breakpoint_size;      /* And its size.  */
 170   const char *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn.  */
 171   int thumb_breakpoint_size;    /* And its size.  */
 172
 173   /* If the Thumb breakpoint is an undefined instruction (which is
 174      affected by IT blocks) rather than a BKPT instruction (which is
 175      not), then we need a 32-bit Thumb breakpoint to preserve the
 176      instruction count in IT blocks.  */
 177   const char *thumb2_breakpoint;
 178   int thumb2_breakpoint_size;
 179
 180   int jb_pc;                    /* Offset to PC value in jump buffer.
 181                                    If this is negative, longjmp support
 182                                    will be disabled.  */
 183   size_t jb_elt_size;           /* And the size of each entry in the buf.  */
 184
 185   /* Convention for returning structures.  */
 186   enum struct_return struct_return;
 187
 188   /* Cached core file helpers.  */
 189   struct regset *gregset, *fpregset;
 190
 191   /* ISA-specific data types.  */
 192   struct type *arm_ext_type;
 193   struct type *neon_double_type;
 194   struct type *neon_quad_type;
 195 };
 196
 197 /* Structures used for displaced stepping.  */
 198
 199 /* The maximum number of temporaries available for displaced instructions.  */
 200 #define DISPLACED_TEMPS                 16
 201 /* The maximum number of modified instructions generated for one single-stepped
 202    instruction, including the breakpoint (usually at the end of the instruction
 203    sequence) and any scratch words, etc.  */
 204 #define DISPLACED_MODIFIED_INSNS        8
 205
 206 struct displaced_step_closure
 207 {
 208   ULONGEST tmp[DISPLACED_TEMPS];
 209   int rd;
 210   int wrote_to_pc;
 211   union
 212   {
 213     struct
 214     {
 215       int xfersize;
 216       int rn;                      /* Writeback register.  */
 217       unsigned int immed : 1;      /* Offset is immediate.  */
 218       unsigned int writeback : 1;  /* Perform base-register writeback.  */
 219       unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
 220     } ldst;
 221
 222     struct
 223     {
 224       unsigned long dest;
 225       unsigned int link : 1;
 226       unsigned int exchange : 1;
 227       unsigned int cond : 4;
 228     } branch;
 229
 230     struct
 231     {
 232       unsigned int regmask;
 233       int rn;
 234       CORE_ADDR xfer_addr;
 235       unsigned int load : 1;
 236       unsigned int user : 1;
 237       unsigned int increment : 1;
 238       unsigned int before : 1;
 239       unsigned int writeback : 1;
 240       unsigned int cond : 4;
 241     } block;
 242
 243     struct
 244     {
 245       unsigned int immed : 1;
 246     } preload;
 247
 248     struct
 249     {
 250       /* If non-NULL, override generic SVC handling (e.g. for a particular
 251          OS).  */
 252       int (*copy_svc_os) (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
 253                           struct regcache *regs,
 254                           struct displaced_step_closure *dsc);
 255     } svc;
 256   } u;
 257   unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
 258   int numinsns;
 259   CORE_ADDR insn_addr;
 260   CORE_ADDR scratch_base;
 261   void (*cleanup) (struct gdbarch *, struct regcache *,
 262                    struct displaced_step_closure *);
 263 };
 264
 265 /* Values for the WRITE_PC argument to displaced_write_reg.  If the register
 266    write may write to the PC, specifies the way the CPSR T bit, etc. is
 267    modified by the instruction.  */
 268
 269 enum pc_write_style
 270 {
 271   BRANCH_WRITE_PC,
 272   BX_WRITE_PC,
 273   LOAD_WRITE_PC,
 274   ALU_WRITE_PC,
 275   CANNOT_WRITE_PC
 276 };
 277
 278 extern void
 279   arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn,
 280                               CORE_ADDR from, CORE_ADDR to,
 281                               struct regcache *regs,
 282                               struct displaced_step_closure *dsc);
 283 extern void
 284   arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
 285                               CORE_ADDR to, struct displaced_step_closure *dsc);
 286 extern ULONGEST
 287   displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno);
 288 extern void
 289   displaced_write_reg (struct regcache *regs,
 290                        struct displaced_step_closure *dsc, int regno,
 291                        ULONGEST val, enum pc_write_style write_pc);
 292
 293 CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
 294 CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
 295 int arm_software_single_step (struct frame_info *);
 296
 297 extern struct displaced_step_closure *
 298   arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
 299                                 struct regcache *);
 300 extern void arm_displaced_step_fixup (struct gdbarch *,
 301                                       struct displaced_step_closure *,
 302                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 303
 304 /* Functions exported from armbsd-tdep.h.  */
 305
 306 /* Return the appropriate register set for the core section identified
 307    by SECT_NAME and SECT_SIZE.  */
 308
 309 extern const struct regset *
 310   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
 311                                    const char *sect_name, size_t sect_size);
 312
 313 #endif /* arm-tdep.h */