1 /* Target-dependent code for Analog Devices Blackfin processor, for GDB.
3 Copyright (C) 2005-2023 Free Software Foundation, Inc.
5 Contributed by Analog Devices, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "arch-utils.h"
28 #include "frame-unwind.h"
29 #include "frame-base.h"
30 #include "trad-frame.h"
32 #include "sim-regno.h"
33 #include "sim/sim-bfin.h"
34 #include "dwarf2/frame.h"
40 #include "xml-syscall.h"
41 #include "bfin-tdep.h"
43 /* Macros used by prologue functions. */
44 #define P_LINKAGE 0xE800
45 #define P_MINUS_SP1 0x0140
46 #define P_MINUS_SP2 0x05C0
47 #define P_MINUS_SP3 0x0540
48 #define P_MINUS_SP4 0x04C0
49 #define P_SP_PLUS 0x6C06
50 #define P_P2_LOW 0xE10A
51 #define P_P2_HIGH 0XE14A
52 #define P_SP_EQ_SP_PLUS_P2 0X5BB2
53 #define P_SP_EQ_P2_PLUS_SP 0x5B96
54 #define P_MINUS_MINUS_SP_EQ_RETS 0x0167
56 /* Macros used for program flow control. */
57 /* 16 bit instruction, max */
58 #define P_16_BIT_INSR_MAX 0xBFFF
59 /* 32 bit instruction, min */
60 #define P_32_BIT_INSR_MIN 0xC000
61 /* 32 bit instruction, max */
62 #define P_32_BIT_INSR_MAX 0xE801
63 /* jump (preg), 16-bit, min */
64 #define P_JUMP_PREG_MIN 0x0050
65 /* jump (preg), 16-bit, max */
66 #define P_JUMP_PREG_MAX 0x0057
67 /* jump (pc+preg), 16-bit, min */
68 #define P_JUMP_PC_PLUS_PREG_MIN 0x0080
69 /* jump (pc+preg), 16-bit, max */
70 #define P_JUMP_PC_PLUS_PREG_MAX 0x0087
71 /* jump.s pcrel13m2, 16-bit, min */
72 #define P_JUMP_S_MIN 0x2000
73 /* jump.s pcrel13m2, 16-bit, max */
74 #define P_JUMP_S_MAX 0x2FFF
75 /* jump.l pcrel25m2, 32-bit, min */
76 #define P_JUMP_L_MIN 0xE200
77 /* jump.l pcrel25m2, 32-bit, max */
78 #define P_JUMP_L_MAX 0xE2FF
79 /* conditional jump pcrel11m2, 16-bit, min */
80 #define P_IF_CC_JUMP_MIN 0x1800
81 /* conditional jump pcrel11m2, 16-bit, max */
82 #define P_IF_CC_JUMP_MAX 0x1BFF
83 /* conditional jump(bp) pcrel11m2, 16-bit, min */
84 #define P_IF_CC_JUMP_BP_MIN 0x1C00
85 /* conditional jump(bp) pcrel11m2, 16-bit, max */
86 #define P_IF_CC_JUMP_BP_MAX 0x1FFF
87 /* conditional !jump pcrel11m2, 16-bit, min */
88 #define P_IF_NOT_CC_JUMP_MIN 0x1000
89 /* conditional !jump pcrel11m2, 16-bit, max */
90 #define P_IF_NOT_CC_JUMP_MAX 0x13FF
91 /* conditional jump(bp) pcrel11m2, 16-bit, min */
92 #define P_IF_NOT_CC_JUMP_BP_MIN 0x1400
93 /* conditional jump(bp) pcrel11m2, 16-bit, max */
94 #define P_IF_NOT_CC_JUMP_BP_MAX 0x17FF
95 /* call (preg), 16-bit, min */
96 #define P_CALL_PREG_MIN 0x0060
97 /* call (preg), 16-bit, max */
98 #define P_CALL_PREG_MAX 0x0067
99 /* call (pc+preg), 16-bit, min */
100 #define P_CALL_PC_PLUS_PREG_MIN 0x0070
101 /* call (pc+preg), 16-bit, max */
102 #define P_CALL_PC_PLUS_PREG_MAX 0x0077
103 /* call pcrel25m2, 32-bit, min */
104 #define P_CALL_MIN 0xE300
105 /* call pcrel25m2, 32-bit, max */
106 #define P_CALL_MAX 0xE3FF
110 #define P_MNOP 0xC803
111 /* EXCPT, 16-bit, min */
112 #define P_EXCPT_MIN 0x00A0
113 /* EXCPT, 16-bit, max */
114 #define P_EXCPT_MAX 0x00AF
115 /* multi instruction mask 1, 16-bit */
116 #define P_BIT_MULTI_INS_1 0xC000
117 /* multi instruction mask 2, 16-bit */
118 #define P_BIT_MULTI_INS_2 0x0800
120 /* The maximum bytes we search to skip the prologue. */
121 #define UPPER_LIMIT 40
124 #define ASTAT_CC_POS 5
125 #define ASTAT_CC (1 << ASTAT_CC_POS)
127 /* Initial value: Register names used in BFIN's ISA documentation. */
129 static const char * const bfin_register_name_strings
[] =
131 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
132 "p0", "p1", "p2", "p3", "p4", "p5", "sp", "fp",
133 "i0", "i1", "i2", "i3", "m0", "m1", "m2", "m3",
134 "b0", "b1", "b2", "b3", "l0", "l1", "l2", "l3",
135 "a0x", "a0w", "a1x", "a1w", "astat", "rets",
136 "lc0", "lt0", "lb0", "lc1", "lt1", "lb1", "cycles", "cycles2",
137 "usp", "seqstat", "syscfg", "reti", "retx", "retn", "rete",
141 #define NUM_BFIN_REGNAMES ARRAY_SIZE (bfin_register_name_strings)
144 /* In this diagram successive memory locations increase downwards or the
145 stack grows upwards with negative indices. (PUSH analogy for stack.)
147 The top frame is the "frame" of the current function being executed.
149 +--------------+ SP -
153 +--------------+ FP |
155 +--------------+ | frame
167 +--------------+ | frame
177 +--------------+<- next frame
183 The frame chain is formed as following:
185 FP has the topmost frame.
186 FP + 4 has the previous FP and so on. */
189 /* Map from DWARF2 register number to GDB register number. */
191 static const int map_gcc_gdb
[] =
225 BFIN_A0_DOT_X_REGNUM
,
226 BFIN_A1_DOT_X_REGNUM
,
244 /* Big enough to hold the size of the largest register in bytes. */
245 #define BFIN_MAX_REGISTER_SIZE 4
247 struct bfin_frame_cache
253 int frameless_pc_value
;
255 /* Saved registers. */
256 CORE_ADDR saved_regs
[BFIN_NUM_REGS
];
259 /* Stack space reserved for local variables. */
263 /* Allocate and initialize a frame cache. */
265 static struct bfin_frame_cache
*
266 bfin_alloc_frame_cache (void)
268 struct bfin_frame_cache
*cache
;
271 cache
= FRAME_OBSTACK_ZALLOC (struct bfin_frame_cache
);
275 cache
->sp_offset
= -4;
277 cache
->frameless_pc_value
= 0;
279 /* Saved registers. We initialize these to -1 since zero is a valid
280 offset (that's where fp is supposed to be stored). */
281 for (i
= 0; i
< BFIN_NUM_REGS
; i
++)
282 cache
->saved_regs
[i
] = -1;
284 /* Frameless until proven otherwise. */
290 static struct bfin_frame_cache
*
291 bfin_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
293 struct bfin_frame_cache
*cache
;
297 return (struct bfin_frame_cache
*) *this_cache
;
299 cache
= bfin_alloc_frame_cache ();
302 cache
->base
= get_frame_register_unsigned (this_frame
, BFIN_FP_REGNUM
);
303 if (cache
->base
== 0)
306 /* For normal frames, PC is stored at [FP + 4]. */
307 cache
->saved_regs
[BFIN_PC_REGNUM
] = 4;
308 cache
->saved_regs
[BFIN_FP_REGNUM
] = 0;
310 /* Adjust all the saved registers such that they contain addresses
311 instead of offsets. */
312 for (i
= 0; i
< BFIN_NUM_REGS
; i
++)
313 if (cache
->saved_regs
[i
] != -1)
314 cache
->saved_regs
[i
] += cache
->base
;
316 cache
->pc
= get_frame_func (this_frame
) ;
317 if (cache
->pc
== 0 || cache
->pc
== get_frame_pc (this_frame
))
319 /* Either there is no prologue (frameless function) or we are at
320 the start of a function. In short we do not have a frame.
321 PC is stored in rets register. FP points to previous frame. */
323 cache
->saved_regs
[BFIN_PC_REGNUM
] =
324 get_frame_register_unsigned (this_frame
, BFIN_RETS_REGNUM
);
325 cache
->frameless_pc_value
= 1;
326 cache
->base
= get_frame_register_unsigned (this_frame
, BFIN_FP_REGNUM
);
327 cache
->saved_regs
[BFIN_FP_REGNUM
] = cache
->base
;
328 cache
->saved_sp
= cache
->base
;
332 cache
->frameless_pc_value
= 0;
334 /* Now that we have the base address for the stack frame we can
335 calculate the value of SP in the calling frame. */
336 cache
->saved_sp
= cache
->base
+ 8;
343 bfin_frame_this_id (frame_info_ptr this_frame
,
345 struct frame_id
*this_id
)
347 struct bfin_frame_cache
*cache
= bfin_frame_cache (this_frame
, this_cache
);
349 /* This marks the outermost frame. */
350 if (cache
->base
== 0)
353 /* See the end of bfin_push_dummy_call. */
354 *this_id
= frame_id_build (cache
->base
+ 8, cache
->pc
);
357 static struct value
*
358 bfin_frame_prev_register (frame_info_ptr this_frame
,
362 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
363 struct bfin_frame_cache
*cache
= bfin_frame_cache (this_frame
, this_cache
);
365 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
366 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
368 if (regnum
< BFIN_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
369 return frame_unwind_got_memory (this_frame
, regnum
,
370 cache
->saved_regs
[regnum
]);
372 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
375 static const struct frame_unwind bfin_frame_unwind
=
379 default_frame_unwind_stop_reason
,
381 bfin_frame_prev_register
,
383 default_frame_sniffer
386 /* Check for "[--SP] = <reg>;" insns. These are appear in function
387 prologues to save misc registers onto the stack. */
390 is_minus_minus_sp (int op
)
394 if ((op
== P_MINUS_SP1
) || (op
== P_MINUS_SP2
)
395 || (op
== P_MINUS_SP3
) || (op
== P_MINUS_SP4
))
401 /* Skip all the insns that appear in generated function prologues. */
404 bfin_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
406 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
407 int op
= read_memory_unsigned_integer (pc
, 2, byte_order
);
408 CORE_ADDR orig_pc
= pc
;
411 /* The new gcc prologue generates the register saves BEFORE the link
412 or RETS saving instruction.
413 So, our job is to stop either at those instructions or some upper
414 limit saying there is no frame! */
418 if (is_minus_minus_sp (op
))
420 while (is_minus_minus_sp (op
))
423 op
= read_memory_unsigned_integer (pc
, 2, byte_order
);
431 else if (op
== P_LINKAGE
)
436 else if (op
== P_MINUS_MINUS_SP_EQ_RETS
)
441 else if (op
== P_RTS
)
445 else if ((op
>= P_JUMP_PREG_MIN
&& op
<= P_JUMP_PREG_MAX
)
446 || (op
>= P_JUMP_PC_PLUS_PREG_MIN
447 && op
<= P_JUMP_PC_PLUS_PREG_MAX
)
448 || (op
== P_JUMP_S_MIN
&& op
<= P_JUMP_S_MAX
))
452 else if (pc
- orig_pc
>= UPPER_LIMIT
)
454 warning (_("Function Prologue not recognised; "
455 "pc will point to ENTRY_POINT of the function"));
461 pc
+= 2; /* Not a terminating instruction go on. */
462 op
= read_memory_unsigned_integer (pc
, 2, byte_order
);
467 Dwarf2 uses entry point value AFTER some register initializations.
468 We should perhaps skip such asssignments as well (R6 = R1, ...). */
473 /* Return the GDB type object for the "standard" data type of data in
474 register N. This should be void pointer for P0-P5, SP, FP;
475 void pointer to function for PC; int otherwise. */
478 bfin_register_type (struct gdbarch
*gdbarch
, int regnum
)
480 if ((regnum
>= BFIN_P0_REGNUM
&& regnum
<= BFIN_FP_REGNUM
)
481 || regnum
== BFIN_USP_REGNUM
)
482 return builtin_type (gdbarch
)->builtin_data_ptr
;
484 if (regnum
== BFIN_PC_REGNUM
|| regnum
== BFIN_RETS_REGNUM
485 || regnum
== BFIN_RETI_REGNUM
|| regnum
== BFIN_RETX_REGNUM
486 || regnum
== BFIN_RETN_REGNUM
|| regnum
== BFIN_RETE_REGNUM
487 || regnum
== BFIN_LT0_REGNUM
|| regnum
== BFIN_LB0_REGNUM
488 || regnum
== BFIN_LT1_REGNUM
|| regnum
== BFIN_LB1_REGNUM
)
489 return builtin_type (gdbarch
)->builtin_func_ptr
;
491 return builtin_type (gdbarch
)->builtin_int32
;
495 bfin_push_dummy_call (struct gdbarch
*gdbarch
,
496 struct value
*function
,
497 struct regcache
*regcache
,
502 function_call_return_method return_method
,
503 CORE_ADDR struct_addr
)
505 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
507 long reg_r0
, reg_r1
, reg_r2
;
510 for (i
= nargs
- 1; i
>= 0; i
--)
512 struct type
*value_type
= value_enclosing_type (args
[i
]);
514 total_len
+= align_up (value_type
->length (), 4);
517 /* At least twelve bytes of stack space must be allocated for the function's
518 arguments, even for functions that have less than 12 bytes of argument
522 sp
-= 12 - total_len
;
524 /* Push arguments in reverse order. */
526 for (i
= nargs
- 1; i
>= 0; i
--)
528 struct type
*value_type
= value_enclosing_type (args
[i
]);
529 struct type
*arg_type
= check_typedef (value_type
);
530 int container_len
= align_up (arg_type
->length (), 4);
533 write_memory (sp
, value_contents (args
[i
]).data (), container_len
);
536 /* Initialize R0, R1, and R2 to the first 3 words of parameters. */
538 reg_r0
= read_memory_integer (sp
, 4, byte_order
);
539 regcache_cooked_write_unsigned (regcache
, BFIN_R0_REGNUM
, reg_r0
);
540 reg_r1
= read_memory_integer (sp
+ 4, 4, byte_order
);
541 regcache_cooked_write_unsigned (regcache
, BFIN_R1_REGNUM
, reg_r1
);
542 reg_r2
= read_memory_integer (sp
+ 8, 4, byte_order
);
543 regcache_cooked_write_unsigned (regcache
, BFIN_R2_REGNUM
, reg_r2
);
545 /* Store struct value address. */
547 if (return_method
== return_method_struct
)
548 regcache_cooked_write_unsigned (regcache
, BFIN_P0_REGNUM
, struct_addr
);
550 /* Set the dummy return value to bp_addr.
551 A dummy breakpoint will be setup to execute the call. */
553 regcache_cooked_write_unsigned (regcache
, BFIN_RETS_REGNUM
, bp_addr
);
555 /* Finally, update the stack pointer. */
557 regcache_cooked_write_unsigned (regcache
, BFIN_SP_REGNUM
, sp
);
562 /* Convert DWARF2 register number REG to the appropriate register number
566 bfin_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
568 if (reg
< 0 || reg
>= ARRAY_SIZE (map_gcc_gdb
))
571 return map_gcc_gdb
[reg
];
574 /* Implement the breakpoint_kind_from_pc gdbarch method. */
577 bfin_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
579 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
582 iw
= read_memory_unsigned_integer (*pcptr
, 2, byte_order
);
584 if ((iw
& 0xf000) >= 0xc000)
585 /* 32-bit instruction. */
591 /* Implement the sw_breakpoint_from_kind gdbarch method. */
593 static const gdb_byte
*
594 bfin_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
596 static unsigned char bfin_breakpoint
[] = {0xa1, 0x00, 0x00, 0x00};
597 static unsigned char bfin_sim_breakpoint
[] = {0x25, 0x00, 0x00, 0x00};
601 if (strcmp (target_shortname (), "sim") == 0)
602 return bfin_sim_breakpoint
;
604 return bfin_breakpoint
;
608 bfin_extract_return_value (struct type
*type
,
609 struct regcache
*regs
,
612 struct gdbarch
*gdbarch
= regs
->arch ();
613 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
614 bfd_byte
*valbuf
= dst
;
615 int len
= type
->length ();
617 int regno
= BFIN_R0_REGNUM
;
619 gdb_assert (len
<= 8);
623 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
624 store_unsigned_integer (valbuf
, (len
> 4 ? 4 : len
), byte_order
, tmp
);
630 /* Write into appropriate registers a function return value of type
631 TYPE, given in virtual format. */
634 bfin_store_return_value (struct type
*type
,
635 struct regcache
*regs
,
638 const bfd_byte
*valbuf
= src
;
640 /* Integral values greater than one word are stored in consecutive
641 registers starting with R0. This will always be a multiple of
642 the register size. */
644 int len
= type
->length ();
645 int regno
= BFIN_R0_REGNUM
;
647 gdb_assert (len
<= 8);
651 regs
->cooked_write (regno
++, valbuf
);
657 /* Determine, for architecture GDBARCH, how a return value of TYPE
658 should be returned. If it is supposed to be returned in registers,
659 and READBUF is nonzero, read the appropriate value from REGCACHE,
660 and copy it into READBUF. If WRITEBUF is nonzero, write the value
661 from WRITEBUF into REGCACHE. */
663 static enum return_value_convention
664 bfin_return_value (struct gdbarch
*gdbarch
,
665 struct value
*function
,
667 struct regcache
*regcache
,
669 const gdb_byte
*writebuf
)
671 if (type
->length () > 8)
672 return RETURN_VALUE_STRUCT_CONVENTION
;
675 bfin_extract_return_value (type
, regcache
, readbuf
);
678 bfin_store_return_value (type
, regcache
, writebuf
);
680 return RETURN_VALUE_REGISTER_CONVENTION
;
683 /* Return the BFIN register name corresponding to register I. */
686 bfin_register_name (struct gdbarch
*gdbarch
, int i
)
688 return bfin_register_name_strings
[i
];
691 static enum register_status
692 bfin_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
693 int regnum
, gdb_byte
*buffer
)
695 gdb_byte buf
[BFIN_MAX_REGISTER_SIZE
];
696 enum register_status status
;
698 if (regnum
!= BFIN_CC_REGNUM
)
699 internal_error (_("invalid register number %d"), regnum
);
701 /* Extract the CC bit from the ASTAT register. */
702 status
= regcache
->raw_read (BFIN_ASTAT_REGNUM
, buf
);
703 if (status
== REG_VALID
)
705 buffer
[1] = buffer
[2] = buffer
[3] = 0;
706 buffer
[0] = !!(buf
[0] & ASTAT_CC
);
712 bfin_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
713 int regnum
, const gdb_byte
*buffer
)
715 gdb_byte buf
[BFIN_MAX_REGISTER_SIZE
];
717 if (regnum
!= BFIN_CC_REGNUM
)
718 internal_error (_("invalid register number %d"), regnum
);
720 /* Overlay the CC bit in the ASTAT register. */
721 regcache
->raw_read (BFIN_ASTAT_REGNUM
, buf
);
722 buf
[0] = (buf
[0] & ~ASTAT_CC
) | ((buffer
[0] & 1) << ASTAT_CC_POS
);
723 regcache
->raw_write (BFIN_ASTAT_REGNUM
, buf
);
727 bfin_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
729 struct bfin_frame_cache
*cache
= bfin_frame_cache (this_frame
, this_cache
);
735 bfin_frame_local_address (frame_info_ptr this_frame
, void **this_cache
)
737 struct bfin_frame_cache
*cache
= bfin_frame_cache (this_frame
, this_cache
);
739 return cache
->base
- 4;
743 bfin_frame_args_address (frame_info_ptr this_frame
, void **this_cache
)
745 struct bfin_frame_cache
*cache
= bfin_frame_cache (this_frame
, this_cache
);
747 return cache
->base
+ 8;
750 static const struct frame_base bfin_frame_base
=
753 bfin_frame_base_address
,
754 bfin_frame_local_address
,
755 bfin_frame_args_address
759 bfin_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
761 return align_down (address
, 4);
765 bfin_abi (struct gdbarch
*gdbarch
)
767 bfin_gdbarch_tdep
*tdep
= gdbarch_tdep
<bfin_gdbarch_tdep
> (gdbarch
);
768 return tdep
->bfin_abi
;
771 /* Initialize the current architecture based on INFO. If possible,
772 re-use an architecture from ARCHES, which is a list of
773 architectures already created during this debugging session.
775 Called e.g. at program startup, when reading a core file, and when
776 reading a binary file. */
778 static struct gdbarch
*
779 bfin_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
785 /* If there is already a candidate, use it. */
787 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
789 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
791 bfin_gdbarch_tdep
*tdep
792 = gdbarch_tdep
<bfin_gdbarch_tdep
> (arches
->gdbarch
);
794 if (tdep
->bfin_abi
!= abi
)
797 return arches
->gdbarch
;
801 = gdbarch_alloc (&info
, gdbarch_tdep_up (new bfin_gdbarch_tdep
));
802 bfin_gdbarch_tdep
*tdep
= gdbarch_tdep
<bfin_gdbarch_tdep
> (gdbarch
);
804 tdep
->bfin_abi
= abi
;
806 set_gdbarch_num_regs (gdbarch
, BFIN_NUM_REGS
);
807 set_gdbarch_pseudo_register_read (gdbarch
, bfin_pseudo_register_read
);
808 set_gdbarch_pseudo_register_write (gdbarch
, bfin_pseudo_register_write
);
809 set_gdbarch_num_pseudo_regs (gdbarch
, BFIN_NUM_PSEUDO_REGS
);
810 set_gdbarch_sp_regnum (gdbarch
, BFIN_SP_REGNUM
);
811 set_gdbarch_pc_regnum (gdbarch
, BFIN_PC_REGNUM
);
812 set_gdbarch_ps_regnum (gdbarch
, BFIN_ASTAT_REGNUM
);
813 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, bfin_reg_to_regnum
);
814 set_gdbarch_register_name (gdbarch
, bfin_register_name
);
815 set_gdbarch_register_type (gdbarch
, bfin_register_type
);
816 set_gdbarch_push_dummy_call (gdbarch
, bfin_push_dummy_call
);
817 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
818 set_gdbarch_return_value (gdbarch
, bfin_return_value
);
819 set_gdbarch_skip_prologue (gdbarch
, bfin_skip_prologue
);
820 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
821 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, bfin_breakpoint_kind_from_pc
);
822 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, bfin_sw_breakpoint_from_kind
);
823 set_gdbarch_decr_pc_after_break (gdbarch
, 2);
824 set_gdbarch_frame_args_skip (gdbarch
, 8);
825 set_gdbarch_frame_align (gdbarch
, bfin_frame_align
);
827 /* Hook in ABI-specific overrides, if they have been registered. */
828 gdbarch_init_osabi (info
, gdbarch
);
830 dwarf2_append_unwinders (gdbarch
);
832 frame_base_set_default (gdbarch
, &bfin_frame_base
);
834 frame_unwind_append_unwinder (gdbarch
, &bfin_frame_unwind
);
839 void _initialize_bfin_tdep ();
841 _initialize_bfin_tdep ()
843 gdbarch_register (bfd_arch_bfin
, bfin_gdbarch_init
);