gdb/config/mips/tm-mips.h

   1 /* Definitions to make GDB run on a mips box under 4.3bsd.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
   3    Free Software Foundation, Inc.
   4    Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
   5    and by Alessandro Forin (af@cs.cmu.edu) at CMU..
   6
   7 This file is part of GDB.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, write to the Free Software
  21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef TM_MIPS_H
  24 #define TM_MIPS_H 1
  25
  26 #ifdef __STDC__
  27 struct frame_info;
  28 struct symbol;
  29 struct type;
  30 struct value;
  31 #endif
  32
  33 #include <bfd.h>
  34 #include "coff/sym.h"           /* Needed for PDR below.  */
  35 #include "coff/symconst.h"
  36
  37 #if !defined (TARGET_BYTE_ORDER)
  38 #define TARGET_BYTE_ORDER LITTLE_ENDIAN
  39 #endif
  40
  41 #if !defined (GDB_TARGET_IS_MIPS64)
  42 #define GDB_TARGET_IS_MIPS64 0
  43 #endif
  44
  45 #if !defined (MIPS_EABI)
  46 #define MIPS_EABI 0
  47 #endif
  48
  49 #if !defined (TARGET_MONITOR_PROMPT)
  50 #define TARGET_MONITOR_PROMPT "<IDT>"
  51 #endif
  52
  53 /* Floating point is IEEE compliant */
  54 #define IEEE_FLOAT
  55
  56 /* Some MIPS boards are provided both with and without a floating
  57    point coprocessor.  The MIPS R4650 chip has only single precision
  58    floating point.  We provide a user settable variable to tell gdb
  59    what type of floating point to use.  */
  60
  61 enum mips_fpu_type
  62 {
  63   MIPS_FPU_DOUBLE,      /* Full double precision floating point.  */
  64   MIPS_FPU_SINGLE,      /* Single precision floating point (R4650).  */
  65   MIPS_FPU_NONE         /* No floating point.  */
  66 };
  67
  68 extern enum mips_fpu_type mips_fpu;
  69
  70 /* The name of the usual type of MIPS processor that is in the target
  71    system.  */
  72
  73 #define DEFAULT_MIPS_TYPE "generic"
  74
  75 /* Remove useless bits from an instruction address.  */
  76
  77 #define ADDR_BITS_REMOVE(addr) mips_addr_bits_remove(addr)
  78 CORE_ADDR mips_addr_bits_remove PARAMS ((CORE_ADDR addr));
  79
  80 /* Remove useless bits from the stack pointer.  */
  81
  82 #define TARGET_READ_SP() ADDR_BITS_REMOVE (read_register (SP_REGNUM))
  83
  84 /* Offset from address of function to start of its code.
  85    Zero on most machines.  */
  86
  87 #define FUNCTION_START_OFFSET 0
  88
  89 /* Advance PC across any function entry prologue instructions
  90    to reach some "real" code.  */
  91
  92 #define SKIP_PROLOGUE(pc)       pc = mips_skip_prologue (pc, 0)
  93 extern CORE_ADDR mips_skip_prologue PARAMS ((CORE_ADDR addr, int lenient));
  94
  95 /* Return non-zero if PC points to an instruction which will cause a step
  96    to execute both the instruction at PC and an instruction at PC+4.  */
  97 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
  98 extern int mips_step_skips_delay PARAMS ((CORE_ADDR));
  99
 100 /* Immediately after a function call, return the saved pc.
 101    Can't always go through the frames for this because on some machines
 102    the new frame is not set up until the new function executes
 103    some instructions.  */
 104
 105 #define SAVED_PC_AFTER_CALL(frame)      read_register(RA_REGNUM)
 106
 107 /* Are we currently handling a signal */
 108
 109 extern int in_sigtramp PARAMS ((CORE_ADDR, char *));
 110 #define IN_SIGTRAMP(pc, name)   in_sigtramp(pc, name)
 111
 112 /* Stack grows downward.  */
 113
 114 #define INNER_THAN <
 115
 116 #define BIG_ENDIAN 4321
 117
 118 /* Old-style breakpoint macros.
 119    The IDT board uses an unusual breakpoint value, and sometimes gets
 120    confused when it sees the usual MIPS breakpoint instruction.  */
 121
 122 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
 123 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
 124 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
 125 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
 126 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
 127 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
 128 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
 129 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
 130
 131 /* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
 132    16- or 32-bit breakpoint should be used.  It returns a pointer
 133    to a string of bytes that encode a breakpoint instruction, stores
 134    the length of the string to *lenptr, and adjusts the pc (if necessary) to
 135    point to the actual memory location where the breakpoint should be
 136    inserted.  */
 137
 138 unsigned char *mips_breakpoint_from_pc PARAMS ((CORE_ADDR *pcptr, int *lenptr));
 139 #define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
 140
 141 /* Amount PC must be decremented by after a breakpoint.
 142    This is often the number of bytes in BREAKPOINT
 143    but not always.  */
 144
 145 #define DECR_PC_AFTER_BREAK 0
 146
 147 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
 148
 149 int mips_about_to_return PARAMS ((CORE_ADDR pc));
 150 #define ABOUT_TO_RETURN(pc) mips_about_to_return (pc)
 151
 152 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 153    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 154    real way to know how big a register is.  */
 155
 156 #define REGISTER_SIZE 4
 157
 158 /* The size of a register.  This is predefined in tm-mips64.h.  We
 159    can't use REGISTER_SIZE because that is used for various other
 160    things.  */
 161
 162 #ifndef MIPS_REGSIZE
 163 #define MIPS_REGSIZE 4
 164 #endif
 165
 166 /* Number of machine registers */
 167
 168 #ifndef NUM_REGS
 169 #define NUM_REGS 90
 170 #endif
 171
 172 /* Initializer for an array of names of registers.
 173    There should be NUM_REGS strings in this initializer.  */
 174
 175 #ifndef REGISTER_NAMES
 176 #define REGISTER_NAMES  \
 177     {   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3", \
 178         "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7", \
 179         "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7", \
 180         "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra", \
 181         "sr",   "lo",   "hi",   "bad",  "cause","pc",    \
 182         "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7", \
 183         "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15", \
 184         "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",\
 185         "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",\
 186         "fsr",  "fir",  "fp",   "", \
 187         "",     "",     "",     "",     "",     "",     "",     "", \
 188         "",     "",     "",     "",     "",     "",     "",     "", \
 189     }
 190 #endif
 191
 192 /* Register numbers of various important registers.
 193    Note that some of these values are "real" register numbers,
 194    and correspond to the general registers of the machine,
 195    and some are "phony" register numbers which are too large
 196    to be actual register numbers as far as the user is concerned
 197    but do serve to get the desired values when passed to read_register.  */
 198
 199 #define ZERO_REGNUM 0           /* read-only register, always 0 */
 200 #define V0_REGNUM 2             /* Function integer return value */
 201 #define A0_REGNUM 4             /* Loc of first arg during a subr call */
 202 #if MIPS_EABI
 203 #  define MIPS_LAST_ARG_REGNUM 11 /* EABI uses R4 through R11 for args */
 204 #  define MIPS_NUM_ARG_REGS 8
 205 #else
 206 #  define MIPS_LAST_ARG_REGNUM 7  /* old ABI uses R4 through R7 for args */
 207 #  define MIPS_NUM_ARG_REGS 4
 208 #endif
 209 #define T9_REGNUM 25            /* Contains address of callee in PIC */
 210 #define SP_REGNUM 29            /* Contains address of top of stack */
 211 #define RA_REGNUM 31            /* Contains return address value */
 212 #define PS_REGNUM 32            /* Contains processor status */
 213 #define HI_REGNUM 34            /* Multiple/divide temp */
 214 #define LO_REGNUM 33            /* ... */
 215 #define BADVADDR_REGNUM 35      /* bad vaddr for addressing exception */
 216 #define CAUSE_REGNUM 36         /* describes last exception */
 217 #define PC_REGNUM 37            /* Contains program counter */
 218 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 219 #define FPA0_REGNUM (FP0_REGNUM+12) /* First float argument register */
 220 #if MIPS_EABI                   /* EABI uses F12 through F19 for args */
 221 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+19)
 222 #  define MIPS_NUM_FP_ARG_REGS 8
 223 #else                           /* old ABI uses F12 through F15 for args */
 224 #  define MIPS_LAST_FP_ARG_REGNUM (FP0_REGNUM+15)
 225 #  define MIPS_NUM_FP_ARG_REGS 4
 226 #endif
 227 #define FCRCS_REGNUM 70         /* FP control/status */
 228 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 229 #define FP_REGNUM 72            /* Pseudo register that contains true address of executing stack frame */
 230 #define UNUSED_REGNUM 73        /* Never used, FIXME */
 231 #define FIRST_EMBED_REGNUM 74   /* First CP0 register for embedded use */
 232 #define PRID_REGNUM 89          /* Processor ID */
 233 #define LAST_EMBED_REGNUM 89    /* Last one */
 234
 235 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
 236    of register dumps. */
 237
 238 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
 239 extern void mips_do_registers_info PARAMS ((int, int));
 240
 241 /* Total amount of space needed to store our copies of the machine's
 242    register state, the array `registers'.  */
 243
 244 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
 245
 246 /* Index within `registers' of the first byte of the space for
 247    register N.  */
 248
 249 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
 250
 251 /* Number of bytes of storage in the actual machine representation
 252    for register N.  On mips, all regs are the same size.  */
 253
 254 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
 255
 256 /* Number of bytes of storage in the program's representation
 257    for register N.  On mips, all regs are the same size.  */
 258
 259 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
 260
 261 /* Largest value REGISTER_RAW_SIZE can have.  */
 262
 263 #define MAX_REGISTER_RAW_SIZE 8
 264
 265 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 266
 267 #define MAX_REGISTER_VIRTUAL_SIZE 8
 268
 269 /* Return the GDB type object for the "standard" data type
 270    of data in register N.  */
 271
 272 #ifndef REGISTER_VIRTUAL_TYPE
 273 #define REGISTER_VIRTUAL_TYPE(N) \
 274         (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32)  \
 275          ? builtin_type_float : builtin_type_int)
 276 #endif
 277
 278 /* All mips targets store doubles in a register pair with the least
 279    significant register in the lower numbered register.
 280    If the target is big endian, double register values need conversion
 281    between memory and register formats.  */
 282
 283 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer)                       \
 284   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 285           && REGISTER_RAW_SIZE (n) == 4                                 \
 286           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 287           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 288           && TYPE_LENGTH(type) == 8) {                                  \
 289         char __temp[4];                                                 \
 290         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 291         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 292         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 293
 294 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer)                     \
 295   do {if (TARGET_BYTE_ORDER == BIG_ENDIAN                               \
 296           && REGISTER_RAW_SIZE (n) == 4                                 \
 297           && (n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32                 \
 298           && TYPE_CODE(type) == TYPE_CODE_FLT                           \
 299           && TYPE_LENGTH(type) == 8) {                                  \
 300         char __temp[4];                                                 \
 301         memcpy (__temp, ((char *)(buffer))+4, 4);                       \
 302         memcpy (((char *)(buffer))+4, (buffer), 4);                     \
 303         memcpy (((char *)(buffer)), __temp, 4); }} while (0)
 304
 305 /* Store the address of the place in which to copy the structure the
 306    subroutine will return.  Handled by mips_push_arguments.  */
 307
 308 #define STORE_STRUCT_RETURN(addr, sp)   /**/
 309
 310 /* Extract from an array REGBUF containing the (raw) register state
 311    a function return value of type TYPE, and copy that, in virtual format,
 312    into VALBUF.  XXX floats */
 313
 314 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 315   mips_extract_return_value(TYPE, REGBUF, VALBUF)
 316 extern void
 317 mips_extract_return_value PARAMS ((struct type *, char [], char *));
 318
 319 /* Write into appropriate registers a function return value
 320    of type TYPE, given in virtual format.  */
 321
 322 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 323   mips_store_return_value(TYPE, VALBUF)
 324 extern void mips_store_return_value PARAMS ((struct type *, char *));
 325
 326 /* Extract from an array REGBUF containing the (raw) register state
 327    the address in which a function should return its structure value,
 328    as a CORE_ADDR (or an expression that can be used as one).  */
 329 /* The address is passed in a0 upon entry to the function, but when
 330    the function exits, the compiler has copied the value to v0.  This
 331    convention is specified by the System V ABI, so I think we can rely
 332    on it.  */
 333
 334 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 335   (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
 336                     REGISTER_RAW_SIZE (V0_REGNUM)))
 337
 338 #if MIPS_EABI
 339 #undef  USE_STRUCT_CONVENTION
 340 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 341   (TYPE_LENGTH (type) > 2 * MIPS_REGSIZE)
 342 #else
 343 /* Structures are returned by ref in extra arg0 */
 344 #define USE_STRUCT_CONVENTION(gcc_p, type)      1
 345 #endif
 346 \f
 347 /* Describe the pointer in each stack frame to the previous stack frame
 348    (its caller).  */
 349
 350 /* FRAME_CHAIN takes a frame's nominal address
 351    and produces the frame's chain-pointer. */
 352
 353 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
 354 extern CORE_ADDR mips_frame_chain PARAMS ((struct frame_info *));
 355
 356 /* Define other aspects of the stack frame.  */
 357
 358
 359 /* A macro that tells us whether the function invocation represented
 360    by FI does not have a frame on the stack associated with it.  If it
 361    does not, FRAMELESS is set to 1, else 0.  */
 362 /* We handle this differently for mips, and maybe we should not */
 363
 364 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS)  {(FRAMELESS) = 0;}
 365
 366 /* Saved Pc.  */
 367
 368 #define FRAME_SAVED_PC(FRAME)   (mips_frame_saved_pc(FRAME))
 369 extern CORE_ADDR mips_frame_saved_pc PARAMS ((struct frame_info *));
 370
 371 #define FRAME_ARGS_ADDRESS(fi)  (fi)->frame
 372
 373 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
 374
 375 /* Return number of args passed to a frame.
 376    Can return -1, meaning no way to tell.  */
 377
 378 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
 379 extern int mips_frame_num_args PARAMS ((struct frame_info *));
 380
 381 /* Return number of bytes at start of arglist that are not really args.  */
 382
 383 #define FRAME_ARGS_SKIP 0
 384
 385 /* Put here the code to store, into a struct frame_saved_regs,
 386    the addresses of the saved registers of frame described by FRAME_INFO.
 387    This includes special registers such as pc and fp saved in special
 388    ways in the stack frame.  sp is even more special:
 389    the address we return for it IS the sp for the next frame.  */
 390
 391 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
 392   do { \
 393     if ((frame_info)->saved_regs == NULL) \
 394       mips_find_saved_regs (frame_info); \
 395     (frame_saved_regs) = *(frame_info)->saved_regs; \
 396     (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
 397   } while (0)
 398 extern void mips_find_saved_regs PARAMS ((struct frame_info *));
 399
 400 \f
 401 /* Things needed for making the inferior call functions.  */
 402
 403 /* Stack must be aligned on 32-bit boundaries when synthesizing
 404    function calls.  We don't need STACK_ALIGN, PUSH_ARGUMENTS will
 405    handle it. */
 406
 407 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 408     sp = mips_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))
 409 extern CORE_ADDR
 410 mips_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
 411
 412 /* Push an empty stack frame, to record the current PC, etc.  */
 413
 414 #define PUSH_DUMMY_FRAME        mips_push_dummy_frame()
 415 extern void mips_push_dummy_frame PARAMS ((void));
 416
 417 /* Discard from the stack the innermost frame, restoring all registers.  */
 418
 419 #define POP_FRAME               mips_pop_frame()
 420 extern void mips_pop_frame PARAMS ((void));
 421
 422 #define CALL_DUMMY { 0 }
 423
 424 #define CALL_DUMMY_START_OFFSET (0)
 425
 426 #define CALL_DUMMY_BREAKPOINT_OFFSET (0)
 427
 428 /* On Irix, $t9 ($25) contains the address of the callee (used for PIC).
 429    It doesn't hurt to do this on other systems; $t9 will be ignored.  */
 430 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
 431     write_register(T9_REGNUM, fun)
 432
 433 #define CALL_DUMMY_LOCATION AT_ENTRY_POINT
 434
 435 #define CALL_DUMMY_ADDRESS() (entry_point_address ())
 436
 437 /* There's a mess in stack frame creation.  See comments in blockframe.c
 438    near reference to INIT_FRAME_PC_FIRST.  */
 439
 440 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
 441
 442 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
 443    mips_init_frame_pc_first(fromleaf, prev)
 444 extern void mips_init_frame_pc_first PARAMS ((int, struct frame_info *));
 445
 446 /* Special symbol found in blocks associated with routines.  We can hang
 447    mips_extra_func_info_t's off of this.  */
 448
 449 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
 450 extern void ecoff_relocate_efi PARAMS ((struct symbol *, CORE_ADDR));
 451
 452 /* Specific information about a procedure.
 453    This overlays the MIPS's PDR records,
 454    mipsread.c (ab)uses this to save memory */
 455
 456 typedef struct mips_extra_func_info {
 457         long    numargs;        /* number of args to procedure (was iopt) */
 458         bfd_vma high_addr;      /* upper address bound */
 459         long    frame_adjust;   /* offset of FP from SP (used on MIPS16) */
 460         PDR     pdr;            /* Procedure descriptor record */
 461 } *mips_extra_func_info_t;
 462
 463 #define EXTRA_FRAME_INFO \
 464   mips_extra_func_info_t proc_desc; \
 465   int num_args;\
 466   struct frame_saved_regs *saved_regs;
 467
 468 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
 469 extern void init_extra_frame_info PARAMS ((struct frame_info *));
 470
 471 #define PRINT_EXTRA_FRAME_INFO(fi) \
 472   { \
 473     if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
 474       printf_filtered (" frame pointer is at %s+%d\n", \
 475                        reg_names[fi->proc_desc->pdr.framereg], \
 476                                  fi->proc_desc->pdr.frameoffset); \
 477   }
 478
 479 /* It takes two values to specify a frame on the MIPS.
 480
 481    In fact, the *PC* is the primary value that sets up a frame.  The
 482    PC is looked up to see what function it's in; symbol information
 483    from that function tells us which register is the frame pointer
 484    base, and what offset from there is the "virtual frame pointer".
 485    (This is usually an offset from SP.)  On most non-MIPS machines,
 486    the primary value is the SP, and the PC, if needed, disambiguates
 487    multiple functions with the same SP.  But on the MIPS we can't do
 488    that since the PC is not stored in the same part of the frame every
 489    time.  This does not seem to be a very clever way to set up frames,
 490    but there is nothing we can do about that).  */
 491
 492 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
 493 extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
 494
 495 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
 496
 497 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
 498
 499 /* Convert a ecoff register number to a gdb REGNUM */
 500
 501 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
 502
 503 /* If the current gcc for for this target does not produce correct debugging
 504    information for float parameters, both prototyped and unprototyped, then
 505    define this macro.  This forces gdb to  always assume that floats are
 506    passed as doubles and then converted in the callee.
 507
 508    For the mips chip, it appears that the debug info marks the parameters as
 509    floats regardless of whether the function is prototyped, but the actual
 510    values are passed as doubles for the non-prototyped case and floats for
 511    the prototyped case.  Thus we choose to make the non-prototyped case work
 512    for C and break the prototyped case, since the non-prototyped case is
 513    probably much more common.  (FIXME). */
 514
 515 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
 516
 517 /* These are defined in mdebugread.c and are used in mips-tdep.c  */
 518 extern CORE_ADDR sigtramp_address, sigtramp_end;
 519 extern void fixup_sigtramp PARAMS ((void));
 520
 521 /* Defined in mips-tdep.c and used in remote-mips.c */
 522 extern char *mips_read_processor_type PARAMS ((void));
 523
 524 /* Functions for dealing with MIPS16 call and return stubs.  */
 525 #define IN_SOLIB_CALL_TRAMPOLINE(pc, name)      mips_in_call_stub (pc, name)
 526 #define IN_SOLIB_RETURN_TRAMPOLINE(pc, name)    mips_in_return_stub (pc, name)
 527 #define SKIP_TRAMPOLINE_CODE(pc)                mips_skip_stub (pc)
 528 #define IGNORE_HELPER_CALL(pc)                  mips_ignore_helper (pc)
 529 extern int mips_in_call_stub PARAMS ((CORE_ADDR pc,  char *name));
 530 extern int mips_in_return_stub PARAMS ((CORE_ADDR pc,  char *name));
 531 extern CORE_ADDR mips_skip_stub PARAMS ((CORE_ADDR pc));
 532 extern int mips_ignore_helper PARAMS ((CORE_ADDR pc));
 533
 534 #ifndef TARGET_MIPS
 535 #define TARGET_MIPS
 536 #endif
 537
 538 /* Definitions and declarations used by mips-tdep.c and remote-mips.c  */
 539 #define MIPS_INSTLEN 4          /* Length of an instruction */
 540 #define MIPS16_INSTLEN 2        /* Length of an instruction on MIPS16*/
 541 #define MIPS_NUMREGS 32         /* Number of integer or float registers */
 542 typedef unsigned long t_inst;   /* Integer big enough to hold an instruction */
 543
 544 /* MIPS16 function addresses are odd (bit 0 is set).  Here are some
 545    macros to test, set, or clear bit 0 of addresses.  */
 546 #define IS_MIPS16_ADDR(addr)     ((addr) & 1)
 547 #define MAKE_MIPS16_ADDR(addr)   ((addr) | 1)
 548 #define UNMAKE_MIPS16_ADDR(addr) ((addr) & ~1)
 549
 550 #endif  /* TM_MIPS_H */
 551
 552 /* Macros for setting and testing a bit in a minimal symbol that
 553    marks it as 16-bit function.  The MSB of the minimal symbol's
 554    "info" field is used for this purpose.  This field is already
 555    being used to store the symbol size, so the assumption is
 556    that the symbol size cannot exceed 2^31.
 557
 558    SYMBOL_IS_SPECIAL    tests whether an ELF symbol is "special", i.e. refers
 559                         to a 16-bit function
 560    MAKE_MSYMBOL_SPECIAL sets a "special" bit in a minimal symbol to mark it
 561                         as a 16-bit function
 562    MSYMBOL_IS_SPECIAL   tests the "special" bit in a minimal symbol
 563    MSYMBOL_SIZE         returns the size of the minimal symbol, i.e.
 564                         the "info" field with the "special" bit masked out
 565 */
 566
 567 #define SYMBOL_IS_SPECIAL(sym) \
 568   (((elf_symbol_type *) sym) -> internal_elf_sym.st_other == STO_MIPS16)
 569 #define MAKE_MSYMBOL_SPECIAL(msym) \
 570   MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000)
 571 #define MSYMBOL_IS_SPECIAL(msym) \
 572   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 573 #define MSYMBOL_SIZE(msym) \
 574   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)