gdb/csky-tdep.h

   1 /* Target-dependent code for the CSKY architecture, for GDB.
   2
   3    Copyright (C) 2010-2022 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef CSKY_TDEP_H
  21 #define CSKY_TDEP_H
  22
  23 #include "gdbarch.h"
  24
  25 /* How to interpret the contents of the link register.  */
  26 enum lr_type_t
  27 {
  28   LR_TYPE_R15,
  29   LR_TYPE_EPC,
  30   LR_TYPE_FPC
  31 };
  32
  33 /* Target-dependent structure in gdbarch.  */
  34 struct csky_gdbarch_tdep : gdbarch_tdep
  35 {
  36   /* Save FPU, VDSP ABI.  */
  37   unsigned int fpu_abi;
  38   unsigned int fpu_hardfp;
  39   unsigned int vdsp_version;
  40 };
  41
  42 /* Instruction sizes.  */
  43 enum csky_insn_size_t
  44 {
  45   CSKY_INSN_SIZE16 = 2,
  46   CSKY_INSN_SIZE32 = 4
  47 };
  48
  49 /* CSKY register numbers.  */
  50 enum csky_regnum
  51 {
  52   CSKY_R0_REGNUM = 0, /* General registers.  */
  53   CSKY_R15_REGNUM = 15,
  54   CSKY_PC_REGNUM = 72,
  55   CSKY_HI_REGNUM = 20,
  56   CSKY_LO_REGNUM = 21,
  57   CSKY_CR0_REGNUM = 89,
  58   CSKY_VBR_REGNUM = CSKY_CR0_REGNUM + 1,
  59   CSKY_EPSR_REGNUM = CSKY_CR0_REGNUM + 2,
  60   CSKY_FPSR_REGNUM = CSKY_CR0_REGNUM + 3,
  61   CSKY_EPC_REGNUM = CSKY_CR0_REGNUM + 4,
  62   CSKY_FPC_REGNUM = CSKY_CR0_REGNUM + 5,
  63
  64   /* Float register 0.  */
  65   CSKY_FR0_REGNUM = 40,
  66   CSKY_VCR0_REGNUM = 121,
  67   CSKY_MMU_REGNUM = 128,
  68   CSKY_PROFCR_REGNUM = 140,
  69   CSKY_PROFGR_REGNUM = 144,
  70   CSKY_FP_REGNUM = 8,
  71
  72   /* Vector register 0.  */
  73   CSKY_VR0_REGNUM = 56,
  74
  75   /* m32r calling convention.  */
  76   CSKY_SP_REGNUM = CSKY_R0_REGNUM + 14,
  77   CSKY_RET_REGNUM = CSKY_R0_REGNUM,
  78
  79   /* Argument registers.  */
  80   CSKY_ABI_A0_REGNUM = 0,
  81   CSKY_ABI_LAST_ARG_REGNUM = 3,
  82
  83   /* Link register, r15.  */
  84   CSKY_LR_REGNUM = CSKY_R15_REGNUM,
  85
  86   /* Processor status register, cr0.  */
  87   CSKY_PSR_REGNUM = CSKY_CR0_REGNUM,
  88
  89   CSKY_MAX_REGISTER_SIZE = 16,
  90   CSKY_MAX_REGS = 253
  91 };
  92
  93 /* ICE registers.  */
  94 #define CSKY_CRBANK_NUM_REGS 32
  95
  96 /* Number of processor registers w/o ICE registers.  */
  97 #define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS)
  98
  99 /* size.  */
 100 #define CSKY_16_ST_SIZE(insn) (1 << ((insn & 0x1800) >> 11))
 101 /* rx.  */
 102 #define CSKY_16_ST_ADDR_REGNUM(insn) ((insn & 0x700) >> 8)
 103 /* disp.  */
 104 #define CSKY_16_ST_OFFSET(insn) ((insn & 0x1f) << ((insn & 0x1800) >> 11))
 105 /* ry.  */
 106 #define CSKY_16_ST_VAL_REGNUM(insn) ((insn & 0xe0) >> 5)
 107
 108 /* st16.w rz, (sp, disp).  */
 109 #define CSKY_16_IS_STWx0(insn) ((insn & 0xf800) == 0xb800)
 110 #define CSKY_16_STWx0_VAL_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
 111
 112 /* disp.  */
 113 #define CSKY_16_STWx0_OFFSET(insn) \
 114   ((((insn & 0x700) >> 3) + (insn & 0x1f)) << 2)
 115
 116 /* Check ld16 but not ld16 sp.  */
 117 #define CSKY_16_IS_LD(insn) \
 118   (((insn & 0xe000) == 0x8000) && (insn & 0x1800) != 0x1800)
 119 /* size.  */
 120 #define CSKY_16_LD_SIZE(insn) CSKY_16_ST_SIZE (insn)
 121 /* rx.  */
 122 #define CSKY_16_LD_ADDR_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
 123 /* disp.  */
 124 #define CSKY_16_LD_OFFSET(insn) CSKY_16_ST_OFFSET (insn)
 125
 126 /* ld16.w rz,(sp,disp).  */
 127 #define CSKY_16_IS_LDWx0(insn) ((insn & 0xf800) == 0x9800)
 128 /*disp.  */
 129 #define CSKY_16_LDWx0_OFFSET(insn) CSKY_16_STWx0_OFFSET (insn)
 130
 131 /* st32.b/h/w/d.  */
 132 #define CSKY_32_IS_ST(insn) ((insn & 0xfc00c000) == 0xdc000000)
 133
 134 /* size: b/h/w/d.  */
 135 #define CSKY_32_ST_SIZE(insn) (1 << ((insn & 0x3000) >> 12))
 136 /* rx.  */
 137 #define CSKY_32_ST_ADDR_REGNUM(insn) ((insn & 0x001f0000) >> 16)
 138 /* disp.  */
 139 #define CSKY_32_ST_OFFSET(insn) ((insn & 0xfff) << ((insn & 0x3000) >> 12))
 140 /* ry.  */
 141 #define CSKY_32_ST_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
 142
 143 /* stw ry, (sp, disp).  */
 144 #define CSKY_32_IS_STWx0(insn) ((insn & 0xfc1ff000) == 0xdc0e2000)
 145
 146 /* stm32 ry-rz, (rx).  */
 147 #define CSKY_32_IS_STM(insn) ((insn & 0xfc00ffe0) == 0xd4001c20)
 148 /* rx.  */
 149 #define CSKY_32_STM_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
 150 /* Count of registers.  */
 151 #define CSKY_32_STM_SIZE(insn) (insn & 0x1f)
 152 /* ry.  */
 153 #define CSKY_32_STM_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
 154 /* stm32 ry-rz, (sp).  */
 155 #define CSKY_32_IS_STMx0(insn) ((insn & 0xfc1fffe0) == 0xd40e1c20)
 156
 157 /* str32.b/h/w rz, (rx, ry << offset).  */
 158 #define CSKY_32_IS_STR(insn) \
 159   (((insn & 0xfc000000) == 0xd4000000) && !(CSKY_32_IS_STM (insn)))
 160 /* rx.  */
 161 #define CSKY_32_STR_X_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
 162 /* ry.  */
 163 #define CSKY_32_STR_Y_REGNUM(insn) ((insn >> 21) & 0x1f)
 164 /* size: b/h/w.  */
 165 #define CSKY_32_STR_SIZE(insn) (1 << ((insn & 0x0c00) >> 10))
 166 /* imm (for rx + ry * imm).  */
 167 #define CSKY_32_STR_OFFSET(insn) ((insn & 0x000003e0) >> 5)
 168
 169 /* stex32.w rz, (rx, disp).  */
 170 #define CSKY_32_IS_STEX(insn) ((insn & 0xfc00f000) == 0xdc007000)
 171 /* rx.  */
 172 #define CSKY_32_STEX_ADDR_REGNUM(insn) ((insn & 0x1f0000) >> 16)
 173 /* disp.  */
 174 #define CSKY_32_STEX_OFFSET(insn) ((insn & 0x0fff) << 2)
 175
 176 /* ld.b/h/w.  */
 177 #define CSKY_32_IS_LD(insn) ((insn & 0xfc00c000) == 0xd8000000)
 178 /* size.  */
 179 #define CSKY_32_LD_SIZE(insn) CSKY_32_ST_SIZE (insn)
 180 /* rx.  */
 181 #define CSKY_32_LD_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
 182 /* disp.  */
 183 #define CSKY_32_LD_OFFSET(insn) CSKY_32_ST_OFFSET (insn)
 184 #define CSKY_32_IS_LDM(insn) ((insn & 0xfc00ffe0) == 0xd0001c20)
 185 /* rx.  */
 186 #define CSKY_32_LDM_ADDR_REGNUM(insn) CSKY_32_STM_ADDR_REGNUM (insn)
 187 /* Count of registers.  */
 188 #define CSKY_32_LDM_SIZE(insn) CSKY_32_STM_SIZE (insn)
 189
 190 /* ldr32.b/h/w rz, (rx, ry << offset).  */
 191 #define CSKY_32_IS_LDR(insn) \
 192   (((insn & 0xfc00fe00) == 0xd0000000) && !(CSKY_32_IS_LDM (insn)))
 193 /* rx.  */
 194 #define CSKY_32_LDR_X_REGNUM(insn) CSKY_32_STR_X_REGNUM (insn)
 195 /* ry.  */
 196 #define CSKY_32_LDR_Y_REGNUM(insn) CSKY_32_STR_Y_REGNUM (insn)
 197 /* size: b/h/w.  */
 198 #define CSKY_32_LDR_SIZE(insn) CSKY_32_STR_SIZE (insn)
 199 /* imm (for rx + ry*imm).  */
 200 #define CSKY_32_LDR_OFFSET(insn) CSKY_32_STR_OFFSET (insn)
 201
 202 #define CSKY_32_IS_LDEX(insn) ((insn & 0xfc00f000) == 0xd8007000)
 203 /* rx.  */
 204 #define CSKY_32_LDEX_ADDR_REGNUM(insn) CSKY_32_STEX_ADDR_REGNUM (insn)
 205 /* disp.  */
 206 #define CSKY_32_LDEX_OFFSET(insn) CSKY_32_STEX_OFFSET (insn)
 207
 208 /* subi.sp sp, disp.  */
 209 #define CSKY_16_IS_SUBI0(insn) ((insn & 0xfce0) == 0x1420)
 210 /* disp.  */
 211 #define CSKY_16_SUBI_IMM(insn) ((((insn & 0x300) >> 3) + (insn & 0x1f)) << 2)
 212
 213 /* subi32 sp,sp,oimm12.  */
 214 #define CSKY_32_IS_SUBI0(insn) ((insn & 0xfffff000) == 0xe5ce1000)
 215 /* oimm12.  */
 216 #define CSKY_32_SUBI_IMM(insn) ((insn & 0xfff) + 1)
 217
 218 /* push16.  */
 219 #define CSKY_16_IS_PUSH(insn) ((insn & 0xffe0) == 0x14c0)
 220 #define CSKY_16_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
 221 #define CSKY_16_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11.  */
 222
 223 /* pop16.  */
 224 #define CSKY_16_IS_POP(insn) ((insn & 0xffe0) == 0x1480)
 225 #define CSKY_16_IS_POP_R15(insn) CSKY_16_IS_PUSH_R15 (insn)
 226 #define CSKY_16_POP_LIST1(insn) CSKY_16_PUSH_LIST1 (insn) /* r4 - r11.  */
 227
 228 /* push32.  */
 229 #define CSKY_32_IS_PUSH(insn) ((insn & 0xfffffe00) == 0xebe00000)
 230 #define CSKY_32_IS_PUSH_R29(insn) ((insn & 0x100) == 0x100)
 231 #define CSKY_32_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
 232 #define CSKY_32_PUSH_LIST1(insn) (insn & 0xf)    /* r4 - r11.  */
 233 #define CSKY_32_PUSH_LIST2(insn) ((insn & 0xe0) >> 5) /* r16 - r17.  */
 234
 235 /* pop32.  */
 236 #define CSKY_32_IS_POP(insn) ((insn & 0xfffffe00) == 0xebc00000)
 237 #define CSKY_32_IS_POP_R29(insn) CSKY_32_IS_PUSH_R29 (insn)
 238 #define CSKY_32_IS_POP_R15(insn) CSKY_32_IS_PUSH_R15 (insn)
 239 #define CSKY_32_POP_LIST1(insn) CSKY_32_PUSH_LIST1 (insn) /* r4 - r11.  */
 240 #define CSKY_32_POP_LIST2(insn) CSKY_32_PUSH_LIST2 (insn) /* r16 - r17.  */
 241
 242 /* Adjust sp by r4(l0).  */
 243 /* lrw r4, literal.  */
 244 #define CSKY_16_IS_LRW4(x) (((x) &0xfce0) == 0x1080)
 245 /* movi r4, imm8.  */
 246 #define CSKY_16_IS_MOVI4(x) (((x) &0xff00) == 0x3400)
 247
 248 /* addi r4, oimm8.  */
 249 #define CSKY_16_IS_ADDI4(x) (((x) &0xff00) == 0x2400)
 250 /* subi r4, oimm8.  */
 251 #define CSKY_16_IS_SUBI4(x) (((x) &0xff00) == 0x2c00)
 252
 253 /* nor16 r4, r4.  */
 254 #define CSKY_16_IS_NOR4(x) ((x) == 0x6d12)
 255
 256 /* lsli r4, r4, imm5.  */
 257 #define CSKY_16_IS_LSLI4(x) (((x) &0xffe0) == 0x4480)
 258 /* bseti r4, imm5.  */
 259 #define CSKY_16_IS_BSETI4(x) (((x) &0xffe0) == 0x3ca0)
 260 /* bclri r4, imm5.  */
 261 #define CSKY_16_IS_BCLRI4(x) (((x) &0xffe0) == 0x3c80)
 262
 263 /* subu sp, r4.  */
 264 #define CSKY_16_IS_SUBU4(x) ((x) == 0x6392)
 265
 266 #define CSKY_16_IS_R4_ADJUSTER(x) \
 267   (CSKY_16_IS_ADDI4 (x) || CSKY_16_IS_SUBI4 (x) || CSKY_16_IS_BSETI4 (x) \
 268    || CSKY_16_IS_BCLRI4 (x) || CSKY_16_IS_NOR4 (x) || CSKY_16_IS_LSLI4 (x))
 269
 270 /* lrw r4, literal.  */
 271 #define CSKY_32_IS_LRW4(x) (((x) &0xffff0000) == 0xea840000)
 272 /* movi r4, imm16.  */
 273 #define CSKY_32_IS_MOVI4(x) (((x) &0xffff0000) == 0xea040000)
 274 /* movih r4, imm16.  */
 275 #define CSKY_32_IS_MOVIH4(x) (((x) &0xffff0000) == 0xea240000)
 276 /* bmaski r4, oimm5.  */
 277 #define CSKY_32_IS_BMASKI4(x) (((x) &0xfc1fffff) == 0xc4005024)
 278 /* addi r4, r4, oimm12.  */
 279 #define CSKY_32_IS_ADDI4(x) (((x) &0xfffff000) == 0xe4840000)
 280 /* subi r4, r4, oimm12.  */
 281 #define CSKY_32_IS_SUBI4(x) (((x) &0xfffff000) == 0xe4810000)
 282
 283 /* nor32 r4, r4, r4.  */
 284 #define CSKY_32_IS_NOR4(x) ((x) == 0xc4842484)
 285 /* rotli r4, r4, imm5.  */
 286 #define CSKY_32_IS_ROTLI4(x) (((x) &0xfc1fffff) == 0xc4044904)
 287 /* lsli r4, r4, imm5.  */
 288 #define CSKY_32_IS_LISI4(x) (((x) &0xfc1fffff) == 0xc4044824)
 289 /* bseti32 r4, r4, imm5.  */
 290 #define CSKY_32_IS_BSETI4(x) (((x) &0xfc1fffff) == 0xc4042844)
 291 /* bclri32 r4, r4, imm5.  */
 292 #define CSKY_32_IS_BCLRI4(x) (((x) &0xfc1fffff) == 0xc4042824)
 293 /* ixh r4, r4, r4.  */
 294 #define CSKY_32_IS_IXH4(x) ((x) == 0xc4840824)
 295 /* ixw r4, r4, r4.  */
 296 #define CSKY_32_IS_IXW4(x) ((x) == 0xc4840844)
 297 /* subu32 sp, sp, r4.  */
 298 #define CSKY_32_IS_SUBU4(x) ((x) == 0xc48e008e)
 299
 300 #define CSKY_32_IS_R4_ADJUSTER(x) \
 301   (CSKY_32_IS_ADDI4 (x) || CSKY_32_IS_SUBI4 (x) || CSKY_32_IS_ROTLI4 (x) \
 302    || CSKY_32_IS_IXH4 (x) || CSKY_32_IS_IXW4 (x) || CSKY_32_IS_NOR4 (x) \
 303    || CSKY_32_IS_BSETI4 (x) || CSKY_32_IS_BCLRI4 (x) || CSKY_32_IS_LISI4 (x))
 304
 305 #define CSKY_IS_R4_ADJUSTER(x)                                          \
 306   (CSKY_32_IS_R4_ADJUSTER (x) || CSKY_16_IS_R4_ADJUSTER (x))
 307 #define CSKY_IS_SUBU4(x) (CSKY_32_IS_SUBU4 (x) || CSKY_16_IS_SUBU4 (x))
 308
 309 /* mfcr rz, epsr.  */
 310 #define CSKY_32_IS_MFCR_EPSR(insn) ((insn & 0xffffffe0) == 0xc0026020)
 311 /* mfcr rz, fpsr.  */
 312 #define CSKY_32_IS_MFCR_FPSR(insn) ((insn & 0xffffffe0) == 0xc0036020)
 313 /* mfcr rz, epc.  */
 314 #define CSKY_32_IS_MFCR_EPC(insn) ((insn & 0xffffffe0) == 0xc0046020)
 315 /* mfcr rz, fpc.  */
 316 #define CSKY_32_IS_MFCR_FPC(insn) ((insn & 0xffffffe0) == 0xc0056020)
 317
 318 #define CSKY_32_IS_RTE(insn) (insn == 0xc0004020)
 319 #define CSKY_32_IS_RFI(insn) (insn == 0xc0004420)
 320 #define CSKY_32_IS_JMP(insn) ((insn & 0xffe0ffff) == 0xe8c00000)
 321 #define CSKY_16_IS_JMP(insn) ((insn & 0xffc3) == 0x7800)
 322 #define CSKY_32_IS_JMPI(insn) ((insn & 0xffff0000) == 0xeac00000)
 323 #define CSKY_32_IS_JMPIX(insn) ((insn & 0xffe0fffc) == 0xe9e00000)
 324 #define CSKY_16_IS_JMPIX(insn) ((insn & 0xf8fc) == 0x38e0)
 325
 326 #define CSKY_16_IS_BR(insn) ((insn & 0xfc00) == 0x0400)
 327 #define CSKY_32_IS_BR(insn) ((insn & 0xffff0000) == 0xe8000000)
 328 #define CSKY_16_IS_MOV_FP_SP(insn) (insn == 0x6e3b)     /* mov r8, r14.  */
 329 #define CSKY_32_IS_MOV_FP_SP(insn) (insn == 0xc40e4828) /* mov r8, r14.  */
 330 #define CSKY_16_IS_MOV_SP_FP(insn) (insn == 0x6fa3)     /* mov r14, r8.  */
 331 #define CSKY_32_INSN_MASK 0xc000
 332 #define CSKY_BKPT_INSN 0x0
 333 #define CSKY_NUM_GREGS 32
 334 /* 32 general regs + 4.  */
 335 #define CSKY_NUM_GREGS_SAVED_GREGS (CSKY_NUM_GREGS + 4)
 336
 337 /* CSKY software bkpt write-mode.  */
 338 #define CSKY_WR_BKPT_MODE 4
 339
 340 /* Define insns for parse rt_sigframe.  */
 341 /* There are three words(sig, pinfo, puc) before siginfo.  */
 342 #define CSKY_SIGINFO_OFFSET 0xc
 343
 344 /* Size of struct siginfo.  */
 345 #define CSKY_SIGINFO_SIZE 0x80
 346
 347 /* There are five words(uc_flags, uc_link, and three for uc_stack)
 348    in struct ucontext before sigcontext.  */
 349 #define CSKY_UCONTEXT_SIGCONTEXT 0x14
 350
 351 /* There is a word(sc_mask) before sc_usp.  */
 352 #define CSKY_SIGCONTEXT_SC_USP 0x4
 353
 354 /* There is a word(sc_usp) before sc_a0.  */
 355 #define CSKY_SIGCONTEXT_SC_A0 0x4
 356
 357 #define CSKY_MOVI_R7_173 0x00adea07
 358 #define CSKY_TRAP_0 0x2020c000
 359
 360 #endif