1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
32 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "gdb/sim-d10v.h"
44 #include "sim-regno.h"
46 #include "gdb_assert.h"
48 struct frame_extra_info
59 unsigned long (*dmap_register
) (int nr
);
60 unsigned long (*imap_register
) (int nr
);
63 /* These are the addresses the D10V-EVA board maps data and
64 instruction memory to. */
67 DMEM_START
= 0x2000000,
68 IMEM_START
= 0x1000000,
69 STACK_START
= 0x200bffe
72 /* d10v register names. */
87 /* d10v calling convention. */
88 ARG1_REGNUM
= R0_REGNUM
,
89 ARGN_REGNUM
= R3_REGNUM
,
90 RET1_REGNUM
= R0_REGNUM
,
93 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
94 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
98 extern void _initialize_d10v_tdep (void);
100 static CORE_ADDR
d10v_read_sp (void);
102 static CORE_ADDR
d10v_read_fp (void);
104 static void d10v_eva_prepare_to_trace (void);
106 static void d10v_eva_get_trace_data (void);
109 d10v_stack_align (CORE_ADDR len
)
111 return (len
+ 1) & ~1;
114 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
115 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
116 and TYPE is the type (which is known to be struct, union or array).
118 The d10v returns anything less than 8 bytes in size in
122 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
126 /* The d10v only passes a struct in a register when that structure
127 has an alignment that matches the size of a register. */
128 /* If the structure doesn't fit in 4 registers, put it on the
130 if (TYPE_LENGTH (type
) > 8)
132 /* If the struct contains only one field, don't put it on the stack
133 - gcc can fit it in one or more registers. */
134 if (TYPE_NFIELDS (type
) == 1)
136 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
137 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
139 /* If the alignment changes, just assume it goes on the
141 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
144 /* If the alignment is suitable for the d10v's 16 bit registers,
145 don't put it on the stack. */
146 if (alignment
== 2 || alignment
== 4)
152 static const unsigned char *
153 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
155 static unsigned char breakpoint
[] =
156 {0x2f, 0x90, 0x5e, 0x00};
157 *lenptr
= sizeof (breakpoint
);
161 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
162 when the reg_nr isn't valid. */
166 TS2_IMAP0_REGNUM
= 32,
167 TS2_DMAP_REGNUM
= 34,
168 TS2_NR_DMAP_REGS
= 1,
173 d10v_ts2_register_name (int reg_nr
)
175 static char *register_names
[] =
177 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
178 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
179 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
180 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
181 "imap0", "imap1", "dmap", "a0", "a1"
185 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
187 return register_names
[reg_nr
];
192 TS3_IMAP0_REGNUM
= 36,
193 TS3_DMAP0_REGNUM
= 38,
194 TS3_NR_DMAP_REGS
= 4,
199 d10v_ts3_register_name (int reg_nr
)
201 static char *register_names
[] =
203 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
204 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
205 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
206 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
210 "dmap0", "dmap1", "dmap2", "dmap3"
214 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
216 return register_names
[reg_nr
];
219 /* Access the DMAP/IMAP registers in a target independent way.
221 Divide the D10V's 64k data space into four 16k segments:
222 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
225 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
226 0x7fff) always map to the on-chip data RAM, and the fourth always
227 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
228 unified memory or instruction memory, under the control of the
229 single DMAP register.
231 On the TS3, there are four DMAP registers, each of which controls
232 one of the segments. */
235 d10v_ts2_dmap_register (int reg_nr
)
243 return read_register (TS2_DMAP_REGNUM
);
250 d10v_ts3_dmap_register (int reg_nr
)
252 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
256 d10v_dmap_register (int reg_nr
)
258 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
262 d10v_ts2_imap_register (int reg_nr
)
264 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
268 d10v_ts3_imap_register (int reg_nr
)
270 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
274 d10v_imap_register (int reg_nr
)
276 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
279 /* MAP GDB's internal register numbering (determined by the layout fo
280 the REGISTER_BYTE array) onto the simulator's register
284 d10v_ts2_register_sim_regno (int nr
)
286 if (legacy_register_sim_regno (nr
) < 0)
287 return legacy_register_sim_regno (nr
);
288 if (nr
>= TS2_IMAP0_REGNUM
289 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
290 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
291 if (nr
== TS2_DMAP_REGNUM
)
292 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
293 if (nr
>= TS2_A0_REGNUM
294 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
295 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
300 d10v_ts3_register_sim_regno (int nr
)
302 if (legacy_register_sim_regno (nr
) < 0)
303 return legacy_register_sim_regno (nr
);
304 if (nr
>= TS3_IMAP0_REGNUM
305 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
306 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
307 if (nr
>= TS3_DMAP0_REGNUM
308 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
309 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
310 if (nr
>= TS3_A0_REGNUM
311 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
312 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
316 /* Index within `registers' of the first byte of the space for
320 d10v_register_byte (int reg_nr
)
322 if (reg_nr
< A0_REGNUM
)
324 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
325 return (A0_REGNUM
* 2
326 + (reg_nr
- A0_REGNUM
) * 8);
328 return (A0_REGNUM
* 2
330 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
333 /* Number of bytes of storage in the actual machine representation for
337 d10v_register_raw_size (int reg_nr
)
339 if (reg_nr
< A0_REGNUM
)
341 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
347 /* Return the GDB type object for the "standard" data type
348 of data in register N. */
351 d10v_register_virtual_type (int reg_nr
)
353 if (reg_nr
== PC_REGNUM
)
354 return builtin_type_void_func_ptr
;
355 if (reg_nr
== _SP_REGNUM
|| reg_nr
== _FP_REGNUM
)
356 return builtin_type_void_data_ptr
;
357 else if (reg_nr
>= A0_REGNUM
358 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
359 return builtin_type_int64
;
361 return builtin_type_int16
;
365 d10v_daddr_p (CORE_ADDR x
)
367 return (((x
) & 0x3000000) == DMEM_START
);
371 d10v_iaddr_p (CORE_ADDR x
)
373 return (((x
) & 0x3000000) == IMEM_START
);
377 d10v_make_daddr (CORE_ADDR x
)
379 return ((x
) | DMEM_START
);
383 d10v_make_iaddr (CORE_ADDR x
)
385 if (d10v_iaddr_p (x
))
386 return x
; /* Idempotency -- x is already in the IMEM space. */
388 return (((x
) << 2) | IMEM_START
);
392 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
394 return (((x
) >> 2) & 0xffff);
398 d10v_convert_daddr_to_raw (CORE_ADDR x
)
400 return ((x
) & 0xffff);
404 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
406 /* Is it a code address? */
407 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
408 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
410 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
411 d10v_convert_iaddr_to_raw (addr
));
415 /* Strip off any upper segment bits. */
416 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
417 d10v_convert_daddr_to_raw (addr
));
422 d10v_pointer_to_address (struct type
*type
, const void *buf
)
424 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
426 /* Is it a code address? */
427 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
428 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
429 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
430 return d10v_make_iaddr (addr
);
432 return d10v_make_daddr (addr
);
435 /* Don't do anything if we have an integer, this way users can type 'x
436 <addr>' w/o having gdb outsmart them. The internal gdb conversions
437 to the correct space are taken care of in the pointer_to_address
438 function. If we don't do this, 'x $fp' wouldn't work. */
440 d10v_integer_to_address (struct type
*type
, void *buf
)
443 val
= unpack_long (type
, buf
);
447 /* Store the address of the place in which to copy the structure the
448 subroutine will return. This is called from call_function.
450 We store structs through a pointer passed in the first Argument
454 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
456 write_register (ARG1_REGNUM
, (addr
));
459 /* Write into appropriate registers a function return value
460 of type TYPE, given in virtual format.
462 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
465 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
468 /* Only char return values need to be shifted right within the first
470 if (TYPE_LENGTH (type
) == 1
471 && TYPE_CODE (type
) == TYPE_CODE_INT
)
474 tmp
[1] = *(bfd_byte
*)valbuf
;
475 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
480 /* A structure is never more than 8 bytes long. See
481 use_struct_convention(). */
482 gdb_assert (TYPE_LENGTH (type
) <= 8);
483 /* Write out most registers, stop loop before trying to write
484 out any dangling byte at the end of the buffer. */
485 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
487 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
488 (bfd_byte
*) valbuf
+ reg
* 2);
490 /* Write out any dangling byte at the end of the buffer. */
491 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
492 regcache_cooked_write_part (regcache
, reg
, 0, 1,
493 (bfd_byte
*) valbuf
+ reg
* 2);
497 /* Extract from an array REGBUF containing the (raw) register state
498 the address in which a function should return its structure value,
499 as a CORE_ADDR (or an expression that can be used as one). */
502 d10v_extract_struct_value_address (struct regcache
*regcache
)
505 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
506 return (addr
| DMEM_START
);
509 /* Immediately after a function call, return the saved pc. We can't
510 use frame->return_pc beause that is determined by reading R13 off
511 the stack and that may not be written yet. */
514 d10v_saved_pc_after_call (struct frame_info
*frame
)
516 return ((read_register (LR_REGNUM
) << 2)
521 check_prologue (unsigned short op
)
524 if ((op
& 0x7E1F) == 0x6C1F)
528 if ((op
& 0x7E3F) == 0x6E1F)
532 if ((op
& 0x7FE1) == 0x01E1)
544 if ((op
& 0x7E1F) == 0x681E)
548 if ((op
& 0x7E3F) == 0x3A1E)
555 d10v_skip_prologue (CORE_ADDR pc
)
558 unsigned short op1
, op2
;
559 CORE_ADDR func_addr
, func_end
;
560 struct symtab_and_line sal
;
562 /* If we have line debugging information, then the end of the */
563 /* prologue should the first assembly instruction of the first source line */
564 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
566 sal
= find_pc_line (func_addr
, 0);
567 if (sal
.end
&& sal
.end
< func_end
)
571 if (target_read_memory (pc
, (char *) &op
, 4))
572 return pc
; /* Can't access it -- assume no prologue. */
576 op
= (unsigned long) read_memory_integer (pc
, 4);
577 if ((op
& 0xC0000000) == 0xC0000000)
579 /* long instruction */
580 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
581 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
582 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
587 /* short instructions */
588 if ((op
& 0xC0000000) == 0x80000000)
590 op2
= (op
& 0x3FFF8000) >> 15;
595 op1
= (op
& 0x3FFF8000) >> 15;
598 if (check_prologue (op1
))
600 if (!check_prologue (op2
))
602 /* if the previous opcode was really part of the prologue */
603 /* and not just a NOP, then we want to break after both instructions */
617 struct d10v_unwind_cache
622 CORE_ADDR
*saved_regs
;
629 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
635 if ((op
& 0x7E1F) == 0x6C1F)
637 n
= (op
& 0x1E0) >> 5;
638 info
->next_addr
-= 2;
639 info
->saved_regs
[n
] = info
->next_addr
;
644 else if ((op
& 0x7E3F) == 0x6E1F)
646 n
= (op
& 0x1E0) >> 5;
647 info
->next_addr
-= 4;
648 info
->saved_regs
[n
] = info
->next_addr
;
649 info
->saved_regs
[n
+ 1] = info
->next_addr
+ 2;
654 if ((op
& 0x7FE1) == 0x01E1)
656 n
= (op
& 0x1E) >> 1;
659 info
->next_addr
-= n
;
666 info
->uses_frame
= 1;
675 if ((op
& 0x7E1F) == 0x681E)
677 n
= (op
& 0x1E0) >> 5;
678 info
->saved_regs
[n
] = info
->next_addr
;
683 if ((op
& 0x7E3F) == 0x3A1E)
685 n
= (op
& 0x1E0) >> 5;
686 info
->saved_regs
[n
] = info
->next_addr
;
687 info
->saved_regs
[n
+ 1] = info
->next_addr
+ 2;
694 /* Put here the code to store, into fi->saved_regs, the addresses of
695 the saved registers of frame described by FRAME_INFO. This
696 includes special registers such as pc and fp saved in special ways
697 in the stack frame. sp is even more special: the address we return
698 for it IS the sp for the next frame. */
700 struct d10v_unwind_cache
*
701 d10v_frame_unwind_cache (struct frame_info
*fi
,
706 unsigned short op1
, op2
;
708 struct d10v_unwind_cache
*info
;
713 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
715 info
->saved_regs
= frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS
);
721 fp
= get_frame_base (fi
);
724 pc
= get_pc_function_start (get_frame_pc (fi
));
726 info
->uses_frame
= 0;
729 op
= (unsigned long) read_memory_integer (pc
, 4);
730 if ((op
& 0xC0000000) == 0xC0000000)
732 /* long instruction */
733 if ((op
& 0x3FFF0000) == 0x01FF0000)
736 short n
= op
& 0xFFFF;
737 info
->next_addr
+= n
;
739 else if ((op
& 0x3F0F0000) == 0x340F0000)
741 /* st rn, @(offset,sp) */
742 short offset
= op
& 0xFFFF;
743 short n
= (op
>> 20) & 0xF;
744 info
->saved_regs
[n
] = info
->next_addr
+ offset
;
746 else if ((op
& 0x3F1F0000) == 0x350F0000)
748 /* st2w rn, @(offset,sp) */
749 short offset
= op
& 0xFFFF;
750 short n
= (op
>> 20) & 0xF;
751 info
->saved_regs
[n
] = info
->next_addr
+ offset
;
752 info
->saved_regs
[n
+ 1] = info
->next_addr
+ offset
+ 2;
759 /* short instructions */
760 if ((op
& 0xC0000000) == 0x80000000)
762 op2
= (op
& 0x3FFF8000) >> 15;
767 op1
= (op
& 0x3FFF8000) >> 15;
770 if (!prologue_find_regs (info
, op1
, pc
)
771 || !prologue_find_regs (info
, op2
, pc
))
777 info
->size
= -info
->next_addr
;
780 fp
= d10v_read_sp ();
782 for (i
= 0; i
< NUM_REGS
- 1; i
++)
783 if (info
->saved_regs
[i
])
785 info
->saved_regs
[i
] = fp
- (info
->next_addr
- info
->saved_regs
[i
]);
788 if (info
->saved_regs
[LR_REGNUM
])
791 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
792 REGISTER_RAW_SIZE (LR_REGNUM
));
793 info
->return_pc
= d10v_make_iaddr (return_pc
);
798 frame_read_unsigned_register (fi
, LR_REGNUM
, &return_pc
);
799 info
->return_pc
= d10v_make_iaddr (return_pc
);
802 /* The SP is not normally (ever?) saved, but check anyway */
803 if (!info
->saved_regs
[SP_REGNUM
])
805 /* if the FP was saved, that means the current FP is valid, */
806 /* otherwise, it isn't being used, so we use the SP instead */
807 if (info
->uses_frame
)
808 info
->saved_regs
[SP_REGNUM
]
809 = d10v_read_fp () + info
->size
;
812 info
->saved_regs
[SP_REGNUM
] = fp
+ info
->size
;
814 info
->saved_regs
[FP_REGNUM
] = 0;
822 show_regs (char *args
, int from_tty
)
825 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
826 (long) read_register (PC_REGNUM
),
827 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
828 (long) read_register (PSW_REGNUM
),
829 (long) read_register (24),
830 (long) read_register (25),
831 (long) read_register (23));
832 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
833 (long) read_register (0),
834 (long) read_register (1),
835 (long) read_register (2),
836 (long) read_register (3),
837 (long) read_register (4),
838 (long) read_register (5),
839 (long) read_register (6),
840 (long) read_register (7));
841 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
842 (long) read_register (8),
843 (long) read_register (9),
844 (long) read_register (10),
845 (long) read_register (11),
846 (long) read_register (12),
847 (long) read_register (13),
848 (long) read_register (14),
849 (long) read_register (15));
850 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
853 printf_filtered (" ");
854 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
856 if (NR_DMAP_REGS
== 1)
857 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
860 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
862 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
864 printf_filtered ("\n");
866 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
868 char *num
= alloca (max_register_size (current_gdbarch
));
869 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
872 printf_filtered (" ");
873 deprecated_read_register_gen (a
, (char *) &num
);
874 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
876 printf_filtered ("%02x", (num
[i
] & 0xff));
880 printf_filtered ("\n");
884 d10v_read_pc (ptid_t ptid
)
890 save_ptid
= inferior_ptid
;
891 inferior_ptid
= ptid
;
892 pc
= (int) read_register (PC_REGNUM
);
893 inferior_ptid
= save_ptid
;
894 retval
= d10v_make_iaddr (pc
);
899 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
903 save_ptid
= inferior_ptid
;
904 inferior_ptid
= ptid
;
905 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
906 inferior_ptid
= save_ptid
;
912 return (d10v_make_daddr (read_register (SP_REGNUM
)));
916 d10v_write_sp (CORE_ADDR val
)
918 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
924 return (d10v_make_daddr (read_register (FP_REGNUM
)));
927 /* Function: push_return_address (pc)
928 Set up the return address for the inferior function call.
929 Needed for targets where we don't actually execute a JSR/BSR instruction */
932 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
934 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
939 /* When arguments must be pushed onto the stack, they go on in reverse
940 order. The below implements a FILO (stack) to do this. */
945 struct stack_item
*prev
;
949 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
950 void *contents
, int len
);
951 static struct stack_item
*
952 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
954 struct stack_item
*si
;
955 si
= xmalloc (sizeof (struct stack_item
));
956 si
->data
= xmalloc (len
);
959 memcpy (si
->data
, contents
, len
);
963 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
964 static struct stack_item
*
965 pop_stack_item (struct stack_item
*si
)
967 struct stack_item
*dead
= si
;
976 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
977 int struct_return
, CORE_ADDR struct_addr
)
980 int regnum
= ARG1_REGNUM
;
981 struct stack_item
*si
= NULL
;
984 /* If struct_return is true, then the struct return address will
985 consume one argument-passing register. No need to actually
986 write the value to the register -- that's done by
987 d10v_store_struct_return(). */
992 /* Fill in registers and arg lists */
993 for (i
= 0; i
< nargs
; i
++)
995 struct value
*arg
= args
[i
];
996 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
997 char *contents
= VALUE_CONTENTS (arg
);
998 int len
= TYPE_LENGTH (type
);
999 int aligned_regnum
= (regnum
+ 1) & ~1;
1001 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1002 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1003 /* fits in a single register, do not align */
1005 val
= extract_unsigned_integer (contents
, len
);
1006 write_register (regnum
++, val
);
1008 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1009 /* value fits in remaining registers, store keeping left
1013 regnum
= aligned_regnum
;
1014 for (b
= 0; b
< (len
& ~1); b
+= 2)
1016 val
= extract_unsigned_integer (&contents
[b
], 2);
1017 write_register (regnum
++, val
);
1021 val
= extract_unsigned_integer (&contents
[b
], 1);
1022 write_register (regnum
++, (val
<< 8));
1027 /* arg will go onto stack */
1028 regnum
= ARGN_REGNUM
+ 1;
1029 si
= push_stack_item (si
, contents
, len
);
1035 sp
= (sp
- si
->len
) & ~1;
1036 write_memory (sp
, si
->data
, si
->len
);
1037 si
= pop_stack_item (si
);
1044 /* Given a return value in `regbuf' with a type `valtype',
1045 extract and copy its value into `valbuf'. */
1048 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1053 printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type
),
1054 TYPE_LENGTH (type
), RET1_REGNUM
- R0_REGNUM
,
1055 (int) extract_unsigned_integer (regbuf
+ REGISTER_BYTE(RET1_REGNUM
),
1056 REGISTER_RAW_SIZE (RET1_REGNUM
)));
1058 if (TYPE_LENGTH (type
) == 1)
1061 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1062 store_unsigned_integer (valbuf
, 1, c
);
1066 /* For return values of odd size, the first byte is in the
1067 least significant part of the first register. The
1068 remaining bytes in remaining registers. Interestingly, when
1069 such values are passed in, the last byte is in the most
1070 significant byte of that same register - wierd. */
1071 int reg
= RET1_REGNUM
;
1073 if (TYPE_LENGTH (type
) & 1)
1075 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1076 (bfd_byte
*)valbuf
+ off
);
1080 /* Transfer the remaining registers. */
1081 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1083 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1084 (bfd_byte
*) valbuf
+ off
);
1089 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1090 understands. Returns number of bytes that can be transfered
1091 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1092 (segmentation fault). Since the simulator knows all about how the
1093 VM system works, we just call that to do the translation. */
1096 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1097 CORE_ADDR
*targ_addr
, int *targ_len
)
1101 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1104 d10v_imap_register
);
1105 *targ_addr
= out_addr
;
1106 *targ_len
= out_len
;
1110 /* The following code implements access to, and display of, the D10V's
1111 instruction trace buffer. The buffer consists of 64K or more
1112 4-byte words of data, of which each words includes an 8-bit count,
1113 an 8-bit segment number, and a 16-bit instruction address.
1115 In theory, the trace buffer is continuously capturing instruction
1116 data that the CPU presents on its "debug bus", but in practice, the
1117 ROMified GDB stub only enables tracing when it continues or steps
1118 the program, and stops tracing when the program stops; so it
1119 actually works for GDB to read the buffer counter out of memory and
1120 then read each trace word. The counter records where the tracing
1121 stops, but there is no record of where it started, so we remember
1122 the PC when we resumed and then search backwards in the trace
1123 buffer for a word that includes that address. This is not perfect,
1124 because you will miss trace data if the resumption PC is the target
1125 of a branch. (The value of the buffer counter is semi-random, any
1126 trace data from a previous program stop is gone.) */
1128 /* The address of the last word recorded in the trace buffer. */
1130 #define DBBC_ADDR (0xd80000)
1132 /* The base of the trace buffer, at least for the "Board_0". */
1134 #define TRACE_BUFFER_BASE (0xf40000)
1136 static void trace_command (char *, int);
1138 static void untrace_command (char *, int);
1140 static void trace_info (char *, int);
1142 static void tdisassemble_command (char *, int);
1144 static void display_trace (int, int);
1146 /* True when instruction traces are being collected. */
1150 /* Remembered PC. */
1152 static CORE_ADDR last_pc
;
1154 /* True when trace output should be displayed whenever program stops. */
1156 static int trace_display
;
1158 /* True when trace listing should include source lines. */
1160 static int default_trace_show_source
= 1;
1171 trace_command (char *args
, int from_tty
)
1173 /* Clear the host-side trace buffer, allocating space if needed. */
1174 trace_data
.size
= 0;
1175 if (trace_data
.counts
== NULL
)
1176 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1177 if (trace_data
.addrs
== NULL
)
1178 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1182 printf_filtered ("Tracing is now on.\n");
1186 untrace_command (char *args
, int from_tty
)
1190 printf_filtered ("Tracing is now off.\n");
1194 trace_info (char *args
, int from_tty
)
1198 if (trace_data
.size
)
1200 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1202 for (i
= 0; i
< trace_data
.size
; ++i
)
1204 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1206 trace_data
.counts
[i
],
1207 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1208 paddr_nz (trace_data
.addrs
[i
]));
1212 printf_filtered ("No entries in trace buffer.\n");
1214 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1217 /* Print the instruction at address MEMADDR in debugged memory,
1218 on STREAM. Returns length of the instruction, in bytes. */
1221 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1223 /* If there's no disassembler, something is very wrong. */
1224 if (tm_print_insn
== NULL
)
1225 internal_error (__FILE__
, __LINE__
,
1226 "print_insn: no disassembler");
1228 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1229 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1231 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1232 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1236 d10v_eva_prepare_to_trace (void)
1241 last_pc
= read_register (PC_REGNUM
);
1244 /* Collect trace data from the target board and format it into a form
1245 more useful for display. */
1248 d10v_eva_get_trace_data (void)
1250 int count
, i
, j
, oldsize
;
1251 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1252 unsigned int last_trace
, trace_word
, next_word
;
1253 unsigned int *tmpspace
;
1258 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1260 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1262 /* Collect buffer contents from the target, stopping when we reach
1263 the word recorded when execution resumed. */
1266 while (last_trace
> 0)
1270 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1271 trace_addr
= trace_word
& 0xffff;
1273 /* Ignore an apparently nonsensical entry. */
1274 if (trace_addr
== 0xffd5)
1276 tmpspace
[count
++] = trace_word
;
1277 if (trace_addr
== last_pc
)
1283 /* Move the data to the host-side trace buffer, adjusting counts to
1284 include the last instruction executed and transforming the address
1285 into something that GDB likes. */
1287 for (i
= 0; i
< count
; ++i
)
1289 trace_word
= tmpspace
[i
];
1290 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1291 trace_addr
= trace_word
& 0xffff;
1292 next_cnt
= (next_word
>> 24) & 0xff;
1293 j
= trace_data
.size
+ count
- i
- 1;
1294 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1295 trace_data
.counts
[j
] = next_cnt
+ 1;
1298 oldsize
= trace_data
.size
;
1299 trace_data
.size
+= count
;
1304 display_trace (oldsize
, trace_data
.size
);
1308 tdisassemble_command (char *arg
, int from_tty
)
1311 CORE_ADDR low
, high
;
1317 high
= trace_data
.size
;
1319 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1321 low
= parse_and_eval_address (arg
);
1326 /* Two arguments. */
1327 *space_index
= '\0';
1328 low
= parse_and_eval_address (arg
);
1329 high
= parse_and_eval_address (space_index
+ 1);
1334 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1336 display_trace (low
, high
);
1338 printf_filtered ("End of trace dump.\n");
1339 gdb_flush (gdb_stdout
);
1343 display_trace (int low
, int high
)
1345 int i
, count
, trace_show_source
, first
, suppress
;
1346 CORE_ADDR next_address
;
1348 trace_show_source
= default_trace_show_source
;
1349 if (!have_full_symbols () && !have_partial_symbols ())
1351 trace_show_source
= 0;
1352 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1353 printf_filtered ("Trace will not display any source.\n");
1358 for (i
= low
; i
< high
; ++i
)
1360 next_address
= trace_data
.addrs
[i
];
1361 count
= trace_data
.counts
[i
];
1365 if (trace_show_source
)
1367 struct symtab_and_line sal
, sal_prev
;
1369 sal_prev
= find_pc_line (next_address
- 4, 0);
1370 sal
= find_pc_line (next_address
, 0);
1374 if (first
|| sal
.line
!= sal_prev
.line
)
1375 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1381 /* FIXME-32x64--assumes sal.pc fits in long. */
1382 printf_filtered ("No source file for address %s.\n",
1383 local_hex_string ((unsigned long) sal
.pc
));
1388 print_address (next_address
, gdb_stdout
);
1389 printf_filtered (":");
1390 printf_filtered ("\t");
1392 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1393 printf_filtered ("\n");
1394 gdb_flush (gdb_stdout
);
1401 d10v_frame_pc_unwind (struct frame_info
*frame
,
1404 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (frame
, cache
);
1405 return info
->return_pc
;
1408 /* Given a GDB frame, determine the address of the calling function's
1409 frame. This will be used to create a new GDB frame struct. */
1412 d10v_frame_id_unwind (struct frame_info
*frame
,
1414 struct frame_id
*id
)
1416 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (frame
, cache
);
1419 /* Start with a NULL frame ID. */
1420 (*id
) = null_frame_id
;
1422 if (info
->return_pc
== IMEM_START
1423 || info
->return_pc
<= IMEM_START
1424 || inside_entry_file (info
->return_pc
))
1426 /* This is meant to halt the backtrace at "_start".
1427 Make sure we don't halt it at a generic dummy frame. */
1431 if (!info
->saved_regs
[FP_REGNUM
])
1433 if (!info
->saved_regs
[SP_REGNUM
]
1434 || info
->saved_regs
[SP_REGNUM
] == STACK_START
)
1437 id
->base
= info
->saved_regs
[SP_REGNUM
];
1438 id
->pc
= info
->return_pc
;
1441 addr
= read_memory_unsigned_integer (info
->saved_regs
[FP_REGNUM
],
1442 REGISTER_RAW_SIZE (FP_REGNUM
));
1446 id
->base
= d10v_make_daddr (addr
);
1447 id
->pc
= info
->return_pc
;
1451 saved_regs_unwinder (struct frame_info
*frame
,
1452 CORE_ADDR
*saved_regs
,
1453 int regnum
, int *optimizedp
,
1454 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1455 int *realnump
, void *bufferp
)
1457 /* If we're using generic dummy frames, we'd better not be in a call
1458 dummy. (generic_call_dummy_register_unwind ought to have been called
1460 gdb_assert (!(DEPRECATED_USE_GENERIC_DUMMY_FRAMES
1461 && (get_frame_type (frame
) == DUMMY_FRAME
)));
1463 if (saved_regs
[regnum
] != 0)
1465 if (regnum
== SP_REGNUM
)
1467 /* SP register treated specially. */
1472 if (bufferp
!= NULL
)
1473 store_address (bufferp
, REGISTER_RAW_SIZE (regnum
),
1474 saved_regs
[regnum
]);
1478 /* Any other register is saved in memory, fetch it but cache
1479 a local copy of its value. */
1481 *lvalp
= lval_memory
;
1482 *addrp
= saved_regs
[regnum
];
1484 if (bufferp
!= NULL
)
1486 /* Read the value in from memory. */
1487 read_memory (saved_regs
[regnum
], bufferp
,
1488 REGISTER_RAW_SIZE (regnum
));
1494 /* No luck, assume this and the next frame have the same register
1495 value. If a value is needed, pass the request on down the chain;
1496 otherwise just return an indication that the value is in the same
1497 register as the next frame. */
1498 frame_register (frame
, regnum
, optimizedp
, lvalp
, addrp
,
1504 d10v_frame_register_unwind (struct frame_info
*frame
,
1506 int regnum
, int *optimizedp
,
1507 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1508 int *realnump
, void *bufferp
)
1510 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (frame
, cache
);
1511 saved_regs_unwinder (frame
, info
->saved_regs
, regnum
, optimizedp
,
1512 lvalp
, addrp
, realnump
, bufferp
);
1517 d10v_frame_pop (struct frame_info
*fi
, void **unwind_cache
,
1518 struct regcache
*regcache
)
1520 struct d10v_unwind_cache
*info
= d10v_frame_unwind_cache (fi
, unwind_cache
);
1525 fp
= get_frame_base (fi
);
1527 /* now update the current registers with the old values */
1528 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
1530 if (info
->saved_regs
[regnum
])
1532 read_memory (info
->saved_regs
[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
1533 deprecated_write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
1534 REGISTER_RAW_SIZE (regnum
));
1537 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
1539 if (info
->saved_regs
[regnum
])
1541 write_register (regnum
, read_memory_unsigned_integer (info
->saved_regs
[regnum
], REGISTER_RAW_SIZE (regnum
)));
1544 if (info
->saved_regs
[PSW_REGNUM
])
1546 write_register (PSW_REGNUM
, read_memory_unsigned_integer (info
->saved_regs
[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
1549 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
1550 write_register (SP_REGNUM
, fp
+ info
->size
);
1551 target_store_registers (-1);
1552 flush_cached_frames ();
1555 static struct frame_unwind d10v_frame_unwind
= {
1557 d10v_frame_pc_unwind
,
1558 d10v_frame_id_unwind
,
1559 d10v_frame_register_unwind
1562 const struct frame_unwind
*
1563 d10v_frame_p (CORE_ADDR pc
)
1565 return &d10v_frame_unwind
;
1568 static gdbarch_init_ftype d10v_gdbarch_init
;
1570 static struct gdbarch
*
1571 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1573 static LONGEST d10v_call_dummy_words
[] =
1575 struct gdbarch
*gdbarch
;
1577 struct gdbarch_tdep
*tdep
;
1578 gdbarch_register_name_ftype
*d10v_register_name
;
1579 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1581 /* Find a candidate among the list of pre-declared architectures. */
1582 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1584 return arches
->gdbarch
;
1586 /* None found, create a new architecture from the information
1588 tdep
= XMALLOC (struct gdbarch_tdep
);
1589 gdbarch
= gdbarch_alloc (&info
, tdep
);
1591 switch (info
.bfd_arch_info
->mach
)
1593 case bfd_mach_d10v_ts2
:
1595 d10v_register_name
= d10v_ts2_register_name
;
1596 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1597 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1598 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1599 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1600 tdep
->imap_register
= d10v_ts2_imap_register
;
1603 case bfd_mach_d10v_ts3
:
1605 d10v_register_name
= d10v_ts3_register_name
;
1606 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1607 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1608 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1609 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1610 tdep
->imap_register
= d10v_ts3_imap_register
;
1614 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1615 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1616 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1617 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1618 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1620 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1621 set_gdbarch_sp_regnum (gdbarch
, 15);
1622 set_gdbarch_fp_regnum (gdbarch
, 11);
1623 set_gdbarch_pc_regnum (gdbarch
, 18);
1624 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1625 set_gdbarch_register_size (gdbarch
, 2);
1626 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1627 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1628 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1629 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1630 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1631 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1632 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1634 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1635 set_gdbarch_addr_bit (gdbarch
, 32);
1636 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1637 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1638 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1639 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1640 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1641 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1642 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1643 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1644 double'' is 64 bits. */
1645 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1646 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1647 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1648 switch (info
.byte_order
)
1650 case BFD_ENDIAN_BIG
:
1651 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1652 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1653 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1655 case BFD_ENDIAN_LITTLE
:
1656 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1657 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1658 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1661 internal_error (__FILE__
, __LINE__
,
1662 "d10v_gdbarch_init: bad byte order for float format");
1665 set_gdbarch_call_dummy_length (gdbarch
, 0);
1666 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1667 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1668 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1669 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1670 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1671 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1672 set_gdbarch_call_dummy_p (gdbarch
, 1);
1673 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1674 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1676 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1677 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1678 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1679 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1681 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1682 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1683 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1684 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1686 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1687 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1688 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1689 set_gdbarch_function_start_offset (gdbarch
, 0);
1690 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1692 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1694 set_gdbarch_frame_args_skip (gdbarch
, 0);
1695 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1697 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1698 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1699 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1701 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1702 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1704 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1710 extern void (*target_resume_hook
) (void);
1711 extern void (*target_wait_loop_hook
) (void);
1714 _initialize_d10v_tdep (void)
1716 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1718 tm_print_insn
= print_insn_d10v
;
1720 target_resume_hook
= d10v_eva_prepare_to_trace
;
1721 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1723 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1725 add_com ("itrace", class_support
, trace_command
,
1726 "Enable tracing of instruction execution.");
1728 add_com ("iuntrace", class_support
, untrace_command
,
1729 "Disable tracing of instruction execution.");
1731 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1732 "Disassemble the trace buffer.\n\
1733 Two optional arguments specify a range of trace buffer entries\n\
1734 as reported by info trace (NOT addresses!).");
1736 add_info ("itrace", trace_info
,
1737 "Display info about the trace data buffer.");
1739 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1740 var_integer
, (char *) &trace_display
,
1741 "Set automatic display of trace.\n", &setlist
),
1743 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1744 var_integer
, (char *) &default_trace_show_source
,
1745 "Set display of source code with trace.\n", &setlist
),