1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
47 #include "gdb_assert.h"
53 unsigned long (*dmap_register
) (int nr
);
54 unsigned long (*imap_register
) (int nr
);
57 /* These are the addresses the D10V-EVA board maps data and
58 instruction memory to. */
61 DMEM_START
= 0x2000000,
62 IMEM_START
= 0x1000000,
63 STACK_START
= 0x200bffe
66 /* d10v register names. */
81 /* d10v calling convention. */
82 ARG1_REGNUM
= R0_REGNUM
,
83 ARGN_REGNUM
= R3_REGNUM
,
84 RET1_REGNUM
= R0_REGNUM
,
88 nr_dmap_regs (struct gdbarch
*gdbarch
)
90 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
94 a0_regnum (struct gdbarch
*gdbarch
)
96 return gdbarch_tdep (gdbarch
)->a0_regnum
;
101 extern void _initialize_d10v_tdep (void);
103 static CORE_ADDR
d10v_read_sp (void);
105 static void d10v_eva_prepare_to_trace (void);
107 static void d10v_eva_get_trace_data (void);
110 d10v_stack_align (CORE_ADDR len
)
112 return (len
+ 1) & ~1;
115 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
116 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
117 and TYPE is the type (which is known to be struct, union or array).
119 The d10v returns anything less than 8 bytes in size in
123 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
127 /* The d10v only passes a struct in a register when that structure
128 has an alignment that matches the size of a register. */
129 /* If the structure doesn't fit in 4 registers, put it on the
131 if (TYPE_LENGTH (type
) > 8)
133 /* If the struct contains only one field, don't put it on the stack
134 - gcc can fit it in one or more registers. */
135 if (TYPE_NFIELDS (type
) == 1)
137 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
138 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
140 /* If the alignment changes, just assume it goes on the
142 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
145 /* If the alignment is suitable for the d10v's 16 bit registers,
146 don't put it on the stack. */
147 if (alignment
== 2 || alignment
== 4)
153 static const unsigned char *
154 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
156 static unsigned char breakpoint
[] =
157 {0x2f, 0x90, 0x5e, 0x00};
158 *lenptr
= sizeof (breakpoint
);
162 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
163 when the reg_nr isn't valid. */
167 TS2_IMAP0_REGNUM
= 32,
168 TS2_DMAP_REGNUM
= 34,
169 TS2_NR_DMAP_REGS
= 1,
174 d10v_ts2_register_name (int reg_nr
)
176 static char *register_names
[] =
178 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
179 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
180 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
181 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
182 "imap0", "imap1", "dmap", "a0", "a1"
186 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
188 return register_names
[reg_nr
];
193 TS3_IMAP0_REGNUM
= 36,
194 TS3_DMAP0_REGNUM
= 38,
195 TS3_NR_DMAP_REGS
= 4,
200 d10v_ts3_register_name (int reg_nr
)
202 static char *register_names
[] =
204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
206 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
207 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
211 "dmap0", "dmap1", "dmap2", "dmap3"
215 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
217 return register_names
[reg_nr
];
220 /* Access the DMAP/IMAP registers in a target independent way.
222 Divide the D10V's 64k data space into four 16k segments:
223 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
226 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
227 0x7fff) always map to the on-chip data RAM, and the fourth always
228 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
229 unified memory or instruction memory, under the control of the
230 single DMAP register.
232 On the TS3, there are four DMAP registers, each of which controls
233 one of the segments. */
236 d10v_ts2_dmap_register (int reg_nr
)
244 return read_register (TS2_DMAP_REGNUM
);
251 d10v_ts3_dmap_register (int reg_nr
)
253 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
257 d10v_dmap_register (int reg_nr
)
259 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
263 d10v_ts2_imap_register (int reg_nr
)
265 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
269 d10v_ts3_imap_register (int reg_nr
)
271 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
275 d10v_imap_register (int reg_nr
)
277 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
280 /* MAP GDB's internal register numbering (determined by the layout fo
281 the REGISTER_BYTE array) onto the simulator's register
285 d10v_ts2_register_sim_regno (int nr
)
287 /* Only makes sense to supply raw registers. */
288 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
289 if (nr
>= TS2_IMAP0_REGNUM
290 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
291 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
292 if (nr
== TS2_DMAP_REGNUM
)
293 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
294 if (nr
>= TS2_A0_REGNUM
295 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
296 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
301 d10v_ts3_register_sim_regno (int nr
)
303 /* Only makes sense to supply raw registers. */
304 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
305 if (nr
>= TS3_IMAP0_REGNUM
306 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
307 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
308 if (nr
>= TS3_DMAP0_REGNUM
309 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
310 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
311 if (nr
>= TS3_A0_REGNUM
312 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
313 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
317 /* Return the GDB type object for the "standard" data type
318 of data in register N. */
321 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
323 if (reg_nr
== PC_REGNUM
)
324 return builtin_type_void_func_ptr
;
325 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
326 return builtin_type_void_data_ptr
;
327 else if (reg_nr
>= a0_regnum (gdbarch
)
328 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
329 return builtin_type_int64
;
331 return builtin_type_int16
;
335 d10v_daddr_p (CORE_ADDR x
)
337 return (((x
) & 0x3000000) == DMEM_START
);
341 d10v_iaddr_p (CORE_ADDR x
)
343 return (((x
) & 0x3000000) == IMEM_START
);
347 d10v_make_daddr (CORE_ADDR x
)
349 return ((x
) | DMEM_START
);
353 d10v_make_iaddr (CORE_ADDR x
)
355 if (d10v_iaddr_p (x
))
356 return x
; /* Idempotency -- x is already in the IMEM space. */
358 return (((x
) << 2) | IMEM_START
);
362 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
364 return (((x
) >> 2) & 0xffff);
368 d10v_convert_daddr_to_raw (CORE_ADDR x
)
370 return ((x
) & 0xffff);
374 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
376 /* Is it a code address? */
377 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
378 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
380 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
381 d10v_convert_iaddr_to_raw (addr
));
385 /* Strip off any upper segment bits. */
386 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
387 d10v_convert_daddr_to_raw (addr
));
392 d10v_pointer_to_address (struct type
*type
, const void *buf
)
394 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
395 /* Is it a code address? */
396 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
397 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
398 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
399 return d10v_make_iaddr (addr
);
401 return d10v_make_daddr (addr
);
404 /* Don't do anything if we have an integer, this way users can type 'x
405 <addr>' w/o having gdb outsmart them. The internal gdb conversions
406 to the correct space are taken care of in the pointer_to_address
407 function. If we don't do this, 'x $fp' wouldn't work. */
409 d10v_integer_to_address (struct type
*type
, void *buf
)
412 val
= unpack_long (type
, buf
);
416 /* Write into appropriate registers a function return value
417 of type TYPE, given in virtual format.
419 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
422 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
425 /* Only char return values need to be shifted right within the first
427 if (TYPE_LENGTH (type
) == 1
428 && TYPE_CODE (type
) == TYPE_CODE_INT
)
431 tmp
[1] = *(bfd_byte
*)valbuf
;
432 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
437 /* A structure is never more than 8 bytes long. See
438 use_struct_convention(). */
439 gdb_assert (TYPE_LENGTH (type
) <= 8);
440 /* Write out most registers, stop loop before trying to write
441 out any dangling byte at the end of the buffer. */
442 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
444 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
445 (bfd_byte
*) valbuf
+ reg
* 2);
447 /* Write out any dangling byte at the end of the buffer. */
448 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
449 regcache_cooked_write_part (regcache
, reg
, 0, 1,
450 (bfd_byte
*) valbuf
+ reg
* 2);
454 /* Extract from an array REGBUF containing the (raw) register state
455 the address in which a function should return its structure value,
456 as a CORE_ADDR (or an expression that can be used as one). */
459 d10v_extract_struct_value_address (struct regcache
*regcache
)
462 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
463 return (addr
| DMEM_START
);
467 check_prologue (unsigned short op
)
470 if ((op
& 0x7E1F) == 0x6C1F)
474 if ((op
& 0x7E3F) == 0x6E1F)
478 if ((op
& 0x7FE1) == 0x01E1)
490 if ((op
& 0x7E1F) == 0x681E)
494 if ((op
& 0x7E3F) == 0x3A1E)
501 d10v_skip_prologue (CORE_ADDR pc
)
504 unsigned short op1
, op2
;
505 CORE_ADDR func_addr
, func_end
;
506 struct symtab_and_line sal
;
508 /* If we have line debugging information, then the end of the */
509 /* prologue should the first assembly instruction of the first source line */
510 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
512 sal
= find_pc_line (func_addr
, 0);
513 if (sal
.end
&& sal
.end
< func_end
)
517 if (target_read_memory (pc
, (char *) &op
, 4))
518 return pc
; /* Can't access it -- assume no prologue. */
522 op
= (unsigned long) read_memory_integer (pc
, 4);
523 if ((op
& 0xC0000000) == 0xC0000000)
525 /* long instruction */
526 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
527 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
528 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
533 /* short instructions */
534 if ((op
& 0xC0000000) == 0x80000000)
536 op2
= (op
& 0x3FFF8000) >> 15;
541 op1
= (op
& 0x3FFF8000) >> 15;
544 if (check_prologue (op1
))
546 if (!check_prologue (op2
))
548 /* if the previous opcode was really part of the prologue */
549 /* and not just a NOP, then we want to break after both instructions */
563 struct d10v_unwind_cache
566 /* The previous frame's inner most stack address. Used as this
567 frame ID's stack_addr. */
569 /* The frame's base, optionally used by the high-level debug info. */
572 CORE_ADDR
*saved_regs
;
573 /* How far the SP and r11 (FP) have been offset from the start of
574 the stack frame (as defined by the previous frame's stack
583 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
589 if ((op
& 0x7E1F) == 0x6C1F)
591 n
= (op
& 0x1E0) >> 5;
592 info
->sp_offset
-= 2;
593 info
->saved_regs
[n
] = info
->sp_offset
;
598 else if ((op
& 0x7E3F) == 0x6E1F)
600 n
= (op
& 0x1E0) >> 5;
601 info
->sp_offset
-= 4;
602 info
->saved_regs
[n
] = info
->sp_offset
;
603 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
608 if ((op
& 0x7FE1) == 0x01E1)
610 n
= (op
& 0x1E) >> 1;
613 info
->sp_offset
-= n
;
620 info
->uses_frame
= 1;
621 info
->r11_offset
= info
->sp_offset
;
626 if ((op
& 0x7E1F) == 0x6816)
628 n
= (op
& 0x1E0) >> 5;
629 info
->saved_regs
[n
] = info
->r11_offset
;
638 if ((op
& 0x7E1F) == 0x681E)
640 n
= (op
& 0x1E0) >> 5;
641 info
->saved_regs
[n
] = info
->sp_offset
;
646 if ((op
& 0x7E3F) == 0x3A1E)
648 n
= (op
& 0x1E0) >> 5;
649 info
->saved_regs
[n
] = info
->sp_offset
;
650 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
657 /* Put here the code to store, into fi->saved_regs, the addresses of
658 the saved registers of frame described by FRAME_INFO. This
659 includes special registers such as pc and fp saved in special ways
660 in the stack frame. sp is even more special: the address we return
661 for it IS the sp for the next frame. */
663 struct d10v_unwind_cache
*
664 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
665 void **this_prologue_cache
)
671 unsigned short op1
, op2
;
673 struct d10v_unwind_cache
*info
;
675 if ((*this_prologue_cache
))
676 return (*this_prologue_cache
);
678 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
679 (*this_prologue_cache
) = info
;
680 info
->saved_regs
= FRAME_OBSTACK_CALLOC (NUM_REGS
, CORE_ADDR
);
686 info
->uses_frame
= 0;
687 for (pc
= frame_func_unwind (next_frame
);
688 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
691 op
= (unsigned long) read_memory_integer (pc
, 4);
692 if ((op
& 0xC0000000) == 0xC0000000)
694 /* long instruction */
695 if ((op
& 0x3FFF0000) == 0x01FF0000)
698 short n
= op
& 0xFFFF;
699 info
->sp_offset
+= n
;
701 else if ((op
& 0x3F0F0000) == 0x340F0000)
703 /* st rn, @(offset,sp) */
704 short offset
= op
& 0xFFFF;
705 short n
= (op
>> 20) & 0xF;
706 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
708 else if ((op
& 0x3F1F0000) == 0x350F0000)
710 /* st2w rn, @(offset,sp) */
711 short offset
= op
& 0xFFFF;
712 short n
= (op
>> 20) & 0xF;
713 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
714 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
721 /* short instructions */
722 if ((op
& 0xC0000000) == 0x80000000)
724 op2
= (op
& 0x3FFF8000) >> 15;
729 op1
= (op
& 0x3FFF8000) >> 15;
732 if (!prologue_find_regs (info
, op1
, pc
)
733 || !prologue_find_regs (info
, op2
, pc
))
738 info
->size
= -info
->sp_offset
;
740 /* Compute the frame's base, and the previous frame's SP. */
741 if (info
->uses_frame
)
743 /* The SP was moved to the FP. This indicates that a new frame
744 was created. Get THIS frame's FP value by unwinding it from
746 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
747 /* The FP points at the last saved register. Adjust the FP back
748 to before the first saved register giving the SP. */
749 prev_sp
= this_base
+ info
->size
;
751 else if (info
->saved_regs
[D10V_SP_REGNUM
])
753 /* The SP was saved (which is very unusual), the frame base is
754 just the PREV's frame's TOP-OF-STACK. */
755 this_base
= read_memory_unsigned_integer (info
->saved_regs
[D10V_SP_REGNUM
],
756 register_size (current_gdbarch
,
762 /* Assume that the FP is this frame's SP but with that pushed
763 stack space added back. */
764 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
765 prev_sp
= this_base
+ info
->size
;
768 info
->base
= d10v_make_daddr (this_base
);
769 info
->prev_sp
= d10v_make_daddr (prev_sp
);
771 /* Adjust all the saved registers so that they contain addresses and
773 for (i
= 0; i
< NUM_REGS
- 1; i
++)
774 if (info
->saved_regs
[i
])
776 info
->saved_regs
[i
] = (info
->prev_sp
+ info
->saved_regs
[i
]);
779 if (info
->saved_regs
[LR_REGNUM
])
782 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
783 register_size (current_gdbarch
, LR_REGNUM
));
784 info
->return_pc
= d10v_make_iaddr (return_pc
);
789 frame_unwind_unsigned_register (next_frame
, LR_REGNUM
, &return_pc
);
790 info
->return_pc
= d10v_make_iaddr (return_pc
);
793 /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the
794 previous frame's SP value is saved. */
795 info
->saved_regs
[D10V_SP_REGNUM
] = info
->prev_sp
;
801 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
802 struct frame_info
*frame
, int regnum
, int all
)
806 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
811 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
812 frame_read_unsigned_register (frame
, PC_REGNUM
, &pc
);
813 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
814 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
815 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
816 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
817 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
818 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
819 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
824 for (group
= 0; group
< 16; group
+= 8)
827 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
828 for (r
= group
; r
< group
+ 8; r
++)
831 frame_read_unsigned_register (frame
, r
, &tmp
);
832 fprintf_filtered (file
, " %04lx", (long) tmp
);
834 fprintf_filtered (file
, "\n");
838 /* Note: The IMAP/DMAP registers don't participate in function
839 calls. Don't bother trying to unwind them. */
843 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
846 fprintf_filtered (file
, " ");
847 fprintf_filtered (file
, "IMAP%d %04lx", a
, d10v_imap_register (a
));
849 if (nr_dmap_regs (gdbarch
) == 1)
850 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
851 fprintf_filtered (file
, " DMAP %04lx\n", d10v_dmap_register (2));
854 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
856 fprintf_filtered (file
, " DMAP%d %04lx", a
, d10v_dmap_register (a
));
858 fprintf_filtered (file
, "\n");
863 char *num
= alloca (max_register_size (gdbarch
));
865 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
866 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
869 fprintf_filtered (file
, " ");
870 frame_read_register (frame
, a
, num
);
871 for (i
= 0; i
< register_size (current_gdbarch
, a
); i
++)
873 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
877 fprintf_filtered (file
, "\n");
881 show_regs (char *args
, int from_tty
)
883 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
884 get_current_frame (), -1, 1);
888 d10v_read_pc (ptid_t ptid
)
894 save_ptid
= inferior_ptid
;
895 inferior_ptid
= ptid
;
896 pc
= (int) read_register (PC_REGNUM
);
897 inferior_ptid
= save_ptid
;
898 retval
= d10v_make_iaddr (pc
);
903 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
907 save_ptid
= inferior_ptid
;
908 inferior_ptid
= ptid
;
909 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
910 inferior_ptid
= save_ptid
;
916 return (d10v_make_daddr (read_register (D10V_SP_REGNUM
)));
919 /* When arguments must be pushed onto the stack, they go on in reverse
920 order. The below implements a FILO (stack) to do this. */
925 struct stack_item
*prev
;
929 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
930 void *contents
, int len
);
931 static struct stack_item
*
932 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
934 struct stack_item
*si
;
935 si
= xmalloc (sizeof (struct stack_item
));
936 si
->data
= xmalloc (len
);
939 memcpy (si
->data
, contents
, len
);
943 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
944 static struct stack_item
*
945 pop_stack_item (struct stack_item
*si
)
947 struct stack_item
*dead
= si
;
956 d10v_push_dummy_call (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
957 CORE_ADDR dummy_addr
, int nargs
, struct value
**args
,
958 CORE_ADDR sp
, int struct_return
, CORE_ADDR struct_addr
)
961 int regnum
= ARG1_REGNUM
;
962 struct stack_item
*si
= NULL
;
965 /* Set the return address. For the d10v, the return breakpoint is
966 always at DUMMY_ADDR. */
967 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
968 d10v_convert_iaddr_to_raw (dummy_addr
));
970 /* If STRUCT_RETURN is true, then the struct return address (in
971 STRUCT_ADDR) will consume the first argument-passing register.
972 Both adjust the register count and store that value. */
975 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
979 /* Fill in registers and arg lists */
980 for (i
= 0; i
< nargs
; i
++)
982 struct value
*arg
= args
[i
];
983 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
984 char *contents
= VALUE_CONTENTS (arg
);
985 int len
= TYPE_LENGTH (type
);
986 int aligned_regnum
= (regnum
+ 1) & ~1;
988 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
989 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
990 /* fits in a single register, do not align */
992 val
= extract_unsigned_integer (contents
, len
);
993 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
995 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
996 /* value fits in remaining registers, store keeping left
1000 regnum
= aligned_regnum
;
1001 for (b
= 0; b
< (len
& ~1); b
+= 2)
1003 val
= extract_unsigned_integer (&contents
[b
], 2);
1004 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1008 val
= extract_unsigned_integer (&contents
[b
], 1);
1009 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1014 /* arg will go onto stack */
1015 regnum
= ARGN_REGNUM
+ 1;
1016 si
= push_stack_item (si
, contents
, len
);
1022 sp
= (sp
- si
->len
) & ~1;
1023 write_memory (sp
, si
->data
, si
->len
);
1024 si
= pop_stack_item (si
);
1027 /* Finally, update the SP register. */
1028 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1029 d10v_convert_daddr_to_raw (sp
));
1035 /* Given a return value in `regbuf' with a type `valtype',
1036 extract and copy its value into `valbuf'. */
1039 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1043 if (TYPE_LENGTH (type
) == 1)
1046 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1047 store_unsigned_integer (valbuf
, 1, c
);
1051 /* For return values of odd size, the first byte is in the
1052 least significant part of the first register. The
1053 remaining bytes in remaining registers. Interestingly, when
1054 such values are passed in, the last byte is in the most
1055 significant byte of that same register - wierd. */
1056 int reg
= RET1_REGNUM
;
1058 if (TYPE_LENGTH (type
) & 1)
1060 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1061 (bfd_byte
*)valbuf
+ off
);
1065 /* Transfer the remaining registers. */
1066 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1068 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1069 (bfd_byte
*) valbuf
+ off
);
1074 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1075 understands. Returns number of bytes that can be transfered
1076 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1077 (segmentation fault). Since the simulator knows all about how the
1078 VM system works, we just call that to do the translation. */
1081 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1082 CORE_ADDR
*targ_addr
, int *targ_len
)
1086 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1089 d10v_imap_register
);
1090 *targ_addr
= out_addr
;
1091 *targ_len
= out_len
;
1095 /* The following code implements access to, and display of, the D10V's
1096 instruction trace buffer. The buffer consists of 64K or more
1097 4-byte words of data, of which each words includes an 8-bit count,
1098 an 8-bit segment number, and a 16-bit instruction address.
1100 In theory, the trace buffer is continuously capturing instruction
1101 data that the CPU presents on its "debug bus", but in practice, the
1102 ROMified GDB stub only enables tracing when it continues or steps
1103 the program, and stops tracing when the program stops; so it
1104 actually works for GDB to read the buffer counter out of memory and
1105 then read each trace word. The counter records where the tracing
1106 stops, but there is no record of where it started, so we remember
1107 the PC when we resumed and then search backwards in the trace
1108 buffer for a word that includes that address. This is not perfect,
1109 because you will miss trace data if the resumption PC is the target
1110 of a branch. (The value of the buffer counter is semi-random, any
1111 trace data from a previous program stop is gone.) */
1113 /* The address of the last word recorded in the trace buffer. */
1115 #define DBBC_ADDR (0xd80000)
1117 /* The base of the trace buffer, at least for the "Board_0". */
1119 #define TRACE_BUFFER_BASE (0xf40000)
1121 static void trace_command (char *, int);
1123 static void untrace_command (char *, int);
1125 static void trace_info (char *, int);
1127 static void tdisassemble_command (char *, int);
1129 static void display_trace (int, int);
1131 /* True when instruction traces are being collected. */
1135 /* Remembered PC. */
1137 static CORE_ADDR last_pc
;
1139 /* True when trace output should be displayed whenever program stops. */
1141 static int trace_display
;
1143 /* True when trace listing should include source lines. */
1145 static int default_trace_show_source
= 1;
1156 trace_command (char *args
, int from_tty
)
1158 /* Clear the host-side trace buffer, allocating space if needed. */
1159 trace_data
.size
= 0;
1160 if (trace_data
.counts
== NULL
)
1161 trace_data
.counts
= XCALLOC (65536, short);
1162 if (trace_data
.addrs
== NULL
)
1163 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1167 printf_filtered ("Tracing is now on.\n");
1171 untrace_command (char *args
, int from_tty
)
1175 printf_filtered ("Tracing is now off.\n");
1179 trace_info (char *args
, int from_tty
)
1183 if (trace_data
.size
)
1185 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1187 for (i
= 0; i
< trace_data
.size
; ++i
)
1189 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1191 trace_data
.counts
[i
],
1192 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1193 paddr_nz (trace_data
.addrs
[i
]));
1197 printf_filtered ("No entries in trace buffer.\n");
1199 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1203 d10v_eva_prepare_to_trace (void)
1208 last_pc
= read_register (PC_REGNUM
);
1211 /* Collect trace data from the target board and format it into a form
1212 more useful for display. */
1215 d10v_eva_get_trace_data (void)
1217 int count
, i
, j
, oldsize
;
1218 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1219 unsigned int last_trace
, trace_word
, next_word
;
1220 unsigned int *tmpspace
;
1225 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1227 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1229 /* Collect buffer contents from the target, stopping when we reach
1230 the word recorded when execution resumed. */
1233 while (last_trace
> 0)
1237 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1238 trace_addr
= trace_word
& 0xffff;
1240 /* Ignore an apparently nonsensical entry. */
1241 if (trace_addr
== 0xffd5)
1243 tmpspace
[count
++] = trace_word
;
1244 if (trace_addr
== last_pc
)
1250 /* Move the data to the host-side trace buffer, adjusting counts to
1251 include the last instruction executed and transforming the address
1252 into something that GDB likes. */
1254 for (i
= 0; i
< count
; ++i
)
1256 trace_word
= tmpspace
[i
];
1257 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1258 trace_addr
= trace_word
& 0xffff;
1259 next_cnt
= (next_word
>> 24) & 0xff;
1260 j
= trace_data
.size
+ count
- i
- 1;
1261 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1262 trace_data
.counts
[j
] = next_cnt
+ 1;
1265 oldsize
= trace_data
.size
;
1266 trace_data
.size
+= count
;
1271 display_trace (oldsize
, trace_data
.size
);
1275 tdisassemble_command (char *arg
, int from_tty
)
1278 CORE_ADDR low
, high
;
1283 high
= trace_data
.size
;
1287 char *space_index
= strchr (arg
, ' ');
1288 if (space_index
== NULL
)
1290 low
= parse_and_eval_address (arg
);
1295 /* Two arguments. */
1296 *space_index
= '\0';
1297 low
= parse_and_eval_address (arg
);
1298 high
= parse_and_eval_address (space_index
+ 1);
1304 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1306 display_trace (low
, high
);
1308 printf_filtered ("End of trace dump.\n");
1309 gdb_flush (gdb_stdout
);
1313 display_trace (int low
, int high
)
1315 int i
, count
, trace_show_source
, first
, suppress
;
1316 CORE_ADDR next_address
;
1318 trace_show_source
= default_trace_show_source
;
1319 if (!have_full_symbols () && !have_partial_symbols ())
1321 trace_show_source
= 0;
1322 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1323 printf_filtered ("Trace will not display any source.\n");
1328 for (i
= low
; i
< high
; ++i
)
1330 next_address
= trace_data
.addrs
[i
];
1331 count
= trace_data
.counts
[i
];
1335 if (trace_show_source
)
1337 struct symtab_and_line sal
, sal_prev
;
1339 sal_prev
= find_pc_line (next_address
- 4, 0);
1340 sal
= find_pc_line (next_address
, 0);
1344 if (first
|| sal
.line
!= sal_prev
.line
)
1345 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1351 /* FIXME-32x64--assumes sal.pc fits in long. */
1352 printf_filtered ("No source file for address %s.\n",
1353 local_hex_string ((unsigned long) sal
.pc
));
1358 print_address (next_address
, gdb_stdout
);
1359 printf_filtered (":");
1360 printf_filtered ("\t");
1362 next_address
+= TARGET_PRINT_INSN (next_address
,
1363 &deprecated_tm_print_insn_info
);
1364 printf_filtered ("\n");
1365 gdb_flush (gdb_stdout
);
1371 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1374 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1375 return d10v_make_iaddr (pc
);
1378 /* Given a GDB frame, determine the address of the calling function's
1379 frame. This will be used to create a new GDB frame struct. */
1382 d10v_frame_this_id (struct frame_info
*next_frame
,
1383 void **this_prologue_cache
,
1384 struct frame_id
*this_id
)
1386 struct d10v_unwind_cache
*info
1387 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1392 /* The FUNC is easy. */
1393 func
= frame_func_unwind (next_frame
);
1395 /* This is meant to halt the backtrace at "_start". Make sure we
1396 don't halt it at a generic dummy frame. */
1397 if (func
<= IMEM_START
|| inside_entry_file (func
))
1400 /* Hopefully the prologue analysis either correctly determined the
1401 frame's base (which is the SP from the previous frame), or set
1402 that base to "NULL". */
1403 base
= info
->prev_sp
;
1404 if (base
== STACK_START
|| base
== 0)
1407 id
= frame_id_build (base
, func
);
1409 /* Check that we're not going round in circles with the same frame
1410 ID (but avoid applying the test to sentinel frames which do go
1411 round in circles). Can't use frame_id_eq() as that doesn't yet
1412 compare the frame's PC value. */
1413 if (frame_relative_level (next_frame
) >= 0
1414 && get_frame_type (next_frame
) != DUMMY_FRAME
1415 && frame_id_eq (get_frame_id (next_frame
), id
))
1422 saved_regs_unwinder (struct frame_info
*next_frame
,
1423 CORE_ADDR
*this_saved_regs
,
1424 int regnum
, int *optimizedp
,
1425 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1426 int *realnump
, void *bufferp
)
1428 if (this_saved_regs
[regnum
] != 0)
1430 if (regnum
== D10V_SP_REGNUM
)
1432 /* SP register treated specially. */
1437 if (bufferp
!= NULL
)
1438 store_unsigned_integer (bufferp
,
1439 register_size (current_gdbarch
, regnum
),
1440 this_saved_regs
[regnum
]);
1444 /* Any other register is saved in memory, fetch it but cache
1445 a local copy of its value. */
1447 *lvalp
= lval_memory
;
1448 *addrp
= this_saved_regs
[regnum
];
1450 if (bufferp
!= NULL
)
1452 /* Read the value in from memory. */
1453 read_memory (this_saved_regs
[regnum
], bufferp
,
1454 register_size (current_gdbarch
, regnum
));
1460 /* No luck, assume this and the next frame have the same register
1461 value. If a value is needed, pass the request on down the chain;
1462 otherwise just return an indication that the value is in the same
1463 register as the next frame. */
1464 frame_register_unwind (next_frame
, regnum
, optimizedp
, lvalp
, addrp
,
1470 d10v_frame_prev_register (struct frame_info
*next_frame
,
1471 void **this_prologue_cache
,
1472 int regnum
, int *optimizedp
,
1473 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1474 int *realnump
, void *bufferp
)
1476 struct d10v_unwind_cache
*info
1477 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1478 if (regnum
== PC_REGNUM
)
1480 /* The call instruction saves the caller's PC in LR. The
1481 function prologue of the callee may then save the LR on the
1482 stack. Find that possibly saved LR value and return it. */
1483 saved_regs_unwinder (next_frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1484 lvalp
, addrp
, realnump
, bufferp
);
1488 saved_regs_unwinder (next_frame
, info
->saved_regs
, regnum
, optimizedp
,
1489 lvalp
, addrp
, realnump
, bufferp
);
1493 static const struct frame_unwind d10v_frame_unwind
= {
1496 d10v_frame_prev_register
1499 const struct frame_unwind
*
1500 d10v_frame_p (CORE_ADDR pc
)
1502 return &d10v_frame_unwind
;
1506 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1508 struct d10v_unwind_cache
*info
1509 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1513 static const struct frame_base d10v_frame_base
= {
1515 d10v_frame_base_address
,
1516 d10v_frame_base_address
,
1517 d10v_frame_base_address
1520 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1521 dummy frame. The frame ID's base needs to match the TOS value
1522 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1525 static struct frame_id
1526 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1529 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &base
);
1530 return frame_id_build (d10v_make_daddr (base
), frame_pc_unwind (next_frame
));
1533 static gdbarch_init_ftype d10v_gdbarch_init
;
1535 static struct gdbarch
*
1536 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1538 struct gdbarch
*gdbarch
;
1540 struct gdbarch_tdep
*tdep
;
1541 gdbarch_register_name_ftype
*d10v_register_name
;
1542 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1544 /* Find a candidate among the list of pre-declared architectures. */
1545 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1547 return arches
->gdbarch
;
1549 /* None found, create a new architecture from the information
1551 tdep
= XMALLOC (struct gdbarch_tdep
);
1552 gdbarch
= gdbarch_alloc (&info
, tdep
);
1554 switch (info
.bfd_arch_info
->mach
)
1556 case bfd_mach_d10v_ts2
:
1558 d10v_register_name
= d10v_ts2_register_name
;
1559 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1560 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1561 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1562 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1563 tdep
->imap_register
= d10v_ts2_imap_register
;
1566 case bfd_mach_d10v_ts3
:
1568 d10v_register_name
= d10v_ts3_register_name
;
1569 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1570 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1571 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1572 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1573 tdep
->imap_register
= d10v_ts3_imap_register
;
1577 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1578 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1579 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1581 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1582 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1583 set_gdbarch_pc_regnum (gdbarch
, 18);
1584 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1585 set_gdbarch_register_size (gdbarch
, 2);
1586 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1587 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1588 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1590 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1591 set_gdbarch_addr_bit (gdbarch
, 32);
1592 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1593 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1594 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1595 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1596 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1597 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1598 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1599 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1600 double'' is 64 bits. */
1601 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1602 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1603 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1604 switch (info
.byte_order
)
1606 case BFD_ENDIAN_BIG
:
1607 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1608 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1609 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1611 case BFD_ENDIAN_LITTLE
:
1612 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1613 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1614 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1617 internal_error (__FILE__
, __LINE__
,
1618 "d10v_gdbarch_init: bad byte order for float format");
1621 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1622 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1623 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1624 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1625 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1627 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1628 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1629 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1630 set_gdbarch_function_start_offset (gdbarch
, 0);
1631 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1633 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1635 set_gdbarch_frame_args_skip (gdbarch
, 0);
1636 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1638 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1639 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1641 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1643 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1645 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1646 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1648 /* Methods for saving / extracting a dummy frame's ID. */
1649 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1650 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1652 /* Return the unwound PC value. */
1653 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1655 set_gdbarch_print_insn (gdbarch
, print_insn_d10v
);
1661 _initialize_d10v_tdep (void)
1663 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1665 target_resume_hook
= d10v_eva_prepare_to_trace
;
1666 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1668 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1671 add_com ("itrace", class_support
, trace_command
,
1672 "Enable tracing of instruction execution.");
1674 add_com ("iuntrace", class_support
, untrace_command
,
1675 "Disable tracing of instruction execution.");
1677 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1678 "Disassemble the trace buffer.\n\
1679 Two optional arguments specify a range of trace buffer entries\n\
1680 as reported by info trace (NOT addresses!).");
1682 add_info ("itrace", trace_info
,
1683 "Display info about the trace data buffer.");
1685 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1686 "Set automatic display of trace.\n",
1687 "Show automatic display of trace.\n",
1688 NULL
, NULL
, &setlist
, &showlist
);
1689 add_setshow_boolean_cmd ("itracesource", no_class
,
1690 &default_trace_show_source
,
1691 "Set display of source code with trace.\n",
1692 "Show display of source code with trace.\n",
1693 NULL
, NULL
, &setlist
, &showlist
);