1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
31 #include "gdb_string.h"
38 #include "arch-utils.h"
41 #include "floatformat.h"
42 #include "gdb/sim-d10v.h"
43 #include "sim-regno.h"
45 #include "gdb_assert.h"
47 struct frame_extra_info
58 unsigned long (*dmap_register
) (int nr
);
59 unsigned long (*imap_register
) (int nr
);
62 /* These are the addresses the D10V-EVA board maps data and
63 instruction memory to. */
66 DMEM_START
= 0x2000000,
67 IMEM_START
= 0x1000000,
68 STACK_START
= 0x200bffe
71 /* d10v register names. */
86 /* d10v calling convention. */
87 ARG1_REGNUM
= R0_REGNUM
,
88 ARGN_REGNUM
= R3_REGNUM
,
89 RET1_REGNUM
= R0_REGNUM
,
92 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
93 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
97 extern void _initialize_d10v_tdep (void);
99 static CORE_ADDR
d10v_read_sp (void);
101 static CORE_ADDR
d10v_read_fp (void);
103 static void d10v_eva_prepare_to_trace (void);
105 static void d10v_eva_get_trace_data (void);
107 static int prologue_find_regs (unsigned short op
, struct frame_info
*fi
,
110 static void d10v_frame_init_saved_regs (struct frame_info
*);
112 static void do_d10v_pop_frame (struct frame_info
*fi
);
115 d10v_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*frame
)
117 return (get_frame_pc (frame
) > IMEM_START
);
121 d10v_stack_align (CORE_ADDR len
)
123 return (len
+ 1) & ~1;
126 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
127 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
128 and TYPE is the type (which is known to be struct, union or array).
130 The d10v returns anything less than 8 bytes in size in
134 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
138 /* The d10v only passes a struct in a register when that structure
139 has an alignment that matches the size of a register. */
140 /* If the structure doesn't fit in 4 registers, put it on the
142 if (TYPE_LENGTH (type
) > 8)
144 /* If the struct contains only one field, don't put it on the stack
145 - gcc can fit it in one or more registers. */
146 if (TYPE_NFIELDS (type
) == 1)
148 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
149 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
151 /* If the alignment changes, just assume it goes on the
153 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
156 /* If the alignment is suitable for the d10v's 16 bit registers,
157 don't put it on the stack. */
158 if (alignment
== 2 || alignment
== 4)
164 static const unsigned char *
165 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
167 static unsigned char breakpoint
[] =
168 {0x2f, 0x90, 0x5e, 0x00};
169 *lenptr
= sizeof (breakpoint
);
173 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
174 when the reg_nr isn't valid. */
178 TS2_IMAP0_REGNUM
= 32,
179 TS2_DMAP_REGNUM
= 34,
180 TS2_NR_DMAP_REGS
= 1,
185 d10v_ts2_register_name (int reg_nr
)
187 static char *register_names
[] =
189 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
190 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
191 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
192 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
193 "imap0", "imap1", "dmap", "a0", "a1"
197 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
199 return register_names
[reg_nr
];
204 TS3_IMAP0_REGNUM
= 36,
205 TS3_DMAP0_REGNUM
= 38,
206 TS3_NR_DMAP_REGS
= 4,
211 d10v_ts3_register_name (int reg_nr
)
213 static char *register_names
[] =
215 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
216 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
217 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
218 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
222 "dmap0", "dmap1", "dmap2", "dmap3"
226 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
228 return register_names
[reg_nr
];
231 /* Access the DMAP/IMAP registers in a target independent way.
233 Divide the D10V's 64k data space into four 16k segments:
234 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
237 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
238 0x7fff) always map to the on-chip data RAM, and the fourth always
239 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
240 unified memory or instruction memory, under the control of the
241 single DMAP register.
243 On the TS3, there are four DMAP registers, each of which controls
244 one of the segments. */
247 d10v_ts2_dmap_register (int reg_nr
)
255 return read_register (TS2_DMAP_REGNUM
);
262 d10v_ts3_dmap_register (int reg_nr
)
264 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
268 d10v_dmap_register (int reg_nr
)
270 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
274 d10v_ts2_imap_register (int reg_nr
)
276 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
280 d10v_ts3_imap_register (int reg_nr
)
282 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
286 d10v_imap_register (int reg_nr
)
288 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
291 /* MAP GDB's internal register numbering (determined by the layout fo
292 the REGISTER_BYTE array) onto the simulator's register
296 d10v_ts2_register_sim_regno (int nr
)
298 if (legacy_register_sim_regno (nr
) < 0)
299 return legacy_register_sim_regno (nr
);
300 if (nr
>= TS2_IMAP0_REGNUM
301 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
302 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
303 if (nr
== TS2_DMAP_REGNUM
)
304 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
305 if (nr
>= TS2_A0_REGNUM
306 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
307 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
312 d10v_ts3_register_sim_regno (int nr
)
314 if (legacy_register_sim_regno (nr
) < 0)
315 return legacy_register_sim_regno (nr
);
316 if (nr
>= TS3_IMAP0_REGNUM
317 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
318 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
319 if (nr
>= TS3_DMAP0_REGNUM
320 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
321 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
322 if (nr
>= TS3_A0_REGNUM
323 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
324 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
328 /* Index within `registers' of the first byte of the space for
332 d10v_register_byte (int reg_nr
)
334 if (reg_nr
< A0_REGNUM
)
336 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
337 return (A0_REGNUM
* 2
338 + (reg_nr
- A0_REGNUM
) * 8);
340 return (A0_REGNUM
* 2
342 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
345 /* Number of bytes of storage in the actual machine representation for
349 d10v_register_raw_size (int reg_nr
)
351 if (reg_nr
< A0_REGNUM
)
353 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
359 /* Return the GDB type object for the "standard" data type
360 of data in register N. */
363 d10v_register_virtual_type (int reg_nr
)
365 if (reg_nr
== PC_REGNUM
)
366 return builtin_type_void_func_ptr
;
367 if (reg_nr
== _SP_REGNUM
|| reg_nr
== _FP_REGNUM
)
368 return builtin_type_void_data_ptr
;
369 else if (reg_nr
>= A0_REGNUM
370 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
371 return builtin_type_int64
;
373 return builtin_type_int16
;
377 d10v_daddr_p (CORE_ADDR x
)
379 return (((x
) & 0x3000000) == DMEM_START
);
383 d10v_iaddr_p (CORE_ADDR x
)
385 return (((x
) & 0x3000000) == IMEM_START
);
389 d10v_make_daddr (CORE_ADDR x
)
391 return ((x
) | DMEM_START
);
395 d10v_make_iaddr (CORE_ADDR x
)
397 if (d10v_iaddr_p (x
))
398 return x
; /* Idempotency -- x is already in the IMEM space. */
400 return (((x
) << 2) | IMEM_START
);
404 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
406 return (((x
) >> 2) & 0xffff);
410 d10v_convert_daddr_to_raw (CORE_ADDR x
)
412 return ((x
) & 0xffff);
416 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
418 /* Is it a code address? */
419 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
420 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
422 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
423 d10v_convert_iaddr_to_raw (addr
));
427 /* Strip off any upper segment bits. */
428 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
429 d10v_convert_daddr_to_raw (addr
));
434 d10v_pointer_to_address (struct type
*type
, const void *buf
)
436 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
438 /* Is it a code address? */
439 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
440 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
441 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
442 return d10v_make_iaddr (addr
);
444 return d10v_make_daddr (addr
);
447 /* Don't do anything if we have an integer, this way users can type 'x
448 <addr>' w/o having gdb outsmart them. The internal gdb conversions
449 to the correct space are taken care of in the pointer_to_address
450 function. If we don't do this, 'x $fp' wouldn't work. */
452 d10v_integer_to_address (struct type
*type
, void *buf
)
455 val
= unpack_long (type
, buf
);
459 /* Store the address of the place in which to copy the structure the
460 subroutine will return. This is called from call_function.
462 We store structs through a pointer passed in the first Argument
466 d10v_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
468 write_register (ARG1_REGNUM
, (addr
));
471 /* Write into appropriate registers a function return value
472 of type TYPE, given in virtual format.
474 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
477 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
480 /* Only char return values need to be shifted right within the first
482 if (TYPE_LENGTH (type
) == 1
483 && TYPE_CODE (type
) == TYPE_CODE_INT
)
486 tmp
[1] = *(bfd_byte
*)valbuf
;
487 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
492 /* A structure is never more than 8 bytes long. See
493 use_struct_convention(). */
494 gdb_assert (TYPE_LENGTH (type
) <= 8);
495 /* Write out most registers, stop loop before trying to write
496 out any dangling byte at the end of the buffer. */
497 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
499 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
500 (bfd_byte
*) valbuf
+ reg
* 2);
502 /* Write out any dangling byte at the end of the buffer. */
503 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
504 regcache_cooked_write_part (regcache
, reg
, 0, 1,
505 (bfd_byte
*) valbuf
+ reg
* 2);
509 /* Extract from an array REGBUF containing the (raw) register state
510 the address in which a function should return its structure value,
511 as a CORE_ADDR (or an expression that can be used as one). */
514 d10v_extract_struct_value_address (struct regcache
*regcache
)
517 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
518 return (addr
| DMEM_START
);
522 d10v_frame_saved_pc (struct frame_info
*frame
)
524 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
525 get_frame_base (frame
),
526 get_frame_base (frame
)))
527 return d10v_make_iaddr (deprecated_read_register_dummy (get_frame_pc (frame
),
528 get_frame_base (frame
),
531 return (get_frame_extra_info (frame
)->return_pc
);
534 /* Immediately after a function call, return the saved pc. We can't
535 use frame->return_pc beause that is determined by reading R13 off
536 the stack and that may not be written yet. */
539 d10v_saved_pc_after_call (struct frame_info
*frame
)
541 return ((read_register (LR_REGNUM
) << 2)
545 /* Discard from the stack the innermost frame, restoring all saved
549 d10v_pop_frame (void)
551 generic_pop_current_frame (do_d10v_pop_frame
);
555 do_d10v_pop_frame (struct frame_info
*fi
)
561 fp
= get_frame_base (fi
);
562 /* fill out fsr with the address of where each */
563 /* register was stored in the frame */
564 d10v_frame_init_saved_regs (fi
);
566 /* now update the current registers with the old values */
567 for (regnum
= A0_REGNUM
; regnum
< A0_REGNUM
+ NR_A_REGS
; regnum
++)
569 if (get_frame_saved_regs (fi
)[regnum
])
571 read_memory (get_frame_saved_regs (fi
)[regnum
], raw_buffer
, REGISTER_RAW_SIZE (regnum
));
572 deprecated_write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
573 REGISTER_RAW_SIZE (regnum
));
576 for (regnum
= 0; regnum
< SP_REGNUM
; regnum
++)
578 if (get_frame_saved_regs (fi
)[regnum
])
580 write_register (regnum
, read_memory_unsigned_integer (get_frame_saved_regs (fi
)[regnum
], REGISTER_RAW_SIZE (regnum
)));
583 if (get_frame_saved_regs (fi
)[PSW_REGNUM
])
585 write_register (PSW_REGNUM
, read_memory_unsigned_integer (get_frame_saved_regs (fi
)[PSW_REGNUM
], REGISTER_RAW_SIZE (PSW_REGNUM
)));
588 write_register (PC_REGNUM
, read_register (LR_REGNUM
));
589 write_register (SP_REGNUM
, fp
+ get_frame_extra_info (fi
)->size
);
590 target_store_registers (-1);
591 flush_cached_frames ();
595 check_prologue (unsigned short op
)
598 if ((op
& 0x7E1F) == 0x6C1F)
602 if ((op
& 0x7E3F) == 0x6E1F)
606 if ((op
& 0x7FE1) == 0x01E1)
618 if ((op
& 0x7E1F) == 0x681E)
622 if ((op
& 0x7E3F) == 0x3A1E)
629 d10v_skip_prologue (CORE_ADDR pc
)
632 unsigned short op1
, op2
;
633 CORE_ADDR func_addr
, func_end
;
634 struct symtab_and_line sal
;
636 /* If we have line debugging information, then the end of the */
637 /* prologue should the first assembly instruction of the first source line */
638 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
640 sal
= find_pc_line (func_addr
, 0);
641 if (sal
.end
&& sal
.end
< func_end
)
645 if (target_read_memory (pc
, (char *) &op
, 4))
646 return pc
; /* Can't access it -- assume no prologue. */
650 op
= (unsigned long) read_memory_integer (pc
, 4);
651 if ((op
& 0xC0000000) == 0xC0000000)
653 /* long instruction */
654 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
655 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
656 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
661 /* short instructions */
662 if ((op
& 0xC0000000) == 0x80000000)
664 op2
= (op
& 0x3FFF8000) >> 15;
669 op1
= (op
& 0x3FFF8000) >> 15;
672 if (check_prologue (op1
))
674 if (!check_prologue (op2
))
676 /* if the previous opcode was really part of the prologue */
677 /* and not just a NOP, then we want to break after both instructions */
691 /* Given a GDB frame, determine the address of the calling function's
692 frame. This will be used to create a new GDB frame struct, and
693 then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be
694 called for the new frame. */
697 d10v_frame_chain (struct frame_info
*fi
)
701 /* A generic call dummy's frame is the same as caller's. */
702 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
703 get_frame_base (fi
)))
704 return get_frame_base (fi
);
706 d10v_frame_init_saved_regs (fi
);
709 if (get_frame_extra_info (fi
)->return_pc
== IMEM_START
710 || inside_entry_file (get_frame_extra_info (fi
)->return_pc
))
712 /* This is meant to halt the backtrace at "_start".
713 Make sure we don't halt it at a generic dummy frame. */
714 if (!DEPRECATED_PC_IN_CALL_DUMMY (get_frame_extra_info (fi
)->return_pc
, 0, 0))
715 return (CORE_ADDR
) 0;
718 if (!get_frame_saved_regs (fi
)[FP_REGNUM
])
720 if (!get_frame_saved_regs (fi
)[SP_REGNUM
]
721 || get_frame_saved_regs (fi
)[SP_REGNUM
] == STACK_START
)
722 return (CORE_ADDR
) 0;
724 return get_frame_saved_regs (fi
)[SP_REGNUM
];
727 addr
= read_memory_unsigned_integer (get_frame_saved_regs (fi
)[FP_REGNUM
],
728 REGISTER_RAW_SIZE (FP_REGNUM
));
730 return (CORE_ADDR
) 0;
732 return d10v_make_daddr (addr
);
735 static int next_addr
, uses_frame
;
738 prologue_find_regs (unsigned short op
, struct frame_info
*fi
, CORE_ADDR addr
)
743 if ((op
& 0x7E1F) == 0x6C1F)
745 n
= (op
& 0x1E0) >> 5;
747 get_frame_saved_regs (fi
)[n
] = next_addr
;
752 else if ((op
& 0x7E3F) == 0x6E1F)
754 n
= (op
& 0x1E0) >> 5;
756 get_frame_saved_regs (fi
)[n
] = next_addr
;
757 get_frame_saved_regs (fi
)[n
+ 1] = next_addr
+ 2;
762 if ((op
& 0x7FE1) == 0x01E1)
764 n
= (op
& 0x1E) >> 1;
783 if ((op
& 0x7E1F) == 0x681E)
785 n
= (op
& 0x1E0) >> 5;
786 get_frame_saved_regs (fi
)[n
] = next_addr
;
791 if ((op
& 0x7E3F) == 0x3A1E)
793 n
= (op
& 0x1E0) >> 5;
794 get_frame_saved_regs (fi
)[n
] = next_addr
;
795 get_frame_saved_regs (fi
)[n
+ 1] = next_addr
+ 2;
802 /* Put here the code to store, into fi->saved_regs, the addresses of
803 the saved registers of frame described by FRAME_INFO. This
804 includes special registers such as pc and fp saved in special ways
805 in the stack frame. sp is even more special: the address we return
806 for it IS the sp for the next frame. */
809 d10v_frame_init_saved_regs (struct frame_info
*fi
)
813 unsigned short op1
, op2
;
816 fp
= get_frame_base (fi
);
817 memset (get_frame_saved_regs (fi
), 0, SIZEOF_FRAME_SAVED_REGS
);
820 pc
= get_pc_function_start (get_frame_pc (fi
));
825 op
= (unsigned long) read_memory_integer (pc
, 4);
826 if ((op
& 0xC0000000) == 0xC0000000)
828 /* long instruction */
829 if ((op
& 0x3FFF0000) == 0x01FF0000)
832 short n
= op
& 0xFFFF;
835 else if ((op
& 0x3F0F0000) == 0x340F0000)
837 /* st rn, @(offset,sp) */
838 short offset
= op
& 0xFFFF;
839 short n
= (op
>> 20) & 0xF;
840 get_frame_saved_regs (fi
)[n
] = next_addr
+ offset
;
842 else if ((op
& 0x3F1F0000) == 0x350F0000)
844 /* st2w rn, @(offset,sp) */
845 short offset
= op
& 0xFFFF;
846 short n
= (op
>> 20) & 0xF;
847 get_frame_saved_regs (fi
)[n
] = next_addr
+ offset
;
848 get_frame_saved_regs (fi
)[n
+ 1] = next_addr
+ offset
+ 2;
855 /* short instructions */
856 if ((op
& 0xC0000000) == 0x80000000)
858 op2
= (op
& 0x3FFF8000) >> 15;
863 op1
= (op
& 0x3FFF8000) >> 15;
866 if (!prologue_find_regs (op1
, fi
, pc
)
867 || !prologue_find_regs (op2
, fi
, pc
))
873 get_frame_extra_info (fi
)->size
= -next_addr
;
876 fp
= d10v_read_sp ();
878 for (i
= 0; i
< NUM_REGS
- 1; i
++)
879 if (get_frame_saved_regs (fi
)[i
])
881 get_frame_saved_regs (fi
)[i
] = fp
- (next_addr
- get_frame_saved_regs (fi
)[i
]);
884 if (get_frame_saved_regs (fi
)[LR_REGNUM
])
887 = read_memory_unsigned_integer (get_frame_saved_regs (fi
)[LR_REGNUM
],
888 REGISTER_RAW_SIZE (LR_REGNUM
));
889 get_frame_extra_info (fi
)->return_pc
= d10v_make_iaddr (return_pc
);
893 get_frame_extra_info (fi
)->return_pc
= d10v_make_iaddr (read_register (LR_REGNUM
));
896 /* The SP is not normally (ever?) saved, but check anyway */
897 if (!get_frame_saved_regs (fi
)[SP_REGNUM
])
899 /* if the FP was saved, that means the current FP is valid, */
900 /* otherwise, it isn't being used, so we use the SP instead */
902 get_frame_saved_regs (fi
)[SP_REGNUM
]
903 = d10v_read_fp () + get_frame_extra_info (fi
)->size
;
906 get_frame_saved_regs (fi
)[SP_REGNUM
] = fp
+ get_frame_extra_info (fi
)->size
;
907 get_frame_extra_info (fi
)->frameless
= 1;
908 get_frame_saved_regs (fi
)[FP_REGNUM
] = 0;
914 d10v_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
916 frame_extra_info_zalloc (fi
, sizeof (struct frame_extra_info
));
917 frame_saved_regs_zalloc (fi
);
919 get_frame_extra_info (fi
)->frameless
= 0;
920 get_frame_extra_info (fi
)->size
= 0;
921 get_frame_extra_info (fi
)->return_pc
= 0;
923 /* If get_frame_pc (fi) is zero, but this is not the outermost frame,
924 then let's snatch the return_pc from the callee, so that
925 DEPRECATED_PC_IN_CALL_DUMMY will work. */
926 if (get_frame_pc (fi
) == 0
927 && frame_relative_level (fi
) != 0 && get_next_frame (fi
) != NULL
)
928 deprecated_update_frame_pc_hack (fi
, d10v_frame_saved_pc (get_next_frame (fi
)));
930 /* The call dummy doesn't save any registers on the stack, so we can
932 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
933 get_frame_base (fi
)))
939 d10v_frame_init_saved_regs (fi
);
944 show_regs (char *args
, int from_tty
)
947 printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
948 (long) read_register (PC_REGNUM
),
949 (long) d10v_make_iaddr (read_register (PC_REGNUM
)),
950 (long) read_register (PSW_REGNUM
),
951 (long) read_register (24),
952 (long) read_register (25),
953 (long) read_register (23));
954 printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
955 (long) read_register (0),
956 (long) read_register (1),
957 (long) read_register (2),
958 (long) read_register (3),
959 (long) read_register (4),
960 (long) read_register (5),
961 (long) read_register (6),
962 (long) read_register (7));
963 printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n",
964 (long) read_register (8),
965 (long) read_register (9),
966 (long) read_register (10),
967 (long) read_register (11),
968 (long) read_register (12),
969 (long) read_register (13),
970 (long) read_register (14),
971 (long) read_register (15));
972 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
975 printf_filtered (" ");
976 printf_filtered ("IMAP%d %04lx", a
, d10v_imap_register (a
));
978 if (NR_DMAP_REGS
== 1)
979 printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2));
982 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
984 printf_filtered (" DMAP%d %04lx", a
, d10v_dmap_register (a
));
986 printf_filtered ("\n");
988 printf_filtered ("A0-A%d", NR_A_REGS
- 1);
989 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
991 char num
[MAX_REGISTER_RAW_SIZE
];
993 printf_filtered (" ");
994 deprecated_read_register_gen (a
, (char *) &num
);
995 for (i
= 0; i
< MAX_REGISTER_RAW_SIZE
; i
++)
997 printf_filtered ("%02x", (num
[i
] & 0xff));
1000 printf_filtered ("\n");
1004 d10v_read_pc (ptid_t ptid
)
1010 save_ptid
= inferior_ptid
;
1011 inferior_ptid
= ptid
;
1012 pc
= (int) read_register (PC_REGNUM
);
1013 inferior_ptid
= save_ptid
;
1014 retval
= d10v_make_iaddr (pc
);
1019 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
1023 save_ptid
= inferior_ptid
;
1024 inferior_ptid
= ptid
;
1025 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
1026 inferior_ptid
= save_ptid
;
1032 return (d10v_make_daddr (read_register (SP_REGNUM
)));
1036 d10v_write_sp (CORE_ADDR val
)
1038 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
1044 return (d10v_make_daddr (read_register (FP_REGNUM
)));
1047 /* Function: push_return_address (pc)
1048 Set up the return address for the inferior function call.
1049 Needed for targets where we don't actually execute a JSR/BSR instruction */
1052 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1054 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
1059 /* When arguments must be pushed onto the stack, they go on in reverse
1060 order. The below implements a FILO (stack) to do this. */
1065 struct stack_item
*prev
;
1069 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
1070 void *contents
, int len
);
1071 static struct stack_item
*
1072 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1074 struct stack_item
*si
;
1075 si
= xmalloc (sizeof (struct stack_item
));
1076 si
->data
= xmalloc (len
);
1079 memcpy (si
->data
, contents
, len
);
1083 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1084 static struct stack_item
*
1085 pop_stack_item (struct stack_item
*si
)
1087 struct stack_item
*dead
= si
;
1096 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1097 int struct_return
, CORE_ADDR struct_addr
)
1100 int regnum
= ARG1_REGNUM
;
1101 struct stack_item
*si
= NULL
;
1104 /* If struct_return is true, then the struct return address will
1105 consume one argument-passing register. No need to actually
1106 write the value to the register -- that's done by
1107 d10v_store_struct_return(). */
1112 /* Fill in registers and arg lists */
1113 for (i
= 0; i
< nargs
; i
++)
1115 struct value
*arg
= args
[i
];
1116 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1117 char *contents
= VALUE_CONTENTS (arg
);
1118 int len
= TYPE_LENGTH (type
);
1119 int aligned_regnum
= (regnum
+ 1) & ~1;
1121 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1122 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1123 /* fits in a single register, do not align */
1125 val
= extract_unsigned_integer (contents
, len
);
1126 write_register (regnum
++, val
);
1128 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1129 /* value fits in remaining registers, store keeping left
1133 regnum
= aligned_regnum
;
1134 for (b
= 0; b
< (len
& ~1); b
+= 2)
1136 val
= extract_unsigned_integer (&contents
[b
], 2);
1137 write_register (regnum
++, val
);
1141 val
= extract_unsigned_integer (&contents
[b
], 1);
1142 write_register (regnum
++, (val
<< 8));
1147 /* arg will go onto stack */
1148 regnum
= ARGN_REGNUM
+ 1;
1149 si
= push_stack_item (si
, contents
, len
);
1155 sp
= (sp
- si
->len
) & ~1;
1156 write_memory (sp
, si
->data
, si
->len
);
1157 si
= pop_stack_item (si
);
1164 /* Given a return value in `regbuf' with a type `valtype',
1165 extract and copy its value into `valbuf'. */
1168 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1173 printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type
),
1174 TYPE_LENGTH (type
), RET1_REGNUM
- R0_REGNUM
,
1175 (int) extract_unsigned_integer (regbuf
+ REGISTER_BYTE(RET1_REGNUM
),
1176 REGISTER_RAW_SIZE (RET1_REGNUM
)));
1178 if (TYPE_LENGTH (type
) == 1)
1181 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1182 store_unsigned_integer (valbuf
, 1, c
);
1186 /* For return values of odd size, the first byte is in the
1187 least significant part of the first register. The
1188 remaining bytes in remaining registers. Interestingly, when
1189 such values are passed in, the last byte is in the most
1190 significant byte of that same register - wierd. */
1191 int reg
= RET1_REGNUM
;
1193 if (TYPE_LENGTH (type
) & 1)
1195 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1196 (bfd_byte
*)valbuf
+ off
);
1200 /* Transfer the remaining registers. */
1201 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1203 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1204 (bfd_byte
*) valbuf
+ off
);
1209 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1210 understands. Returns number of bytes that can be transfered
1211 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1212 (segmentation fault). Since the simulator knows all about how the
1213 VM system works, we just call that to do the translation. */
1216 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1217 CORE_ADDR
*targ_addr
, int *targ_len
)
1221 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1224 d10v_imap_register
);
1225 *targ_addr
= out_addr
;
1226 *targ_len
= out_len
;
1230 /* The following code implements access to, and display of, the D10V's
1231 instruction trace buffer. The buffer consists of 64K or more
1232 4-byte words of data, of which each words includes an 8-bit count,
1233 an 8-bit segment number, and a 16-bit instruction address.
1235 In theory, the trace buffer is continuously capturing instruction
1236 data that the CPU presents on its "debug bus", but in practice, the
1237 ROMified GDB stub only enables tracing when it continues or steps
1238 the program, and stops tracing when the program stops; so it
1239 actually works for GDB to read the buffer counter out of memory and
1240 then read each trace word. The counter records where the tracing
1241 stops, but there is no record of where it started, so we remember
1242 the PC when we resumed and then search backwards in the trace
1243 buffer for a word that includes that address. This is not perfect,
1244 because you will miss trace data if the resumption PC is the target
1245 of a branch. (The value of the buffer counter is semi-random, any
1246 trace data from a previous program stop is gone.) */
1248 /* The address of the last word recorded in the trace buffer. */
1250 #define DBBC_ADDR (0xd80000)
1252 /* The base of the trace buffer, at least for the "Board_0". */
1254 #define TRACE_BUFFER_BASE (0xf40000)
1256 static void trace_command (char *, int);
1258 static void untrace_command (char *, int);
1260 static void trace_info (char *, int);
1262 static void tdisassemble_command (char *, int);
1264 static void display_trace (int, int);
1266 /* True when instruction traces are being collected. */
1270 /* Remembered PC. */
1272 static CORE_ADDR last_pc
;
1274 /* True when trace output should be displayed whenever program stops. */
1276 static int trace_display
;
1278 /* True when trace listing should include source lines. */
1280 static int default_trace_show_source
= 1;
1291 trace_command (char *args
, int from_tty
)
1293 /* Clear the host-side trace buffer, allocating space if needed. */
1294 trace_data
.size
= 0;
1295 if (trace_data
.counts
== NULL
)
1296 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1297 if (trace_data
.addrs
== NULL
)
1298 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1302 printf_filtered ("Tracing is now on.\n");
1306 untrace_command (char *args
, int from_tty
)
1310 printf_filtered ("Tracing is now off.\n");
1314 trace_info (char *args
, int from_tty
)
1318 if (trace_data
.size
)
1320 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1322 for (i
= 0; i
< trace_data
.size
; ++i
)
1324 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1326 trace_data
.counts
[i
],
1327 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1328 paddr_nz (trace_data
.addrs
[i
]));
1332 printf_filtered ("No entries in trace buffer.\n");
1334 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1337 /* Print the instruction at address MEMADDR in debugged memory,
1338 on STREAM. Returns length of the instruction, in bytes. */
1341 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1343 /* If there's no disassembler, something is very wrong. */
1344 if (tm_print_insn
== NULL
)
1345 internal_error (__FILE__
, __LINE__
,
1346 "print_insn: no disassembler");
1348 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1349 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1351 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1352 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1356 d10v_eva_prepare_to_trace (void)
1361 last_pc
= read_register (PC_REGNUM
);
1364 /* Collect trace data from the target board and format it into a form
1365 more useful for display. */
1368 d10v_eva_get_trace_data (void)
1370 int count
, i
, j
, oldsize
;
1371 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1372 unsigned int last_trace
, trace_word
, next_word
;
1373 unsigned int *tmpspace
;
1378 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1380 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1382 /* Collect buffer contents from the target, stopping when we reach
1383 the word recorded when execution resumed. */
1386 while (last_trace
> 0)
1390 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1391 trace_addr
= trace_word
& 0xffff;
1393 /* Ignore an apparently nonsensical entry. */
1394 if (trace_addr
== 0xffd5)
1396 tmpspace
[count
++] = trace_word
;
1397 if (trace_addr
== last_pc
)
1403 /* Move the data to the host-side trace buffer, adjusting counts to
1404 include the last instruction executed and transforming the address
1405 into something that GDB likes. */
1407 for (i
= 0; i
< count
; ++i
)
1409 trace_word
= tmpspace
[i
];
1410 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1411 trace_addr
= trace_word
& 0xffff;
1412 next_cnt
= (next_word
>> 24) & 0xff;
1413 j
= trace_data
.size
+ count
- i
- 1;
1414 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1415 trace_data
.counts
[j
] = next_cnt
+ 1;
1418 oldsize
= trace_data
.size
;
1419 trace_data
.size
+= count
;
1424 display_trace (oldsize
, trace_data
.size
);
1428 tdisassemble_command (char *arg
, int from_tty
)
1431 CORE_ADDR low
, high
;
1437 high
= trace_data
.size
;
1439 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1441 low
= parse_and_eval_address (arg
);
1446 /* Two arguments. */
1447 *space_index
= '\0';
1448 low
= parse_and_eval_address (arg
);
1449 high
= parse_and_eval_address (space_index
+ 1);
1454 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1456 display_trace (low
, high
);
1458 printf_filtered ("End of trace dump.\n");
1459 gdb_flush (gdb_stdout
);
1463 display_trace (int low
, int high
)
1465 int i
, count
, trace_show_source
, first
, suppress
;
1466 CORE_ADDR next_address
;
1468 trace_show_source
= default_trace_show_source
;
1469 if (!have_full_symbols () && !have_partial_symbols ())
1471 trace_show_source
= 0;
1472 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1473 printf_filtered ("Trace will not display any source.\n");
1478 for (i
= low
; i
< high
; ++i
)
1480 next_address
= trace_data
.addrs
[i
];
1481 count
= trace_data
.counts
[i
];
1485 if (trace_show_source
)
1487 struct symtab_and_line sal
, sal_prev
;
1489 sal_prev
= find_pc_line (next_address
- 4, 0);
1490 sal
= find_pc_line (next_address
, 0);
1494 if (first
|| sal
.line
!= sal_prev
.line
)
1495 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1501 /* FIXME-32x64--assumes sal.pc fits in long. */
1502 printf_filtered ("No source file for address %s.\n",
1503 local_hex_string ((unsigned long) sal
.pc
));
1508 print_address (next_address
, gdb_stdout
);
1509 printf_filtered (":");
1510 printf_filtered ("\t");
1512 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1513 printf_filtered ("\n");
1514 gdb_flush (gdb_stdout
);
1520 static gdbarch_init_ftype d10v_gdbarch_init
;
1522 static struct gdbarch
*
1523 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1525 static LONGEST d10v_call_dummy_words
[] =
1527 struct gdbarch
*gdbarch
;
1529 struct gdbarch_tdep
*tdep
;
1530 gdbarch_register_name_ftype
*d10v_register_name
;
1531 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1533 /* Find a candidate among the list of pre-declared architectures. */
1534 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1536 return arches
->gdbarch
;
1538 /* None found, create a new architecture from the information
1540 tdep
= XMALLOC (struct gdbarch_tdep
);
1541 gdbarch
= gdbarch_alloc (&info
, tdep
);
1543 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
1544 ready to unwind the PC first (see frame.c:get_prev_frame()). */
1545 set_gdbarch_deprecated_init_frame_pc (gdbarch
, init_frame_pc_default
);
1547 switch (info
.bfd_arch_info
->mach
)
1549 case bfd_mach_d10v_ts2
:
1551 d10v_register_name
= d10v_ts2_register_name
;
1552 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1553 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1554 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1555 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1556 tdep
->imap_register
= d10v_ts2_imap_register
;
1559 case bfd_mach_d10v_ts3
:
1561 d10v_register_name
= d10v_ts3_register_name
;
1562 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1563 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1564 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1565 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1566 tdep
->imap_register
= d10v_ts3_imap_register
;
1570 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1571 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1572 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1573 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1574 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1576 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1577 set_gdbarch_sp_regnum (gdbarch
, 15);
1578 set_gdbarch_fp_regnum (gdbarch
, 11);
1579 set_gdbarch_pc_regnum (gdbarch
, 18);
1580 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1581 set_gdbarch_register_size (gdbarch
, 2);
1582 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1583 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1584 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1585 set_gdbarch_max_register_raw_size (gdbarch
, 8);
1586 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1587 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
1588 set_gdbarch_register_virtual_type (gdbarch
, d10v_register_virtual_type
);
1590 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1591 set_gdbarch_addr_bit (gdbarch
, 32);
1592 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1593 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1594 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1595 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1596 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1597 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1598 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1599 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1600 double'' is 64 bits. */
1601 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1602 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1603 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1604 switch (info
.byte_order
)
1606 case BFD_ENDIAN_BIG
:
1607 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1608 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1609 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1611 case BFD_ENDIAN_LITTLE
:
1612 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1613 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1614 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1617 internal_error (__FILE__
, __LINE__
,
1618 "d10v_gdbarch_init: bad byte order for float format");
1621 set_gdbarch_call_dummy_length (gdbarch
, 0);
1622 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1623 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1624 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1625 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1626 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1627 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1628 set_gdbarch_call_dummy_p (gdbarch
, 1);
1629 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
1630 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1632 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1633 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1634 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
1635 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1637 set_gdbarch_store_struct_return (gdbarch
, d10v_store_struct_return
);
1638 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1639 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1640 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1642 set_gdbarch_frame_init_saved_regs (gdbarch
, d10v_frame_init_saved_regs
);
1643 set_gdbarch_init_extra_frame_info (gdbarch
, d10v_init_extra_frame_info
);
1645 set_gdbarch_pop_frame (gdbarch
, d10v_pop_frame
);
1647 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1648 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1649 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1650 set_gdbarch_function_start_offset (gdbarch
, 0);
1651 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1653 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1655 set_gdbarch_frame_args_skip (gdbarch
, 0);
1656 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1657 set_gdbarch_frame_chain (gdbarch
, d10v_frame_chain
);
1658 set_gdbarch_frame_chain_valid (gdbarch
, d10v_frame_chain_valid
);
1659 set_gdbarch_frame_saved_pc (gdbarch
, d10v_frame_saved_pc
);
1661 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1662 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1663 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1665 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1666 set_gdbarch_extra_stack_alignment_needed (gdbarch
, 0);
1672 extern void (*target_resume_hook
) (void);
1673 extern void (*target_wait_loop_hook
) (void);
1676 _initialize_d10v_tdep (void)
1678 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1680 tm_print_insn
= print_insn_d10v
;
1682 target_resume_hook
= d10v_eva_prepare_to_trace
;
1683 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1685 add_com ("regs", class_vars
, show_regs
, "Print all registers");
1687 add_com ("itrace", class_support
, trace_command
,
1688 "Enable tracing of instruction execution.");
1690 add_com ("iuntrace", class_support
, untrace_command
,
1691 "Disable tracing of instruction execution.");
1693 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1694 "Disassemble the trace buffer.\n\
1695 Two optional arguments specify a range of trace buffer entries\n\
1696 as reported by info trace (NOT addresses!).");
1698 add_info ("itrace", trace_info
,
1699 "Display info about the trace data buffer.");
1701 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1702 var_integer
, (char *) &trace_display
,
1703 "Set automatic display of trace.\n", &setlist
),
1705 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1706 var_integer
, (char *) &default_trace_show_source
,
1707 "Set display of source code with trace.\n", &setlist
),