1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
32 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "floatformat.h"
43 #include "gdb/sim-d10v.h"
44 #include "sim-regno.h"
46 #include "gdb_assert.h"
52 unsigned long (*dmap_register
) (int nr
);
53 unsigned long (*imap_register
) (int nr
);
56 /* These are the addresses the D10V-EVA board maps data and
57 instruction memory to. */
60 DMEM_START
= 0x2000000,
61 IMEM_START
= 0x1000000,
62 STACK_START
= 0x200bffe
65 /* d10v register names. */
80 /* d10v calling convention. */
81 ARG1_REGNUM
= R0_REGNUM
,
82 ARGN_REGNUM
= R3_REGNUM
,
83 RET1_REGNUM
= R0_REGNUM
,
86 #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs)
87 #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum)
91 extern void _initialize_d10v_tdep (void);
93 static CORE_ADDR
d10v_read_sp (void);
95 static CORE_ADDR
d10v_read_fp (void);
97 static void d10v_eva_prepare_to_trace (void);
99 static void d10v_eva_get_trace_data (void);
102 d10v_stack_align (CORE_ADDR len
)
104 return (len
+ 1) & ~1;
107 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
108 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
109 and TYPE is the type (which is known to be struct, union or array).
111 The d10v returns anything less than 8 bytes in size in
115 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
119 /* The d10v only passes a struct in a register when that structure
120 has an alignment that matches the size of a register. */
121 /* If the structure doesn't fit in 4 registers, put it on the
123 if (TYPE_LENGTH (type
) > 8)
125 /* If the struct contains only one field, don't put it on the stack
126 - gcc can fit it in one or more registers. */
127 if (TYPE_NFIELDS (type
) == 1)
129 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
130 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
132 /* If the alignment changes, just assume it goes on the
134 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
137 /* If the alignment is suitable for the d10v's 16 bit registers,
138 don't put it on the stack. */
139 if (alignment
== 2 || alignment
== 4)
145 static const unsigned char *
146 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
148 static unsigned char breakpoint
[] =
149 {0x2f, 0x90, 0x5e, 0x00};
150 *lenptr
= sizeof (breakpoint
);
154 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
155 when the reg_nr isn't valid. */
159 TS2_IMAP0_REGNUM
= 32,
160 TS2_DMAP_REGNUM
= 34,
161 TS2_NR_DMAP_REGS
= 1,
166 d10v_ts2_register_name (int reg_nr
)
168 static char *register_names
[] =
170 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
171 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
172 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
173 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
174 "imap0", "imap1", "dmap", "a0", "a1"
178 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
180 return register_names
[reg_nr
];
185 TS3_IMAP0_REGNUM
= 36,
186 TS3_DMAP0_REGNUM
= 38,
187 TS3_NR_DMAP_REGS
= 4,
192 d10v_ts3_register_name (int reg_nr
)
194 static char *register_names
[] =
196 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
197 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
198 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
199 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
203 "dmap0", "dmap1", "dmap2", "dmap3"
207 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
209 return register_names
[reg_nr
];
212 /* Access the DMAP/IMAP registers in a target independent way.
214 Divide the D10V's 64k data space into four 16k segments:
215 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
218 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
219 0x7fff) always map to the on-chip data RAM, and the fourth always
220 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
221 unified memory or instruction memory, under the control of the
222 single DMAP register.
224 On the TS3, there are four DMAP registers, each of which controls
225 one of the segments. */
228 d10v_ts2_dmap_register (int reg_nr
)
236 return read_register (TS2_DMAP_REGNUM
);
243 d10v_ts3_dmap_register (int reg_nr
)
245 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
249 d10v_dmap_register (int reg_nr
)
251 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
255 d10v_ts2_imap_register (int reg_nr
)
257 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
261 d10v_ts3_imap_register (int reg_nr
)
263 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
267 d10v_imap_register (int reg_nr
)
269 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
272 /* MAP GDB's internal register numbering (determined by the layout fo
273 the REGISTER_BYTE array) onto the simulator's register
277 d10v_ts2_register_sim_regno (int nr
)
279 if (legacy_register_sim_regno (nr
) < 0)
280 return legacy_register_sim_regno (nr
);
281 if (nr
>= TS2_IMAP0_REGNUM
282 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
283 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
284 if (nr
== TS2_DMAP_REGNUM
)
285 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
286 if (nr
>= TS2_A0_REGNUM
287 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
288 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
293 d10v_ts3_register_sim_regno (int nr
)
295 if (legacy_register_sim_regno (nr
) < 0)
296 return legacy_register_sim_regno (nr
);
297 if (nr
>= TS3_IMAP0_REGNUM
298 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
299 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
300 if (nr
>= TS3_DMAP0_REGNUM
301 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
302 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
303 if (nr
>= TS3_A0_REGNUM
304 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
305 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
309 /* Index within `registers' of the first byte of the space for
313 d10v_register_byte (int reg_nr
)
315 if (reg_nr
< A0_REGNUM
)
317 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
318 return (A0_REGNUM
* 2
319 + (reg_nr
- A0_REGNUM
) * 8);
321 return (A0_REGNUM
* 2
323 + (reg_nr
- A0_REGNUM
- NR_A_REGS
) * 2);
326 /* Number of bytes of storage in the actual machine representation for
330 d10v_register_raw_size (int reg_nr
)
332 if (reg_nr
< A0_REGNUM
)
334 else if (reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
340 /* Return the GDB type object for the "standard" data type
341 of data in register N. */
344 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
346 if (reg_nr
== PC_REGNUM
)
347 return builtin_type_void_func_ptr
;
348 if (reg_nr
== _SP_REGNUM
|| reg_nr
== _FP_REGNUM
)
349 return builtin_type_void_data_ptr
;
350 else if (reg_nr
>= A0_REGNUM
351 && reg_nr
< (A0_REGNUM
+ NR_A_REGS
))
352 return builtin_type_int64
;
354 return builtin_type_int16
;
358 d10v_daddr_p (CORE_ADDR x
)
360 return (((x
) & 0x3000000) == DMEM_START
);
364 d10v_iaddr_p (CORE_ADDR x
)
366 return (((x
) & 0x3000000) == IMEM_START
);
370 d10v_make_daddr (CORE_ADDR x
)
372 return ((x
) | DMEM_START
);
376 d10v_make_iaddr (CORE_ADDR x
)
378 if (d10v_iaddr_p (x
))
379 return x
; /* Idempotency -- x is already in the IMEM space. */
381 return (((x
) << 2) | IMEM_START
);
385 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
387 return (((x
) >> 2) & 0xffff);
391 d10v_convert_daddr_to_raw (CORE_ADDR x
)
393 return ((x
) & 0xffff);
397 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
399 /* Is it a code address? */
400 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
401 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
403 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
404 d10v_convert_iaddr_to_raw (addr
));
408 /* Strip off any upper segment bits. */
409 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
410 d10v_convert_daddr_to_raw (addr
));
415 d10v_pointer_to_address (struct type
*type
, const void *buf
)
417 CORE_ADDR addr
= extract_address (buf
, TYPE_LENGTH (type
));
419 /* Is it a code address? */
420 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
421 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
422 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
423 return d10v_make_iaddr (addr
);
425 return d10v_make_daddr (addr
);
428 /* Don't do anything if we have an integer, this way users can type 'x
429 <addr>' w/o having gdb outsmart them. The internal gdb conversions
430 to the correct space are taken care of in the pointer_to_address
431 function. If we don't do this, 'x $fp' wouldn't work. */
433 d10v_integer_to_address (struct type
*type
, void *buf
)
436 val
= unpack_long (type
, buf
);
440 /* Write into appropriate registers a function return value
441 of type TYPE, given in virtual format.
443 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
446 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
449 /* Only char return values need to be shifted right within the first
451 if (TYPE_LENGTH (type
) == 1
452 && TYPE_CODE (type
) == TYPE_CODE_INT
)
455 tmp
[1] = *(bfd_byte
*)valbuf
;
456 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
461 /* A structure is never more than 8 bytes long. See
462 use_struct_convention(). */
463 gdb_assert (TYPE_LENGTH (type
) <= 8);
464 /* Write out most registers, stop loop before trying to write
465 out any dangling byte at the end of the buffer. */
466 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
468 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
469 (bfd_byte
*) valbuf
+ reg
* 2);
471 /* Write out any dangling byte at the end of the buffer. */
472 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
473 regcache_cooked_write_part (regcache
, reg
, 0, 1,
474 (bfd_byte
*) valbuf
+ reg
* 2);
478 /* Extract from an array REGBUF containing the (raw) register state
479 the address in which a function should return its structure value,
480 as a CORE_ADDR (or an expression that can be used as one). */
483 d10v_extract_struct_value_address (struct regcache
*regcache
)
486 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
487 return (addr
| DMEM_START
);
490 /* Immediately after a function call, return the saved pc. We can't
491 use frame->return_pc beause that is determined by reading R13 off
492 the stack and that may not be written yet. */
495 d10v_saved_pc_after_call (struct frame_info
*frame
)
497 return ((read_register (LR_REGNUM
) << 2)
502 check_prologue (unsigned short op
)
505 if ((op
& 0x7E1F) == 0x6C1F)
509 if ((op
& 0x7E3F) == 0x6E1F)
513 if ((op
& 0x7FE1) == 0x01E1)
525 if ((op
& 0x7E1F) == 0x681E)
529 if ((op
& 0x7E3F) == 0x3A1E)
536 d10v_skip_prologue (CORE_ADDR pc
)
539 unsigned short op1
, op2
;
540 CORE_ADDR func_addr
, func_end
;
541 struct symtab_and_line sal
;
543 /* If we have line debugging information, then the end of the */
544 /* prologue should the first assembly instruction of the first source line */
545 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
547 sal
= find_pc_line (func_addr
, 0);
548 if (sal
.end
&& sal
.end
< func_end
)
552 if (target_read_memory (pc
, (char *) &op
, 4))
553 return pc
; /* Can't access it -- assume no prologue. */
557 op
= (unsigned long) read_memory_integer (pc
, 4);
558 if ((op
& 0xC0000000) == 0xC0000000)
560 /* long instruction */
561 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
562 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
563 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
568 /* short instructions */
569 if ((op
& 0xC0000000) == 0x80000000)
571 op2
= (op
& 0x3FFF8000) >> 15;
576 op1
= (op
& 0x3FFF8000) >> 15;
579 if (check_prologue (op1
))
581 if (!check_prologue (op2
))
583 /* if the previous opcode was really part of the prologue */
584 /* and not just a NOP, then we want to break after both instructions */
598 struct d10v_unwind_cache
601 /* The frame's base. Used when constructing a frame ID. */
604 CORE_ADDR
*saved_regs
;
605 /* How far the SP and r11 (FP) have been offset from the start of
606 the stack frame (as defined by the previous frame's stack
615 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
621 if ((op
& 0x7E1F) == 0x6C1F)
623 n
= (op
& 0x1E0) >> 5;
624 info
->sp_offset
-= 2;
625 info
->saved_regs
[n
] = info
->sp_offset
;
630 else if ((op
& 0x7E3F) == 0x6E1F)
632 n
= (op
& 0x1E0) >> 5;
633 info
->sp_offset
-= 4;
634 info
->saved_regs
[n
] = info
->sp_offset
;
635 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
640 if ((op
& 0x7FE1) == 0x01E1)
642 n
= (op
& 0x1E) >> 1;
645 info
->sp_offset
-= n
;
652 info
->uses_frame
= 1;
653 info
->r11_offset
= info
->sp_offset
;
658 if ((op
& 0x7E1F) == 0x6816)
660 n
= (op
& 0x1E0) >> 5;
661 info
->saved_regs
[n
] = info
->r11_offset
;
670 if ((op
& 0x7E1F) == 0x681E)
672 n
= (op
& 0x1E0) >> 5;
673 info
->saved_regs
[n
] = info
->sp_offset
;
678 if ((op
& 0x7E3F) == 0x3A1E)
680 n
= (op
& 0x1E0) >> 5;
681 info
->saved_regs
[n
] = info
->sp_offset
;
682 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
689 /* Put here the code to store, into fi->saved_regs, the addresses of
690 the saved registers of frame described by FRAME_INFO. This
691 includes special registers such as pc and fp saved in special ways
692 in the stack frame. sp is even more special: the address we return
693 for it IS the sp for the next frame. */
695 struct d10v_unwind_cache
*
696 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
697 void **this_prologue_cache
)
703 unsigned short op1
, op2
;
705 struct d10v_unwind_cache
*info
;
707 if ((*this_prologue_cache
))
708 return (*this_prologue_cache
);
710 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
711 (*this_prologue_cache
) = info
;
712 info
->saved_regs
= frame_obstack_zalloc (SIZEOF_FRAME_SAVED_REGS
);
718 pc
= get_pc_function_start (frame_pc_unwind (next_frame
));
720 info
->uses_frame
= 0;
723 op
= (unsigned long) read_memory_integer (pc
, 4);
724 if ((op
& 0xC0000000) == 0xC0000000)
726 /* long instruction */
727 if ((op
& 0x3FFF0000) == 0x01FF0000)
730 short n
= op
& 0xFFFF;
731 info
->sp_offset
+= n
;
733 else if ((op
& 0x3F0F0000) == 0x340F0000)
735 /* st rn, @(offset,sp) */
736 short offset
= op
& 0xFFFF;
737 short n
= (op
>> 20) & 0xF;
738 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
740 else if ((op
& 0x3F1F0000) == 0x350F0000)
742 /* st2w rn, @(offset,sp) */
743 short offset
= op
& 0xFFFF;
744 short n
= (op
>> 20) & 0xF;
745 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
746 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
753 /* short instructions */
754 if ((op
& 0xC0000000) == 0x80000000)
756 op2
= (op
& 0x3FFF8000) >> 15;
761 op1
= (op
& 0x3FFF8000) >> 15;
764 if (!prologue_find_regs (info
, op1
, pc
)
765 || !prologue_find_regs (info
, op2
, pc
))
771 info
->size
= -info
->sp_offset
;
773 /* Compute the frame's base, and the previous frame's SP. */
774 if (info
->uses_frame
)
776 /* The SP was moved to the FP. This indicates that a new frame
777 was created. Get THIS frame's FP value by unwinding it from
779 frame_unwind_unsigned_register (next_frame
, FP_REGNUM
, &this_base
);
780 /* The FP points at the last saved register. Adjust the FP back
781 to before the first saved register giving the SP. */
782 prev_sp
= this_base
+ info
->size
;
784 else if (info
->saved_regs
[SP_REGNUM
])
786 /* The SP was saved (which is very unusual), the frame base is
787 just the PREV's frame's TOP-OF-STACK. */
788 this_base
= read_memory_unsigned_integer (info
->saved_regs
[SP_REGNUM
],
789 register_size (current_gdbarch
,
795 /* Assume that the FP is this frame's SP but with that pushed
796 stack space added back. */
797 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &this_base
);
798 prev_sp
= this_base
+ info
->size
;
801 info
->base
= d10v_make_daddr (this_base
);
802 prev_sp
= d10v_make_daddr (prev_sp
);
804 /* Adjust all the saved registers so that they contain addresses and
806 for (i
= 0; i
< NUM_REGS
- 1; i
++)
807 if (info
->saved_regs
[i
])
809 info
->saved_regs
[i
] = (prev_sp
+ info
->saved_regs
[i
]);
812 if (info
->saved_regs
[LR_REGNUM
])
815 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
816 register_size (current_gdbarch
, LR_REGNUM
));
817 info
->return_pc
= d10v_make_iaddr (return_pc
);
822 frame_unwind_unsigned_register (next_frame
, LR_REGNUM
, &return_pc
);
823 info
->return_pc
= d10v_make_iaddr (return_pc
);
826 /* The SP_REGNUM is special. Instead of the address of the SP, the
827 previous frame's SP value is saved. */
828 info
->saved_regs
[SP_REGNUM
] = prev_sp
;
834 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
835 struct frame_info
*frame
, int regnum
, int all
)
839 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
844 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
845 frame_read_unsigned_register (frame
, PC_REGNUM
, &pc
);
846 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
847 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
848 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
849 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
850 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
851 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
852 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
857 for (group
= 0; group
< 16; group
+= 8)
860 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
861 for (r
= group
; r
< group
+ 8; r
++)
864 frame_read_unsigned_register (frame
, r
, &tmp
);
865 fprintf_filtered (file
, " %04lx", (long) tmp
);
867 fprintf_filtered (file
, "\n");
871 /* Note: The IMAP/DMAP registers don't participate in function
872 calls. Don't bother trying to unwind them. */
876 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
879 fprintf_filtered (file
, " ");
880 fprintf_filtered (file
, "IMAP%d %04lx", a
, d10v_imap_register (a
));
882 if (NR_DMAP_REGS
== 1)
883 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
884 fprintf_filtered (file
, " DMAP %04lx\n", d10v_dmap_register (2));
887 for (a
= 0; a
< NR_DMAP_REGS
; a
++)
889 fprintf_filtered (file
, " DMAP%d %04lx", a
, d10v_dmap_register (a
));
891 fprintf_filtered (file
, "\n");
896 char *num
= alloca (max_register_size (gdbarch
));
898 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
899 for (a
= A0_REGNUM
; a
< A0_REGNUM
+ NR_A_REGS
; a
++)
902 fprintf_filtered (file
, " ");
903 frame_register_read (frame
, a
, num
);
904 for (i
= 0; i
< max_register_size (current_gdbarch
); i
++)
906 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
910 fprintf_filtered (file
, "\n");
914 show_regs (char *args
, int from_tty
)
916 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
917 get_current_frame (), -1, 1);
921 d10v_read_pc (ptid_t ptid
)
927 save_ptid
= inferior_ptid
;
928 inferior_ptid
= ptid
;
929 pc
= (int) read_register (PC_REGNUM
);
930 inferior_ptid
= save_ptid
;
931 retval
= d10v_make_iaddr (pc
);
936 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
940 save_ptid
= inferior_ptid
;
941 inferior_ptid
= ptid
;
942 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
943 inferior_ptid
= save_ptid
;
949 return (d10v_make_daddr (read_register (SP_REGNUM
)));
953 d10v_write_sp (CORE_ADDR val
)
955 write_register (SP_REGNUM
, d10v_convert_daddr_to_raw (val
));
961 return (d10v_make_daddr (read_register (FP_REGNUM
)));
964 /* Function: push_return_address (pc)
965 Set up the return address for the inferior function call.
966 Needed for targets where we don't actually execute a JSR/BSR instruction */
969 d10v_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
971 write_register (LR_REGNUM
, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ()));
976 /* When arguments must be pushed onto the stack, they go on in reverse
977 order. The below implements a FILO (stack) to do this. */
982 struct stack_item
*prev
;
986 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
987 void *contents
, int len
);
988 static struct stack_item
*
989 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
991 struct stack_item
*si
;
992 si
= xmalloc (sizeof (struct stack_item
));
993 si
->data
= xmalloc (len
);
996 memcpy (si
->data
, contents
, len
);
1000 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
1001 static struct stack_item
*
1002 pop_stack_item (struct stack_item
*si
)
1004 struct stack_item
*dead
= si
;
1013 d10v_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1014 int struct_return
, CORE_ADDR struct_addr
)
1017 int regnum
= ARG1_REGNUM
;
1018 struct stack_item
*si
= NULL
;
1021 /* If STRUCT_RETURN is true, then the struct return address (in
1022 STRUCT_ADDR) will consume the first argument-passing register.
1023 Both adjust the register count and store that value. */
1026 write_register (regnum
, struct_addr
);
1030 /* Fill in registers and arg lists */
1031 for (i
= 0; i
< nargs
; i
++)
1033 struct value
*arg
= args
[i
];
1034 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
1035 char *contents
= VALUE_CONTENTS (arg
);
1036 int len
= TYPE_LENGTH (type
);
1037 int aligned_regnum
= (regnum
+ 1) & ~1;
1039 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
1040 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
1041 /* fits in a single register, do not align */
1043 val
= extract_unsigned_integer (contents
, len
);
1044 write_register (regnum
++, val
);
1046 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1047 /* value fits in remaining registers, store keeping left
1051 regnum
= aligned_regnum
;
1052 for (b
= 0; b
< (len
& ~1); b
+= 2)
1054 val
= extract_unsigned_integer (&contents
[b
], 2);
1055 write_register (regnum
++, val
);
1059 val
= extract_unsigned_integer (&contents
[b
], 1);
1060 write_register (regnum
++, (val
<< 8));
1065 /* arg will go onto stack */
1066 regnum
= ARGN_REGNUM
+ 1;
1067 si
= push_stack_item (si
, contents
, len
);
1073 sp
= (sp
- si
->len
) & ~1;
1074 write_memory (sp
, si
->data
, si
->len
);
1075 si
= pop_stack_item (si
);
1082 /* Given a return value in `regbuf' with a type `valtype',
1083 extract and copy its value into `valbuf'. */
1086 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1091 printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type
),
1092 TYPE_LENGTH (type
), RET1_REGNUM
- R0_REGNUM
,
1093 (int) extract_unsigned_integer (regbuf
+ REGISTER_BYTE(RET1_REGNUM
),
1094 register_size (current_gdbarch
, RET1_REGNUM
)));
1096 if (TYPE_LENGTH (type
) == 1)
1099 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1100 store_unsigned_integer (valbuf
, 1, c
);
1104 /* For return values of odd size, the first byte is in the
1105 least significant part of the first register. The
1106 remaining bytes in remaining registers. Interestingly, when
1107 such values are passed in, the last byte is in the most
1108 significant byte of that same register - wierd. */
1109 int reg
= RET1_REGNUM
;
1111 if (TYPE_LENGTH (type
) & 1)
1113 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1114 (bfd_byte
*)valbuf
+ off
);
1118 /* Transfer the remaining registers. */
1119 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1121 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1122 (bfd_byte
*) valbuf
+ off
);
1127 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1128 understands. Returns number of bytes that can be transfered
1129 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1130 (segmentation fault). Since the simulator knows all about how the
1131 VM system works, we just call that to do the translation. */
1134 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1135 CORE_ADDR
*targ_addr
, int *targ_len
)
1139 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1142 d10v_imap_register
);
1143 *targ_addr
= out_addr
;
1144 *targ_len
= out_len
;
1148 /* The following code implements access to, and display of, the D10V's
1149 instruction trace buffer. The buffer consists of 64K or more
1150 4-byte words of data, of which each words includes an 8-bit count,
1151 an 8-bit segment number, and a 16-bit instruction address.
1153 In theory, the trace buffer is continuously capturing instruction
1154 data that the CPU presents on its "debug bus", but in practice, the
1155 ROMified GDB stub only enables tracing when it continues or steps
1156 the program, and stops tracing when the program stops; so it
1157 actually works for GDB to read the buffer counter out of memory and
1158 then read each trace word. The counter records where the tracing
1159 stops, but there is no record of where it started, so we remember
1160 the PC when we resumed and then search backwards in the trace
1161 buffer for a word that includes that address. This is not perfect,
1162 because you will miss trace data if the resumption PC is the target
1163 of a branch. (The value of the buffer counter is semi-random, any
1164 trace data from a previous program stop is gone.) */
1166 /* The address of the last word recorded in the trace buffer. */
1168 #define DBBC_ADDR (0xd80000)
1170 /* The base of the trace buffer, at least for the "Board_0". */
1172 #define TRACE_BUFFER_BASE (0xf40000)
1174 static void trace_command (char *, int);
1176 static void untrace_command (char *, int);
1178 static void trace_info (char *, int);
1180 static void tdisassemble_command (char *, int);
1182 static void display_trace (int, int);
1184 /* True when instruction traces are being collected. */
1188 /* Remembered PC. */
1190 static CORE_ADDR last_pc
;
1192 /* True when trace output should be displayed whenever program stops. */
1194 static int trace_display
;
1196 /* True when trace listing should include source lines. */
1198 static int default_trace_show_source
= 1;
1209 trace_command (char *args
, int from_tty
)
1211 /* Clear the host-side trace buffer, allocating space if needed. */
1212 trace_data
.size
= 0;
1213 if (trace_data
.counts
== NULL
)
1214 trace_data
.counts
= (short *) xmalloc (65536 * sizeof (short));
1215 if (trace_data
.addrs
== NULL
)
1216 trace_data
.addrs
= (CORE_ADDR
*) xmalloc (65536 * sizeof (CORE_ADDR
));
1220 printf_filtered ("Tracing is now on.\n");
1224 untrace_command (char *args
, int from_tty
)
1228 printf_filtered ("Tracing is now off.\n");
1232 trace_info (char *args
, int from_tty
)
1236 if (trace_data
.size
)
1238 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1240 for (i
= 0; i
< trace_data
.size
; ++i
)
1242 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1244 trace_data
.counts
[i
],
1245 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1246 paddr_nz (trace_data
.addrs
[i
]));
1250 printf_filtered ("No entries in trace buffer.\n");
1252 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1255 /* Print the instruction at address MEMADDR in debugged memory,
1256 on STREAM. Returns length of the instruction, in bytes. */
1259 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1261 /* If there's no disassembler, something is very wrong. */
1262 if (tm_print_insn
== NULL
)
1263 internal_error (__FILE__
, __LINE__
,
1264 "print_insn: no disassembler");
1266 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1267 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1269 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1270 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1274 d10v_eva_prepare_to_trace (void)
1279 last_pc
= read_register (PC_REGNUM
);
1282 /* Collect trace data from the target board and format it into a form
1283 more useful for display. */
1286 d10v_eva_get_trace_data (void)
1288 int count
, i
, j
, oldsize
;
1289 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1290 unsigned int last_trace
, trace_word
, next_word
;
1291 unsigned int *tmpspace
;
1296 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1298 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1300 /* Collect buffer contents from the target, stopping when we reach
1301 the word recorded when execution resumed. */
1304 while (last_trace
> 0)
1308 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1309 trace_addr
= trace_word
& 0xffff;
1311 /* Ignore an apparently nonsensical entry. */
1312 if (trace_addr
== 0xffd5)
1314 tmpspace
[count
++] = trace_word
;
1315 if (trace_addr
== last_pc
)
1321 /* Move the data to the host-side trace buffer, adjusting counts to
1322 include the last instruction executed and transforming the address
1323 into something that GDB likes. */
1325 for (i
= 0; i
< count
; ++i
)
1327 trace_word
= tmpspace
[i
];
1328 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1329 trace_addr
= trace_word
& 0xffff;
1330 next_cnt
= (next_word
>> 24) & 0xff;
1331 j
= trace_data
.size
+ count
- i
- 1;
1332 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1333 trace_data
.counts
[j
] = next_cnt
+ 1;
1336 oldsize
= trace_data
.size
;
1337 trace_data
.size
+= count
;
1342 display_trace (oldsize
, trace_data
.size
);
1346 tdisassemble_command (char *arg
, int from_tty
)
1349 CORE_ADDR low
, high
;
1355 high
= trace_data
.size
;
1357 else if (!(space_index
= (char *) strchr (arg
, ' ')))
1359 low
= parse_and_eval_address (arg
);
1364 /* Two arguments. */
1365 *space_index
= '\0';
1366 low
= parse_and_eval_address (arg
);
1367 high
= parse_and_eval_address (space_index
+ 1);
1372 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1374 display_trace (low
, high
);
1376 printf_filtered ("End of trace dump.\n");
1377 gdb_flush (gdb_stdout
);
1381 display_trace (int low
, int high
)
1383 int i
, count
, trace_show_source
, first
, suppress
;
1384 CORE_ADDR next_address
;
1386 trace_show_source
= default_trace_show_source
;
1387 if (!have_full_symbols () && !have_partial_symbols ())
1389 trace_show_source
= 0;
1390 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1391 printf_filtered ("Trace will not display any source.\n");
1396 for (i
= low
; i
< high
; ++i
)
1398 next_address
= trace_data
.addrs
[i
];
1399 count
= trace_data
.counts
[i
];
1403 if (trace_show_source
)
1405 struct symtab_and_line sal
, sal_prev
;
1407 sal_prev
= find_pc_line (next_address
- 4, 0);
1408 sal
= find_pc_line (next_address
, 0);
1412 if (first
|| sal
.line
!= sal_prev
.line
)
1413 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1419 /* FIXME-32x64--assumes sal.pc fits in long. */
1420 printf_filtered ("No source file for address %s.\n",
1421 local_hex_string ((unsigned long) sal
.pc
));
1426 print_address (next_address
, gdb_stdout
);
1427 printf_filtered (":");
1428 printf_filtered ("\t");
1430 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1431 printf_filtered ("\n");
1432 gdb_flush (gdb_stdout
);
1438 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1441 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1442 return d10v_make_iaddr (pc
);
1445 /* Given a GDB frame, determine the address of the calling function's
1446 frame. This will be used to create a new GDB frame struct. */
1449 d10v_frame_this_id (struct frame_info
*next_frame
,
1450 void **this_prologue_cache
,
1451 struct frame_id
*this_id
)
1453 struct d10v_unwind_cache
*info
1454 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1458 /* Start with a NULL frame ID. */
1459 (*this_id
) = null_frame_id
;
1461 /* The PC is easy. */
1462 pc
= frame_pc_unwind (next_frame
);
1464 /* This is meant to halt the backtrace at "_start". Make sure we
1465 don't halt it at a generic dummy frame. */
1466 if (pc
== IMEM_START
|| pc
<= IMEM_START
|| inside_entry_file (pc
))
1469 /* Hopefully the prologue analysis either correctly determined the
1470 frame's base (which is the SP from the previous frame), or set
1471 that base to "NULL". */
1473 if (base
== STACK_START
|| base
== 0)
1476 /* Check that we're not going round in circles with the same frame
1477 ID (but avoid applying the test to sentinel frames which do go
1478 round in circles). Can't use frame_id_eq() as that doesn't yet
1479 compare the frame's PC value. */
1480 if (frame_relative_level (next_frame
) >= 0
1481 && get_frame_type (next_frame
) != DUMMY_FRAME
1482 && get_frame_id (next_frame
).pc
== pc
1483 && get_frame_id (next_frame
).base
== base
)
1486 this_id
->base
= base
;
1491 saved_regs_unwinder (struct frame_info
*next_frame
,
1492 CORE_ADDR
*this_saved_regs
,
1493 int regnum
, int *optimizedp
,
1494 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1495 int *realnump
, void *bufferp
)
1497 if (this_saved_regs
[regnum
] != 0)
1499 if (regnum
== SP_REGNUM
)
1501 /* SP register treated specially. */
1506 if (bufferp
!= NULL
)
1507 store_address (bufferp
, register_size (current_gdbarch
, regnum
),
1508 this_saved_regs
[regnum
]);
1512 /* Any other register is saved in memory, fetch it but cache
1513 a local copy of its value. */
1515 *lvalp
= lval_memory
;
1516 *addrp
= this_saved_regs
[regnum
];
1518 if (bufferp
!= NULL
)
1520 /* Read the value in from memory. */
1521 read_memory (this_saved_regs
[regnum
], bufferp
,
1522 register_size (current_gdbarch
, regnum
));
1528 /* No luck, assume this and the next frame have the same register
1529 value. If a value is needed, pass the request on down the chain;
1530 otherwise just return an indication that the value is in the same
1531 register as the next frame. */
1532 frame_register_unwind (next_frame
, regnum
, optimizedp
, lvalp
, addrp
,
1538 d10v_frame_prev_register (struct frame_info
*next_frame
,
1539 void **this_prologue_cache
,
1540 int regnum
, int *optimizedp
,
1541 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1542 int *realnump
, void *bufferp
)
1544 struct d10v_unwind_cache
*info
1545 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1546 if (regnum
== PC_REGNUM
)
1548 /* The call instruction saves the caller's PC in LR. The
1549 function prologue of the callee may then save the LR on the
1550 stack. Find that possibly saved LR value and return it. */
1551 saved_regs_unwinder (next_frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1552 lvalp
, addrp
, realnump
, bufferp
);
1556 saved_regs_unwinder (next_frame
, info
->saved_regs
, regnum
, optimizedp
,
1557 lvalp
, addrp
, realnump
, bufferp
);
1562 static struct frame_unwind d10v_frame_unwind
= {
1564 d10v_frame_prev_register
1567 const struct frame_unwind
*
1568 d10v_frame_p (CORE_ADDR pc
)
1570 return &d10v_frame_unwind
;
1573 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1574 dummy frame. The frame ID's base needs to match the TOS value
1575 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1578 static struct frame_id
1579 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1583 id
.pc
= frame_pc_unwind (next_frame
);
1584 frame_unwind_unsigned_register (next_frame
, SP_REGNUM
, &base
);
1585 id
.base
= d10v_make_daddr (base
);
1589 static gdbarch_init_ftype d10v_gdbarch_init
;
1591 static struct gdbarch
*
1592 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1594 static LONGEST d10v_call_dummy_words
[] =
1596 struct gdbarch
*gdbarch
;
1598 struct gdbarch_tdep
*tdep
;
1599 gdbarch_register_name_ftype
*d10v_register_name
;
1600 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1602 /* Find a candidate among the list of pre-declared architectures. */
1603 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1605 return arches
->gdbarch
;
1607 /* None found, create a new architecture from the information
1609 tdep
= XMALLOC (struct gdbarch_tdep
);
1610 gdbarch
= gdbarch_alloc (&info
, tdep
);
1612 switch (info
.bfd_arch_info
->mach
)
1614 case bfd_mach_d10v_ts2
:
1616 d10v_register_name
= d10v_ts2_register_name
;
1617 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1618 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1619 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1620 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1621 tdep
->imap_register
= d10v_ts2_imap_register
;
1624 case bfd_mach_d10v_ts3
:
1626 d10v_register_name
= d10v_ts3_register_name
;
1627 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1628 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1629 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1630 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1631 tdep
->imap_register
= d10v_ts3_imap_register
;
1635 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1636 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1637 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1638 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1639 set_gdbarch_write_sp (gdbarch
, d10v_write_sp
);
1641 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1642 set_gdbarch_sp_regnum (gdbarch
, 15);
1643 set_gdbarch_fp_regnum (gdbarch
, 11);
1644 set_gdbarch_pc_regnum (gdbarch
, 18);
1645 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1646 set_gdbarch_register_size (gdbarch
, 2);
1647 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1648 set_gdbarch_register_byte (gdbarch
, d10v_register_byte
);
1649 set_gdbarch_register_raw_size (gdbarch
, d10v_register_raw_size
);
1650 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1651 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1653 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1654 set_gdbarch_addr_bit (gdbarch
, 32);
1655 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1656 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1657 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1658 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1659 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1660 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1661 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1662 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1663 double'' is 64 bits. */
1664 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1665 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1666 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1667 switch (info
.byte_order
)
1669 case BFD_ENDIAN_BIG
:
1670 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1671 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1672 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1674 case BFD_ENDIAN_LITTLE
:
1675 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1676 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1677 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1680 internal_error (__FILE__
, __LINE__
,
1681 "d10v_gdbarch_init: bad byte order for float format");
1684 set_gdbarch_call_dummy_length (gdbarch
, 0);
1685 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
1686 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
1687 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
1688 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
1689 set_gdbarch_call_dummy_words (gdbarch
, d10v_call_dummy_words
);
1690 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (d10v_call_dummy_words
));
1691 set_gdbarch_call_dummy_p (gdbarch
, 1);
1692 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
1694 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1695 set_gdbarch_push_arguments (gdbarch
, d10v_push_arguments
);
1696 set_gdbarch_push_return_address (gdbarch
, d10v_push_return_address
);
1698 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1699 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1700 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1702 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1703 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1704 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1705 set_gdbarch_function_start_offset (gdbarch
, 0);
1706 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1708 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1710 set_gdbarch_frame_args_skip (gdbarch
, 0);
1711 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1713 set_gdbarch_saved_pc_after_call (gdbarch
, d10v_saved_pc_after_call
);
1714 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1715 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1717 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1719 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1721 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1723 /* Methods for saving / extracting a dummy frame's ID. */
1724 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1725 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1727 /* Return the unwound PC value. */
1728 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1734 extern void (*target_resume_hook
) (void);
1735 extern void (*target_wait_loop_hook
) (void);
1738 _initialize_d10v_tdep (void)
1740 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1742 tm_print_insn
= print_insn_d10v
;
1744 target_resume_hook
= d10v_eva_prepare_to_trace
;
1745 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1747 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1750 add_com ("itrace", class_support
, trace_command
,
1751 "Enable tracing of instruction execution.");
1753 add_com ("iuntrace", class_support
, untrace_command
,
1754 "Disable tracing of instruction execution.");
1756 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1757 "Disassemble the trace buffer.\n\
1758 Two optional arguments specify a range of trace buffer entries\n\
1759 as reported by info trace (NOT addresses!).");
1761 add_info ("itrace", trace_info
,
1762 "Display info about the trace data buffer.");
1764 add_show_from_set (add_set_cmd ("itracedisplay", no_class
,
1765 var_integer
, (char *) &trace_display
,
1766 "Set automatic display of trace.\n", &setlist
),
1768 add_show_from_set (add_set_cmd ("itracesource", no_class
,
1769 var_integer
, (char *) &default_trace_show_source
,
1770 "Set display of source code with trace.\n", &setlist
),