1 /* Target-dependent code for Mitsubishi D10V, for GDB.
3 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* Contributed by Martin Hunt, hunt@cygnus.com */
27 #include "frame-unwind.h"
28 #include "frame-base.h"
33 #include "gdb_string.h"
40 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "gdb/sim-d10v.h"
45 #include "sim-regno.h"
47 #include "gdb_assert.h"
53 unsigned long (*dmap_register
) (int nr
);
54 unsigned long (*imap_register
) (int nr
);
57 /* These are the addresses the D10V-EVA board maps data and
58 instruction memory to. */
61 DMEM_START
= 0x2000000,
62 IMEM_START
= 0x1000000,
63 STACK_START
= 0x200bffe
66 /* d10v register names. */
81 /* d10v calling convention. */
82 ARG1_REGNUM
= R0_REGNUM
,
83 ARGN_REGNUM
= R3_REGNUM
,
84 RET1_REGNUM
= R0_REGNUM
,
88 nr_dmap_regs (struct gdbarch
*gdbarch
)
90 return gdbarch_tdep (gdbarch
)->nr_dmap_regs
;
94 a0_regnum (struct gdbarch
*gdbarch
)
96 return gdbarch_tdep (gdbarch
)->a0_regnum
;
101 extern void _initialize_d10v_tdep (void);
103 static CORE_ADDR
d10v_read_sp (void);
105 static CORE_ADDR
d10v_read_fp (void);
107 static void d10v_eva_prepare_to_trace (void);
109 static void d10v_eva_get_trace_data (void);
112 d10v_stack_align (CORE_ADDR len
)
114 return (len
+ 1) & ~1;
117 /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of
118 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc
119 and TYPE is the type (which is known to be struct, union or array).
121 The d10v returns anything less than 8 bytes in size in
125 d10v_use_struct_convention (int gcc_p
, struct type
*type
)
129 /* The d10v only passes a struct in a register when that structure
130 has an alignment that matches the size of a register. */
131 /* If the structure doesn't fit in 4 registers, put it on the
133 if (TYPE_LENGTH (type
) > 8)
135 /* If the struct contains only one field, don't put it on the stack
136 - gcc can fit it in one or more registers. */
137 if (TYPE_NFIELDS (type
) == 1)
139 alignment
= TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0));
140 for (i
= 1; i
< TYPE_NFIELDS (type
); i
++)
142 /* If the alignment changes, just assume it goes on the
144 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, i
)) != alignment
)
147 /* If the alignment is suitable for the d10v's 16 bit registers,
148 don't put it on the stack. */
149 if (alignment
== 2 || alignment
== 4)
155 static const unsigned char *
156 d10v_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
158 static unsigned char breakpoint
[] =
159 {0x2f, 0x90, 0x5e, 0x00};
160 *lenptr
= sizeof (breakpoint
);
164 /* Map the REG_NR onto an ascii name. Return NULL or an empty string
165 when the reg_nr isn't valid. */
169 TS2_IMAP0_REGNUM
= 32,
170 TS2_DMAP_REGNUM
= 34,
171 TS2_NR_DMAP_REGS
= 1,
176 d10v_ts2_register_name (int reg_nr
)
178 static char *register_names
[] =
180 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
182 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
183 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
184 "imap0", "imap1", "dmap", "a0", "a1"
188 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
190 return register_names
[reg_nr
];
195 TS3_IMAP0_REGNUM
= 36,
196 TS3_DMAP0_REGNUM
= 38,
197 TS3_NR_DMAP_REGS
= 4,
202 d10v_ts3_register_name (int reg_nr
)
204 static char *register_names
[] =
206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c",
209 "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15",
213 "dmap0", "dmap1", "dmap2", "dmap3"
217 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
219 return register_names
[reg_nr
];
222 /* Access the DMAP/IMAP registers in a target independent way.
224 Divide the D10V's 64k data space into four 16k segments:
225 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and
228 On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 --
229 0x7fff) always map to the on-chip data RAM, and the fourth always
230 maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into
231 unified memory or instruction memory, under the control of the
232 single DMAP register.
234 On the TS3, there are four DMAP registers, each of which controls
235 one of the segments. */
238 d10v_ts2_dmap_register (int reg_nr
)
246 return read_register (TS2_DMAP_REGNUM
);
253 d10v_ts3_dmap_register (int reg_nr
)
255 return read_register (TS3_DMAP0_REGNUM
+ reg_nr
);
259 d10v_dmap_register (int reg_nr
)
261 return gdbarch_tdep (current_gdbarch
)->dmap_register (reg_nr
);
265 d10v_ts2_imap_register (int reg_nr
)
267 return read_register (TS2_IMAP0_REGNUM
+ reg_nr
);
271 d10v_ts3_imap_register (int reg_nr
)
273 return read_register (TS3_IMAP0_REGNUM
+ reg_nr
);
277 d10v_imap_register (int reg_nr
)
279 return gdbarch_tdep (current_gdbarch
)->imap_register (reg_nr
);
282 /* MAP GDB's internal register numbering (determined by the layout fo
283 the REGISTER_BYTE array) onto the simulator's register
287 d10v_ts2_register_sim_regno (int nr
)
289 /* Only makes sense to supply raw registers. */
290 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
291 if (nr
>= TS2_IMAP0_REGNUM
292 && nr
< TS2_IMAP0_REGNUM
+ NR_IMAP_REGS
)
293 return nr
- TS2_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
294 if (nr
== TS2_DMAP_REGNUM
)
295 return nr
- TS2_DMAP_REGNUM
+ SIM_D10V_TS2_DMAP_REGNUM
;
296 if (nr
>= TS2_A0_REGNUM
297 && nr
< TS2_A0_REGNUM
+ NR_A_REGS
)
298 return nr
- TS2_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
303 d10v_ts3_register_sim_regno (int nr
)
305 /* Only makes sense to supply raw registers. */
306 gdb_assert (nr
>= 0 && nr
< NUM_REGS
);
307 if (nr
>= TS3_IMAP0_REGNUM
308 && nr
< TS3_IMAP0_REGNUM
+ NR_IMAP_REGS
)
309 return nr
- TS3_IMAP0_REGNUM
+ SIM_D10V_IMAP0_REGNUM
;
310 if (nr
>= TS3_DMAP0_REGNUM
311 && nr
< TS3_DMAP0_REGNUM
+ TS3_NR_DMAP_REGS
)
312 return nr
- TS3_DMAP0_REGNUM
+ SIM_D10V_DMAP0_REGNUM
;
313 if (nr
>= TS3_A0_REGNUM
314 && nr
< TS3_A0_REGNUM
+ NR_A_REGS
)
315 return nr
- TS3_A0_REGNUM
+ SIM_D10V_A0_REGNUM
;
319 /* Return the GDB type object for the "standard" data type
320 of data in register N. */
323 d10v_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
325 if (reg_nr
== PC_REGNUM
)
326 return builtin_type_void_func_ptr
;
327 if (reg_nr
== D10V_SP_REGNUM
|| reg_nr
== D10V_FP_REGNUM
)
328 return builtin_type_void_data_ptr
;
329 else if (reg_nr
>= a0_regnum (gdbarch
)
330 && reg_nr
< (a0_regnum (gdbarch
) + NR_A_REGS
))
331 return builtin_type_int64
;
333 return builtin_type_int16
;
337 d10v_daddr_p (CORE_ADDR x
)
339 return (((x
) & 0x3000000) == DMEM_START
);
343 d10v_iaddr_p (CORE_ADDR x
)
345 return (((x
) & 0x3000000) == IMEM_START
);
349 d10v_make_daddr (CORE_ADDR x
)
351 return ((x
) | DMEM_START
);
355 d10v_make_iaddr (CORE_ADDR x
)
357 if (d10v_iaddr_p (x
))
358 return x
; /* Idempotency -- x is already in the IMEM space. */
360 return (((x
) << 2) | IMEM_START
);
364 d10v_convert_iaddr_to_raw (CORE_ADDR x
)
366 return (((x
) >> 2) & 0xffff);
370 d10v_convert_daddr_to_raw (CORE_ADDR x
)
372 return ((x
) & 0xffff);
376 d10v_address_to_pointer (struct type
*type
, void *buf
, CORE_ADDR addr
)
378 /* Is it a code address? */
379 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
380 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
)
382 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
383 d10v_convert_iaddr_to_raw (addr
));
387 /* Strip off any upper segment bits. */
388 store_unsigned_integer (buf
, TYPE_LENGTH (type
),
389 d10v_convert_daddr_to_raw (addr
));
394 d10v_pointer_to_address (struct type
*type
, const void *buf
)
396 CORE_ADDR addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
397 /* Is it a code address? */
398 if (TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_FUNC
399 || TYPE_CODE (TYPE_TARGET_TYPE (type
)) == TYPE_CODE_METHOD
400 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type
)))
401 return d10v_make_iaddr (addr
);
403 return d10v_make_daddr (addr
);
406 /* Don't do anything if we have an integer, this way users can type 'x
407 <addr>' w/o having gdb outsmart them. The internal gdb conversions
408 to the correct space are taken care of in the pointer_to_address
409 function. If we don't do this, 'x $fp' wouldn't work. */
411 d10v_integer_to_address (struct type
*type
, void *buf
)
414 val
= unpack_long (type
, buf
);
418 /* Write into appropriate registers a function return value
419 of type TYPE, given in virtual format.
421 Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */
424 d10v_store_return_value (struct type
*type
, struct regcache
*regcache
,
427 /* Only char return values need to be shifted right within the first
429 if (TYPE_LENGTH (type
) == 1
430 && TYPE_CODE (type
) == TYPE_CODE_INT
)
433 tmp
[1] = *(bfd_byte
*)valbuf
;
434 regcache_cooked_write (regcache
, RET1_REGNUM
, tmp
);
439 /* A structure is never more than 8 bytes long. See
440 use_struct_convention(). */
441 gdb_assert (TYPE_LENGTH (type
) <= 8);
442 /* Write out most registers, stop loop before trying to write
443 out any dangling byte at the end of the buffer. */
444 for (reg
= 0; (reg
* 2) + 1 < TYPE_LENGTH (type
); reg
++)
446 regcache_cooked_write (regcache
, RET1_REGNUM
+ reg
,
447 (bfd_byte
*) valbuf
+ reg
* 2);
449 /* Write out any dangling byte at the end of the buffer. */
450 if ((reg
* 2) + 1 == TYPE_LENGTH (type
))
451 regcache_cooked_write_part (regcache
, reg
, 0, 1,
452 (bfd_byte
*) valbuf
+ reg
* 2);
456 /* Extract from an array REGBUF containing the (raw) register state
457 the address in which a function should return its structure value,
458 as a CORE_ADDR (or an expression that can be used as one). */
461 d10v_extract_struct_value_address (struct regcache
*regcache
)
464 regcache_cooked_read_unsigned (regcache
, ARG1_REGNUM
, &addr
);
465 return (addr
| DMEM_START
);
469 check_prologue (unsigned short op
)
472 if ((op
& 0x7E1F) == 0x6C1F)
476 if ((op
& 0x7E3F) == 0x6E1F)
480 if ((op
& 0x7FE1) == 0x01E1)
492 if ((op
& 0x7E1F) == 0x681E)
496 if ((op
& 0x7E3F) == 0x3A1E)
503 d10v_skip_prologue (CORE_ADDR pc
)
506 unsigned short op1
, op2
;
507 CORE_ADDR func_addr
, func_end
;
508 struct symtab_and_line sal
;
510 /* If we have line debugging information, then the end of the */
511 /* prologue should the first assembly instruction of the first source line */
512 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
514 sal
= find_pc_line (func_addr
, 0);
515 if (sal
.end
&& sal
.end
< func_end
)
519 if (target_read_memory (pc
, (char *) &op
, 4))
520 return pc
; /* Can't access it -- assume no prologue. */
524 op
= (unsigned long) read_memory_integer (pc
, 4);
525 if ((op
& 0xC0000000) == 0xC0000000)
527 /* long instruction */
528 if (((op
& 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */
529 ((op
& 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */
530 ((op
& 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */
535 /* short instructions */
536 if ((op
& 0xC0000000) == 0x80000000)
538 op2
= (op
& 0x3FFF8000) >> 15;
543 op1
= (op
& 0x3FFF8000) >> 15;
546 if (check_prologue (op1
))
548 if (!check_prologue (op2
))
550 /* if the previous opcode was really part of the prologue */
551 /* and not just a NOP, then we want to break after both instructions */
565 struct d10v_unwind_cache
568 /* The previous frame's inner most stack address. Used as this
569 frame ID's stack_addr. */
571 /* The frame's base, optionally used by the high-level debug info. */
574 CORE_ADDR
*saved_regs
;
575 /* How far the SP and r11 (FP) have been offset from the start of
576 the stack frame (as defined by the previous frame's stack
585 prologue_find_regs (struct d10v_unwind_cache
*info
, unsigned short op
,
591 if ((op
& 0x7E1F) == 0x6C1F)
593 n
= (op
& 0x1E0) >> 5;
594 info
->sp_offset
-= 2;
595 info
->saved_regs
[n
] = info
->sp_offset
;
600 else if ((op
& 0x7E3F) == 0x6E1F)
602 n
= (op
& 0x1E0) >> 5;
603 info
->sp_offset
-= 4;
604 info
->saved_regs
[n
] = info
->sp_offset
;
605 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
610 if ((op
& 0x7FE1) == 0x01E1)
612 n
= (op
& 0x1E) >> 1;
615 info
->sp_offset
-= n
;
622 info
->uses_frame
= 1;
623 info
->r11_offset
= info
->sp_offset
;
628 if ((op
& 0x7E1F) == 0x6816)
630 n
= (op
& 0x1E0) >> 5;
631 info
->saved_regs
[n
] = info
->r11_offset
;
640 if ((op
& 0x7E1F) == 0x681E)
642 n
= (op
& 0x1E0) >> 5;
643 info
->saved_regs
[n
] = info
->sp_offset
;
648 if ((op
& 0x7E3F) == 0x3A1E)
650 n
= (op
& 0x1E0) >> 5;
651 info
->saved_regs
[n
] = info
->sp_offset
;
652 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ 2;
659 /* Put here the code to store, into fi->saved_regs, the addresses of
660 the saved registers of frame described by FRAME_INFO. This
661 includes special registers such as pc and fp saved in special ways
662 in the stack frame. sp is even more special: the address we return
663 for it IS the sp for the next frame. */
665 struct d10v_unwind_cache
*
666 d10v_frame_unwind_cache (struct frame_info
*next_frame
,
667 void **this_prologue_cache
)
673 unsigned short op1
, op2
;
675 struct d10v_unwind_cache
*info
;
677 if ((*this_prologue_cache
))
678 return (*this_prologue_cache
);
680 info
= FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache
);
681 (*this_prologue_cache
) = info
;
682 info
->saved_regs
= FRAME_OBSTACK_CALLOC (NUM_REGS
, CORE_ADDR
);
688 info
->uses_frame
= 0;
689 for (pc
= frame_func_unwind (next_frame
);
690 pc
> 0 && pc
< frame_pc_unwind (next_frame
);
693 op
= (unsigned long) read_memory_integer (pc
, 4);
694 if ((op
& 0xC0000000) == 0xC0000000)
696 /* long instruction */
697 if ((op
& 0x3FFF0000) == 0x01FF0000)
700 short n
= op
& 0xFFFF;
701 info
->sp_offset
+= n
;
703 else if ((op
& 0x3F0F0000) == 0x340F0000)
705 /* st rn, @(offset,sp) */
706 short offset
= op
& 0xFFFF;
707 short n
= (op
>> 20) & 0xF;
708 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
710 else if ((op
& 0x3F1F0000) == 0x350F0000)
712 /* st2w rn, @(offset,sp) */
713 short offset
= op
& 0xFFFF;
714 short n
= (op
>> 20) & 0xF;
715 info
->saved_regs
[n
] = info
->sp_offset
+ offset
;
716 info
->saved_regs
[n
+ 1] = info
->sp_offset
+ offset
+ 2;
723 /* short instructions */
724 if ((op
& 0xC0000000) == 0x80000000)
726 op2
= (op
& 0x3FFF8000) >> 15;
731 op1
= (op
& 0x3FFF8000) >> 15;
734 if (!prologue_find_regs (info
, op1
, pc
)
735 || !prologue_find_regs (info
, op2
, pc
))
740 info
->size
= -info
->sp_offset
;
742 /* Compute the frame's base, and the previous frame's SP. */
743 if (info
->uses_frame
)
745 /* The SP was moved to the FP. This indicates that a new frame
746 was created. Get THIS frame's FP value by unwinding it from
748 frame_unwind_unsigned_register (next_frame
, D10V_FP_REGNUM
, &this_base
);
749 /* The FP points at the last saved register. Adjust the FP back
750 to before the first saved register giving the SP. */
751 prev_sp
= this_base
+ info
->size
;
753 else if (info
->saved_regs
[D10V_SP_REGNUM
])
755 /* The SP was saved (which is very unusual), the frame base is
756 just the PREV's frame's TOP-OF-STACK. */
757 this_base
= read_memory_unsigned_integer (info
->saved_regs
[D10V_SP_REGNUM
],
758 register_size (current_gdbarch
,
764 /* Assume that the FP is this frame's SP but with that pushed
765 stack space added back. */
766 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &this_base
);
767 prev_sp
= this_base
+ info
->size
;
770 info
->base
= d10v_make_daddr (this_base
);
771 info
->prev_sp
= d10v_make_daddr (prev_sp
);
773 /* Adjust all the saved registers so that they contain addresses and
775 for (i
= 0; i
< NUM_REGS
- 1; i
++)
776 if (info
->saved_regs
[i
])
778 info
->saved_regs
[i
] = (info
->prev_sp
+ info
->saved_regs
[i
]);
781 if (info
->saved_regs
[LR_REGNUM
])
784 = read_memory_unsigned_integer (info
->saved_regs
[LR_REGNUM
],
785 register_size (current_gdbarch
, LR_REGNUM
));
786 info
->return_pc
= d10v_make_iaddr (return_pc
);
791 frame_unwind_unsigned_register (next_frame
, LR_REGNUM
, &return_pc
);
792 info
->return_pc
= d10v_make_iaddr (return_pc
);
795 /* The D10V_SP_REGNUM is special. Instead of the address of the SP, the
796 previous frame's SP value is saved. */
797 info
->saved_regs
[D10V_SP_REGNUM
] = info
->prev_sp
;
803 d10v_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
804 struct frame_info
*frame
, int regnum
, int all
)
808 default_print_registers_info (gdbarch
, file
, frame
, regnum
, all
);
813 ULONGEST pc
, psw
, rpt_s
, rpt_e
, rpt_c
;
814 frame_read_unsigned_register (frame
, PC_REGNUM
, &pc
);
815 frame_read_unsigned_register (frame
, PSW_REGNUM
, &psw
);
816 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_s", -1), &rpt_s
);
817 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_e", -1), &rpt_e
);
818 frame_read_unsigned_register (frame
, frame_map_name_to_regnum ("rpt_c", -1), &rpt_c
);
819 fprintf_filtered (file
, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n",
820 (long) pc
, (long) d10v_make_iaddr (pc
), (long) psw
,
821 (long) rpt_s
, (long) rpt_e
, (long) rpt_c
);
826 for (group
= 0; group
< 16; group
+= 8)
829 fprintf_filtered (file
, "R%d-R%-2d", group
, group
+ 7);
830 for (r
= group
; r
< group
+ 8; r
++)
833 frame_read_unsigned_register (frame
, r
, &tmp
);
834 fprintf_filtered (file
, " %04lx", (long) tmp
);
836 fprintf_filtered (file
, "\n");
840 /* Note: The IMAP/DMAP registers don't participate in function
841 calls. Don't bother trying to unwind them. */
845 for (a
= 0; a
< NR_IMAP_REGS
; a
++)
848 fprintf_filtered (file
, " ");
849 fprintf_filtered (file
, "IMAP%d %04lx", a
, d10v_imap_register (a
));
851 if (nr_dmap_regs (gdbarch
) == 1)
852 /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */
853 fprintf_filtered (file
, " DMAP %04lx\n", d10v_dmap_register (2));
856 for (a
= 0; a
< nr_dmap_regs (gdbarch
); a
++)
858 fprintf_filtered (file
, " DMAP%d %04lx", a
, d10v_dmap_register (a
));
860 fprintf_filtered (file
, "\n");
865 char *num
= alloca (max_register_size (gdbarch
));
867 fprintf_filtered (file
, "A0-A%d", NR_A_REGS
- 1);
868 for (a
= a0_regnum (gdbarch
); a
< a0_regnum (gdbarch
) + NR_A_REGS
; a
++)
871 fprintf_filtered (file
, " ");
872 frame_read_register (frame
, a
, num
);
873 for (i
= 0; i
< register_size (current_gdbarch
, a
); i
++)
875 fprintf_filtered (file
, "%02x", (num
[i
] & 0xff));
879 fprintf_filtered (file
, "\n");
883 show_regs (char *args
, int from_tty
)
885 d10v_print_registers_info (current_gdbarch
, gdb_stdout
,
886 get_current_frame (), -1, 1);
890 d10v_read_pc (ptid_t ptid
)
896 save_ptid
= inferior_ptid
;
897 inferior_ptid
= ptid
;
898 pc
= (int) read_register (PC_REGNUM
);
899 inferior_ptid
= save_ptid
;
900 retval
= d10v_make_iaddr (pc
);
905 d10v_write_pc (CORE_ADDR val
, ptid_t ptid
)
909 save_ptid
= inferior_ptid
;
910 inferior_ptid
= ptid
;
911 write_register (PC_REGNUM
, d10v_convert_iaddr_to_raw (val
));
912 inferior_ptid
= save_ptid
;
918 return (d10v_make_daddr (read_register (D10V_SP_REGNUM
)));
924 return (d10v_make_daddr (read_register (D10V_FP_REGNUM
)));
927 /* When arguments must be pushed onto the stack, they go on in reverse
928 order. The below implements a FILO (stack) to do this. */
933 struct stack_item
*prev
;
937 static struct stack_item
*push_stack_item (struct stack_item
*prev
,
938 void *contents
, int len
);
939 static struct stack_item
*
940 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
942 struct stack_item
*si
;
943 si
= xmalloc (sizeof (struct stack_item
));
944 si
->data
= xmalloc (len
);
947 memcpy (si
->data
, contents
, len
);
951 static struct stack_item
*pop_stack_item (struct stack_item
*si
);
952 static struct stack_item
*
953 pop_stack_item (struct stack_item
*si
)
955 struct stack_item
*dead
= si
;
964 d10v_push_dummy_call (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
965 CORE_ADDR dummy_addr
, int nargs
, struct value
**args
,
966 CORE_ADDR sp
, int struct_return
, CORE_ADDR struct_addr
)
969 int regnum
= ARG1_REGNUM
;
970 struct stack_item
*si
= NULL
;
973 /* Set the return address. For the d10v, the return breakpoint is
974 always at DUMMY_ADDR. */
975 regcache_cooked_write_unsigned (regcache
, LR_REGNUM
,
976 d10v_convert_iaddr_to_raw (dummy_addr
));
978 /* If STRUCT_RETURN is true, then the struct return address (in
979 STRUCT_ADDR) will consume the first argument-passing register.
980 Both adjust the register count and store that value. */
983 regcache_cooked_write_unsigned (regcache
, regnum
, struct_addr
);
987 /* Fill in registers and arg lists */
988 for (i
= 0; i
< nargs
; i
++)
990 struct value
*arg
= args
[i
];
991 struct type
*type
= check_typedef (VALUE_TYPE (arg
));
992 char *contents
= VALUE_CONTENTS (arg
);
993 int len
= TYPE_LENGTH (type
);
994 int aligned_regnum
= (regnum
+ 1) & ~1;
996 /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */
997 if (len
<= 2 && regnum
<= ARGN_REGNUM
)
998 /* fits in a single register, do not align */
1000 val
= extract_unsigned_integer (contents
, len
);
1001 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1003 else if (len
<= (ARGN_REGNUM
- aligned_regnum
+ 1) * 2)
1004 /* value fits in remaining registers, store keeping left
1008 regnum
= aligned_regnum
;
1009 for (b
= 0; b
< (len
& ~1); b
+= 2)
1011 val
= extract_unsigned_integer (&contents
[b
], 2);
1012 regcache_cooked_write_unsigned (regcache
, regnum
++, val
);
1016 val
= extract_unsigned_integer (&contents
[b
], 1);
1017 regcache_cooked_write_unsigned (regcache
, regnum
++, (val
<< 8));
1022 /* arg will go onto stack */
1023 regnum
= ARGN_REGNUM
+ 1;
1024 si
= push_stack_item (si
, contents
, len
);
1030 sp
= (sp
- si
->len
) & ~1;
1031 write_memory (sp
, si
->data
, si
->len
);
1032 si
= pop_stack_item (si
);
1035 /* Finally, update the SP register. */
1036 regcache_cooked_write_unsigned (regcache
, D10V_SP_REGNUM
,
1037 d10v_convert_daddr_to_raw (sp
));
1043 /* Given a return value in `regbuf' with a type `valtype',
1044 extract and copy its value into `valbuf'. */
1047 d10v_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1051 if (TYPE_LENGTH (type
) == 1)
1054 regcache_cooked_read_unsigned (regcache
, RET1_REGNUM
, &c
);
1055 store_unsigned_integer (valbuf
, 1, c
);
1059 /* For return values of odd size, the first byte is in the
1060 least significant part of the first register. The
1061 remaining bytes in remaining registers. Interestingly, when
1062 such values are passed in, the last byte is in the most
1063 significant byte of that same register - wierd. */
1064 int reg
= RET1_REGNUM
;
1066 if (TYPE_LENGTH (type
) & 1)
1068 regcache_cooked_read_part (regcache
, RET1_REGNUM
, 1, 1,
1069 (bfd_byte
*)valbuf
+ off
);
1073 /* Transfer the remaining registers. */
1074 for (; off
< TYPE_LENGTH (type
); reg
++, off
+= 2)
1076 regcache_cooked_read (regcache
, RET1_REGNUM
+ reg
,
1077 (bfd_byte
*) valbuf
+ off
);
1082 /* Translate a GDB virtual ADDR/LEN into a format the remote target
1083 understands. Returns number of bytes that can be transfered
1084 starting at TARG_ADDR. Return ZERO if no bytes can be transfered
1085 (segmentation fault). Since the simulator knows all about how the
1086 VM system works, we just call that to do the translation. */
1089 remote_d10v_translate_xfer_address (CORE_ADDR memaddr
, int nr_bytes
,
1090 CORE_ADDR
*targ_addr
, int *targ_len
)
1094 out_len
= sim_d10v_translate_addr (memaddr
, nr_bytes
,
1097 d10v_imap_register
);
1098 *targ_addr
= out_addr
;
1099 *targ_len
= out_len
;
1103 /* The following code implements access to, and display of, the D10V's
1104 instruction trace buffer. The buffer consists of 64K or more
1105 4-byte words of data, of which each words includes an 8-bit count,
1106 an 8-bit segment number, and a 16-bit instruction address.
1108 In theory, the trace buffer is continuously capturing instruction
1109 data that the CPU presents on its "debug bus", but in practice, the
1110 ROMified GDB stub only enables tracing when it continues or steps
1111 the program, and stops tracing when the program stops; so it
1112 actually works for GDB to read the buffer counter out of memory and
1113 then read each trace word. The counter records where the tracing
1114 stops, but there is no record of where it started, so we remember
1115 the PC when we resumed and then search backwards in the trace
1116 buffer for a word that includes that address. This is not perfect,
1117 because you will miss trace data if the resumption PC is the target
1118 of a branch. (The value of the buffer counter is semi-random, any
1119 trace data from a previous program stop is gone.) */
1121 /* The address of the last word recorded in the trace buffer. */
1123 #define DBBC_ADDR (0xd80000)
1125 /* The base of the trace buffer, at least for the "Board_0". */
1127 #define TRACE_BUFFER_BASE (0xf40000)
1129 static void trace_command (char *, int);
1131 static void untrace_command (char *, int);
1133 static void trace_info (char *, int);
1135 static void tdisassemble_command (char *, int);
1137 static void display_trace (int, int);
1139 /* True when instruction traces are being collected. */
1143 /* Remembered PC. */
1145 static CORE_ADDR last_pc
;
1147 /* True when trace output should be displayed whenever program stops. */
1149 static int trace_display
;
1151 /* True when trace listing should include source lines. */
1153 static int default_trace_show_source
= 1;
1164 trace_command (char *args
, int from_tty
)
1166 /* Clear the host-side trace buffer, allocating space if needed. */
1167 trace_data
.size
= 0;
1168 if (trace_data
.counts
== NULL
)
1169 trace_data
.counts
= XCALLOC (65536, short);
1170 if (trace_data
.addrs
== NULL
)
1171 trace_data
.addrs
= XCALLOC (65536, CORE_ADDR
);
1175 printf_filtered ("Tracing is now on.\n");
1179 untrace_command (char *args
, int from_tty
)
1183 printf_filtered ("Tracing is now off.\n");
1187 trace_info (char *args
, int from_tty
)
1191 if (trace_data
.size
)
1193 printf_filtered ("%d entries in trace buffer:\n", trace_data
.size
);
1195 for (i
= 0; i
< trace_data
.size
; ++i
)
1197 printf_filtered ("%d: %d instruction%s at 0x%s\n",
1199 trace_data
.counts
[i
],
1200 (trace_data
.counts
[i
] == 1 ? "" : "s"),
1201 paddr_nz (trace_data
.addrs
[i
]));
1205 printf_filtered ("No entries in trace buffer.\n");
1207 printf_filtered ("Tracing is currently %s.\n", (tracing
? "on" : "off"));
1210 /* Print the instruction at address MEMADDR in debugged memory,
1211 on STREAM. Returns length of the instruction, in bytes. */
1214 print_insn (CORE_ADDR memaddr
, struct ui_file
*stream
)
1216 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1217 tm_print_insn_info
.endian
= BFD_ENDIAN_BIG
;
1219 tm_print_insn_info
.endian
= BFD_ENDIAN_LITTLE
;
1220 return TARGET_PRINT_INSN (memaddr
, &tm_print_insn_info
);
1224 d10v_eva_prepare_to_trace (void)
1229 last_pc
= read_register (PC_REGNUM
);
1232 /* Collect trace data from the target board and format it into a form
1233 more useful for display. */
1236 d10v_eva_get_trace_data (void)
1238 int count
, i
, j
, oldsize
;
1239 int trace_addr
, trace_seg
, trace_cnt
, next_cnt
;
1240 unsigned int last_trace
, trace_word
, next_word
;
1241 unsigned int *tmpspace
;
1246 tmpspace
= xmalloc (65536 * sizeof (unsigned int));
1248 last_trace
= read_memory_unsigned_integer (DBBC_ADDR
, 2) << 2;
1250 /* Collect buffer contents from the target, stopping when we reach
1251 the word recorded when execution resumed. */
1254 while (last_trace
> 0)
1258 read_memory_unsigned_integer (TRACE_BUFFER_BASE
+ last_trace
, 4);
1259 trace_addr
= trace_word
& 0xffff;
1261 /* Ignore an apparently nonsensical entry. */
1262 if (trace_addr
== 0xffd5)
1264 tmpspace
[count
++] = trace_word
;
1265 if (trace_addr
== last_pc
)
1271 /* Move the data to the host-side trace buffer, adjusting counts to
1272 include the last instruction executed and transforming the address
1273 into something that GDB likes. */
1275 for (i
= 0; i
< count
; ++i
)
1277 trace_word
= tmpspace
[i
];
1278 next_word
= ((i
== 0) ? 0 : tmpspace
[i
- 1]);
1279 trace_addr
= trace_word
& 0xffff;
1280 next_cnt
= (next_word
>> 24) & 0xff;
1281 j
= trace_data
.size
+ count
- i
- 1;
1282 trace_data
.addrs
[j
] = (trace_addr
<< 2) + 0x1000000;
1283 trace_data
.counts
[j
] = next_cnt
+ 1;
1286 oldsize
= trace_data
.size
;
1287 trace_data
.size
+= count
;
1292 display_trace (oldsize
, trace_data
.size
);
1296 tdisassemble_command (char *arg
, int from_tty
)
1299 CORE_ADDR low
, high
;
1304 high
= trace_data
.size
;
1308 char *space_index
= strchr (arg
, ' ');
1309 if (space_index
== NULL
)
1311 low
= parse_and_eval_address (arg
);
1316 /* Two arguments. */
1317 *space_index
= '\0';
1318 low
= parse_and_eval_address (arg
);
1319 high
= parse_and_eval_address (space_index
+ 1);
1325 printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low
), paddr_u (high
));
1327 display_trace (low
, high
);
1329 printf_filtered ("End of trace dump.\n");
1330 gdb_flush (gdb_stdout
);
1334 display_trace (int low
, int high
)
1336 int i
, count
, trace_show_source
, first
, suppress
;
1337 CORE_ADDR next_address
;
1339 trace_show_source
= default_trace_show_source
;
1340 if (!have_full_symbols () && !have_partial_symbols ())
1342 trace_show_source
= 0;
1343 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1344 printf_filtered ("Trace will not display any source.\n");
1349 for (i
= low
; i
< high
; ++i
)
1351 next_address
= trace_data
.addrs
[i
];
1352 count
= trace_data
.counts
[i
];
1356 if (trace_show_source
)
1358 struct symtab_and_line sal
, sal_prev
;
1360 sal_prev
= find_pc_line (next_address
- 4, 0);
1361 sal
= find_pc_line (next_address
, 0);
1365 if (first
|| sal
.line
!= sal_prev
.line
)
1366 print_source_lines (sal
.symtab
, sal
.line
, sal
.line
+ 1, 0);
1372 /* FIXME-32x64--assumes sal.pc fits in long. */
1373 printf_filtered ("No source file for address %s.\n",
1374 local_hex_string ((unsigned long) sal
.pc
));
1379 print_address (next_address
, gdb_stdout
);
1380 printf_filtered (":");
1381 printf_filtered ("\t");
1383 next_address
= next_address
+ print_insn (next_address
, gdb_stdout
);
1384 printf_filtered ("\n");
1385 gdb_flush (gdb_stdout
);
1391 d10v_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1394 frame_unwind_unsigned_register (next_frame
, PC_REGNUM
, &pc
);
1395 return d10v_make_iaddr (pc
);
1398 /* Given a GDB frame, determine the address of the calling function's
1399 frame. This will be used to create a new GDB frame struct. */
1402 d10v_frame_this_id (struct frame_info
*next_frame
,
1403 void **this_prologue_cache
,
1404 struct frame_id
*this_id
)
1406 struct d10v_unwind_cache
*info
1407 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1412 /* The FUNC is easy. */
1413 func
= frame_func_unwind (next_frame
);
1415 /* This is meant to halt the backtrace at "_start". Make sure we
1416 don't halt it at a generic dummy frame. */
1417 if (func
<= IMEM_START
|| inside_entry_file (func
))
1420 /* Hopefully the prologue analysis either correctly determined the
1421 frame's base (which is the SP from the previous frame), or set
1422 that base to "NULL". */
1423 base
= info
->prev_sp
;
1424 if (base
== STACK_START
|| base
== 0)
1427 id
= frame_id_build (base
, func
);
1429 /* Check that we're not going round in circles with the same frame
1430 ID (but avoid applying the test to sentinel frames which do go
1431 round in circles). Can't use frame_id_eq() as that doesn't yet
1432 compare the frame's PC value. */
1433 if (frame_relative_level (next_frame
) >= 0
1434 && get_frame_type (next_frame
) != DUMMY_FRAME
1435 && frame_id_eq (get_frame_id (next_frame
), id
))
1442 saved_regs_unwinder (struct frame_info
*next_frame
,
1443 CORE_ADDR
*this_saved_regs
,
1444 int regnum
, int *optimizedp
,
1445 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1446 int *realnump
, void *bufferp
)
1448 if (this_saved_regs
[regnum
] != 0)
1450 if (regnum
== D10V_SP_REGNUM
)
1452 /* SP register treated specially. */
1457 if (bufferp
!= NULL
)
1458 store_unsigned_integer (bufferp
,
1459 register_size (current_gdbarch
, regnum
),
1460 this_saved_regs
[regnum
]);
1464 /* Any other register is saved in memory, fetch it but cache
1465 a local copy of its value. */
1467 *lvalp
= lval_memory
;
1468 *addrp
= this_saved_regs
[regnum
];
1470 if (bufferp
!= NULL
)
1472 /* Read the value in from memory. */
1473 read_memory (this_saved_regs
[regnum
], bufferp
,
1474 register_size (current_gdbarch
, regnum
));
1480 /* No luck, assume this and the next frame have the same register
1481 value. If a value is needed, pass the request on down the chain;
1482 otherwise just return an indication that the value is in the same
1483 register as the next frame. */
1484 frame_register_unwind (next_frame
, regnum
, optimizedp
, lvalp
, addrp
,
1490 d10v_frame_prev_register (struct frame_info
*next_frame
,
1491 void **this_prologue_cache
,
1492 int regnum
, int *optimizedp
,
1493 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1494 int *realnump
, void *bufferp
)
1496 struct d10v_unwind_cache
*info
1497 = d10v_frame_unwind_cache (next_frame
, this_prologue_cache
);
1498 if (regnum
== PC_REGNUM
)
1500 /* The call instruction saves the caller's PC in LR. The
1501 function prologue of the callee may then save the LR on the
1502 stack. Find that possibly saved LR value and return it. */
1503 saved_regs_unwinder (next_frame
, info
->saved_regs
, LR_REGNUM
, optimizedp
,
1504 lvalp
, addrp
, realnump
, bufferp
);
1508 saved_regs_unwinder (next_frame
, info
->saved_regs
, regnum
, optimizedp
,
1509 lvalp
, addrp
, realnump
, bufferp
);
1513 static const struct frame_unwind d10v_frame_unwind
= {
1516 d10v_frame_prev_register
1519 const struct frame_unwind
*
1520 d10v_frame_p (CORE_ADDR pc
)
1522 return &d10v_frame_unwind
;
1526 d10v_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1528 struct d10v_unwind_cache
*info
1529 = d10v_frame_unwind_cache (next_frame
, this_cache
);
1533 static const struct frame_base d10v_frame_base
= {
1535 d10v_frame_base_address
,
1536 d10v_frame_base_address
,
1537 d10v_frame_base_address
1540 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1541 dummy frame. The frame ID's base needs to match the TOS value
1542 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1545 static struct frame_id
1546 d10v_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1549 frame_unwind_unsigned_register (next_frame
, D10V_SP_REGNUM
, &base
);
1550 return frame_id_build (d10v_make_daddr (base
), frame_pc_unwind (next_frame
));
1553 static gdbarch_init_ftype d10v_gdbarch_init
;
1555 static struct gdbarch
*
1556 d10v_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1558 struct gdbarch
*gdbarch
;
1560 struct gdbarch_tdep
*tdep
;
1561 gdbarch_register_name_ftype
*d10v_register_name
;
1562 gdbarch_register_sim_regno_ftype
*d10v_register_sim_regno
;
1564 /* Find a candidate among the list of pre-declared architectures. */
1565 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1567 return arches
->gdbarch
;
1569 /* None found, create a new architecture from the information
1571 tdep
= XMALLOC (struct gdbarch_tdep
);
1572 gdbarch
= gdbarch_alloc (&info
, tdep
);
1574 switch (info
.bfd_arch_info
->mach
)
1576 case bfd_mach_d10v_ts2
:
1578 d10v_register_name
= d10v_ts2_register_name
;
1579 d10v_register_sim_regno
= d10v_ts2_register_sim_regno
;
1580 tdep
->a0_regnum
= TS2_A0_REGNUM
;
1581 tdep
->nr_dmap_regs
= TS2_NR_DMAP_REGS
;
1582 tdep
->dmap_register
= d10v_ts2_dmap_register
;
1583 tdep
->imap_register
= d10v_ts2_imap_register
;
1586 case bfd_mach_d10v_ts3
:
1588 d10v_register_name
= d10v_ts3_register_name
;
1589 d10v_register_sim_regno
= d10v_ts3_register_sim_regno
;
1590 tdep
->a0_regnum
= TS3_A0_REGNUM
;
1591 tdep
->nr_dmap_regs
= TS3_NR_DMAP_REGS
;
1592 tdep
->dmap_register
= d10v_ts3_dmap_register
;
1593 tdep
->imap_register
= d10v_ts3_imap_register
;
1597 set_gdbarch_read_pc (gdbarch
, d10v_read_pc
);
1598 set_gdbarch_write_pc (gdbarch
, d10v_write_pc
);
1599 set_gdbarch_read_fp (gdbarch
, d10v_read_fp
);
1600 set_gdbarch_read_sp (gdbarch
, d10v_read_sp
);
1602 set_gdbarch_num_regs (gdbarch
, d10v_num_regs
);
1603 set_gdbarch_sp_regnum (gdbarch
, D10V_SP_REGNUM
);
1604 set_gdbarch_pc_regnum (gdbarch
, 18);
1605 set_gdbarch_register_name (gdbarch
, d10v_register_name
);
1606 set_gdbarch_register_size (gdbarch
, 2);
1607 set_gdbarch_register_bytes (gdbarch
, (d10v_num_regs
- 2) * 2 + 16);
1608 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
1609 set_gdbarch_register_type (gdbarch
, d10v_register_type
);
1611 set_gdbarch_ptr_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1612 set_gdbarch_addr_bit (gdbarch
, 32);
1613 set_gdbarch_address_to_pointer (gdbarch
, d10v_address_to_pointer
);
1614 set_gdbarch_pointer_to_address (gdbarch
, d10v_pointer_to_address
);
1615 set_gdbarch_integer_to_address (gdbarch
, d10v_integer_to_address
);
1616 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1617 set_gdbarch_int_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
1618 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1619 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1620 /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
1621 double'' is 64 bits. */
1622 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1623 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
1624 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
1625 switch (info
.byte_order
)
1627 case BFD_ENDIAN_BIG
:
1628 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
1629 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_big
);
1630 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
1632 case BFD_ENDIAN_LITTLE
:
1633 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
1634 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_single_little
);
1635 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_little
);
1638 internal_error (__FILE__
, __LINE__
,
1639 "d10v_gdbarch_init: bad byte order for float format");
1642 set_gdbarch_extract_return_value (gdbarch
, d10v_extract_return_value
);
1643 set_gdbarch_push_dummy_call (gdbarch
, d10v_push_dummy_call
);
1644 set_gdbarch_store_return_value (gdbarch
, d10v_store_return_value
);
1645 set_gdbarch_extract_struct_value_address (gdbarch
, d10v_extract_struct_value_address
);
1646 set_gdbarch_use_struct_convention (gdbarch
, d10v_use_struct_convention
);
1648 set_gdbarch_skip_prologue (gdbarch
, d10v_skip_prologue
);
1649 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1650 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
1651 set_gdbarch_function_start_offset (gdbarch
, 0);
1652 set_gdbarch_breakpoint_from_pc (gdbarch
, d10v_breakpoint_from_pc
);
1654 set_gdbarch_remote_translate_xfer_address (gdbarch
, remote_d10v_translate_xfer_address
);
1656 set_gdbarch_frame_args_skip (gdbarch
, 0);
1657 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
1659 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
1660 set_gdbarch_stack_align (gdbarch
, d10v_stack_align
);
1662 set_gdbarch_register_sim_regno (gdbarch
, d10v_register_sim_regno
);
1664 set_gdbarch_print_registers_info (gdbarch
, d10v_print_registers_info
);
1666 frame_unwind_append_predicate (gdbarch
, d10v_frame_p
);
1667 frame_base_set_default (gdbarch
, &d10v_frame_base
);
1669 /* Methods for saving / extracting a dummy frame's ID. */
1670 set_gdbarch_unwind_dummy_id (gdbarch
, d10v_unwind_dummy_id
);
1671 set_gdbarch_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
1673 /* Return the unwound PC value. */
1674 set_gdbarch_unwind_pc (gdbarch
, d10v_unwind_pc
);
1680 _initialize_d10v_tdep (void)
1682 register_gdbarch_init (bfd_arch_d10v
, d10v_gdbarch_init
);
1684 tm_print_insn
= print_insn_d10v
;
1686 target_resume_hook
= d10v_eva_prepare_to_trace
;
1687 target_wait_loop_hook
= d10v_eva_get_trace_data
;
1689 deprecate_cmd (add_com ("regs", class_vars
, show_regs
, "Print all registers"),
1692 add_com ("itrace", class_support
, trace_command
,
1693 "Enable tracing of instruction execution.");
1695 add_com ("iuntrace", class_support
, untrace_command
,
1696 "Disable tracing of instruction execution.");
1698 add_com ("itdisassemble", class_vars
, tdisassemble_command
,
1699 "Disassemble the trace buffer.\n\
1700 Two optional arguments specify a range of trace buffer entries\n\
1701 as reported by info trace (NOT addresses!).");
1703 add_info ("itrace", trace_info
,
1704 "Display info about the trace data buffer.");
1706 add_setshow_boolean_cmd ("itracedisplay", no_class
, &trace_display
,
1707 "Set automatic display of trace.\n",
1708 "Show automatic display of trace.\n",
1709 NULL
, NULL
, &setlist
, &showlist
);
1710 add_setshow_boolean_cmd ("itracesource", no_class
,
1711 &default_trace_show_source
,
1712 "Set display of source code with trace.\n",
1713 "Show display of source code with trace.\n",
1714 NULL
, NULL
, &setlist
, &showlist
);