2 <!-- Copyright (C) 2009-2022 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 Copying and distribution of this file, with or without modification,
6 are permitted in any medium without royalty provided the copyright
7 notice and this notice are preserved. -->
9 <!DOCTYPE feature SYSTEM
"gdb-target.dtd">
10 <feature name=
"org.gnu.gdb.aarch64.fpu">
11 <vector id=
"v2d" type=
"ieee_double" count=
"2"/>
12 <vector id=
"v2u" type=
"uint64" count=
"2"/>
13 <vector id=
"v2i" type=
"int64" count=
"2"/>
14 <vector id=
"v4f" type=
"ieee_single" count=
"4"/>
15 <vector id=
"v4u" type=
"uint32" count=
"4"/>
16 <vector id=
"v4i" type=
"int32" count=
"4"/>
17 <vector id=
"v8f" type=
"ieee_half" count=
"8"/>
18 <vector id=
"v8u" type=
"uint16" count=
"8"/>
19 <vector id=
"v8i" type=
"int16" count=
"8"/>
20 <vector id=
"v8bf16" type=
"bfloat16" count=
"8"/>
21 <vector id=
"v16u" type=
"uint8" count=
"16"/>
22 <vector id=
"v16i" type=
"int8" count=
"16"/>
23 <vector id=
"v1u" type=
"uint128" count=
"1"/>
24 <vector id=
"v1i" type=
"int128" count=
"1"/>
26 <field name=
"f" type=
"v2d"/>
27 <field name=
"u" type=
"v2u"/>
28 <field name=
"s" type=
"v2i"/>
31 <field name=
"f" type=
"v4f"/>
32 <field name=
"u" type=
"v4u"/>
33 <field name=
"s" type=
"v4i"/>
36 <field name=
"bf" type=
"v8bf16"/>
37 <field name=
"f" type=
"v8f"/>
38 <field name=
"u" type=
"v8u"/>
39 <field name=
"s" type=
"v8i"/>
42 <field name=
"u" type=
"v16u"/>
43 <field name=
"s" type=
"v16i"/>
46 <field name=
"u" type=
"v1u"/>
47 <field name=
"s" type=
"v1i"/>
50 <field name=
"d" type=
"vnd"/>
51 <field name=
"s" type=
"vns"/>
52 <field name=
"h" type=
"vnh"/>
53 <field name=
"b" type=
"vnb"/>
54 <field name=
"q" type=
"vnq"/>
56 <reg name=
"v0" bitsize=
"128" type=
"aarch64v" regnum=
"34"/>
57 <reg name=
"v1" bitsize=
"128" type=
"aarch64v" />
58 <reg name=
"v2" bitsize=
"128" type=
"aarch64v" />
59 <reg name=
"v3" bitsize=
"128" type=
"aarch64v" />
60 <reg name=
"v4" bitsize=
"128" type=
"aarch64v" />
61 <reg name=
"v5" bitsize=
"128" type=
"aarch64v" />
62 <reg name=
"v6" bitsize=
"128" type=
"aarch64v" />
63 <reg name=
"v7" bitsize=
"128" type=
"aarch64v" />
64 <reg name=
"v8" bitsize=
"128" type=
"aarch64v" />
65 <reg name=
"v9" bitsize=
"128" type=
"aarch64v" />
66 <reg name=
"v10" bitsize=
"128" type=
"aarch64v"/>
67 <reg name=
"v11" bitsize=
"128" type=
"aarch64v"/>
68 <reg name=
"v12" bitsize=
"128" type=
"aarch64v"/>
69 <reg name=
"v13" bitsize=
"128" type=
"aarch64v"/>
70 <reg name=
"v14" bitsize=
"128" type=
"aarch64v"/>
71 <reg name=
"v15" bitsize=
"128" type=
"aarch64v"/>
72 <reg name=
"v16" bitsize=
"128" type=
"aarch64v"/>
73 <reg name=
"v17" bitsize=
"128" type=
"aarch64v"/>
74 <reg name=
"v18" bitsize=
"128" type=
"aarch64v"/>
75 <reg name=
"v19" bitsize=
"128" type=
"aarch64v"/>
76 <reg name=
"v20" bitsize=
"128" type=
"aarch64v"/>
77 <reg name=
"v21" bitsize=
"128" type=
"aarch64v"/>
78 <reg name=
"v22" bitsize=
"128" type=
"aarch64v"/>
79 <reg name=
"v23" bitsize=
"128" type=
"aarch64v"/>
80 <reg name=
"v24" bitsize=
"128" type=
"aarch64v"/>
81 <reg name=
"v25" bitsize=
"128" type=
"aarch64v"/>
82 <reg name=
"v26" bitsize=
"128" type=
"aarch64v"/>
83 <reg name=
"v27" bitsize=
"128" type=
"aarch64v"/>
84 <reg name=
"v28" bitsize=
"128" type=
"aarch64v"/>
85 <reg name=
"v29" bitsize=
"128" type=
"aarch64v"/>
86 <reg name=
"v30" bitsize=
"128" type=
"aarch64v"/>
87 <reg name=
"v31" bitsize=
"128" type=
"aarch64v"/>
89 <flags id=
"fpsr_flags" size=
"4">
90 <!-- Invalid Operation cumulative floating-point exception bit. -->
91 <field name=
"IOC" start=
"0" end=
"0"/>
92 <!-- Divide by Zero cumulative floating-point exception bit. -->
93 <field name=
"DZC" start=
"1" end=
"1"/>
94 <!-- Overflow cumulative floating-point exception bit. -->
95 <field name=
"OFC" start=
"2" end=
"2"/>
96 <!-- Underflow cumulative floating-point exception bit. -->
97 <field name=
"UFC" start=
"3" end=
"3"/>
98 <!-- Inexact cumulative floating-point exception bit.. -->
99 <field name=
"IXC" start=
"4" end=
"4"/>
100 <!-- Input Denormal cumulative floating-point exception bit. -->
101 <field name=
"IDC" start=
"7" end=
"7"/>
102 <!-- Cumulative saturation bit, Advanced SIMD only. -->
103 <field name=
"QC" start=
"27" end=
"27"/>
104 <!-- When AArch32 is supported at any Exception level and AArch32
105 floating-point is implemented: Overflow condition flag for AArch32
106 floating-point comparison operations. -->
107 <field name=
"V" start=
"28" end=
"28"/>
108 <!-- When AArch32 is supported at any Exception level and AArch32
109 floating-point is implemented:
110 Carry condition flag for AArch32 floating-point comparison operations.
112 <field name=
"C" start=
"29" end=
"29"/>
113 <!-- When AArch32 is supported at any Exception level and AArch32
114 floating-point is implemented:
115 Zero condition flag for AArch32 floating-point comparison operations.
117 <field name=
"Z" start=
"30" end=
"30"/>
118 <!-- When AArch32 is supported at any Exception level and AArch32
119 floating-point is implemented:
120 Negative condition flag for AArch32 floating-point comparison
122 <field name=
"N" start=
"31" end=
"31"/>
124 <reg name=
"fpsr" bitsize=
"32" type=
"fpsr_flags"/>
126 <flags id=
"fpcr_flags" size=
"4">
127 <!-- Flush Inputs to Zero (part of Armv8.7). -->
128 <field name=
"FIZ" start=
"0" end=
"0"/>
129 <!-- Alternate Handling (part of Armv8.7). -->
130 <field name=
"AH" start=
"1" end=
"1"/>
131 <!-- Controls how the output elements other than the lowest element of the
132 vector are determined for Advanced SIMD scalar instructions (part of
134 <field name=
"NEP" start=
"2" end=
"2"/>
135 <!-- Invalid Operation floating-point exception trap enable. -->
136 <field name=
"IOE" start=
"8" end=
"8"/>
137 <!-- Divide by Zero floating-point exception trap enable. -->
138 <field name=
"DZE" start=
"9" end=
"9"/>
139 <!-- Overflow floating-point exception trap enable. -->
140 <field name=
"OFE" start=
"10" end=
"10"/>
141 <!-- Underflow floating-point exception trap enable. -->
142 <field name=
"UFE" start=
"11" end=
"11"/>
143 <!-- Inexact floating-point exception trap enable. -->
144 <field name=
"IXE" start=
"12" end=
"12"/>
145 <!-- Input Denormal floating-point exception trap enable. -->
146 <field name=
"IDE" start=
"15" end=
"15"/>
147 <!-- Flush-to-zero mode control bit on half-precision data-processing
149 <field name=
"FZ16" start=
"19" end=
"19"/>
150 <!-- Rounding Mode control field. -->
151 <field name=
"RMode" start=
"22" end=
"23"/>
152 <!-- Flush-to-zero mode control bit. -->
153 <field name=
"FZ" start=
"24" end=
"24"/>
154 <!-- Default NaN mode control bit. -->
155 <field name=
"DN" start=
"25" end=
"25"/>
156 <!-- Alternative half-precision control bit. -->
157 <field name=
"AHP" start=
"26" end=
"26"/>
159 <reg name=
"fpcr" bitsize=
"32" type=
"fpcr_flags"/>