1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
30 #include "sim-regno.h"
31 #include "gdb/sim-frv.h"
32 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
42 struct frv_unwind_cache
/* was struct frame_extra_info */
44 /* The previous frame's inner-most stack address. Used as this
45 frame ID's stack_addr. */
48 /* The frame's base, optionally used by the high-level debug info. */
51 /* Table indicating the location of each and every register. */
52 trad_frame_saved_reg
*saved_regs
;
55 /* A structure describing a particular variant of the FRV.
56 We allocate and initialize one of these structures when we create
57 the gdbarch object for a variant.
59 At the moment, all the FR variants we support differ only in which
60 registers are present; the portable code of GDB knows that
61 registers whose names are the empty string don't exist, so the
62 `register_names' array captures all the per-variant information we
65 in the future, if we need to have per-variant maps for raw size,
66 virtual type, etc., we should replace register_names with an array
67 of structures, each of which gives all the necessary info for one
68 register. Don't stick parallel arrays in here --- that's so
70 struct frv_gdbarch_tdep
: gdbarch_tdep
72 /* Which ABI is in use? */
73 enum frv_abi frv_abi
{};
75 /* How many general-purpose registers does this variant have? */
78 /* How many floating-point registers does this variant have? */
81 /* How many hardware watchpoints can it support? */
82 int num_hw_watchpoints
= 0;
84 /* How many hardware breakpoints can it support? */
85 int num_hw_breakpoints
= 0;
88 const char **register_names
= nullptr;
91 /* Return the FR-V ABI associated with GDBARCH. */
93 frv_abi (struct gdbarch
*gdbarch
)
95 frv_gdbarch_tdep
*tdep
= (frv_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
99 /* Fetch the interpreter and executable loadmap addresses (for shared
100 library support) for the FDPIC ABI. Return 0 if successful, -1 if
101 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
103 frv_fdpic_loadmap_addresses (struct gdbarch
*gdbarch
, CORE_ADDR
*interp_addr
,
104 CORE_ADDR
*exec_addr
)
106 if (frv_abi (gdbarch
) != FRV_ABI_FDPIC
)
110 struct regcache
*regcache
= get_current_regcache ();
112 if (interp_addr
!= NULL
)
115 regcache_cooked_read_unsigned (regcache
,
116 fdpic_loadmap_interp_regnum
, &val
);
119 if (exec_addr
!= NULL
)
122 regcache_cooked_read_unsigned (regcache
,
123 fdpic_loadmap_exec_regnum
, &val
);
130 /* Allocate a new variant structure, and set up default values for all
132 static frv_gdbarch_tdep
*
137 frv_gdbarch_tdep
*var
= new frv_gdbarch_tdep
;
139 var
->frv_abi
= FRV_ABI_EABI
;
142 var
->num_hw_watchpoints
= 0;
143 var
->num_hw_breakpoints
= 0;
145 /* By default, don't supply any general-purpose or floating-point
148 = (const char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
149 * sizeof (const char *));
150 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
151 var
->register_names
[r
] = "";
153 /* Do, however, supply default names for the known special-purpose
156 var
->register_names
[pc_regnum
] = "pc";
157 var
->register_names
[lr_regnum
] = "lr";
158 var
->register_names
[lcr_regnum
] = "lcr";
160 var
->register_names
[psr_regnum
] = "psr";
161 var
->register_names
[ccr_regnum
] = "ccr";
162 var
->register_names
[cccr_regnum
] = "cccr";
163 var
->register_names
[tbr_regnum
] = "tbr";
165 /* Debug registers. */
166 var
->register_names
[brr_regnum
] = "brr";
167 var
->register_names
[dbar0_regnum
] = "dbar0";
168 var
->register_names
[dbar1_regnum
] = "dbar1";
169 var
->register_names
[dbar2_regnum
] = "dbar2";
170 var
->register_names
[dbar3_regnum
] = "dbar3";
172 /* iacc0 (Only found on MB93405.) */
173 var
->register_names
[iacc0h_regnum
] = "iacc0h";
174 var
->register_names
[iacc0l_regnum
] = "iacc0l";
175 var
->register_names
[iacc0_regnum
] = "iacc0";
177 /* fsr0 (Found on FR555 and FR501.) */
178 var
->register_names
[fsr0_regnum
] = "fsr0";
180 /* acc0 - acc7. The architecture provides for the possibility of many
181 more (up to 64 total), but we don't want to make that big of a hole
182 in the G packet. If we need more in the future, we'll add them
184 for (r
= acc0_regnum
; r
<= acc7_regnum
; r
++)
187 buf
= xstrprintf ("acc%d", r
- acc0_regnum
);
188 var
->register_names
[r
] = buf
;
191 /* accg0 - accg7: These are one byte registers. The remote protocol
192 provides the raw values packed four into a slot. accg0123 and
193 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
194 We don't provide names for accg0123 and accg4567 since the user will
195 likely not want to see these raw values. */
197 for (r
= accg0_regnum
; r
<= accg7_regnum
; r
++)
200 buf
= xstrprintf ("accg%d", r
- accg0_regnum
);
201 var
->register_names
[r
] = buf
;
206 var
->register_names
[msr0_regnum
] = "msr0";
207 var
->register_names
[msr1_regnum
] = "msr1";
209 /* gner and fner registers. */
210 var
->register_names
[gner0_regnum
] = "gner0";
211 var
->register_names
[gner1_regnum
] = "gner1";
212 var
->register_names
[fner0_regnum
] = "fner0";
213 var
->register_names
[fner1_regnum
] = "fner1";
219 /* Indicate that the variant VAR has NUM_GPRS general-purpose
220 registers, and fill in the names array appropriately. */
222 set_variant_num_gprs (frv_gdbarch_tdep
*var
, int num_gprs
)
226 var
->num_gprs
= num_gprs
;
228 for (r
= 0; r
< num_gprs
; ++r
)
232 xsnprintf (buf
, sizeof (buf
), "gr%d", r
);
233 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
238 /* Indicate that the variant VAR has NUM_FPRS floating-point
239 registers, and fill in the names array appropriately. */
241 set_variant_num_fprs (frv_gdbarch_tdep
*var
, int num_fprs
)
245 var
->num_fprs
= num_fprs
;
247 for (r
= 0; r
< num_fprs
; ++r
)
251 xsnprintf (buf
, sizeof (buf
), "fr%d", r
);
252 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
257 set_variant_abi_fdpic (frv_gdbarch_tdep
*var
)
259 var
->frv_abi
= FRV_ABI_FDPIC
;
260 var
->register_names
[fdpic_loadmap_exec_regnum
] = xstrdup ("loadmap_exec");
261 var
->register_names
[fdpic_loadmap_interp_regnum
]
262 = xstrdup ("loadmap_interp");
266 set_variant_scratch_registers (frv_gdbarch_tdep
*var
)
268 var
->register_names
[scr0_regnum
] = xstrdup ("scr0");
269 var
->register_names
[scr1_regnum
] = xstrdup ("scr1");
270 var
->register_names
[scr2_regnum
] = xstrdup ("scr2");
271 var
->register_names
[scr3_regnum
] = xstrdup ("scr3");
275 frv_register_name (struct gdbarch
*gdbarch
, int reg
)
280 if (reg
>= frv_num_regs
+ frv_num_pseudo_regs
)
283 frv_gdbarch_tdep
*tdep
= (frv_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
284 return tdep
->register_names
[reg
];
289 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
291 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
292 return builtin_type (gdbarch
)->builtin_float
;
293 else if (reg
== iacc0_regnum
)
294 return builtin_type (gdbarch
)->builtin_int64
;
296 return builtin_type (gdbarch
)->builtin_int32
;
299 static enum register_status
300 frv_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
301 int reg
, gdb_byte
*buffer
)
303 enum register_status status
;
305 if (reg
== iacc0_regnum
)
307 status
= regcache
->raw_read (iacc0h_regnum
, buffer
);
308 if (status
== REG_VALID
)
309 status
= regcache
->raw_read (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
311 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
313 /* The accg raw registers have four values in each slot with the
314 lowest register number occupying the first byte. */
316 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
317 int byte_num
= (reg
- accg0_regnum
) % 4;
320 status
= regcache
->raw_read (raw_regnum
, buf
);
321 if (status
== REG_VALID
)
323 memset (buffer
, 0, 4);
324 /* FR-V is big endian, so put the requested byte in the
325 first byte of the buffer allocated to hold the
327 buffer
[0] = buf
[byte_num
];
331 gdb_assert_not_reached ("invalid pseudo register number");
337 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
338 int reg
, const gdb_byte
*buffer
)
340 if (reg
== iacc0_regnum
)
342 regcache
->raw_write (iacc0h_regnum
, buffer
);
343 regcache
->raw_write (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
345 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
347 /* The accg raw registers have four values in each slot with the
348 lowest register number occupying the first byte. */
350 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
351 int byte_num
= (reg
- accg0_regnum
) % 4;
354 regcache
->raw_read (raw_regnum
, buf
);
355 buf
[byte_num
] = ((bfd_byte
*) buffer
)[0];
356 regcache
->raw_write (raw_regnum
, buf
);
361 frv_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
363 static const int spr_map
[] =
365 H_SPR_PSR
, /* psr_regnum */
366 H_SPR_CCR
, /* ccr_regnum */
367 H_SPR_CCCR
, /* cccr_regnum */
368 -1, /* fdpic_loadmap_exec_regnum */
369 -1, /* fdpic_loadmap_interp_regnum */
371 H_SPR_TBR
, /* tbr_regnum */
372 H_SPR_BRR
, /* brr_regnum */
373 H_SPR_DBAR0
, /* dbar0_regnum */
374 H_SPR_DBAR1
, /* dbar1_regnum */
375 H_SPR_DBAR2
, /* dbar2_regnum */
376 H_SPR_DBAR3
, /* dbar3_regnum */
377 H_SPR_SCR0
, /* scr0_regnum */
378 H_SPR_SCR1
, /* scr1_regnum */
379 H_SPR_SCR2
, /* scr2_regnum */
380 H_SPR_SCR3
, /* scr3_regnum */
381 H_SPR_LR
, /* lr_regnum */
382 H_SPR_LCR
, /* lcr_regnum */
383 H_SPR_IACC0H
, /* iacc0h_regnum */
384 H_SPR_IACC0L
, /* iacc0l_regnum */
385 H_SPR_FSR0
, /* fsr0_regnum */
386 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
387 -1, /* acc0_regnum */
388 -1, /* acc1_regnum */
389 -1, /* acc2_regnum */
390 -1, /* acc3_regnum */
391 -1, /* acc4_regnum */
392 -1, /* acc5_regnum */
393 -1, /* acc6_regnum */
394 -1, /* acc7_regnum */
395 -1, /* acc0123_regnum */
396 -1, /* acc4567_regnum */
397 H_SPR_MSR0
, /* msr0_regnum */
398 H_SPR_MSR1
, /* msr1_regnum */
399 H_SPR_GNER0
, /* gner0_regnum */
400 H_SPR_GNER1
, /* gner1_regnum */
401 H_SPR_FNER0
, /* fner0_regnum */
402 H_SPR_FNER1
, /* fner1_regnum */
405 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
407 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
408 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
409 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
410 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
411 else if (pc_regnum
== reg
)
412 return SIM_FRV_PC_REGNUM
;
413 else if (reg
>= first_spr_regnum
414 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
416 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
418 if (spr_reg_offset
< 0)
419 return SIM_REGNO_DOES_NOT_EXIST
;
421 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
424 internal_error (__FILE__
, __LINE__
, _("Bad register number %d"), reg
);
427 constexpr gdb_byte frv_break_insn
[] = {0xc0, 0x70, 0x00, 0x01};
429 typedef BP_MANIPULATION (frv_break_insn
) frv_breakpoint
;
431 /* Define the maximum number of instructions which may be packed into a
432 bundle (VLIW instruction). */
433 static const int max_instrs_per_bundle
= 8;
435 /* Define the size (in bytes) of an FR-V instruction. */
436 static const int frv_instr_size
= 4;
438 /* Adjust a breakpoint's address to account for the FR-V architecture's
439 constraint that a break instruction must not appear as any but the
440 first instruction in the bundle. */
442 frv_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
444 int count
= max_instrs_per_bundle
;
445 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
446 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
448 /* Find the end of the previous packing sequence. This will be indicated
449 by either attempting to access some inaccessible memory or by finding
450 an instruction word whose packing bit is set to one. */
451 while (count
-- > 0 && addr
>= func_start
)
453 gdb_byte instr
[frv_instr_size
];
456 status
= target_read_memory (addr
, instr
, sizeof instr
);
461 /* This is a big endian architecture, so byte zero will have most
462 significant byte. The most significant bit of this byte is the
467 addr
-= frv_instr_size
;
471 bpaddr
= addr
+ frv_instr_size
;
477 /* Return true if REG is a caller-saves ("scratch") register,
480 is_caller_saves_reg (int reg
)
482 return ((4 <= reg
&& reg
<= 7)
483 || (14 <= reg
&& reg
<= 15)
484 || (32 <= reg
&& reg
<= 47));
488 /* Return true if REG is a callee-saves register, false otherwise. */
490 is_callee_saves_reg (int reg
)
492 return ((16 <= reg
&& reg
<= 31)
493 || (48 <= reg
&& reg
<= 63));
497 /* Return true if REG is an argument register, false otherwise. */
499 is_argument_reg (int reg
)
501 return (8 <= reg
&& reg
<= 13);
504 /* Scan an FR-V prologue, starting at PC, until frame->PC.
505 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
506 We assume FRAME's saved_regs array has already been allocated and cleared.
507 Return the first PC value after the prologue.
509 Note that, for unoptimized code, we almost don't need this function
510 at all; all arguments and locals live on the stack, so we just need
511 the FP to find everything. The catch: structures passed by value
512 have their addresses living in registers; they're never spilled to
513 the stack. So if you ever want to be able to get to these
514 arguments in any frame but the top, you'll need to do this serious
515 prologue analysis. */
517 frv_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
518 struct frame_info
*this_frame
,
519 struct frv_unwind_cache
*info
)
521 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
523 /* When writing out instruction bitpatterns, we use the following
524 letters to label instruction fields:
525 P - The parallel bit. We don't use this.
526 J - The register number of GRj in the instruction description.
527 K - The register number of GRk in the instruction description.
528 I - The register number of GRi.
529 S - a signed immediate offset.
530 U - an unsigned immediate offset.
532 The dots below the numbers indicate where hex digit boundaries
533 fall, to make it easier to check the numbers. */
535 /* Non-zero iff we've seen the instruction that initializes the
536 frame pointer for this function's frame. */
539 /* If fp_set is non_zero, then this is the distance from
540 the stack pointer to frame pointer: fp = sp + fp_offset. */
543 /* Total size of frame prior to any alloca operations. */
546 /* Flag indicating if lr has been saved on the stack. */
547 int lr_saved_on_stack
= 0;
549 /* The number of the general-purpose register we saved the return
550 address ("link register") in, or -1 if we haven't moved it yet. */
551 int lr_save_reg
= -1;
553 /* Offset (from sp) at which lr has been saved on the stack. */
555 int lr_sp_offset
= 0;
557 /* If gr_saved[i] is non-zero, then we've noticed that general
558 register i has been saved at gr_sp_offset[i] from the stack
561 int gr_sp_offset
[64];
563 /* The address of the most recently scanned prologue instruction. */
564 CORE_ADDR last_prologue_pc
;
566 /* The address of the next instruction. */
569 /* The upper bound to of the pc values to scan. */
572 memset (gr_saved
, 0, sizeof (gr_saved
));
574 last_prologue_pc
= pc
;
576 /* Try to compute an upper limit (on how far to scan) based on the
578 lim_pc
= skip_prologue_using_sal (gdbarch
, pc
);
579 /* If there's no line number info, lim_pc will be 0. In that case,
580 set the limit to be 100 instructions away from pc. Hopefully, this
581 will be far enough away to account for the entire prologue. Don't
582 worry about overshooting the end of the function. The scan loop
583 below contains some checks to avoid scanning unreasonably far. */
587 /* If we have a frame, we don't want to scan past the frame's pc. This
588 will catch those cases where the pc is in the prologue. */
591 CORE_ADDR frame_pc
= get_frame_pc (this_frame
);
592 if (frame_pc
< lim_pc
)
596 /* Scan the prologue. */
599 gdb_byte buf
[frv_instr_size
];
602 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
604 op
= extract_signed_integer (buf
, sizeof buf
, byte_order
);
608 /* The tests in this chain of ifs should be in order of
609 decreasing selectivity, so that more particular patterns get
610 to fire before less particular patterns. */
612 /* Some sort of control transfer instruction: stop scanning prologue.
613 Integer Conditional Branch:
614 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
615 Floating-point / media Conditional Branch:
616 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
617 LCR Conditional Branch to LR
618 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
619 Integer conditional Branches to LR
620 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
621 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
622 Floating-point/Media Branches to LR
623 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
624 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
626 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
627 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
629 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
631 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
632 Integer Conditional Trap
633 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
634 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
635 Floating-point /media Conditional Trap
636 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
637 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
639 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
641 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
642 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
643 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
644 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
645 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
647 /* Stop scanning; not in prologue any longer. */
651 /* Loading something from memory into fp probably means that
652 we're in the epilogue. Stop scanning the prologue.
654 X 000010 0000010 XXXXXX 000100 XXXXXX
656 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
657 else if ((op
& 0x7ffc0fc0) == 0x04080100
658 || (op
& 0x7ffc0000) == 0x04c80000)
663 /* Setting the FP from the SP:
665 P 000010 0100010 000001 000000000000 = 0x04881000
666 0 111111 1111111 111111 111111111111 = 0x7fffffff
668 We treat this as part of the prologue. */
669 else if ((op
& 0x7fffffff) == 0x04881000)
673 last_prologue_pc
= next_pc
;
676 /* Move the link register to the scratch register grJ, before saving:
678 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
679 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
681 We treat this as part of the prologue. */
682 else if ((op
& 0x7fffffc0) == 0x080d01c0)
684 int gr_j
= op
& 0x3f;
686 /* If we're moving it to a scratch register, that's fine. */
687 if (is_caller_saves_reg (gr_j
))
690 last_prologue_pc
= next_pc
;
694 /* To save multiple callee-saves registers on the stack, at
698 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
699 0 000000 1111111 111111 111111 111111 = 0x01ffffff
702 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
703 0 000000 1111111 111111 111111 111111 = 0x01ffffff
705 We treat this as part of the prologue, and record the register's
706 saved address in the frame structure. */
707 else if ((op
& 0x01ffffff) == 0x000c10c0
708 || (op
& 0x01ffffff) == 0x000c1100)
710 int gr_k
= ((op
>> 25) & 0x3f);
711 int ope
= ((op
>> 6) & 0x3f);
715 /* Is it an std or an stq? */
721 /* Is it really a callee-saves register? */
722 if (is_callee_saves_reg (gr_k
))
724 for (i
= 0; i
< count
; i
++)
726 gr_saved
[gr_k
+ i
] = 1;
727 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
729 last_prologue_pc
= next_pc
;
733 /* Adjusting the stack pointer. (The stack pointer is GR1.)
735 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
736 0 111111 1111111 111111 000000000000 = 0x7ffff000
738 We treat this as part of the prologue. */
739 else if ((op
& 0x7ffff000) == 0x02401000)
743 /* Sign-extend the twelve-bit field.
744 (Isn't there a better way to do this?) */
745 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
748 last_prologue_pc
= pc
;
752 /* If the prologue is being adjusted again, we've
753 likely gone too far; i.e. we're probably in the
759 /* Setting the FP to a constant distance from the SP:
761 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
762 0 111111 1111111 111111 000000000000 = 0x7ffff000
764 We treat this as part of the prologue. */
765 else if ((op
& 0x7ffff000) == 0x04401000)
767 /* Sign-extend the twelve-bit field.
768 (Isn't there a better way to do this?) */
769 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
772 last_prologue_pc
= pc
;
775 /* To spill an argument register to a scratch register:
777 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
778 0 000000 1111111 000000 111111111111 = 0x01fc0fff
780 For the time being, we treat this as a prologue instruction,
781 assuming that GRi is an argument register. This one's kind
782 of suspicious, because it seems like it could be part of a
783 legitimate body instruction. But we only come here when the
784 source info wasn't helpful, so we have to do the best we can.
785 Hopefully once GCC and GDB agree on how to emit line number
786 info for prologues, then this code will never come into play. */
787 else if ((op
& 0x01fc0fff) == 0x00880000)
789 int gr_i
= ((op
>> 12) & 0x3f);
791 /* Make sure that the source is an arg register; if it is, we'll
792 treat it as a prologue instruction. */
793 if (is_argument_reg (gr_i
))
794 last_prologue_pc
= next_pc
;
797 /* To spill 16-bit values to the stack:
799 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
800 0 000000 1111111 111111 000000000000 = 0x01fff000
802 And for 8-bit values, we use STB instructions.
804 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
805 0 000000 1111111 111111 000000000000 = 0x01fff000
807 We check that GRk is really an argument register, and treat
808 all such as part of the prologue. */
809 else if ( (op
& 0x01fff000) == 0x01442000
810 || (op
& 0x01fff000) == 0x01402000)
812 int gr_k
= ((op
>> 25) & 0x3f);
814 /* Make sure that GRk is really an argument register; treat
815 it as a prologue instruction if so. */
816 if (is_argument_reg (gr_k
))
817 last_prologue_pc
= next_pc
;
820 /* To save multiple callee-saves register on the stack, at a
824 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
825 0 000000 1111111 111111 000000000000 = 0x01fff000
828 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
829 0 000000 1111111 111111 000000000000 = 0x01fff000
831 We treat this as part of the prologue, and record the register's
832 saved address in the frame structure. */
833 else if ((op
& 0x01fff000) == 0x014c1000
834 || (op
& 0x01fff000) == 0x01501000)
836 int gr_k
= ((op
>> 25) & 0x3f);
840 /* Is it a stdi or a stqi? */
841 if ((op
& 0x01fff000) == 0x014c1000)
846 /* Is it really a callee-saves register? */
847 if (is_callee_saves_reg (gr_k
))
849 /* Sign-extend the twelve-bit field.
850 (Isn't there a better way to do this?) */
851 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
853 for (i
= 0; i
< count
; i
++)
855 gr_saved
[gr_k
+ i
] = 1;
856 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
858 last_prologue_pc
= next_pc
;
862 /* Storing any kind of integer register at any constant offset
863 from any other register.
866 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
867 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
870 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
871 0 000000 1111111 000000 000000000000 = 0x01fc0000
873 These could be almost anything, but a lot of prologue
874 instructions fall into this pattern, so let's decode the
875 instruction once, and then work at a higher level. */
876 else if (((op
& 0x01fc0fff) == 0x000c0080)
877 || ((op
& 0x01fc0000) == 0x01480000))
879 int gr_k
= ((op
>> 25) & 0x3f);
880 int gr_i
= ((op
>> 12) & 0x3f);
883 /* Are we storing with gr0 as an offset, or using an
885 if ((op
& 0x01fc0fff) == 0x000c0080)
888 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
890 /* If the address isn't relative to the SP or FP, it's not a
891 prologue instruction. */
892 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
894 /* Do nothing; not a prologue instruction. */
897 /* Saving the old FP in the new frame (relative to the SP). */
898 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
900 gr_saved
[fp_regnum
] = 1;
901 gr_sp_offset
[fp_regnum
] = offset
;
902 last_prologue_pc
= next_pc
;
905 /* Saving callee-saves register(s) on the stack, relative to
907 else if (gr_i
== sp_regnum
908 && is_callee_saves_reg (gr_k
))
911 if (gr_i
== sp_regnum
)
912 gr_sp_offset
[gr_k
] = offset
;
914 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
915 last_prologue_pc
= next_pc
;
918 /* Saving the scratch register holding the return address. */
919 else if (lr_save_reg
!= -1
920 && gr_k
== lr_save_reg
)
922 lr_saved_on_stack
= 1;
923 if (gr_i
== sp_regnum
)
924 lr_sp_offset
= offset
;
926 lr_sp_offset
= offset
+ fp_offset
;
927 last_prologue_pc
= next_pc
;
930 /* Spilling int-sized arguments to the stack. */
931 else if (is_argument_reg (gr_k
))
932 last_prologue_pc
= next_pc
;
937 if (this_frame
&& info
)
942 /* If we know the relationship between the stack and frame
943 pointers, record the addresses of the registers we noticed.
944 Note that we have to do this as a separate step at the end,
945 because instructions may save relative to the SP, but we need
946 their addresses relative to the FP. */
948 this_base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
950 this_base
= get_frame_register_unsigned (this_frame
, sp_regnum
);
952 for (i
= 0; i
< 64; i
++)
954 info
->saved_regs
[i
].set_addr (this_base
- fp_offset
957 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
958 info
->base
= this_base
;
960 /* If LR was saved on the stack, record its location. */
961 if (lr_saved_on_stack
)
962 info
->saved_regs
[lr_regnum
].set_addr (this_base
- fp_offset
965 /* The call instruction moves the caller's PC in the callee's LR.
966 Since this is an unwind, do the reverse. Copy the location of LR
967 into PC (the address / regnum) so that a request for PC will be
968 converted into a request for the LR. */
969 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
971 /* Save the previous frame's computed SP value. */
972 info
->saved_regs
[sp_regnum
].set_value (info
->prev_sp
);
975 return last_prologue_pc
;
980 frv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
982 CORE_ADDR func_addr
, func_end
, new_pc
;
986 /* If the line table has entry for a line *within* the function
987 (i.e., not in the prologue, and not past the end), then that's
989 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
991 struct symtab_and_line sal
;
993 sal
= find_pc_line (func_addr
, 0);
995 if (sal
.line
!= 0 && sal
.end
< func_end
)
1001 /* The FR-V prologue is at least five instructions long (twenty bytes).
1002 If we didn't find a real source location past that, then
1003 do a full analysis of the prologue. */
1004 if (new_pc
< pc
+ 20)
1005 new_pc
= frv_analyze_prologue (gdbarch
, pc
, 0, 0);
1011 /* Examine the instruction pointed to by PC. If it corresponds to
1012 a call to __main, return the address of the next instruction.
1013 Otherwise, return PC. */
1016 frv_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1018 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1021 CORE_ADDR orig_pc
= pc
;
1023 if (target_read_memory (pc
, buf
, 4))
1025 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1027 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1028 to the call instruction.
1030 Skip over this instruction if present. It won't be present in
1031 non-PIC code, and even in PIC code, it might not be present.
1032 (This is due to the fact that GR15, the FDPIC register, already
1033 contains the correct value.)
1035 The general form of the LDI is given first, followed by the
1036 specific instruction with the GRi and GRk filled in as FP and
1039 ldi @(GRi, d12), GRk
1040 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1041 0 000000 1111111 000000 000000000000 = 0x01fc0000
1043 ldi @(FP, d12), GR15
1044 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1045 0 001111 1111111 000010 000000000000 = 0x7ffff000
1048 if ((op
& 0x7ffff000) == 0x1ec82000)
1051 if (target_read_memory (pc
, buf
, 4))
1053 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1056 /* The format of an FRV CALL instruction is as follows:
1059 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1060 0 000000 1111111 000000000000000000 = 0x01fc0000
1063 where label24 is constructed by concatenating the H bits with the
1064 L bits. The call target is PC + (4 * sign_ext(label24)). */
1066 if ((op
& 0x01fc0000) == 0x003c0000)
1069 CORE_ADDR call_dest
;
1070 struct bound_minimal_symbol s
;
1072 displ
= ((op
& 0xfe000000) >> 7) | (op
& 0x0003ffff);
1073 if ((displ
& 0x00800000) != 0)
1074 displ
|= ~((LONGEST
) 0x00ffffff);
1076 call_dest
= pc
+ 4 * displ
;
1077 s
= lookup_minimal_symbol_by_pc (call_dest
);
1079 if (s
.minsym
!= NULL
1080 && s
.minsym
->linkage_name () != NULL
1081 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1091 static struct frv_unwind_cache
*
1092 frv_frame_unwind_cache (struct frame_info
*this_frame
,
1093 void **this_prologue_cache
)
1095 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1096 struct frv_unwind_cache
*info
;
1098 if ((*this_prologue_cache
))
1099 return (struct frv_unwind_cache
*) (*this_prologue_cache
);
1101 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
1102 (*this_prologue_cache
) = info
;
1103 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1105 /* Prologue analysis does the rest... */
1106 frv_analyze_prologue (gdbarch
,
1107 get_frame_func (this_frame
), this_frame
, info
);
1113 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1116 struct gdbarch
*gdbarch
= regcache
->arch ();
1117 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1118 int len
= TYPE_LENGTH (type
);
1123 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1124 store_unsigned_integer (valbuf
, len
, byte_order
, gpr8_val
);
1130 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1131 store_unsigned_integer (valbuf
, 4, byte_order
, regval
);
1132 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1133 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, byte_order
, regval
);
1136 internal_error (__FILE__
, __LINE__
,
1137 _("Illegal return value length: %d"), len
);
1141 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1143 /* Require dword alignment. */
1144 return align_down (sp
, 8);
1148 find_func_descr (struct gdbarch
*gdbarch
, CORE_ADDR entry_point
)
1150 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1153 CORE_ADDR start_addr
;
1155 /* If we can't find the function in the symbol table, then we assume
1156 that the function address is already in descriptor form. */
1157 if (!find_pc_partial_function (entry_point
, NULL
, &start_addr
, NULL
)
1158 || entry_point
!= start_addr
)
1161 descr
= frv_fdpic_find_canonical_descriptor (entry_point
);
1166 /* Construct a non-canonical descriptor from space allocated on
1169 descr
= value_as_long (value_allocate_space_in_inferior (8));
1170 store_unsigned_integer (valbuf
, 4, byte_order
, entry_point
);
1171 write_memory (descr
, valbuf
, 4);
1172 store_unsigned_integer (valbuf
, 4, byte_order
,
1173 frv_fdpic_find_global_pointer (entry_point
));
1174 write_memory (descr
+ 4, valbuf
, 4);
1179 frv_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1180 struct target_ops
*targ
)
1182 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1183 CORE_ADDR entry_point
;
1184 CORE_ADDR got_address
;
1186 entry_point
= get_target_memory_unsigned (targ
, addr
, 4, byte_order
);
1187 got_address
= get_target_memory_unsigned (targ
, addr
+ 4, 4, byte_order
);
1189 if (got_address
== frv_fdpic_find_global_pointer (entry_point
))
1196 frv_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1197 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1198 int nargs
, struct value
**args
, CORE_ADDR sp
,
1199 function_call_return_method return_method
,
1200 CORE_ADDR struct_addr
)
1202 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1205 const gdb_byte
*val
;
1208 struct type
*arg_type
;
1210 enum type_code typecode
;
1214 enum frv_abi abi
= frv_abi (gdbarch
);
1215 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1218 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1219 nargs
, (int) sp
, struct_return
, struct_addr
);
1223 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1224 stack_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
1226 stack_space
-= (6 * 4);
1227 if (stack_space
> 0)
1230 /* Make sure stack is dword aligned. */
1231 sp
= align_down (sp
, 8);
1237 if (return_method
== return_method_struct
)
1238 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1241 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1244 arg_type
= check_typedef (value_type (arg
));
1245 len
= TYPE_LENGTH (arg_type
);
1246 typecode
= arg_type
->code ();
1248 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1250 store_unsigned_integer (valbuf
, 4, byte_order
,
1251 value_address (arg
));
1252 typecode
= TYPE_CODE_PTR
;
1256 else if (abi
== FRV_ABI_FDPIC
1258 && typecode
== TYPE_CODE_PTR
1259 && TYPE_TARGET_TYPE (arg_type
)->code () == TYPE_CODE_FUNC
)
1261 /* The FDPIC ABI requires function descriptors to be passed instead
1263 CORE_ADDR addr
= extract_unsigned_integer
1264 (value_contents (arg
).data (), 4, byte_order
);
1265 addr
= find_func_descr (gdbarch
, addr
);
1266 store_unsigned_integer (valbuf
, 4, byte_order
, addr
);
1267 typecode
= TYPE_CODE_PTR
;
1273 val
= value_contents (arg
).data ();
1278 int partial_len
= (len
< 4 ? len
: 4);
1282 regval
= extract_unsigned_integer (val
, partial_len
, byte_order
);
1284 printf(" Argnum %d data %x -> reg %d\n",
1285 argnum
, (int) regval
, argreg
);
1287 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1293 printf(" Argnum %d data %x -> offset %d (%x)\n",
1294 argnum
, *((int *)val
), stack_offset
,
1295 (int) (sp
+ stack_offset
));
1297 write_memory (sp
+ stack_offset
, val
, partial_len
);
1298 stack_offset
+= align_up (partial_len
, 4);
1305 /* Set the return address. For the frv, the return breakpoint is
1306 always at BP_ADDR. */
1307 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1309 if (abi
== FRV_ABI_FDPIC
)
1311 /* Set the GOT register for the FDPIC ABI. */
1312 regcache_cooked_write_unsigned
1313 (regcache
, first_gpr_regnum
+ 15,
1314 frv_fdpic_find_global_pointer (func_addr
));
1317 /* Finally, update the SP register. */
1318 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1324 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1325 const gdb_byte
*valbuf
)
1327 int len
= TYPE_LENGTH (type
);
1332 memset (val
, 0, sizeof (val
));
1333 memcpy (val
+ (4 - len
), valbuf
, len
);
1334 regcache
->cooked_write (8, val
);
1338 regcache
->cooked_write (8, valbuf
);
1339 regcache
->cooked_write (9, (bfd_byte
*) valbuf
+ 4);
1342 internal_error (__FILE__
, __LINE__
,
1343 _("Don't know how to return a %d-byte value."), len
);
1346 static enum return_value_convention
1347 frv_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1348 struct type
*valtype
, struct regcache
*regcache
,
1349 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1351 int struct_return
= valtype
->code () == TYPE_CODE_STRUCT
1352 || valtype
->code () == TYPE_CODE_UNION
1353 || valtype
->code () == TYPE_CODE_ARRAY
;
1355 if (writebuf
!= NULL
)
1357 gdb_assert (!struct_return
);
1358 frv_store_return_value (valtype
, regcache
, writebuf
);
1361 if (readbuf
!= NULL
)
1363 gdb_assert (!struct_return
);
1364 frv_extract_return_value (valtype
, regcache
, readbuf
);
1368 return RETURN_VALUE_STRUCT_CONVENTION
;
1370 return RETURN_VALUE_REGISTER_CONVENTION
;
1373 /* Given a GDB frame, determine the address of the calling function's
1374 frame. This will be used to create a new GDB frame struct. */
1377 frv_frame_this_id (struct frame_info
*this_frame
,
1378 void **this_prologue_cache
, struct frame_id
*this_id
)
1380 struct frv_unwind_cache
*info
1381 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1384 struct bound_minimal_symbol msym_stack
;
1387 /* The FUNC is easy. */
1388 func
= get_frame_func (this_frame
);
1390 /* Check if the stack is empty. */
1391 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1392 if (msym_stack
.minsym
&& info
->base
== BMSYMBOL_VALUE_ADDRESS (msym_stack
))
1395 /* Hopefully the prologue analysis either correctly determined the
1396 frame's base (which is the SP from the previous frame), or set
1397 that base to "NULL". */
1398 base
= info
->prev_sp
;
1402 id
= frame_id_build (base
, func
);
1406 static struct value
*
1407 frv_frame_prev_register (struct frame_info
*this_frame
,
1408 void **this_prologue_cache
, int regnum
)
1410 struct frv_unwind_cache
*info
1411 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1412 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1415 static const struct frame_unwind frv_frame_unwind
= {
1418 default_frame_unwind_stop_reason
,
1420 frv_frame_prev_register
,
1422 default_frame_sniffer
1426 frv_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1428 struct frv_unwind_cache
*info
1429 = frv_frame_unwind_cache (this_frame
, this_cache
);
1433 static const struct frame_base frv_frame_base
= {
1435 frv_frame_base_address
,
1436 frv_frame_base_address
,
1437 frv_frame_base_address
1440 static struct gdbarch
*
1441 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1443 struct gdbarch
*gdbarch
;
1446 /* Check to see if we've already built an appropriate architecture
1447 object for this executable. */
1448 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1450 return arches
->gdbarch
;
1452 /* Select the right tdep structure for this variant. */
1453 frv_gdbarch_tdep
*var
= new_variant ();
1454 switch (info
.bfd_arch_info
->mach
)
1457 case bfd_mach_frvsimple
:
1458 case bfd_mach_fr300
:
1459 case bfd_mach_fr500
:
1460 case bfd_mach_frvtomcat
:
1461 case bfd_mach_fr550
:
1462 set_variant_num_gprs (var
, 64);
1463 set_variant_num_fprs (var
, 64);
1466 case bfd_mach_fr400
:
1467 case bfd_mach_fr450
:
1468 set_variant_num_gprs (var
, 32);
1469 set_variant_num_fprs (var
, 32);
1473 /* Never heard of this variant. */
1477 /* Extract the ELF flags, if available. */
1478 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1479 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1481 if (elf_flags
& EF_FRV_FDPIC
)
1482 set_variant_abi_fdpic (var
);
1484 if (elf_flags
& EF_FRV_CPU_FR450
)
1485 set_variant_scratch_registers (var
);
1487 gdbarch
= gdbarch_alloc (&info
, var
);
1489 set_gdbarch_short_bit (gdbarch
, 16);
1490 set_gdbarch_int_bit (gdbarch
, 32);
1491 set_gdbarch_long_bit (gdbarch
, 32);
1492 set_gdbarch_long_long_bit (gdbarch
, 64);
1493 set_gdbarch_float_bit (gdbarch
, 32);
1494 set_gdbarch_double_bit (gdbarch
, 64);
1495 set_gdbarch_long_double_bit (gdbarch
, 64);
1496 set_gdbarch_ptr_bit (gdbarch
, 32);
1498 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1499 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1501 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1502 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1503 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1505 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1506 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1507 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1509 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1510 set_gdbarch_pseudo_register_write (gdbarch
, frv_pseudo_register_write
);
1512 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1513 set_gdbarch_skip_main_prologue (gdbarch
, frv_skip_main_prologue
);
1514 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, frv_breakpoint::kind_from_pc
);
1515 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, frv_breakpoint::bp_from_kind
);
1516 set_gdbarch_adjust_breakpoint_address
1517 (gdbarch
, frv_adjust_breakpoint_address
);
1519 set_gdbarch_return_value (gdbarch
, frv_return_value
);
1522 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1523 frame_base_set_default (gdbarch
, &frv_frame_base
);
1524 /* We set the sniffer lower down after the OSABI hooks have been
1527 /* Settings for calling functions in the inferior. */
1528 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1530 /* Settings that should be unnecessary. */
1531 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1533 /* Hardware watchpoint / breakpoint support. */
1534 switch (info
.bfd_arch_info
->mach
)
1537 case bfd_mach_frvsimple
:
1538 case bfd_mach_fr300
:
1539 case bfd_mach_fr500
:
1540 case bfd_mach_frvtomcat
:
1541 /* fr500-style hardware debugging support. */
1542 var
->num_hw_watchpoints
= 4;
1543 var
->num_hw_breakpoints
= 4;
1546 case bfd_mach_fr400
:
1547 case bfd_mach_fr450
:
1548 /* fr400-style hardware debugging support. */
1549 var
->num_hw_watchpoints
= 2;
1550 var
->num_hw_breakpoints
= 4;
1554 /* Otherwise, assume we don't have hardware debugging support. */
1555 var
->num_hw_watchpoints
= 0;
1556 var
->num_hw_breakpoints
= 0;
1560 if (frv_abi (gdbarch
) == FRV_ABI_FDPIC
)
1561 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
1562 frv_convert_from_func_ptr_addr
);
1564 set_solib_ops (gdbarch
, &frv_so_ops
);
1566 /* Hook in ABI-specific overrides, if they have been registered. */
1567 gdbarch_init_osabi (info
, gdbarch
);
1569 /* Set the fallback (prologue based) frame sniffer. */
1570 frame_unwind_append_unwinder (gdbarch
, &frv_frame_unwind
);
1572 /* Enable TLS support. */
1573 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1574 frv_fetch_objfile_link_map
);
1579 void _initialize_frv_tdep ();
1581 _initialize_frv_tdep ()
1583 register_gdbarch_init (bfd_arch_frv
, frv_gdbarch_init
);