1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
30 #include "sim-regno.h"
31 #include "sim/sim-frv.h"
32 #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */
43 struct frv_unwind_cache
/* was struct frame_extra_info */
45 /* The previous frame's inner-most stack address. Used as this
46 frame ID's stack_addr. */
49 /* The frame's base, optionally used by the high-level debug info. */
52 /* Table indicating the location of each and every register. */
53 trad_frame_saved_reg
*saved_regs
;
56 /* A structure describing a particular variant of the FRV.
57 We allocate and initialize one of these structures when we create
58 the gdbarch object for a variant.
60 At the moment, all the FR variants we support differ only in which
61 registers are present; the portable code of GDB knows that
62 registers whose names are the empty string don't exist, so the
63 `register_names' array captures all the per-variant information we
66 in the future, if we need to have per-variant maps for raw size,
67 virtual type, etc., we should replace register_names with an array
68 of structures, each of which gives all the necessary info for one
69 register. Don't stick parallel arrays in here --- that's so
71 struct frv_gdbarch_tdep
: gdbarch_tdep_base
73 /* Which ABI is in use? */
74 enum frv_abi frv_abi
{};
76 /* How many general-purpose registers does this variant have? */
79 /* How many floating-point registers does this variant have? */
82 /* How many hardware watchpoints can it support? */
83 int num_hw_watchpoints
= 0;
85 /* How many hardware breakpoints can it support? */
86 int num_hw_breakpoints
= 0;
89 const char **register_names
= nullptr;
92 using frv_gdbarch_tdep_up
= std::unique_ptr
<frv_gdbarch_tdep
>;
94 /* Return the FR-V ABI associated with GDBARCH. */
96 frv_abi (struct gdbarch
*gdbarch
)
98 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
102 /* Fetch the interpreter and executable loadmap addresses (for shared
103 library support) for the FDPIC ABI. Return 0 if successful, -1 if
104 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
106 frv_fdpic_loadmap_addresses (struct gdbarch
*gdbarch
, CORE_ADDR
*interp_addr
,
107 CORE_ADDR
*exec_addr
)
109 if (frv_abi (gdbarch
) != FRV_ABI_FDPIC
)
113 struct regcache
*regcache
= get_current_regcache ();
115 if (interp_addr
!= NULL
)
118 regcache_cooked_read_unsigned (regcache
,
119 fdpic_loadmap_interp_regnum
, &val
);
122 if (exec_addr
!= NULL
)
125 regcache_cooked_read_unsigned (regcache
,
126 fdpic_loadmap_exec_regnum
, &val
);
133 /* Allocate a new variant structure, and set up default values for all
135 static frv_gdbarch_tdep_up
140 frv_gdbarch_tdep_up
var (new frv_gdbarch_tdep
);
142 var
->frv_abi
= FRV_ABI_EABI
;
145 var
->num_hw_watchpoints
= 0;
146 var
->num_hw_breakpoints
= 0;
148 /* By default, don't supply any general-purpose or floating-point
151 = (const char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
152 * sizeof (const char *));
153 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
154 var
->register_names
[r
] = "";
156 /* Do, however, supply default names for the known special-purpose
159 var
->register_names
[pc_regnum
] = "pc";
160 var
->register_names
[lr_regnum
] = "lr";
161 var
->register_names
[lcr_regnum
] = "lcr";
163 var
->register_names
[psr_regnum
] = "psr";
164 var
->register_names
[ccr_regnum
] = "ccr";
165 var
->register_names
[cccr_regnum
] = "cccr";
166 var
->register_names
[tbr_regnum
] = "tbr";
168 /* Debug registers. */
169 var
->register_names
[brr_regnum
] = "brr";
170 var
->register_names
[dbar0_regnum
] = "dbar0";
171 var
->register_names
[dbar1_regnum
] = "dbar1";
172 var
->register_names
[dbar2_regnum
] = "dbar2";
173 var
->register_names
[dbar3_regnum
] = "dbar3";
175 /* iacc0 (Only found on MB93405.) */
176 var
->register_names
[iacc0h_regnum
] = "iacc0h";
177 var
->register_names
[iacc0l_regnum
] = "iacc0l";
178 var
->register_names
[iacc0_regnum
] = "iacc0";
180 /* fsr0 (Found on FR555 and FR501.) */
181 var
->register_names
[fsr0_regnum
] = "fsr0";
183 /* acc0 - acc7. The architecture provides for the possibility of many
184 more (up to 64 total), but we don't want to make that big of a hole
185 in the G packet. If we need more in the future, we'll add them
187 for (r
= acc0_regnum
; r
<= acc7_regnum
; r
++)
188 var
->register_names
[r
]
189 = xstrprintf ("acc%d", r
- acc0_regnum
).release ();
191 /* accg0 - accg7: These are one byte registers. The remote protocol
192 provides the raw values packed four into a slot. accg0123 and
193 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
194 We don't provide names for accg0123 and accg4567 since the user will
195 likely not want to see these raw values. */
197 for (r
= accg0_regnum
; r
<= accg7_regnum
; r
++)
198 var
->register_names
[r
]
199 = xstrprintf ("accg%d", r
- accg0_regnum
).release ();
203 var
->register_names
[msr0_regnum
] = "msr0";
204 var
->register_names
[msr1_regnum
] = "msr1";
206 /* gner and fner registers. */
207 var
->register_names
[gner0_regnum
] = "gner0";
208 var
->register_names
[gner1_regnum
] = "gner1";
209 var
->register_names
[fner0_regnum
] = "fner0";
210 var
->register_names
[fner1_regnum
] = "fner1";
216 /* Indicate that the variant VAR has NUM_GPRS general-purpose
217 registers, and fill in the names array appropriately. */
219 set_variant_num_gprs (frv_gdbarch_tdep
*var
, int num_gprs
)
223 var
->num_gprs
= num_gprs
;
225 for (r
= 0; r
< num_gprs
; ++r
)
229 xsnprintf (buf
, sizeof (buf
), "gr%d", r
);
230 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
235 /* Indicate that the variant VAR has NUM_FPRS floating-point
236 registers, and fill in the names array appropriately. */
238 set_variant_num_fprs (frv_gdbarch_tdep
*var
, int num_fprs
)
242 var
->num_fprs
= num_fprs
;
244 for (r
= 0; r
< num_fprs
; ++r
)
248 xsnprintf (buf
, sizeof (buf
), "fr%d", r
);
249 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
254 set_variant_abi_fdpic (frv_gdbarch_tdep
*var
)
256 var
->frv_abi
= FRV_ABI_FDPIC
;
257 var
->register_names
[fdpic_loadmap_exec_regnum
] = xstrdup ("loadmap_exec");
258 var
->register_names
[fdpic_loadmap_interp_regnum
]
259 = xstrdup ("loadmap_interp");
263 set_variant_scratch_registers (frv_gdbarch_tdep
*var
)
265 var
->register_names
[scr0_regnum
] = xstrdup ("scr0");
266 var
->register_names
[scr1_regnum
] = xstrdup ("scr1");
267 var
->register_names
[scr2_regnum
] = xstrdup ("scr2");
268 var
->register_names
[scr3_regnum
] = xstrdup ("scr3");
272 frv_register_name (struct gdbarch
*gdbarch
, int reg
)
274 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
275 return tdep
->register_names
[reg
];
280 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
282 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
283 return builtin_type (gdbarch
)->builtin_float
;
284 else if (reg
== iacc0_regnum
)
285 return builtin_type (gdbarch
)->builtin_int64
;
287 return builtin_type (gdbarch
)->builtin_int32
;
290 static enum register_status
291 frv_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
292 int reg
, gdb_byte
*buffer
)
294 enum register_status status
;
296 if (reg
== iacc0_regnum
)
298 status
= regcache
->raw_read (iacc0h_regnum
, buffer
);
299 if (status
== REG_VALID
)
300 status
= regcache
->raw_read (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
302 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
304 /* The accg raw registers have four values in each slot with the
305 lowest register number occupying the first byte. */
307 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
308 int byte_num
= (reg
- accg0_regnum
) % 4;
311 status
= regcache
->raw_read (raw_regnum
, buf
);
312 if (status
== REG_VALID
)
314 memset (buffer
, 0, 4);
315 /* FR-V is big endian, so put the requested byte in the
316 first byte of the buffer allocated to hold the
318 buffer
[0] = buf
[byte_num
];
322 gdb_assert_not_reached ("invalid pseudo register number");
328 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
329 int reg
, const gdb_byte
*buffer
)
331 if (reg
== iacc0_regnum
)
333 regcache
->raw_write (iacc0h_regnum
, buffer
);
334 regcache
->raw_write (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
336 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
338 /* The accg raw registers have four values in each slot with the
339 lowest register number occupying the first byte. */
341 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
342 int byte_num
= (reg
- accg0_regnum
) % 4;
345 regcache
->raw_read (raw_regnum
, buf
);
346 buf
[byte_num
] = ((bfd_byte
*) buffer
)[0];
347 regcache
->raw_write (raw_regnum
, buf
);
352 frv_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
354 static const int spr_map
[] =
356 H_SPR_PSR
, /* psr_regnum */
357 H_SPR_CCR
, /* ccr_regnum */
358 H_SPR_CCCR
, /* cccr_regnum */
359 -1, /* fdpic_loadmap_exec_regnum */
360 -1, /* fdpic_loadmap_interp_regnum */
362 H_SPR_TBR
, /* tbr_regnum */
363 H_SPR_BRR
, /* brr_regnum */
364 H_SPR_DBAR0
, /* dbar0_regnum */
365 H_SPR_DBAR1
, /* dbar1_regnum */
366 H_SPR_DBAR2
, /* dbar2_regnum */
367 H_SPR_DBAR3
, /* dbar3_regnum */
368 H_SPR_SCR0
, /* scr0_regnum */
369 H_SPR_SCR1
, /* scr1_regnum */
370 H_SPR_SCR2
, /* scr2_regnum */
371 H_SPR_SCR3
, /* scr3_regnum */
372 H_SPR_LR
, /* lr_regnum */
373 H_SPR_LCR
, /* lcr_regnum */
374 H_SPR_IACC0H
, /* iacc0h_regnum */
375 H_SPR_IACC0L
, /* iacc0l_regnum */
376 H_SPR_FSR0
, /* fsr0_regnum */
377 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
378 -1, /* acc0_regnum */
379 -1, /* acc1_regnum */
380 -1, /* acc2_regnum */
381 -1, /* acc3_regnum */
382 -1, /* acc4_regnum */
383 -1, /* acc5_regnum */
384 -1, /* acc6_regnum */
385 -1, /* acc7_regnum */
386 -1, /* acc0123_regnum */
387 -1, /* acc4567_regnum */
388 H_SPR_MSR0
, /* msr0_regnum */
389 H_SPR_MSR1
, /* msr1_regnum */
390 H_SPR_GNER0
, /* gner0_regnum */
391 H_SPR_GNER1
, /* gner1_regnum */
392 H_SPR_FNER0
, /* fner0_regnum */
393 H_SPR_FNER1
, /* fner1_regnum */
396 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
398 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
399 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
400 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
401 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
402 else if (pc_regnum
== reg
)
403 return SIM_FRV_PC_REGNUM
;
404 else if (reg
>= first_spr_regnum
405 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
407 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
409 if (spr_reg_offset
< 0)
410 return SIM_REGNO_DOES_NOT_EXIST
;
412 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
415 internal_error (_("Bad register number %d"), reg
);
418 constexpr gdb_byte frv_break_insn
[] = {0xc0, 0x70, 0x00, 0x01};
420 typedef BP_MANIPULATION (frv_break_insn
) frv_breakpoint
;
422 /* Define the maximum number of instructions which may be packed into a
423 bundle (VLIW instruction). */
424 static const int max_instrs_per_bundle
= 8;
426 /* Define the size (in bytes) of an FR-V instruction. */
427 static const int frv_instr_size
= 4;
429 /* Adjust a breakpoint's address to account for the FR-V architecture's
430 constraint that a break instruction must not appear as any but the
431 first instruction in the bundle. */
433 frv_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
435 int count
= max_instrs_per_bundle
;
436 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
437 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
439 /* Find the end of the previous packing sequence. This will be indicated
440 by either attempting to access some inaccessible memory or by finding
441 an instruction word whose packing bit is set to one. */
442 while (count
-- > 0 && addr
>= func_start
)
444 gdb_byte instr
[frv_instr_size
];
447 status
= target_read_memory (addr
, instr
, sizeof instr
);
452 /* This is a big endian architecture, so byte zero will have most
453 significant byte. The most significant bit of this byte is the
458 addr
-= frv_instr_size
;
462 bpaddr
= addr
+ frv_instr_size
;
468 /* Return true if REG is a caller-saves ("scratch") register,
471 is_caller_saves_reg (int reg
)
473 return ((4 <= reg
&& reg
<= 7)
474 || (14 <= reg
&& reg
<= 15)
475 || (32 <= reg
&& reg
<= 47));
479 /* Return true if REG is a callee-saves register, false otherwise. */
481 is_callee_saves_reg (int reg
)
483 return ((16 <= reg
&& reg
<= 31)
484 || (48 <= reg
&& reg
<= 63));
488 /* Return true if REG is an argument register, false otherwise. */
490 is_argument_reg (int reg
)
492 return (8 <= reg
&& reg
<= 13);
495 /* Scan an FR-V prologue, starting at PC, until frame->PC.
496 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
497 We assume FRAME's saved_regs array has already been allocated and cleared.
498 Return the first PC value after the prologue.
500 Note that, for unoptimized code, we almost don't need this function
501 at all; all arguments and locals live on the stack, so we just need
502 the FP to find everything. The catch: structures passed by value
503 have their addresses living in registers; they're never spilled to
504 the stack. So if you ever want to be able to get to these
505 arguments in any frame but the top, you'll need to do this serious
506 prologue analysis. */
508 frv_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
509 frame_info_ptr this_frame
,
510 struct frv_unwind_cache
*info
)
512 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
514 /* When writing out instruction bitpatterns, we use the following
515 letters to label instruction fields:
516 P - The parallel bit. We don't use this.
517 J - The register number of GRj in the instruction description.
518 K - The register number of GRk in the instruction description.
519 I - The register number of GRi.
520 S - a signed immediate offset.
521 U - an unsigned immediate offset.
523 The dots below the numbers indicate where hex digit boundaries
524 fall, to make it easier to check the numbers. */
526 /* Non-zero iff we've seen the instruction that initializes the
527 frame pointer for this function's frame. */
530 /* If fp_set is non_zero, then this is the distance from
531 the stack pointer to frame pointer: fp = sp + fp_offset. */
534 /* Total size of frame prior to any alloca operations. */
537 /* Flag indicating if lr has been saved on the stack. */
538 int lr_saved_on_stack
= 0;
540 /* The number of the general-purpose register we saved the return
541 address ("link register") in, or -1 if we haven't moved it yet. */
542 int lr_save_reg
= -1;
544 /* Offset (from sp) at which lr has been saved on the stack. */
546 int lr_sp_offset
= 0;
548 /* If gr_saved[i] is non-zero, then we've noticed that general
549 register i has been saved at gr_sp_offset[i] from the stack
552 int gr_sp_offset
[64];
554 /* The address of the most recently scanned prologue instruction. */
555 CORE_ADDR last_prologue_pc
;
557 /* The address of the next instruction. */
560 /* The upper bound to of the pc values to scan. */
563 memset (gr_saved
, 0, sizeof (gr_saved
));
565 last_prologue_pc
= pc
;
567 /* Try to compute an upper limit (on how far to scan) based on the
569 lim_pc
= skip_prologue_using_sal (gdbarch
, pc
);
570 /* If there's no line number info, lim_pc will be 0. In that case,
571 set the limit to be 100 instructions away from pc. Hopefully, this
572 will be far enough away to account for the entire prologue. Don't
573 worry about overshooting the end of the function. The scan loop
574 below contains some checks to avoid scanning unreasonably far. */
578 /* If we have a frame, we don't want to scan past the frame's pc. This
579 will catch those cases where the pc is in the prologue. */
582 CORE_ADDR frame_pc
= get_frame_pc (this_frame
);
583 if (frame_pc
< lim_pc
)
587 /* Scan the prologue. */
590 gdb_byte buf
[frv_instr_size
];
593 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
595 op
= extract_signed_integer (buf
, byte_order
);
599 /* The tests in this chain of ifs should be in order of
600 decreasing selectivity, so that more particular patterns get
601 to fire before less particular patterns. */
603 /* Some sort of control transfer instruction: stop scanning prologue.
604 Integer Conditional Branch:
605 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
606 Floating-point / media Conditional Branch:
607 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
608 LCR Conditional Branch to LR
609 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
610 Integer conditional Branches to LR
611 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
612 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
613 Floating-point/Media Branches to LR
614 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
615 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
617 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
618 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
620 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
622 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
623 Integer Conditional Trap
624 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
625 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
626 Floating-point /media Conditional Trap
627 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
628 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
630 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
632 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
633 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
634 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
635 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
636 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
638 /* Stop scanning; not in prologue any longer. */
642 /* Loading something from memory into fp probably means that
643 we're in the epilogue. Stop scanning the prologue.
645 X 000010 0000010 XXXXXX 000100 XXXXXX
647 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
648 else if ((op
& 0x7ffc0fc0) == 0x04080100
649 || (op
& 0x7ffc0000) == 0x04c80000)
654 /* Setting the FP from the SP:
656 P 000010 0100010 000001 000000000000 = 0x04881000
657 0 111111 1111111 111111 111111111111 = 0x7fffffff
659 We treat this as part of the prologue. */
660 else if ((op
& 0x7fffffff) == 0x04881000)
664 last_prologue_pc
= next_pc
;
667 /* Move the link register to the scratch register grJ, before saving:
669 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
670 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
672 We treat this as part of the prologue. */
673 else if ((op
& 0x7fffffc0) == 0x080d01c0)
675 int gr_j
= op
& 0x3f;
677 /* If we're moving it to a scratch register, that's fine. */
678 if (is_caller_saves_reg (gr_j
))
681 last_prologue_pc
= next_pc
;
685 /* To save multiple callee-saves registers on the stack, at
689 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
690 0 000000 1111111 111111 111111 111111 = 0x01ffffff
693 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
694 0 000000 1111111 111111 111111 111111 = 0x01ffffff
696 We treat this as part of the prologue, and record the register's
697 saved address in the frame structure. */
698 else if ((op
& 0x01ffffff) == 0x000c10c0
699 || (op
& 0x01ffffff) == 0x000c1100)
701 int gr_k
= ((op
>> 25) & 0x3f);
702 int ope
= ((op
>> 6) & 0x3f);
706 /* Is it an std or an stq? */
712 /* Is it really a callee-saves register? */
713 if (is_callee_saves_reg (gr_k
))
715 for (i
= 0; i
< count
; i
++)
717 gr_saved
[gr_k
+ i
] = 1;
718 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
720 last_prologue_pc
= next_pc
;
724 /* Adjusting the stack pointer. (The stack pointer is GR1.)
726 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
727 0 111111 1111111 111111 000000000000 = 0x7ffff000
729 We treat this as part of the prologue. */
730 else if ((op
& 0x7ffff000) == 0x02401000)
734 /* Sign-extend the twelve-bit field.
735 (Isn't there a better way to do this?) */
736 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
739 last_prologue_pc
= pc
;
743 /* If the prologue is being adjusted again, we've
744 likely gone too far; i.e. we're probably in the
750 /* Setting the FP to a constant distance from the SP:
752 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
753 0 111111 1111111 111111 000000000000 = 0x7ffff000
755 We treat this as part of the prologue. */
756 else if ((op
& 0x7ffff000) == 0x04401000)
758 /* Sign-extend the twelve-bit field.
759 (Isn't there a better way to do this?) */
760 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
763 last_prologue_pc
= pc
;
766 /* To spill an argument register to a scratch register:
768 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
769 0 000000 1111111 000000 111111111111 = 0x01fc0fff
771 For the time being, we treat this as a prologue instruction,
772 assuming that GRi is an argument register. This one's kind
773 of suspicious, because it seems like it could be part of a
774 legitimate body instruction. But we only come here when the
775 source info wasn't helpful, so we have to do the best we can.
776 Hopefully once GCC and GDB agree on how to emit line number
777 info for prologues, then this code will never come into play. */
778 else if ((op
& 0x01fc0fff) == 0x00880000)
780 int gr_i
= ((op
>> 12) & 0x3f);
782 /* Make sure that the source is an arg register; if it is, we'll
783 treat it as a prologue instruction. */
784 if (is_argument_reg (gr_i
))
785 last_prologue_pc
= next_pc
;
788 /* To spill 16-bit values to the stack:
790 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
791 0 000000 1111111 111111 000000000000 = 0x01fff000
793 And for 8-bit values, we use STB instructions.
795 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
796 0 000000 1111111 111111 000000000000 = 0x01fff000
798 We check that GRk is really an argument register, and treat
799 all such as part of the prologue. */
800 else if ( (op
& 0x01fff000) == 0x01442000
801 || (op
& 0x01fff000) == 0x01402000)
803 int gr_k
= ((op
>> 25) & 0x3f);
805 /* Make sure that GRk is really an argument register; treat
806 it as a prologue instruction if so. */
807 if (is_argument_reg (gr_k
))
808 last_prologue_pc
= next_pc
;
811 /* To save multiple callee-saves register on the stack, at a
815 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
816 0 000000 1111111 111111 000000000000 = 0x01fff000
819 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
820 0 000000 1111111 111111 000000000000 = 0x01fff000
822 We treat this as part of the prologue, and record the register's
823 saved address in the frame structure. */
824 else if ((op
& 0x01fff000) == 0x014c1000
825 || (op
& 0x01fff000) == 0x01501000)
827 int gr_k
= ((op
>> 25) & 0x3f);
831 /* Is it a stdi or a stqi? */
832 if ((op
& 0x01fff000) == 0x014c1000)
837 /* Is it really a callee-saves register? */
838 if (is_callee_saves_reg (gr_k
))
840 /* Sign-extend the twelve-bit field.
841 (Isn't there a better way to do this?) */
842 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
844 for (i
= 0; i
< count
; i
++)
846 gr_saved
[gr_k
+ i
] = 1;
847 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
849 last_prologue_pc
= next_pc
;
853 /* Storing any kind of integer register at any constant offset
854 from any other register.
857 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
858 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
861 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
862 0 000000 1111111 000000 000000000000 = 0x01fc0000
864 These could be almost anything, but a lot of prologue
865 instructions fall into this pattern, so let's decode the
866 instruction once, and then work at a higher level. */
867 else if (((op
& 0x01fc0fff) == 0x000c0080)
868 || ((op
& 0x01fc0000) == 0x01480000))
870 int gr_k
= ((op
>> 25) & 0x3f);
871 int gr_i
= ((op
>> 12) & 0x3f);
874 /* Are we storing with gr0 as an offset, or using an
876 if ((op
& 0x01fc0fff) == 0x000c0080)
879 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
881 /* If the address isn't relative to the SP or FP, it's not a
882 prologue instruction. */
883 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
885 /* Do nothing; not a prologue instruction. */
888 /* Saving the old FP in the new frame (relative to the SP). */
889 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
891 gr_saved
[fp_regnum
] = 1;
892 gr_sp_offset
[fp_regnum
] = offset
;
893 last_prologue_pc
= next_pc
;
896 /* Saving callee-saves register(s) on the stack, relative to
898 else if (gr_i
== sp_regnum
899 && is_callee_saves_reg (gr_k
))
902 if (gr_i
== sp_regnum
)
903 gr_sp_offset
[gr_k
] = offset
;
905 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
906 last_prologue_pc
= next_pc
;
909 /* Saving the scratch register holding the return address. */
910 else if (lr_save_reg
!= -1
911 && gr_k
== lr_save_reg
)
913 lr_saved_on_stack
= 1;
914 if (gr_i
== sp_regnum
)
915 lr_sp_offset
= offset
;
917 lr_sp_offset
= offset
+ fp_offset
;
918 last_prologue_pc
= next_pc
;
921 /* Spilling int-sized arguments to the stack. */
922 else if (is_argument_reg (gr_k
))
923 last_prologue_pc
= next_pc
;
928 if (this_frame
&& info
)
933 /* If we know the relationship between the stack and frame
934 pointers, record the addresses of the registers we noticed.
935 Note that we have to do this as a separate step at the end,
936 because instructions may save relative to the SP, but we need
937 their addresses relative to the FP. */
939 this_base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
941 this_base
= get_frame_register_unsigned (this_frame
, sp_regnum
);
943 for (i
= 0; i
< 64; i
++)
945 info
->saved_regs
[i
].set_addr (this_base
- fp_offset
948 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
949 info
->base
= this_base
;
951 /* If LR was saved on the stack, record its location. */
952 if (lr_saved_on_stack
)
953 info
->saved_regs
[lr_regnum
].set_addr (this_base
- fp_offset
956 /* The call instruction moves the caller's PC in the callee's LR.
957 Since this is an unwind, do the reverse. Copy the location of LR
958 into PC (the address / regnum) so that a request for PC will be
959 converted into a request for the LR. */
960 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
962 /* Save the previous frame's computed SP value. */
963 info
->saved_regs
[sp_regnum
].set_value (info
->prev_sp
);
966 return last_prologue_pc
;
971 frv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
973 CORE_ADDR func_addr
, func_end
, new_pc
;
977 /* If the line table has entry for a line *within* the function
978 (i.e., not in the prologue, and not past the end), then that's
980 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
982 struct symtab_and_line sal
;
984 sal
= find_pc_line (func_addr
, 0);
986 if (sal
.line
!= 0 && sal
.end
< func_end
)
992 /* The FR-V prologue is at least five instructions long (twenty bytes).
993 If we didn't find a real source location past that, then
994 do a full analysis of the prologue. */
995 if (new_pc
< pc
+ 20)
996 new_pc
= frv_analyze_prologue (gdbarch
, pc
, 0, 0);
1002 /* Examine the instruction pointed to by PC. If it corresponds to
1003 a call to __main, return the address of the next instruction.
1004 Otherwise, return PC. */
1007 frv_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1009 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1012 CORE_ADDR orig_pc
= pc
;
1014 if (target_read_memory (pc
, buf
, 4))
1016 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1018 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1019 to the call instruction.
1021 Skip over this instruction if present. It won't be present in
1022 non-PIC code, and even in PIC code, it might not be present.
1023 (This is due to the fact that GR15, the FDPIC register, already
1024 contains the correct value.)
1026 The general form of the LDI is given first, followed by the
1027 specific instruction with the GRi and GRk filled in as FP and
1030 ldi @(GRi, d12), GRk
1031 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1032 0 000000 1111111 000000 000000000000 = 0x01fc0000
1034 ldi @(FP, d12), GR15
1035 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1036 0 001111 1111111 000010 000000000000 = 0x7ffff000
1039 if ((op
& 0x7ffff000) == 0x1ec82000)
1042 if (target_read_memory (pc
, buf
, 4))
1044 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1047 /* The format of an FRV CALL instruction is as follows:
1050 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1051 0 000000 1111111 000000000000000000 = 0x01fc0000
1054 where label24 is constructed by concatenating the H bits with the
1055 L bits. The call target is PC + (4 * sign_ext(label24)). */
1057 if ((op
& 0x01fc0000) == 0x003c0000)
1060 CORE_ADDR call_dest
;
1061 struct bound_minimal_symbol s
;
1063 displ
= ((op
& 0xfe000000) >> 7) | (op
& 0x0003ffff);
1064 if ((displ
& 0x00800000) != 0)
1065 displ
|= ~((LONGEST
) 0x00ffffff);
1067 call_dest
= pc
+ 4 * displ
;
1068 s
= lookup_minimal_symbol_by_pc (call_dest
);
1070 if (s
.minsym
!= NULL
1071 && s
.minsym
->linkage_name () != NULL
1072 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1082 static struct frv_unwind_cache
*
1083 frv_frame_unwind_cache (frame_info_ptr this_frame
,
1084 void **this_prologue_cache
)
1086 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1087 struct frv_unwind_cache
*info
;
1089 if ((*this_prologue_cache
))
1090 return (struct frv_unwind_cache
*) (*this_prologue_cache
);
1092 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
1093 (*this_prologue_cache
) = info
;
1094 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1096 /* Prologue analysis does the rest... */
1097 frv_analyze_prologue (gdbarch
,
1098 get_frame_func (this_frame
), this_frame
, info
);
1104 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1107 struct gdbarch
*gdbarch
= regcache
->arch ();
1108 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1109 int len
= type
->length ();
1114 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1115 store_unsigned_integer (valbuf
, len
, byte_order
, gpr8_val
);
1121 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1122 store_unsigned_integer (valbuf
, 4, byte_order
, regval
);
1123 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1124 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, byte_order
, regval
);
1127 internal_error (_("Illegal return value length: %d"), len
);
1131 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1133 /* Require dword alignment. */
1134 return align_down (sp
, 8);
1138 find_func_descr (struct gdbarch
*gdbarch
, CORE_ADDR entry_point
)
1140 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1143 CORE_ADDR start_addr
;
1145 /* If we can't find the function in the symbol table, then we assume
1146 that the function address is already in descriptor form. */
1147 if (!find_pc_partial_function (entry_point
, NULL
, &start_addr
, NULL
)
1148 || entry_point
!= start_addr
)
1151 descr
= frv_fdpic_find_canonical_descriptor (entry_point
);
1156 /* Construct a non-canonical descriptor from space allocated on
1159 descr
= value_as_long (value_allocate_space_in_inferior (8));
1160 store_unsigned_integer (valbuf
, 4, byte_order
, entry_point
);
1161 write_memory (descr
, valbuf
, 4);
1162 store_unsigned_integer (valbuf
, 4, byte_order
,
1163 frv_fdpic_find_global_pointer (entry_point
));
1164 write_memory (descr
+ 4, valbuf
, 4);
1169 frv_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1170 struct target_ops
*targ
)
1172 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1173 CORE_ADDR entry_point
;
1174 CORE_ADDR got_address
;
1176 entry_point
= get_target_memory_unsigned (targ
, addr
, 4, byte_order
);
1177 got_address
= get_target_memory_unsigned (targ
, addr
+ 4, 4, byte_order
);
1179 if (got_address
== frv_fdpic_find_global_pointer (entry_point
))
1186 frv_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1187 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1188 int nargs
, struct value
**args
, CORE_ADDR sp
,
1189 function_call_return_method return_method
,
1190 CORE_ADDR struct_addr
)
1192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1195 const gdb_byte
*val
;
1198 struct type
*arg_type
;
1200 enum type_code typecode
;
1204 enum frv_abi abi
= frv_abi (gdbarch
);
1205 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1208 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1209 nargs
, (int) sp
, struct_return
, struct_addr
);
1213 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1214 stack_space
+= align_up (args
[argnum
]->type ()->length (), 4);
1216 stack_space
-= (6 * 4);
1217 if (stack_space
> 0)
1220 /* Make sure stack is dword aligned. */
1221 sp
= align_down (sp
, 8);
1227 if (return_method
== return_method_struct
)
1228 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1231 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1234 arg_type
= check_typedef (arg
->type ());
1235 len
= arg_type
->length ();
1236 typecode
= arg_type
->code ();
1238 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1240 store_unsigned_integer (valbuf
, 4, byte_order
,
1242 typecode
= TYPE_CODE_PTR
;
1246 else if (abi
== FRV_ABI_FDPIC
1248 && typecode
== TYPE_CODE_PTR
1249 && arg_type
->target_type ()->code () == TYPE_CODE_FUNC
)
1251 /* The FDPIC ABI requires function descriptors to be passed instead
1253 CORE_ADDR addr
= extract_unsigned_integer
1254 (value_contents (arg
).data (), 4, byte_order
);
1255 addr
= find_func_descr (gdbarch
, addr
);
1256 store_unsigned_integer (valbuf
, 4, byte_order
, addr
);
1257 typecode
= TYPE_CODE_PTR
;
1263 val
= value_contents (arg
).data ();
1268 int partial_len
= (len
< 4 ? len
: 4);
1272 regval
= extract_unsigned_integer (val
, partial_len
, byte_order
);
1274 printf(" Argnum %d data %x -> reg %d\n",
1275 argnum
, (int) regval
, argreg
);
1277 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1283 printf(" Argnum %d data %x -> offset %d (%x)\n",
1284 argnum
, *((int *)val
), stack_offset
,
1285 (int) (sp
+ stack_offset
));
1287 write_memory (sp
+ stack_offset
, val
, partial_len
);
1288 stack_offset
+= align_up (partial_len
, 4);
1295 /* Set the return address. For the frv, the return breakpoint is
1296 always at BP_ADDR. */
1297 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1299 if (abi
== FRV_ABI_FDPIC
)
1301 /* Set the GOT register for the FDPIC ABI. */
1302 regcache_cooked_write_unsigned
1303 (regcache
, first_gpr_regnum
+ 15,
1304 frv_fdpic_find_global_pointer (func_addr
));
1307 /* Finally, update the SP register. */
1308 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1314 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1315 const gdb_byte
*valbuf
)
1317 int len
= type
->length ();
1322 memset (val
, 0, sizeof (val
));
1323 memcpy (val
+ (4 - len
), valbuf
, len
);
1324 regcache
->cooked_write (8, val
);
1328 regcache
->cooked_write (8, valbuf
);
1329 regcache
->cooked_write (9, (bfd_byte
*) valbuf
+ 4);
1332 internal_error (_("Don't know how to return a %d-byte value."), len
);
1335 static enum return_value_convention
1336 frv_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1337 struct type
*valtype
, struct regcache
*regcache
,
1338 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1340 int struct_return
= valtype
->code () == TYPE_CODE_STRUCT
1341 || valtype
->code () == TYPE_CODE_UNION
1342 || valtype
->code () == TYPE_CODE_ARRAY
;
1344 if (writebuf
!= NULL
)
1346 gdb_assert (!struct_return
);
1347 frv_store_return_value (valtype
, regcache
, writebuf
);
1350 if (readbuf
!= NULL
)
1352 gdb_assert (!struct_return
);
1353 frv_extract_return_value (valtype
, regcache
, readbuf
);
1357 return RETURN_VALUE_STRUCT_CONVENTION
;
1359 return RETURN_VALUE_REGISTER_CONVENTION
;
1362 /* Given a GDB frame, determine the address of the calling function's
1363 frame. This will be used to create a new GDB frame struct. */
1366 frv_frame_this_id (frame_info_ptr this_frame
,
1367 void **this_prologue_cache
, struct frame_id
*this_id
)
1369 struct frv_unwind_cache
*info
1370 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1373 struct bound_minimal_symbol msym_stack
;
1376 /* The FUNC is easy. */
1377 func
= get_frame_func (this_frame
);
1379 /* Check if the stack is empty. */
1380 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1381 if (msym_stack
.minsym
&& info
->base
== msym_stack
.value_address ())
1384 /* Hopefully the prologue analysis either correctly determined the
1385 frame's base (which is the SP from the previous frame), or set
1386 that base to "NULL". */
1387 base
= info
->prev_sp
;
1391 id
= frame_id_build (base
, func
);
1395 static struct value
*
1396 frv_frame_prev_register (frame_info_ptr this_frame
,
1397 void **this_prologue_cache
, int regnum
)
1399 struct frv_unwind_cache
*info
1400 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1401 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1404 static const struct frame_unwind frv_frame_unwind
= {
1407 default_frame_unwind_stop_reason
,
1409 frv_frame_prev_register
,
1411 default_frame_sniffer
1415 frv_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
1417 struct frv_unwind_cache
*info
1418 = frv_frame_unwind_cache (this_frame
, this_cache
);
1422 static const struct frame_base frv_frame_base
= {
1424 frv_frame_base_address
,
1425 frv_frame_base_address
,
1426 frv_frame_base_address
1429 static struct gdbarch
*
1430 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1434 /* Check to see if we've already built an appropriate architecture
1435 object for this executable. */
1436 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1438 return arches
->gdbarch
;
1440 /* Select the right tdep structure for this variant. */
1441 gdbarch
*gdbarch
= gdbarch_alloc (&info
, new_variant ());
1442 frv_gdbarch_tdep
*var
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
1444 switch (info
.bfd_arch_info
->mach
)
1447 case bfd_mach_frvsimple
:
1448 case bfd_mach_fr300
:
1449 case bfd_mach_fr500
:
1450 case bfd_mach_frvtomcat
:
1451 case bfd_mach_fr550
:
1452 set_variant_num_gprs (var
, 64);
1453 set_variant_num_fprs (var
, 64);
1456 case bfd_mach_fr400
:
1457 case bfd_mach_fr450
:
1458 set_variant_num_gprs (var
, 32);
1459 set_variant_num_fprs (var
, 32);
1463 /* Never heard of this variant. */
1467 /* Extract the ELF flags, if available. */
1468 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1469 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1471 if (elf_flags
& EF_FRV_FDPIC
)
1472 set_variant_abi_fdpic (var
);
1474 if (elf_flags
& EF_FRV_CPU_FR450
)
1475 set_variant_scratch_registers (var
);
1477 set_gdbarch_short_bit (gdbarch
, 16);
1478 set_gdbarch_int_bit (gdbarch
, 32);
1479 set_gdbarch_long_bit (gdbarch
, 32);
1480 set_gdbarch_long_long_bit (gdbarch
, 64);
1481 set_gdbarch_float_bit (gdbarch
, 32);
1482 set_gdbarch_double_bit (gdbarch
, 64);
1483 set_gdbarch_long_double_bit (gdbarch
, 64);
1484 set_gdbarch_ptr_bit (gdbarch
, 32);
1486 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1487 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1489 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1490 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1491 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1493 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1494 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1495 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1497 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1498 set_gdbarch_pseudo_register_write (gdbarch
, frv_pseudo_register_write
);
1500 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1501 set_gdbarch_skip_main_prologue (gdbarch
, frv_skip_main_prologue
);
1502 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, frv_breakpoint::kind_from_pc
);
1503 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, frv_breakpoint::bp_from_kind
);
1504 set_gdbarch_adjust_breakpoint_address
1505 (gdbarch
, frv_adjust_breakpoint_address
);
1507 set_gdbarch_return_value (gdbarch
, frv_return_value
);
1510 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1511 frame_base_set_default (gdbarch
, &frv_frame_base
);
1512 /* We set the sniffer lower down after the OSABI hooks have been
1515 /* Settings for calling functions in the inferior. */
1516 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1518 /* Settings that should be unnecessary. */
1519 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1521 /* Hardware watchpoint / breakpoint support. */
1522 switch (info
.bfd_arch_info
->mach
)
1525 case bfd_mach_frvsimple
:
1526 case bfd_mach_fr300
:
1527 case bfd_mach_fr500
:
1528 case bfd_mach_frvtomcat
:
1529 /* fr500-style hardware debugging support. */
1530 var
->num_hw_watchpoints
= 4;
1531 var
->num_hw_breakpoints
= 4;
1534 case bfd_mach_fr400
:
1535 case bfd_mach_fr450
:
1536 /* fr400-style hardware debugging support. */
1537 var
->num_hw_watchpoints
= 2;
1538 var
->num_hw_breakpoints
= 4;
1542 /* Otherwise, assume we don't have hardware debugging support. */
1543 var
->num_hw_watchpoints
= 0;
1544 var
->num_hw_breakpoints
= 0;
1548 if (frv_abi (gdbarch
) == FRV_ABI_FDPIC
)
1549 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
1550 frv_convert_from_func_ptr_addr
);
1552 set_gdbarch_so_ops (gdbarch
, &frv_so_ops
);
1554 /* Hook in ABI-specific overrides, if they have been registered. */
1555 gdbarch_init_osabi (info
, gdbarch
);
1557 /* Set the fallback (prologue based) frame sniffer. */
1558 frame_unwind_append_unwinder (gdbarch
, &frv_frame_unwind
);
1560 /* Enable TLS support. */
1561 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1562 frv_fetch_objfile_link_map
);
1567 void _initialize_frv_tdep ();
1569 _initialize_frv_tdep ()
1571 gdbarch_register (bfd_arch_frv
, frv_gdbarch_init
);