1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2015 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
40 #include "gdb_proc_service.h"
42 /* Defined in auto-generated files. */
43 void init_registers_aarch64 (void);
44 extern const struct target_desc
*tdesc_aarch64
;
50 #define AARCH64_X_REGS_NUM 31
51 #define AARCH64_V_REGS_NUM 32
52 #define AARCH64_X0_REGNO 0
53 #define AARCH64_SP_REGNO 31
54 #define AARCH64_PC_REGNO 32
55 #define AARCH64_CPSR_REGNO 33
56 #define AARCH64_V0_REGNO 34
57 #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
58 #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
60 #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
62 /* Per-process arch-specific data we want to keep. */
64 struct arch_process_info
66 /* Hardware breakpoint/watchpoint data.
67 The reason for them to be per-process rather than per-thread is
68 due to the lack of information in the gdbserver environment;
69 gdbserver is not told that whether a requested hardware
70 breakpoint/watchpoint is thread specific or not, so it has to set
71 each hw bp/wp for every thread in the current process. The
72 higher level bp/wp management in gdb will resume a thread if a hw
73 bp/wp trap is not expected for it. Since the hw bp/wp setting is
74 same for each thread, it is reasonable for the data to live here.
76 struct aarch64_debug_reg_state debug_reg_state
;
79 /* Return true if the size of register 0 is 8 byte. */
84 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
86 return register_size (regcache
->tdesc
, 0) == 8;
89 /* Implementation of linux_target_ops method "cannot_store_register". */
92 aarch64_cannot_store_register (int regno
)
94 return regno
>= AARCH64_NUM_REGS
;
97 /* Implementation of linux_target_ops method "cannot_fetch_register". */
100 aarch64_cannot_fetch_register (int regno
)
102 return regno
>= AARCH64_NUM_REGS
;
106 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
108 struct user_pt_regs
*regset
= buf
;
111 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
112 collect_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
113 collect_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
114 collect_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
115 collect_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
119 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
121 const struct user_pt_regs
*regset
= buf
;
124 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
125 supply_register (regcache
, AARCH64_X0_REGNO
+ i
, ®set
->regs
[i
]);
126 supply_register (regcache
, AARCH64_SP_REGNO
, ®set
->sp
);
127 supply_register (regcache
, AARCH64_PC_REGNO
, ®set
->pc
);
128 supply_register (regcache
, AARCH64_CPSR_REGNO
, ®set
->pstate
);
132 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
134 struct user_fpsimd_state
*regset
= buf
;
137 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
138 collect_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
139 collect_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
140 collect_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
144 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
146 const struct user_fpsimd_state
*regset
= buf
;
149 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
150 supply_register (regcache
, AARCH64_V0_REGNO
+ i
, ®set
->vregs
[i
]);
151 supply_register (regcache
, AARCH64_FPSR_REGNO
, ®set
->fpsr
);
152 supply_register (regcache
, AARCH64_FPCR_REGNO
, ®set
->fpcr
);
155 /* Enable miscellaneous debugging output. The name is historical - it
156 was originally used to debug LinuxThreads support. */
157 extern int debug_threads
;
159 /* Implementation of linux_target_ops method "get_pc". */
162 aarch64_get_pc (struct regcache
*regcache
)
164 if (register_size (regcache
->tdesc
, 0) == 8)
168 collect_register_by_name (regcache
, "pc", &pc
);
170 debug_printf ("stop pc is %08lx\n", pc
);
177 collect_register_by_name (regcache
, "pc", &pc
);
179 debug_printf ("stop pc is %04x\n", pc
);
184 /* Implementation of linux_target_ops method "set_pc". */
187 aarch64_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
189 if (register_size (regcache
->tdesc
, 0) == 8)
191 unsigned long newpc
= pc
;
192 supply_register_by_name (regcache
, "pc", &newpc
);
196 unsigned int newpc
= pc
;
197 supply_register_by_name (regcache
, "pc", &newpc
);
201 #define aarch64_breakpoint_len 4
203 /* AArch64 BRK software debug mode instruction.
204 This instruction needs to match gdb/aarch64-tdep.c
205 (aarch64_default_breakpoint). */
206 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
208 /* Implementation of linux_target_ops method "breakpoint_at". */
211 aarch64_breakpoint_at (CORE_ADDR where
)
213 gdb_byte insn
[aarch64_breakpoint_len
];
215 (*the_target
->read_memory
) (where
, (unsigned char *) &insn
,
216 aarch64_breakpoint_len
);
217 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
224 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
228 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
230 state
->dr_addr_bp
[i
] = 0;
231 state
->dr_ctrl_bp
[i
] = 0;
232 state
->dr_ref_count_bp
[i
] = 0;
235 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
237 state
->dr_addr_wp
[i
] = 0;
238 state
->dr_ctrl_wp
[i
] = 0;
239 state
->dr_ref_count_wp
[i
] = 0;
243 /* Return the pointer to the debug register state structure in the
244 current process' arch-specific data area. */
246 struct aarch64_debug_reg_state
*
247 aarch64_get_debug_reg_state (pid_t pid
)
249 struct process_info
*proc
= find_process_pid (pid
);
251 return &proc
->priv
->arch_private
->debug_reg_state
;
254 /* Implementation of linux_target_ops method "supports_z_point_type". */
257 aarch64_supports_z_point_type (char z_type
)
263 if (!extended_protocol
&& is_64bit_tdesc ())
265 /* Only enable Z0 packet in non-multi-arch debugging. If
266 extended protocol is used, don't enable Z0 packet because
267 GDBserver may attach to 32-bit process. */
272 /* Disable Z0 packet so that GDBserver doesn't have to handle
273 different breakpoint instructions (aarch64, arm, thumb etc)
274 in multi-arch debugging. */
279 case Z_PACKET_WRITE_WP
:
280 case Z_PACKET_READ_WP
:
281 case Z_PACKET_ACCESS_WP
:
288 /* Implementation of linux_target_ops method "insert_point".
290 It actually only records the info of the to-be-inserted bp/wp;
291 the actual insertion will happen when threads are resumed. */
294 aarch64_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
295 int len
, struct raw_breakpoint
*bp
)
298 enum target_hw_bp_type targ_type
;
299 struct aarch64_debug_reg_state
*state
300 = aarch64_get_debug_reg_state (pid_of (current_thread
));
303 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
304 (unsigned long) addr
, len
);
306 /* Determine the type from the raw breakpoint type. */
307 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
309 if (targ_type
!= hw_execute
)
311 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
312 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
313 1 /* is_insert */, state
);
319 aarch64_handle_breakpoint (targ_type
, addr
, len
, 1 /* is_insert */,
323 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
329 /* Implementation of linux_target_ops method "remove_point".
331 It actually only records the info of the to-be-removed bp/wp,
332 the actual removal will be done when threads are resumed. */
335 aarch64_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
336 int len
, struct raw_breakpoint
*bp
)
339 enum target_hw_bp_type targ_type
;
340 struct aarch64_debug_reg_state
*state
341 = aarch64_get_debug_reg_state (pid_of (current_thread
));
344 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
345 (unsigned long) addr
, len
);
347 /* Determine the type from the raw breakpoint type. */
348 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
350 /* Set up state pointers. */
351 if (targ_type
!= hw_execute
)
353 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
357 aarch64_handle_breakpoint (targ_type
, addr
, len
, 0 /* is_insert */,
361 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
367 /* Implementation of linux_target_ops method "stopped_data_address". */
370 aarch64_stopped_data_address (void)
374 struct aarch64_debug_reg_state
*state
;
376 pid
= lwpid_of (current_thread
);
378 /* Get the siginfo. */
379 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
380 return (CORE_ADDR
) 0;
382 /* Need to be a hardware breakpoint/watchpoint trap. */
383 if (siginfo
.si_signo
!= SIGTRAP
384 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
385 return (CORE_ADDR
) 0;
387 /* Check if the address matches any watched address. */
388 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
389 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
391 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
392 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
393 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
];
394 if (state
->dr_ref_count_wp
[i
]
395 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
396 && addr_trap
>= addr_watch
397 && addr_trap
< addr_watch
+ len
)
401 return (CORE_ADDR
) 0;
404 /* Implementation of linux_target_ops method "stopped_by_watchpoint". */
407 aarch64_stopped_by_watchpoint (void)
409 if (aarch64_stopped_data_address () != 0)
415 /* Fetch the thread-local storage pointer for libthread_db. */
418 ps_get_thread_area (const struct ps_prochandle
*ph
,
419 lwpid_t lwpid
, int idx
, void **base
)
421 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
425 /* Implementation of linux_target_ops method "siginfo_fixup". */
428 aarch64_linux_siginfo_fixup (siginfo_t
*native
, void *inf
, int direction
)
430 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
431 if (!is_64bit_tdesc ())
434 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
437 aarch64_siginfo_from_compat_siginfo (native
,
438 (struct compat_siginfo
*) inf
);
446 /* Implementation of linux_target_ops method "linux_new_process". */
448 static struct arch_process_info
*
449 aarch64_linux_new_process (void)
451 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
453 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
458 /* Implementation of linux_target_ops method "linux_new_fork". */
461 aarch64_linux_new_fork (struct process_info
*parent
,
462 struct process_info
*child
)
464 /* These are allocated by linux_add_process. */
465 gdb_assert (parent
->priv
!= NULL
466 && parent
->priv
->arch_private
!= NULL
);
467 gdb_assert (child
->priv
!= NULL
468 && child
->priv
->arch_private
!= NULL
);
470 /* Linux kernel before 2.6.33 commit
471 72f674d203cd230426437cdcf7dd6f681dad8b0d
472 will inherit hardware debug registers from parent
473 on fork/vfork/clone. Newer Linux kernels create such tasks with
474 zeroed debug registers.
476 GDB core assumes the child inherits the watchpoints/hw
477 breakpoints of the parent, and will remove them all from the
478 forked off process. Copy the debug registers mirrors into the
479 new process so that all breakpoints and watchpoints can be
480 removed together. The debug registers mirror will become zeroed
481 in the end before detaching the forked off process, thus making
482 this compatible with older Linux kernels too. */
484 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
487 /* Return the right target description according to the ELF file of
490 static const struct target_desc
*
491 aarch64_linux_read_description (void)
493 unsigned int machine
;
497 tid
= lwpid_of (current_thread
);
499 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
502 return tdesc_aarch64
;
504 return tdesc_arm_with_neon
;
507 /* Implementation of linux_target_ops method "arch_setup". */
510 aarch64_arch_setup (void)
512 current_process ()->tdesc
= aarch64_linux_read_description ();
514 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
517 static struct regset_info aarch64_regsets
[] =
519 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
520 sizeof (struct user_pt_regs
), GENERAL_REGS
,
521 aarch64_fill_gregset
, aarch64_store_gregset
},
522 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
523 sizeof (struct user_fpsimd_state
), FP_REGS
,
524 aarch64_fill_fpregset
, aarch64_store_fpregset
526 { 0, 0, 0, -1, -1, NULL
, NULL
}
529 static struct regsets_info aarch64_regsets_info
=
531 aarch64_regsets
, /* regsets */
533 NULL
, /* disabled_regsets */
536 static struct regs_info regs_info_aarch64
=
538 NULL
, /* regset_bitmap */
540 &aarch64_regsets_info
,
543 /* Implementation of linux_target_ops method "regs_info". */
545 static const struct regs_info
*
546 aarch64_regs_info (void)
548 if (is_64bit_tdesc ())
549 return ®s_info_aarch64
;
551 return ®s_info_aarch32
;
554 /* Implementation of linux_target_ops method "supports_tracepoints". */
557 aarch64_supports_tracepoints (void)
559 if (current_thread
== NULL
)
563 /* We don't support tracepoints on aarch32 now. */
564 return is_64bit_tdesc ();
568 /* Implementation of linux_target_ops method "get_thread_area". */
571 aarch64_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
576 iovec
.iov_base
= ®
;
577 iovec
.iov_len
= sizeof (reg
);
579 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
587 /* List of opcodes that we need for building the jump pad and relocating
592 /* B 0001 01ii iiii iiii iiii iiii iiii iiii */
593 /* BL 1001 01ii iiii iiii iiii iiii iiii iiii */
594 /* B.COND 0101 0100 iiii iiii iiii iiii iii0 cccc */
595 /* CBZ s011 0100 iiii iiii iiii iiii iiir rrrr */
596 /* CBNZ s011 0101 iiii iiii iiii iiii iiir rrrr */
597 /* TBZ b011 0110 bbbb biii iiii iiii iiir rrrr */
598 /* TBNZ b011 0111 bbbb biii iiii iiii iiir rrrr */
601 BCOND
= 0x40000000 | B
,
602 CBZ
= 0x20000000 | B
,
603 CBNZ
= 0x21000000 | B
,
604 TBZ
= 0x36000000 | B
,
605 TBNZ
= 0x37000000 | B
,
606 /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
608 /* RET 1101 0110 0101 1111 0000 00rr rrr0 0000 */
610 /* STP s010 100o o0ii iiii irrr rrrr rrrr rrrr */
611 /* LDP s010 100o o1ii iiii irrr rrrr rrrr rrrr */
612 /* STP (SIMD&VFP) ss10 110o o0ii iiii irrr rrrr rrrr rrrr */
613 /* LDP (SIMD&VFP) ss10 110o o1ii iiii irrr rrrr rrrr rrrr */
616 STP_SIMD_VFP
= 0x04000000 | STP
,
617 LDP_SIMD_VFP
= 0x04000000 | LDP
,
618 /* STR ss11 100o 00xi iiii iiii xxrr rrrr rrrr */
619 /* LDR ss11 100o 01xi iiii iiii xxrr rrrr rrrr */
620 /* LDRSW 1011 100o 10xi iiii iiii xxrr rrrr rrrr */
622 LDR
= 0x00400000 | STR
,
623 LDRSW
= 0x80800000 | STR
,
624 /* LDAXR ss00 1000 0101 1111 1111 11rr rrrr rrrr */
626 /* STXR ss00 1000 000r rrrr 0111 11rr rrrr rrrr */
628 /* STLR ss00 1000 1001 1111 1111 11rr rrrr rrrr */
630 /* MOV s101 0010 1xxi iiii iiii iiii iiir rrrr */
631 /* MOVK s111 0010 1xxi iiii iiii iiii iiir rrrr */
633 MOVK
= 0x20000000 | MOV
,
634 /* ADD s00o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
635 /* SUB s10o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
636 /* SUBS s11o ooo1 xxxx xxxx xxxx xxxx xxxx xxxx */
638 SUB
= 0x40000000 | ADD
,
639 SUBS
= 0x20000000 | SUB
,
640 /* AND s000 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
641 /* ORR s010 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
642 /* ORN s010 1010 xx1x xxxx xxxx xxxx xxxx xxxx */
643 /* EOR s100 1010 xx0x xxxx xxxx xxxx xxxx xxxx */
645 ORR
= 0x20000000 | AND
,
646 ORN
= 0x00200000 | ORR
,
647 EOR
= 0x40000000 | AND
,
648 /* LSLV s001 1010 110r rrrr 0010 00rr rrrr rrrr */
649 /* LSRV s001 1010 110r rrrr 0010 01rr rrrr rrrr */
650 /* ASRV s001 1010 110r rrrr 0010 10rr rrrr rrrr */
652 LSRV
= 0x00000400 | LSLV
,
653 ASRV
= 0x00000800 | LSLV
,
654 /* SBFM s001 0011 0nii iiii iiii iirr rrrr rrrr */
656 /* UBFM s101 0011 0nii iiii iiii iirr rrrr rrrr */
657 UBFM
= 0x40000000 | SBFM
,
658 /* CSINC s001 1010 100r rrrr cccc 01rr rrrr rrrr */
660 /* MUL s001 1011 000r rrrr 0111 11rr rrrr rrrr */
662 /* MSR (register) 1101 0101 0001 oooo oooo oooo ooor rrrr */
663 /* MRS 1101 0101 0011 oooo oooo oooo ooor rrrr */
665 MRS
= 0x00200000 | MSR
,
666 /* HINT 1101 0101 0000 0011 0010 oooo ooo1 1111 */
668 SEVL
= (5 << 5) | HINT
,
669 WFE
= (2 << 5) | HINT
,
670 NOP
= (0 << 5) | HINT
,
673 /* List of condition codes that we need. */
675 enum aarch64_condition_codes
686 /* Representation of a general purpose register of the form xN or wN.
688 This type is used by emitting functions that take registers as operands. */
690 struct aarch64_register
696 /* Representation of an operand. At this time, it only supports register
697 and immediate types. */
699 struct aarch64_operand
701 /* Type of the operand. */
707 /* Value of the operand according to the type. */
711 struct aarch64_register reg
;
715 /* List of registers that we are currently using, we can add more here as
716 we need to use them. */
718 /* General purpose scratch registers (64 bit). */
719 static const struct aarch64_register x0
= { 0, 1 };
720 static const struct aarch64_register x1
= { 1, 1 };
721 static const struct aarch64_register x2
= { 2, 1 };
722 static const struct aarch64_register x3
= { 3, 1 };
723 static const struct aarch64_register x4
= { 4, 1 };
725 /* General purpose scratch registers (32 bit). */
726 static const struct aarch64_register w0
= { 0, 0 };
727 static const struct aarch64_register w2
= { 2, 0 };
729 /* Intra-procedure scratch registers. */
730 static const struct aarch64_register ip0
= { 16, 1 };
732 /* Special purpose registers. */
733 static const struct aarch64_register fp
= { 29, 1 };
734 static const struct aarch64_register lr
= { 30, 1 };
735 static const struct aarch64_register sp
= { 31, 1 };
736 static const struct aarch64_register xzr
= { 31, 1 };
738 /* Dynamically allocate a new register. If we know the register
739 statically, we should make it a global as above instead of using this
742 static struct aarch64_register
743 aarch64_register (unsigned num
, int is64
)
745 return (struct aarch64_register
) { num
, is64
};
748 /* Helper function to create a register operand, for instructions with
749 different types of operands.
752 p += emit_mov (p, x0, register_operand (x1)); */
754 static struct aarch64_operand
755 register_operand (struct aarch64_register reg
)
757 struct aarch64_operand operand
;
759 operand
.type
= OPERAND_REGISTER
;
765 /* Helper function to create an immediate operand, for instructions with
766 different types of operands.
769 p += emit_mov (p, x0, immediate_operand (12)); */
771 static struct aarch64_operand
772 immediate_operand (uint32_t imm
)
774 struct aarch64_operand operand
;
776 operand
.type
= OPERAND_IMMEDIATE
;
782 /* Representation of a memory operand, used for load and store
785 The types correspond to the following variants:
787 MEMORY_OPERAND_OFFSET: LDR rt, [rn, #offset]
788 MEMORY_OPERAND_PREINDEX: LDR rt, [rn, #index]!
789 MEMORY_OPERAND_POSTINDEX: LDR rt, [rn], #index */
791 struct aarch64_memory_operand
793 /* Type of the operand. */
796 MEMORY_OPERAND_OFFSET
,
797 MEMORY_OPERAND_PREINDEX
,
798 MEMORY_OPERAND_POSTINDEX
,
800 /* Index from the base register. */
804 /* Helper function to create an offset memory operand.
807 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
809 static struct aarch64_memory_operand
810 offset_memory_operand (int32_t offset
)
812 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
815 /* Helper function to create a pre-index memory operand.
818 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
820 static struct aarch64_memory_operand
821 preindex_memory_operand (int32_t index
)
823 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
826 /* Helper function to create a post-index memory operand.
829 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
831 static struct aarch64_memory_operand
832 postindex_memory_operand (int32_t index
)
834 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
837 /* System control registers. These special registers can be written and
838 read with the MRS and MSR instructions.
840 - NZCV: Condition flags. GDB refers to this register under the CPSR
842 - FPSR: Floating-point status register.
843 - FPCR: Floating-point control registers.
844 - TPIDR_EL0: Software thread ID register. */
846 enum aarch64_system_control_registers
848 /* op0 op1 crn crm op2 */
849 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
850 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
851 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
852 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
855 /* Helper macro to mask and shift a value into a bitfield. */
857 #define ENCODE(val, size, offset) \
858 ((uint32_t) ((val & ((1ULL << size) - 1)) << offset))
860 /* Write a 32-bit unsigned integer INSN info *BUF. Return the number of
861 instructions written (aka. 1). */
864 emit_insn (uint32_t *buf
, uint32_t insn
)
870 /* Write a B or BL instruction into *BUF.
875 IS_BL specifies if the link register should be updated.
876 OFFSET is the immediate offset from the current PC. It is
877 byte-addressed but should be 4 bytes aligned. It has a limited range of
878 +/- 128MB (26 bits << 2). */
881 emit_b (uint32_t *buf
, int is_bl
, int32_t offset
)
883 uint32_t imm26
= ENCODE (offset
>> 2, 26, 0);
886 return emit_insn (buf
, BL
| imm26
);
888 return emit_insn (buf
, B
| imm26
);
891 /* Write a BCOND instruction into *BUF.
895 COND specifies the condition field.
896 OFFSET is the immediate offset from the current PC. It is
897 byte-addressed but should be 4 bytes aligned. It has a limited range of
898 +/- 1MB (19 bits << 2). */
901 emit_bcond (uint32_t *buf
, unsigned cond
, int32_t offset
)
903 return emit_insn (buf
, BCOND
| ENCODE (offset
>> 2, 19, 5)
904 | ENCODE (cond
, 4, 0));
907 /* Write a CBZ or CBNZ instruction into *BUF.
912 IS_CBNZ distinguishes between CBZ and CBNZ instructions.
913 RN is the register to test.
914 OFFSET is the immediate offset from the current PC. It is
915 byte-addressed but should be 4 bytes aligned. It has a limited range of
916 +/- 1MB (19 bits << 2). */
919 emit_cb (uint32_t *buf
, int is_cbnz
, struct aarch64_register rt
,
922 uint32_t imm19
= ENCODE (offset
>> 2, 19, 5);
923 uint32_t sf
= ENCODE (rt
.is64
, 1, 31);
926 return emit_insn (buf
, CBNZ
| sf
| imm19
| ENCODE (rt
.num
, 5, 0));
928 return emit_insn (buf
, CBZ
| sf
| imm19
| ENCODE (rt
.num
, 5, 0));
931 /* Write a TBZ or TBNZ instruction into *BUF.
933 TBZ rt, #bit, #offset
934 TBNZ rt, #bit, #offset
936 IS_TBNZ distinguishes between TBZ and TBNZ instructions.
937 RT is the register to test.
938 BIT is the index of the bit to test in register RT.
939 OFFSET is the immediate offset from the current PC. It is
940 byte-addressed but should be 4 bytes aligned. It has a limited range of
941 +/- 32KB (14 bits << 2). */
944 emit_tb (uint32_t *buf
, int is_tbnz
, unsigned bit
,
945 struct aarch64_register rt
, int32_t offset
)
947 uint32_t imm14
= ENCODE (offset
>> 2, 14, 5);
948 uint32_t b40
= ENCODE (bit
, 5, 19);
949 uint32_t b5
= ENCODE (bit
>> 5, 1, 31);
952 return emit_insn (buf
, TBNZ
| b5
| b40
| imm14
| ENCODE (rt
.num
, 5, 0));
954 return emit_insn (buf
, TBZ
| b5
| b40
| imm14
| ENCODE (rt
.num
, 5, 0));
957 /* Write a BLR instruction into *BUF.
961 RN is the register to branch to. */
964 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
966 return emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
969 /* Write a RET instruction into *BUF.
973 RN is the register to branch to. */
976 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
978 return emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
982 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
983 struct aarch64_register rt
,
984 struct aarch64_register rt2
,
985 struct aarch64_register rn
,
986 struct aarch64_memory_operand operand
)
993 opc
= ENCODE (2, 2, 30);
995 opc
= ENCODE (0, 2, 30);
997 switch (operand
.type
)
999 case MEMORY_OPERAND_OFFSET
:
1001 pre_index
= ENCODE (1, 1, 24);
1002 write_back
= ENCODE (0, 1, 23);
1005 case MEMORY_OPERAND_POSTINDEX
:
1007 pre_index
= ENCODE (0, 1, 24);
1008 write_back
= ENCODE (1, 1, 23);
1011 case MEMORY_OPERAND_PREINDEX
:
1013 pre_index
= ENCODE (1, 1, 24);
1014 write_back
= ENCODE (1, 1, 23);
1021 return emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1022 | ENCODE (operand
.index
>> 3, 7, 15)
1023 | ENCODE (rt2
.num
, 5, 10)
1024 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1027 /* Write a STP instruction into *BUF.
1029 STP rt, rt2, [rn, #offset]
1030 STP rt, rt2, [rn, #index]!
1031 STP rt, rt2, [rn], #index
1033 RT and RT2 are the registers to store.
1034 RN is the base address register.
1035 OFFSET is the immediate to add to the base address. It is limited to a
1036 -512 .. 504 range (7 bits << 3). */
1039 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1040 struct aarch64_register rt2
, struct aarch64_register rn
,
1041 struct aarch64_memory_operand operand
)
1043 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1046 /* Write a LDP instruction into *BUF.
1048 LDP rt, rt2, [rn, #offset]
1049 LDP rt, rt2, [rn, #index]!
1050 LDP rt, rt2, [rn], #index
1052 RT and RT2 are the registers to store.
1053 RN is the base address register.
1054 OFFSET is the immediate to add to the base address. It is limited to a
1055 -512 .. 504 range (7 bits << 3). */
1058 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1059 struct aarch64_register rt2
, struct aarch64_register rn
,
1060 struct aarch64_memory_operand operand
)
1062 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1065 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1067 LDP qt, qt2, [rn, #offset]
1069 RT and RT2 are the Q registers to store.
1070 RN is the base address register.
1071 OFFSET is the immediate to add to the base address. It is limited to
1072 -1024 .. 1008 range (7 bits << 4). */
1075 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1076 struct aarch64_register rn
, int32_t offset
)
1078 uint32_t opc
= ENCODE (2, 2, 30);
1079 uint32_t pre_index
= ENCODE (1, 1, 24);
1081 return emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1082 | ENCODE (offset
>> 4, 7, 15) | ENCODE (rt2
, 5, 10)
1083 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1086 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1088 STP qt, qt2, [rn, #offset]
1090 RT and RT2 are the Q registers to store.
1091 RN is the base address register.
1092 OFFSET is the immediate to add to the base address. It is limited to
1093 -1024 .. 1008 range (7 bits << 4). */
1096 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1097 struct aarch64_register rn
, int32_t offset
)
1099 uint32_t opc
= ENCODE (2, 2, 30);
1100 uint32_t pre_index
= ENCODE (1, 1, 24);
1102 return emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1103 | ENCODE (offset
>> 4, 7, 15) | ENCODE (rt2
, 5, 10)
1104 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1107 /* Helper function emitting a load or store instruction. */
1110 emit_load_store (uint32_t *buf
, uint32_t size
, enum aarch64_opcodes opcode
,
1111 struct aarch64_register rt
, struct aarch64_register rn
,
1112 struct aarch64_memory_operand operand
)
1116 switch (operand
.type
)
1118 case MEMORY_OPERAND_OFFSET
:
1120 op
= ENCODE (1, 1, 24);
1122 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1123 | ENCODE (operand
.index
>> 3, 12, 10)
1124 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1126 case MEMORY_OPERAND_POSTINDEX
:
1128 uint32_t post_index
= ENCODE (1, 2, 10);
1130 op
= ENCODE (0, 1, 24);
1132 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1133 | post_index
| ENCODE (operand
.index
, 9, 12)
1134 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1136 case MEMORY_OPERAND_PREINDEX
:
1138 uint32_t pre_index
= ENCODE (3, 2, 10);
1140 op
= ENCODE (0, 1, 24);
1142 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30) | op
1143 | pre_index
| ENCODE (operand
.index
, 9, 12)
1144 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1151 /* Write a LDR instruction into *BUF.
1153 LDR rt, [rn, #offset]
1154 LDR rt, [rn, #index]!
1155 LDR rt, [rn], #index
1157 RT is the register to store.
1158 RN is the base address register.
1159 OFFSET is the immediate to add to the base address. It is limited to
1160 0 .. 32760 range (12 bits << 3). */
1163 emit_ldr (uint32_t *buf
, struct aarch64_register rt
,
1164 struct aarch64_register rn
, struct aarch64_memory_operand operand
)
1166 return emit_load_store (buf
, rt
.is64
? 3 : 2, LDR
, rt
, rn
, operand
);
1169 /* Write a LDRH instruction into *BUF.
1171 LDRH wt, [xn, #offset]
1172 LDRH wt, [xn, #index]!
1173 LDRH wt, [xn], #index
1175 RT is the register to store.
1176 RN is the base address register.
1177 OFFSET is the immediate to add to the base address. It is limited to
1178 0 .. 32760 range (12 bits << 3). */
1181 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1182 struct aarch64_register rn
,
1183 struct aarch64_memory_operand operand
)
1185 return emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1188 /* Write a LDRB instruction into *BUF.
1190 LDRB wt, [xn, #offset]
1191 LDRB wt, [xn, #index]!
1192 LDRB wt, [xn], #index
1194 RT is the register to store.
1195 RN is the base address register.
1196 OFFSET is the immediate to add to the base address. It is limited to
1197 0 .. 32760 range (12 bits << 3). */
1200 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1201 struct aarch64_register rn
,
1202 struct aarch64_memory_operand operand
)
1204 return emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1207 /* Write a LDRSW instruction into *BUF. The register size is 64-bit.
1209 LDRSW xt, [rn, #offset]
1210 LDRSW xt, [rn, #index]!
1211 LDRSW xt, [rn], #index
1213 RT is the register to store.
1214 RN is the base address register.
1215 OFFSET is the immediate to add to the base address. It is limited to
1216 0 .. 16380 range (12 bits << 2). */
1219 emit_ldrsw (uint32_t *buf
, struct aarch64_register rt
,
1220 struct aarch64_register rn
,
1221 struct aarch64_memory_operand operand
)
1223 return emit_load_store (buf
, 3, LDRSW
, rt
, rn
, operand
);
1226 /* Write a STR instruction into *BUF.
1228 STR rt, [rn, #offset]
1229 STR rt, [rn, #index]!
1230 STR rt, [rn], #index
1232 RT is the register to store.
1233 RN is the base address register.
1234 OFFSET is the immediate to add to the base address. It is limited to
1235 0 .. 32760 range (12 bits << 3). */
1238 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1239 struct aarch64_register rn
,
1240 struct aarch64_memory_operand operand
)
1242 return emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1245 /* Helper function emitting an exclusive load or store instruction. */
1248 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1249 enum aarch64_opcodes opcode
,
1250 struct aarch64_register rs
,
1251 struct aarch64_register rt
,
1252 struct aarch64_register rt2
,
1253 struct aarch64_register rn
)
1255 return emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1256 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1257 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1260 /* Write a LAXR instruction into *BUF.
1264 RT is the destination register.
1265 RN is the base address register. */
1268 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1269 struct aarch64_register rn
)
1271 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1275 /* Write a STXR instruction into *BUF.
1279 RS is the result register, it indicates if the store succeeded or not.
1280 RT is the destination register.
1281 RN is the base address register. */
1284 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1285 struct aarch64_register rt
, struct aarch64_register rn
)
1287 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1291 /* Write a STLR instruction into *BUF.
1295 RT is the register to store.
1296 RN is the base address register. */
1299 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1300 struct aarch64_register rn
)
1302 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1306 /* Helper function for data processing instructions with register sources. */
1309 emit_data_processing_reg (uint32_t *buf
, enum aarch64_opcodes opcode
,
1310 struct aarch64_register rd
,
1311 struct aarch64_register rn
,
1312 struct aarch64_register rm
)
1314 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1316 return emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1317 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1320 /* Helper function for data processing instructions taking either a register
1324 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1325 struct aarch64_register rd
,
1326 struct aarch64_register rn
,
1327 struct aarch64_operand operand
)
1329 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1330 /* The opcode is different for register and immediate source operands. */
1331 uint32_t operand_opcode
;
1333 if (operand
.type
== OPERAND_IMMEDIATE
)
1335 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1336 operand_opcode
= ENCODE (8, 4, 25);
1338 return emit_insn (buf
, opcode
| operand_opcode
| size
1339 | ENCODE (operand
.imm
, 12, 10)
1340 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1344 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1345 operand_opcode
= ENCODE (5, 4, 25);
1347 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1352 /* Write an ADD instruction into *BUF.
1357 This function handles both an immediate and register add.
1359 RD is the destination register.
1360 RN is the input register.
1361 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1362 OPERAND_REGISTER. */
1365 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1366 struct aarch64_register rn
, struct aarch64_operand operand
)
1368 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1371 /* Write a SUB instruction into *BUF.
1376 This function handles both an immediate and register sub.
1378 RD is the destination register.
1379 RN is the input register.
1380 IMM is the immediate to substract to RN. */
1383 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1384 struct aarch64_register rn
, struct aarch64_operand operand
)
1386 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1389 /* Write a MOV instruction into *BUF.
1394 This function handles both a wide immediate move and a register move,
1395 with the condition that the source register is not xzr. xzr and the
1396 stack pointer share the same encoding and this function only supports
1399 RD is the destination register.
1400 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1401 OPERAND_REGISTER. */
1404 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1405 struct aarch64_operand operand
)
1407 if (operand
.type
== OPERAND_IMMEDIATE
)
1409 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1410 /* Do not shift the immediate. */
1411 uint32_t shift
= ENCODE (0, 2, 21);
1413 return emit_insn (buf
, MOV
| size
| shift
1414 | ENCODE (operand
.imm
, 16, 5)
1415 | ENCODE (rd
.num
, 5, 0));
1418 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1421 /* Write a MOVK instruction into *BUF.
1423 MOVK rd, #imm, lsl #shift
1425 RD is the destination register.
1426 IMM is the immediate.
1427 SHIFT is the logical shift left to apply to IMM. */
1430 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1433 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1435 return emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1436 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1439 /* Write instructions into *BUF in order to move ADDR into a register.
1440 ADDR can be a 64-bit value.
1442 This function will emit a series of MOV and MOVK instructions, such as:
1445 MOVK xd, #(addr >> 16), lsl #16
1446 MOVK xd, #(addr >> 32), lsl #32
1447 MOVK xd, #(addr >> 48), lsl #48 */
1450 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1454 /* The MOV (wide immediate) instruction clears to top bits of the
1456 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1458 if ((addr
>> 16) != 0)
1459 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1463 if ((addr
>> 32) != 0)
1464 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1468 if ((addr
>> 48) != 0)
1469 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1474 /* Write a SUBS instruction into *BUF.
1478 This instruction update the condition flags.
1480 RD is the destination register.
1481 RN and RM are the source registers. */
1484 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1485 struct aarch64_register rn
, struct aarch64_operand operand
)
1487 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1490 /* Write a CMP instruction into *BUF.
1494 This instruction is an alias of SUBS xzr, rn, rm.
1496 RN and RM are the registers to compare. */
1499 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1500 struct aarch64_operand operand
)
1502 return emit_subs (buf
, xzr
, rn
, operand
);
1505 /* Write a AND instruction into *BUF.
1509 RD is the destination register.
1510 RN and RM are the source registers. */
1513 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1514 struct aarch64_register rn
, struct aarch64_register rm
)
1516 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1519 /* Write a ORR instruction into *BUF.
1523 RD is the destination register.
1524 RN and RM are the source registers. */
1527 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1528 struct aarch64_register rn
, struct aarch64_register rm
)
1530 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1533 /* Write a ORN instruction into *BUF.
1537 RD is the destination register.
1538 RN and RM are the source registers. */
1541 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1542 struct aarch64_register rn
, struct aarch64_register rm
)
1544 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1547 /* Write a EOR instruction into *BUF.
1551 RD is the destination register.
1552 RN and RM are the source registers. */
1555 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1556 struct aarch64_register rn
, struct aarch64_register rm
)
1558 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1561 /* Write a MVN instruction into *BUF.
1565 This is an alias for ORN rd, xzr, rm.
1567 RD is the destination register.
1568 RM is the source register. */
1571 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1572 struct aarch64_register rm
)
1574 return emit_orn (buf
, rd
, xzr
, rm
);
1577 /* Write a LSLV instruction into *BUF.
1581 RD is the destination register.
1582 RN and RM are the source registers. */
1585 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1586 struct aarch64_register rn
, struct aarch64_register rm
)
1588 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1591 /* Write a LSRV instruction into *BUF.
1595 RD is the destination register.
1596 RN and RM are the source registers. */
1599 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1600 struct aarch64_register rn
, struct aarch64_register rm
)
1602 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1605 /* Write a ASRV instruction into *BUF.
1609 RD is the destination register.
1610 RN and RM are the source registers. */
1613 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1614 struct aarch64_register rn
, struct aarch64_register rm
)
1616 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1619 /* Write a MUL instruction into *BUF.
1623 RD is the destination register.
1624 RN and RM are the source registers. */
1627 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1628 struct aarch64_register rn
, struct aarch64_register rm
)
1630 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1633 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1637 RT is the destination register.
1638 SYSTEM_REG is special purpose register to read. */
1641 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1642 enum aarch64_system_control_registers system_reg
)
1644 return emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1645 | ENCODE (rt
.num
, 5, 0));
1648 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1652 SYSTEM_REG is special purpose register to write.
1653 RT is the input register. */
1656 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1657 struct aarch64_register rt
)
1659 return emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1660 | ENCODE (rt
.num
, 5, 0));
1663 /* Write a SEVL instruction into *BUF.
1665 This is a hint instruction telling the hardware to trigger an event. */
1668 emit_sevl (uint32_t *buf
)
1670 return emit_insn (buf
, SEVL
);
1673 /* Write a WFE instruction into *BUF.
1675 This is a hint instruction telling the hardware to wait for an event. */
1678 emit_wfe (uint32_t *buf
)
1680 return emit_insn (buf
, WFE
);
1683 /* Write a SBFM instruction into *BUF.
1685 SBFM rd, rn, #immr, #imms
1687 This instruction moves the bits from #immr to #imms into the
1688 destination, sign extending the result.
1690 RD is the destination register.
1691 RN is the source register.
1692 IMMR is the bit number to start at (least significant bit).
1693 IMMS is the bit number to stop at (most significant bit). */
1696 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1697 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1699 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1700 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1702 return emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1703 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1704 | ENCODE (rd
.num
, 5, 0));
1707 /* Write a SBFX instruction into *BUF.
1709 SBFX rd, rn, #lsb, #width
1711 This instruction moves #width bits from #lsb into the destination, sign
1712 extending the result. This is an alias for:
1714 SBFM rd, rn, #lsb, #(lsb + width - 1)
1716 RD is the destination register.
1717 RN is the source register.
1718 LSB is the bit number to start at (least significant bit).
1719 WIDTH is the number of bits to move. */
1722 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1723 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1725 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1728 /* Write a UBFM instruction into *BUF.
1730 UBFM rd, rn, #immr, #imms
1732 This instruction moves the bits from #immr to #imms into the
1733 destination, extending the result with zeros.
1735 RD is the destination register.
1736 RN is the source register.
1737 IMMR is the bit number to start at (least significant bit).
1738 IMMS is the bit number to stop at (most significant bit). */
1741 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1742 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1744 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1745 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1747 return emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1748 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1749 | ENCODE (rd
.num
, 5, 0));
1752 /* Write a UBFX instruction into *BUF.
1754 UBFX rd, rn, #lsb, #width
1756 This instruction moves #width bits from #lsb into the destination,
1757 extending the result with zeros. This is an alias for:
1759 UBFM rd, rn, #lsb, #(lsb + width - 1)
1761 RD is the destination register.
1762 RN is the source register.
1763 LSB is the bit number to start at (least significant bit).
1764 WIDTH is the number of bits to move. */
1767 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1768 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1770 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1773 /* Write a CSINC instruction into *BUF.
1775 CSINC rd, rn, rm, cond
1777 This instruction conditionally increments rn or rm and places the result
1778 in rd. rn is chosen is the condition is true.
1780 RD is the destination register.
1781 RN and RM are the source registers.
1782 COND is the encoded condition. */
1785 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1786 struct aarch64_register rn
, struct aarch64_register rm
,
1789 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1791 return emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1792 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1793 | ENCODE (rd
.num
, 5, 0));
1796 /* Write a CSET instruction into *BUF.
1800 This instruction conditionally write 1 or 0 in the destination register.
1801 1 is written if the condition is true. This is an alias for:
1803 CSINC rd, xzr, xzr, !cond
1805 Note that the condition needs to be inverted.
1807 RD is the destination register.
1808 RN and RM are the source registers.
1809 COND is the encoded condition. */
1812 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1814 /* The least significant bit of the condition needs toggling in order to
1816 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1819 /* Write a NOP instruction into *BUF. */
1822 emit_nop (uint32_t *buf
)
1824 return emit_insn (buf
, NOP
);
1827 /* Write LEN instructions from BUF into the inferior memory at *TO.
1829 Note instructions are always little endian on AArch64, unlike data. */
1832 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1834 size_t byte_len
= len
* sizeof (uint32_t);
1835 #if (__BYTE_ORDER == __BIG_ENDIAN)
1836 uint32_t *le_buf
= xmalloc (byte_len
);
1839 for (i
= 0; i
< len
; i
++)
1840 le_buf
[i
] = htole32 (buf
[i
]);
1842 write_inferior_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1846 write_inferior_memory (*to
, (const unsigned char *) buf
, byte_len
);
1852 /* Helper function. Return 1 if VAL can be encoded in BITS bits. */
1855 can_encode_int32 (int32_t val
, unsigned bits
)
1857 /* This must be an arithemic shift. */
1858 int32_t rest
= val
>> bits
;
1860 return rest
== 0 || rest
== -1;
1863 /* Sub-class of struct aarch64_insn_data, store information of
1864 instruction relocation for fast tracepoint. Visitor can
1865 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1866 the relocated instructions in buffer pointed by INSN_PTR. */
1868 struct aarch64_insn_relocation_data
1870 struct aarch64_insn_data base
;
1872 /* The new address the instruction is relocated to. */
1874 /* Pointer to the buffer of relocated instruction(s). */
1878 /* Implementation of aarch64_insn_visitor method "b". */
1881 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1882 struct aarch64_insn_data
*data
)
1884 struct aarch64_insn_relocation_data
*insn_reloc
1885 = (struct aarch64_insn_relocation_data
*) data
;
1887 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1889 if (can_encode_int32 (new_offset
, 28))
1890 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1893 /* Implementation of aarch64_insn_visitor method "b_cond". */
1896 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1897 struct aarch64_insn_data
*data
)
1899 struct aarch64_insn_relocation_data
*insn_reloc
1900 = (struct aarch64_insn_relocation_data
*) data
;
1902 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1904 if (can_encode_int32 (new_offset
, 21))
1906 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1909 else if (can_encode_int32 (new_offset
, 28))
1911 /* The offset is out of range for a conditional branch
1912 instruction but not for a unconditional branch. We can use
1913 the following instructions instead:
1915 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1916 B NOT_TAKEN ; Else jump over TAKEN and continue.
1923 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1924 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1925 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1929 /* Implementation of aarch64_insn_visitor method "cb". */
1932 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1933 const unsigned rn
, int is64
,
1934 struct aarch64_insn_data
*data
)
1936 struct aarch64_insn_relocation_data
*insn_reloc
1937 = (struct aarch64_insn_relocation_data
*) data
;
1939 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1941 if (can_encode_int32 (new_offset
, 21))
1943 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1944 aarch64_register (rn
, is64
), new_offset
);
1946 else if (can_encode_int32 (new_offset
, 28))
1948 /* The offset is out of range for a compare and branch
1949 instruction but not for a unconditional branch. We can use
1950 the following instructions instead:
1952 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1953 B NOT_TAKEN ; Else jump over TAKEN and continue.
1959 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1960 aarch64_register (rn
, is64
), 8);
1961 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1962 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1966 /* Implementation of aarch64_insn_visitor method "tb". */
1969 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1970 const unsigned rt
, unsigned bit
,
1971 struct aarch64_insn_data
*data
)
1973 struct aarch64_insn_relocation_data
*insn_reloc
1974 = (struct aarch64_insn_relocation_data
*) data
;
1976 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1978 if (can_encode_int32 (new_offset
, 16))
1980 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1981 aarch64_register (rt
, 1), new_offset
);
1983 else if (can_encode_int32 (new_offset
, 28))
1985 /* The offset is out of range for a test bit and branch
1986 instruction but not for a unconditional branch. We can use
1987 the following instructions instead:
1989 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1990 B NOT_TAKEN ; Else jump over TAKEN and continue.
1996 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1997 aarch64_register (rt
, 1), 8);
1998 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1999 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
2004 /* Implementation of aarch64_insn_visitor method "adr". */
2007 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
2009 struct aarch64_insn_data
*data
)
2011 struct aarch64_insn_relocation_data
*insn_reloc
2012 = (struct aarch64_insn_relocation_data
*) data
;
2013 /* We know exactly the address the ADR{P,} instruction will compute.
2014 We can just write it to the destination register. */
2015 CORE_ADDR address
= data
->insn_addr
+ offset
;
2019 /* Clear the lower 12 bits of the offset to get the 4K page. */
2020 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2021 aarch64_register (rd
, 1),
2025 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2026 aarch64_register (rd
, 1), address
);
2029 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2032 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
2033 const unsigned rt
, const int is64
,
2034 struct aarch64_insn_data
*data
)
2036 struct aarch64_insn_relocation_data
*insn_reloc
2037 = (struct aarch64_insn_relocation_data
*) data
;
2038 CORE_ADDR address
= data
->insn_addr
+ offset
;
2040 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
2041 aarch64_register (rt
, 1), address
);
2043 /* We know exactly what address to load from, and what register we
2046 MOV xd, #(oldloc + offset)
2047 MOVK xd, #((oldloc + offset) >> 16), lsl #16
2050 LDR xd, [xd] ; or LDRSW xd, [xd]
2055 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
2056 aarch64_register (rt
, 1),
2057 aarch64_register (rt
, 1),
2058 offset_memory_operand (0));
2060 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
2061 aarch64_register (rt
, is64
),
2062 aarch64_register (rt
, 1),
2063 offset_memory_operand (0));
2066 /* Implementation of aarch64_insn_visitor method "others". */
2069 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
2070 struct aarch64_insn_data
*data
)
2072 struct aarch64_insn_relocation_data
*insn_reloc
2073 = (struct aarch64_insn_relocation_data
*) data
;
2075 /* The instruction is not PC relative. Just re-emit it at the new
2077 insn_reloc
->insn_ptr
+= emit_insn (insn_reloc
->insn_ptr
, insn
);
2080 static const struct aarch64_insn_visitor visitor
=
2082 aarch64_ftrace_insn_reloc_b
,
2083 aarch64_ftrace_insn_reloc_b_cond
,
2084 aarch64_ftrace_insn_reloc_cb
,
2085 aarch64_ftrace_insn_reloc_tb
,
2086 aarch64_ftrace_insn_reloc_adr
,
2087 aarch64_ftrace_insn_reloc_ldr_literal
,
2088 aarch64_ftrace_insn_reloc_others
,
2091 /* Implementation of linux_target_ops method
2092 "install_fast_tracepoint_jump_pad". */
2095 aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
2097 CORE_ADDR collector
,
2100 CORE_ADDR
*jump_entry
,
2101 CORE_ADDR
*trampoline
,
2102 ULONGEST
*trampoline_size
,
2103 unsigned char *jjump_pad_insn
,
2104 ULONGEST
*jjump_pad_insn_size
,
2105 CORE_ADDR
*adjusted_insn_addr
,
2106 CORE_ADDR
*adjusted_insn_addr_end
,
2114 CORE_ADDR buildaddr
= *jump_entry
;
2115 struct aarch64_insn_relocation_data insn_data
;
2117 /* We need to save the current state on the stack both to restore it
2118 later and to collect register values when the tracepoint is hit.
2120 The saved registers are pushed in a layout that needs to be in sync
2121 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2122 the supply_fast_tracepoint_registers function will fill in the
2123 register cache from a pointer to saved registers on the stack we build
2126 For simplicity, we set the size of each cell on the stack to 16 bytes.
2127 This way one cell can hold any register type, from system registers
2128 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2129 has to be 16 bytes aligned anyway.
2131 Note that the CPSR register does not exist on AArch64. Instead we
2132 can access system bits describing the process state with the
2133 MRS/MSR instructions, namely the condition flags. We save them as
2134 if they are part of a CPSR register because that's how GDB
2135 interprets these system bits. At the moment, only the condition
2136 flags are saved in CPSR (NZCV).
2138 Stack layout, each cell is 16 bytes (descending):
2140 High *-------- SIMD&FP registers from 31 down to 0. --------*
2146 *---- General purpose registers from 30 down to 0. ----*
2152 *------------- Special purpose registers. -------------*
2155 | CPSR (NZCV) | 5 cells
2158 *------------- collecting_t object --------------------*
2159 | TPIDR_EL0 | struct tracepoint * |
2160 Low *------------------------------------------------------*
2162 After this stack is set up, we issue a call to the collector, passing
2163 it the saved registers at (SP + 16). */
2165 /* Push SIMD&FP registers on the stack:
2167 SUB sp, sp, #(32 * 16)
2169 STP q30, q31, [sp, #(30 * 16)]
2174 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2175 for (i
= 30; i
>= 0; i
-= 2)
2176 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2178 /* Push general puspose registers on the stack. Note that we do not need
2179 to push x31 as it represents the xzr register and not the stack
2180 pointer in a STR instruction.
2182 SUB sp, sp, #(31 * 16)
2184 STR x30, [sp, #(30 * 16)]
2189 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2190 for (i
= 30; i
>= 0; i
-= 1)
2191 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2192 offset_memory_operand (i
* 16));
2194 /* Make space for 5 more cells.
2196 SUB sp, sp, #(5 * 16)
2199 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2204 ADD x4, sp, #((32 + 31 + 5) * 16)
2205 STR x4, [sp, #(4 * 16)]
2208 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2209 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2211 /* Save PC (tracepoint address):
2216 STR x3, [sp, #(3 * 16)]
2220 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2221 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2223 /* Save CPSR (NZCV), FPSR and FPCR:
2229 STR x2, [sp, #(2 * 16)]
2230 STR x1, [sp, #(1 * 16)]
2231 STR x0, [sp, #(0 * 16)]
2234 p
+= emit_mrs (p
, x2
, NZCV
);
2235 p
+= emit_mrs (p
, x1
, FPSR
);
2236 p
+= emit_mrs (p
, x0
, FPCR
);
2237 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2238 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2239 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2241 /* Push the collecting_t object. It consist of the address of the
2242 tracepoint and an ID for the current thread. We get the latter by
2243 reading the tpidr_el0 system register. It corresponds to the
2244 NT_ARM_TLS register accessible with ptrace.
2251 STP x0, x1, [sp, #-16]!
2255 p
+= emit_mov_addr (p
, x0
, tpoint
);
2256 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2257 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2261 The shared memory for the lock is at lockaddr. It will hold zero
2262 if no-one is holding the lock, otherwise it contains the address of
2263 the collecting_t object on the stack of the thread which acquired it.
2265 At this stage, the stack pointer points to this thread's collecting_t
2268 We use the following registers:
2269 - x0: Address of the lock.
2270 - x1: Pointer to collecting_t object.
2271 - x2: Scratch register.
2277 ; Trigger an event local to this core. So the following WFE
2278 ; instruction is ignored.
2281 ; Wait for an event. The event is triggered by either the SEVL
2282 ; or STLR instructions (store release).
2285 ; Atomically read at lockaddr. This marks the memory location as
2286 ; exclusive. This instruction also has memory constraints which
2287 ; make sure all previous data reads and writes are done before
2291 ; Try again if another thread holds the lock.
2294 ; We can lock it! Write the address of the collecting_t object.
2295 ; This instruction will fail if the memory location is not marked
2296 ; as exclusive anymore. If it succeeds, it will remove the
2297 ; exclusive mark on the memory location. This way, if another
2298 ; thread executes this instruction before us, we will fail and try
2305 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2306 p
+= emit_mov (p
, x1
, register_operand (sp
));
2310 p
+= emit_ldaxr (p
, x2
, x0
);
2311 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2312 p
+= emit_stxr (p
, w2
, x1
, x0
);
2313 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2315 /* Call collector (struct tracepoint *, unsigned char *):
2320 ; Saved registers start after the collecting_t object.
2323 ; We use an intra-procedure-call scratch register.
2324 MOV ip0, #(collector)
2327 ; And call back to C!
2332 p
+= emit_mov_addr (p
, x0
, tpoint
);
2333 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2335 p
+= emit_mov_addr (p
, ip0
, collector
);
2336 p
+= emit_blr (p
, ip0
);
2338 /* Release the lock.
2343 ; This instruction is a normal store with memory ordering
2344 ; constraints. Thanks to this we do not have to put a data
2345 ; barrier instruction to make sure all data read and writes are done
2346 ; before this instruction is executed. Furthermore, this instrucion
2347 ; will trigger an event, letting other threads know they can grab
2352 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2353 p
+= emit_stlr (p
, xzr
, x0
);
2355 /* Free collecting_t object:
2360 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2362 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2363 registers from the stack.
2365 LDR x2, [sp, #(2 * 16)]
2366 LDR x1, [sp, #(1 * 16)]
2367 LDR x0, [sp, #(0 * 16)]
2373 ADD sp, sp #(5 * 16)
2376 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2377 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2378 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2379 p
+= emit_msr (p
, NZCV
, x2
);
2380 p
+= emit_msr (p
, FPSR
, x1
);
2381 p
+= emit_msr (p
, FPCR
, x0
);
2383 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2385 /* Pop general purpose registers:
2389 LDR x30, [sp, #(30 * 16)]
2391 ADD sp, sp, #(31 * 16)
2394 for (i
= 0; i
<= 30; i
+= 1)
2395 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2396 offset_memory_operand (i
* 16));
2397 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2399 /* Pop SIMD&FP registers:
2403 LDP q30, q31, [sp, #(30 * 16)]
2405 ADD sp, sp, #(32 * 16)
2408 for (i
= 0; i
<= 30; i
+= 2)
2409 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2410 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2412 /* Write the code into the inferior memory. */
2413 append_insns (&buildaddr
, p
- buf
, buf
);
2415 /* Now emit the relocated instruction. */
2416 *adjusted_insn_addr
= buildaddr
;
2417 target_read_uint32 (tpaddr
, &insn
);
2419 insn_data
.base
.insn_addr
= tpaddr
;
2420 insn_data
.new_addr
= buildaddr
;
2421 insn_data
.insn_ptr
= buf
;
2423 aarch64_relocate_instruction (insn
, &visitor
,
2424 (struct aarch64_insn_data
*) &insn_data
);
2426 /* We may not have been able to relocate the instruction. */
2427 if (insn_data
.insn_ptr
== buf
)
2430 "E.Could not relocate instruction from %s to %s.",
2431 core_addr_to_string_nz (tpaddr
),
2432 core_addr_to_string_nz (buildaddr
));
2436 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2437 *adjusted_insn_addr_end
= buildaddr
;
2439 /* Go back to the start of the buffer. */
2442 /* Emit a branch back from the jump pad. */
2443 offset
= (tpaddr
+ orig_size
- buildaddr
);
2444 if (!can_encode_int32 (offset
, 28))
2447 "E.Jump back from jump pad too far from tracepoint "
2448 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2453 p
+= emit_b (p
, 0, offset
);
2454 append_insns (&buildaddr
, p
- buf
, buf
);
2456 /* Give the caller a branch instruction into the jump pad. */
2457 offset
= (*jump_entry
- tpaddr
);
2458 if (!can_encode_int32 (offset
, 28))
2461 "E.Jump pad too far from tracepoint "
2462 "(offset 0x%" PRIx32
" cannot be encoded in 28 bits).",
2467 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2468 *jjump_pad_insn_size
= 4;
2470 /* Return the end address of our pad. */
2471 *jump_entry
= buildaddr
;
2476 /* Helper function writing LEN instructions from START into
2477 current_insn_ptr. */
2480 emit_ops_insns (const uint32_t *start
, int len
)
2482 CORE_ADDR buildaddr
= current_insn_ptr
;
2485 debug_printf ("Adding %d instrucions at %s\n",
2486 len
, paddress (buildaddr
));
2488 append_insns (&buildaddr
, len
, start
);
2489 current_insn_ptr
= buildaddr
;
2492 /* Pop a register from the stack. */
2495 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2497 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2500 /* Push a register on the stack. */
2503 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2505 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2508 /* Implementation of emit_ops method "emit_prologue". */
2511 aarch64_emit_prologue (void)
2516 /* This function emit a prologue for the following function prototype:
2518 enum eval_result_type f (unsigned char *regs,
2521 The first argument is a buffer of raw registers. The second
2522 argument is the result of
2523 evaluating the expression, which will be set to whatever is on top of
2524 the stack at the end.
2526 The stack set up by the prologue is as such:
2528 High *------------------------------------------------------*
2531 | x1 (ULONGEST *value) |
2532 | x0 (unsigned char *regs) |
2533 Low *------------------------------------------------------*
2535 As we are implementing a stack machine, each opcode can expand the
2536 stack so we never know how far we are from the data saved by this
2537 prologue. In order to be able refer to value and regs later, we save
2538 the current stack pointer in the frame pointer. This way, it is not
2539 clobbered when calling C functions.
2541 Finally, throughtout every operation, we are using register x0 as the
2542 top of the stack, and x1 as a scratch register. */
2544 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2545 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2546 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2548 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2551 emit_ops_insns (buf
, p
- buf
);
2554 /* Implementation of emit_ops method "emit_epilogue". */
2557 aarch64_emit_epilogue (void)
2562 /* Store the result of the expression (x0) in *value. */
2563 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2564 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2565 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2567 /* Restore the previous state. */
2568 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2569 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2571 /* Return expr_eval_no_error. */
2572 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2573 p
+= emit_ret (p
, lr
);
2575 emit_ops_insns (buf
, p
- buf
);
2578 /* Implementation of emit_ops method "emit_add". */
2581 aarch64_emit_add (void)
2586 p
+= emit_pop (p
, x1
);
2587 p
+= emit_add (p
, x0
, x0
, register_operand (x1
));
2589 emit_ops_insns (buf
, p
- buf
);
2592 /* Implementation of emit_ops method "emit_sub". */
2595 aarch64_emit_sub (void)
2600 p
+= emit_pop (p
, x1
);
2601 p
+= emit_sub (p
, x0
, x0
, register_operand (x1
));
2603 emit_ops_insns (buf
, p
- buf
);
2606 /* Implementation of emit_ops method "emit_mul". */
2609 aarch64_emit_mul (void)
2614 p
+= emit_pop (p
, x1
);
2615 p
+= emit_mul (p
, x0
, x1
, x0
);
2617 emit_ops_insns (buf
, p
- buf
);
2620 /* Implementation of emit_ops method "emit_lsh". */
2623 aarch64_emit_lsh (void)
2628 p
+= emit_pop (p
, x1
);
2629 p
+= emit_lslv (p
, x0
, x1
, x0
);
2631 emit_ops_insns (buf
, p
- buf
);
2634 /* Implementation of emit_ops method "emit_rsh_signed". */
2637 aarch64_emit_rsh_signed (void)
2642 p
+= emit_pop (p
, x1
);
2643 p
+= emit_asrv (p
, x0
, x1
, x0
);
2645 emit_ops_insns (buf
, p
- buf
);
2648 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2651 aarch64_emit_rsh_unsigned (void)
2656 p
+= emit_pop (p
, x1
);
2657 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2659 emit_ops_insns (buf
, p
- buf
);
2662 /* Implementation of emit_ops method "emit_ext". */
2665 aarch64_emit_ext (int arg
)
2670 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2672 emit_ops_insns (buf
, p
- buf
);
2675 /* Implementation of emit_ops method "emit_log_not". */
2678 aarch64_emit_log_not (void)
2683 /* If the top of the stack is 0, replace it with 1. Else replace it with
2686 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2687 p
+= emit_cset (p
, x0
, EQ
);
2689 emit_ops_insns (buf
, p
- buf
);
2692 /* Implementation of emit_ops method "emit_bit_and". */
2695 aarch64_emit_bit_and (void)
2700 p
+= emit_pop (p
, x1
);
2701 p
+= emit_and (p
, x0
, x0
, x1
);
2703 emit_ops_insns (buf
, p
- buf
);
2706 /* Implementation of emit_ops method "emit_bit_or". */
2709 aarch64_emit_bit_or (void)
2714 p
+= emit_pop (p
, x1
);
2715 p
+= emit_orr (p
, x0
, x0
, x1
);
2717 emit_ops_insns (buf
, p
- buf
);
2720 /* Implementation of emit_ops method "emit_bit_xor". */
2723 aarch64_emit_bit_xor (void)
2728 p
+= emit_pop (p
, x1
);
2729 p
+= emit_eor (p
, x0
, x0
, x1
);
2731 emit_ops_insns (buf
, p
- buf
);
2734 /* Implementation of emit_ops method "emit_bit_not". */
2737 aarch64_emit_bit_not (void)
2742 p
+= emit_mvn (p
, x0
, x0
);
2744 emit_ops_insns (buf
, p
- buf
);
2747 /* Implementation of emit_ops method "emit_equal". */
2750 aarch64_emit_equal (void)
2755 p
+= emit_pop (p
, x1
);
2756 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2757 p
+= emit_cset (p
, x0
, EQ
);
2759 emit_ops_insns (buf
, p
- buf
);
2762 /* Implementation of emit_ops method "emit_less_signed". */
2765 aarch64_emit_less_signed (void)
2770 p
+= emit_pop (p
, x1
);
2771 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2772 p
+= emit_cset (p
, x0
, LT
);
2774 emit_ops_insns (buf
, p
- buf
);
2777 /* Implementation of emit_ops method "emit_less_unsigned". */
2780 aarch64_emit_less_unsigned (void)
2785 p
+= emit_pop (p
, x1
);
2786 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2787 p
+= emit_cset (p
, x0
, LO
);
2789 emit_ops_insns (buf
, p
- buf
);
2792 /* Implementation of emit_ops method "emit_ref". */
2795 aarch64_emit_ref (int size
)
2803 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2806 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2809 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2812 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2815 /* Unknown size, bail on compilation. */
2820 emit_ops_insns (buf
, p
- buf
);
2823 /* Implementation of emit_ops method "emit_if_goto". */
2826 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2831 /* The Z flag is set or cleared here. */
2832 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2833 /* This instruction must not change the Z flag. */
2834 p
+= emit_pop (p
, x0
);
2835 /* Branch over the next instruction if x0 == 0. */
2836 p
+= emit_bcond (p
, EQ
, 8);
2838 /* The NOP instruction will be patched with an unconditional branch. */
2840 *offset_p
= (p
- buf
) * 4;
2845 emit_ops_insns (buf
, p
- buf
);
2848 /* Implementation of emit_ops method "emit_goto". */
2851 aarch64_emit_goto (int *offset_p
, int *size_p
)
2856 /* The NOP instruction will be patched with an unconditional branch. */
2863 emit_ops_insns (buf
, p
- buf
);
2866 /* Implementation of emit_ops method "write_goto_address". */
2869 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2873 emit_b (&insn
, 0, to
- from
);
2874 append_insns (&from
, 1, &insn
);
2877 /* Implementation of emit_ops method "emit_const". */
2880 aarch64_emit_const (LONGEST num
)
2885 p
+= emit_mov_addr (p
, x0
, num
);
2887 emit_ops_insns (buf
, p
- buf
);
2890 /* Implementation of emit_ops method "emit_call". */
2893 aarch64_emit_call (CORE_ADDR fn
)
2898 p
+= emit_mov_addr (p
, ip0
, fn
);
2899 p
+= emit_blr (p
, ip0
);
2901 emit_ops_insns (buf
, p
- buf
);
2904 /* Implementation of emit_ops method "emit_reg". */
2907 aarch64_emit_reg (int reg
)
2912 /* Set x0 to unsigned char *regs. */
2913 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2914 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2915 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2917 emit_ops_insns (buf
, p
- buf
);
2919 aarch64_emit_call (get_raw_reg_func_addr ());
2922 /* Implementation of emit_ops method "emit_pop". */
2925 aarch64_emit_pop (void)
2930 p
+= emit_pop (p
, x0
);
2932 emit_ops_insns (buf
, p
- buf
);
2935 /* Implementation of emit_ops method "emit_stack_flush". */
2938 aarch64_emit_stack_flush (void)
2943 p
+= emit_push (p
, x0
);
2945 emit_ops_insns (buf
, p
- buf
);
2948 /* Implementation of emit_ops method "emit_zero_ext". */
2951 aarch64_emit_zero_ext (int arg
)
2956 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2958 emit_ops_insns (buf
, p
- buf
);
2961 /* Implementation of emit_ops method "emit_swap". */
2964 aarch64_emit_swap (void)
2969 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2970 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2971 p
+= emit_mov (p
, x0
, register_operand (x1
));
2973 emit_ops_insns (buf
, p
- buf
);
2976 /* Implementation of emit_ops method "emit_stack_adjust". */
2979 aarch64_emit_stack_adjust (int n
)
2981 /* This is not needed with our design. */
2985 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2987 emit_ops_insns (buf
, p
- buf
);
2990 /* Implementation of emit_ops method "emit_int_call_1". */
2993 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2998 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3000 emit_ops_insns (buf
, p
- buf
);
3002 aarch64_emit_call (fn
);
3005 /* Implementation of emit_ops method "emit_void_call_2". */
3008 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3013 /* Push x0 on the stack. */
3014 aarch64_emit_stack_flush ();
3016 /* Setup arguments for the function call:
3019 x1: top of the stack
3024 p
+= emit_mov (p
, x1
, register_operand (x0
));
3025 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
3027 emit_ops_insns (buf
, p
- buf
);
3029 aarch64_emit_call (fn
);
3032 aarch64_emit_pop ();
3035 /* Implementation of emit_ops method "emit_eq_goto". */
3038 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
3043 p
+= emit_pop (p
, x1
);
3044 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3045 /* Branch over the next instruction if x0 != x1. */
3046 p
+= emit_bcond (p
, NE
, 8);
3047 /* The NOP instruction will be patched with an unconditional branch. */
3049 *offset_p
= (p
- buf
) * 4;
3054 emit_ops_insns (buf
, p
- buf
);
3057 /* Implementation of emit_ops method "emit_ne_goto". */
3060 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
3065 p
+= emit_pop (p
, x1
);
3066 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3067 /* Branch over the next instruction if x0 == x1. */
3068 p
+= emit_bcond (p
, EQ
, 8);
3069 /* The NOP instruction will be patched with an unconditional branch. */
3071 *offset_p
= (p
- buf
) * 4;
3076 emit_ops_insns (buf
, p
- buf
);
3079 /* Implementation of emit_ops method "emit_lt_goto". */
3082 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
3087 p
+= emit_pop (p
, x1
);
3088 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3089 /* Branch over the next instruction if x0 >= x1. */
3090 p
+= emit_bcond (p
, GE
, 8);
3091 /* The NOP instruction will be patched with an unconditional branch. */
3093 *offset_p
= (p
- buf
) * 4;
3098 emit_ops_insns (buf
, p
- buf
);
3101 /* Implementation of emit_ops method "emit_le_goto". */
3104 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
3109 p
+= emit_pop (p
, x1
);
3110 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3111 /* Branch over the next instruction if x0 > x1. */
3112 p
+= emit_bcond (p
, GT
, 8);
3113 /* The NOP instruction will be patched with an unconditional branch. */
3115 *offset_p
= (p
- buf
) * 4;
3120 emit_ops_insns (buf
, p
- buf
);
3123 /* Implementation of emit_ops method "emit_gt_goto". */
3126 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3131 p
+= emit_pop (p
, x1
);
3132 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3133 /* Branch over the next instruction if x0 <= x1. */
3134 p
+= emit_bcond (p
, LE
, 8);
3135 /* The NOP instruction will be patched with an unconditional branch. */
3137 *offset_p
= (p
- buf
) * 4;
3142 emit_ops_insns (buf
, p
- buf
);
3145 /* Implementation of emit_ops method "emit_ge_got". */
3148 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3153 p
+= emit_pop (p
, x1
);
3154 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3155 /* Branch over the next instruction if x0 <= x1. */
3156 p
+= emit_bcond (p
, LT
, 8);
3157 /* The NOP instruction will be patched with an unconditional branch. */
3159 *offset_p
= (p
- buf
) * 4;
3164 emit_ops_insns (buf
, p
- buf
);
3167 static struct emit_ops aarch64_emit_ops_impl
=
3169 aarch64_emit_prologue
,
3170 aarch64_emit_epilogue
,
3175 aarch64_emit_rsh_signed
,
3176 aarch64_emit_rsh_unsigned
,
3178 aarch64_emit_log_not
,
3179 aarch64_emit_bit_and
,
3180 aarch64_emit_bit_or
,
3181 aarch64_emit_bit_xor
,
3182 aarch64_emit_bit_not
,
3184 aarch64_emit_less_signed
,
3185 aarch64_emit_less_unsigned
,
3187 aarch64_emit_if_goto
,
3189 aarch64_write_goto_address
,
3194 aarch64_emit_stack_flush
,
3195 aarch64_emit_zero_ext
,
3197 aarch64_emit_stack_adjust
,
3198 aarch64_emit_int_call_1
,
3199 aarch64_emit_void_call_2
,
3200 aarch64_emit_eq_goto
,
3201 aarch64_emit_ne_goto
,
3202 aarch64_emit_lt_goto
,
3203 aarch64_emit_le_goto
,
3204 aarch64_emit_gt_goto
,
3205 aarch64_emit_ge_got
,
3208 /* Implementation of linux_target_ops method "emit_ops". */
3210 static struct emit_ops
*
3211 aarch64_emit_ops (void)
3213 return &aarch64_emit_ops_impl
;
3216 /* Implementation of linux_target_ops method
3217 "get_min_fast_tracepoint_insn_len". */
3220 aarch64_get_min_fast_tracepoint_insn_len (void)
3225 /* Implementation of linux_target_ops method "supports_range_stepping". */
3228 aarch64_supports_range_stepping (void)
3233 struct linux_target_ops the_low_target
=
3237 aarch64_cannot_fetch_register
,
3238 aarch64_cannot_store_register
,
3239 NULL
, /* fetch_register */
3242 (const unsigned char *) &aarch64_breakpoint
,
3243 aarch64_breakpoint_len
,
3244 NULL
, /* breakpoint_reinsert_addr */
3245 0, /* decr_pc_after_break */
3246 aarch64_breakpoint_at
,
3247 aarch64_supports_z_point_type
,
3248 aarch64_insert_point
,
3249 aarch64_remove_point
,
3250 aarch64_stopped_by_watchpoint
,
3251 aarch64_stopped_data_address
,
3252 NULL
, /* collect_ptrace_register */
3253 NULL
, /* supply_ptrace_register */
3254 aarch64_linux_siginfo_fixup
,
3255 aarch64_linux_new_process
,
3256 aarch64_linux_new_thread
,
3257 aarch64_linux_new_fork
,
3258 aarch64_linux_prepare_to_resume
,
3259 NULL
, /* process_qsupported */
3260 aarch64_supports_tracepoints
,
3261 aarch64_get_thread_area
,
3262 aarch64_install_fast_tracepoint_jump_pad
,
3264 aarch64_get_min_fast_tracepoint_insn_len
,
3265 aarch64_supports_range_stepping
,
3269 initialize_low_arch (void)
3271 init_registers_aarch64 ();
3273 initialize_low_arch_aarch32 ();
3275 initialize_regsets_info (&aarch64_regsets_info
);