1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988, 1989 Free Software Foundation, Inc.
4 This file is part of GDB.
6 GDB is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 1, or (at your option)
11 GDB is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GDB; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 * The main tables describing the instructions is essentially a copy
27 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
28 * Programmers Manual. Usually, there is a capital letter, followed
29 * by a small letter. The capital letter tell the addressing mode,
30 * and the small letter tells about the operand size. Refer to
31 * the Intel manual for details.
37 #define Eb OP_E, b_mode
38 #define indirEb OP_indirE, b_mode
39 #define Gb OP_G, b_mode
40 #define Ev OP_E, v_mode
41 #define indirEv OP_indirE, v_mode
42 #define Ew OP_E, w_mode
43 #define Ma OP_E, v_mode
45 #define Mp OP_E, 0 /* ? */
46 #define Gv OP_G, v_mode
47 #define Gw OP_G, w_mode
48 #define Rw OP_rm, w_mode
49 #define Rd OP_rm, d_mode
50 #define Ib OP_I, b_mode
51 #define sIb OP_sI, b_mode /* sign extened byte */
52 #define Iv OP_I, v_mode
53 #define Iw OP_I, w_mode
54 #define Jb OP_J, b_mode
55 #define Jv OP_J, v_mode
57 #define Cd OP_C, d_mode
58 #define Dd OP_D, d_mode
59 #define Td OP_T, d_mode
61 #define eAX OP_REG, eAX_reg
62 #define eBX OP_REG, eBX_reg
63 #define eCX OP_REG, eCX_reg
64 #define eDX OP_REG, eDX_reg
65 #define eSP OP_REG, eSP_reg
66 #define eBP OP_REG, eBP_reg
67 #define eSI OP_REG, eSI_reg
68 #define eDI OP_REG, eDI_reg
69 #define AL OP_REG, al_reg
70 #define CL OP_REG, cl_reg
71 #define DL OP_REG, dl_reg
72 #define BL OP_REG, bl_reg
73 #define AH OP_REG, ah_reg
74 #define CH OP_REG, ch_reg
75 #define DH OP_REG, dh_reg
76 #define BH OP_REG, bh_reg
77 #define AX OP_REG, ax_reg
78 #define DX OP_REG, dx_reg
79 #define indirDX OP_REG, indir_dx_reg
81 #define Sw OP_SEG, w_mode
82 #define Ap OP_DIR, lptr
83 #define Av OP_DIR, v_mode
84 #define Ob OP_OFF, b_mode
85 #define Ov OP_OFF, v_mode
86 #define Xb OP_DSSI, b_mode
87 #define Xv OP_DSSI, v_mode
88 #define Yb OP_ESDI, b_mode
89 #define Yv OP_ESDI, v_mode
91 #define es OP_REG, es_reg
92 #define ss OP_REG, ss_reg
93 #define cs OP_REG, cs_reg
94 #define ds OP_REG, ds_reg
95 #define fs OP_REG, fs_reg
96 #define gs OP_REG, gs_reg
98 int OP_E(), OP_indirE(), OP_G(), OP_I(), OP_sI(), OP_REG();
100 int OP_DIR(), OP_OFF(), OP_DSSI(), OP_ESDI(), OP_ONE(), OP_C();
101 int OP_D(), OP_T(), OP_rm();
144 #define indir_dx_reg 150
146 #define GRP1b NULL, NULL, 0
147 #define GRP1S NULL, NULL, 1
148 #define GRP1Ss NULL, NULL, 2
149 #define GRP2b NULL, NULL, 3
150 #define GRP2S NULL, NULL, 4
151 #define GRP2b_one NULL, NULL, 5
152 #define GRP2S_one NULL, NULL, 6
153 #define GRP2b_cl NULL, NULL, 7
154 #define GRP2S_cl NULL, NULL, 8
155 #define GRP3b NULL, NULL, 9
156 #define GRP3S NULL, NULL, 10
157 #define GRP4 NULL, NULL, 11
158 #define GRP5 NULL, NULL, 12
159 #define GRP6 NULL, NULL, 13
160 #define GRP7 NULL, NULL, 14
161 #define GRP8 NULL, NULL, 15
164 #define FLOAT NULL, NULL, FLOATCODE
176 struct dis386 dis386
[] = {
194 { "(bad)" }, /* 0x0f extended opcode escape */
220 { "(bad)" }, /* SEG ES prefix */
229 { "(bad)" }, /* SEG CS prefix */
238 { "(bad)" }, /* SEG SS prefix */
247 { "(bad)" }, /* SEG DS prefix */
288 { "boundS", Gv
, Ma
},
290 { "(bad)" }, /* seg fs */
291 { "(bad)" }, /* seg gs */
292 { "(bad)" }, /* op size prefix */
293 { "(bad)" }, /* adr size prefix */
295 { "pushS", Iv
}, /* 386 book wrong */
296 { "imulS", Gv
, Ev
, Iv
},
297 { "pushl", sIb
}, /* push of byte really pushes 4 bytes */
298 { "imulS", Gv
, Ev
, Ib
},
299 { "insb", Yb
, indirDX
},
300 { "insS", Yv
, indirDX
},
301 { "outsb", indirDX
, Xb
},
302 { "outsS", indirDX
, Xv
},
341 { "xchgS", eCX
, eAX
},
342 { "xchgS", eDX
, eAX
},
343 { "xchgS", eBX
, eAX
},
344 { "xchgS", eSP
, eAX
},
345 { "xchgS", eBP
, eAX
},
346 { "xchgS", eSI
, eAX
},
347 { "xchgS", eDI
, eAX
},
352 { "(bad)" }, /* fwait */
368 { "testS", eAX
, Iv
},
370 { "stosS", Yv
, eAX
},
372 { "lodsS", eAX
, Xv
},
374 { "scasS", eAX
, Xv
},
443 { "inb", AL
, indirDX
},
444 { "inS", eAX
, indirDX
},
445 { "outb", indirDX
, AL
},
446 { "outS", indirDX
, eAX
},
448 { "(bad)" }, /* lock prefix */
450 { "(bad)" }, /* repne */
451 { "(bad)" }, /* repz */
467 struct dis386 dis386_twobyte
[] = {
478 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
479 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
481 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
482 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
484 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
485 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
487 /* these are all backward in appendix A of the intel book */
497 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
498 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
500 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
501 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
503 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
504 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
506 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
507 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
509 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
510 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
512 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
513 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
515 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
516 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
518 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
519 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
521 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
522 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
524 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
525 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
527 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
528 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
570 { "shldS", Ev
, Gv
, Ib
},
571 { "shldS", Ev
, Gv
, CL
},
579 { "shrdS", Ev
, Gv
, Ib
},
580 { "shrdS", Ev
, Gv
, CL
},
586 { "lssS", Gv
, Mp
}, /* 386 lists only Mp */
588 { "lfsS", Gv
, Mp
}, /* 386 lists only Mp */
589 { "lgsS", Gv
, Mp
}, /* 386 lists only Mp */
590 { "movzbS", Gv
, Eb
},
591 { "movzwS", Gv
, Ew
},
599 { "movsbS", Gv
, Eb
},
600 { "movswS", Gv
, Ew
},
602 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
603 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
605 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
606 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
608 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
609 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
611 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
612 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
614 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
615 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
617 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
618 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
620 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
621 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
623 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
624 { "(bad)" }, { "(bad)" }, { "(bad)" }, { "(bad)" },
627 static char obuf
[100];
629 static char scratchbuf
[100];
630 static unsigned char *start_codep
;
631 static unsigned char *codep
;
635 static void oappend ();
637 static char *names32
[]={
638 "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
640 static char *names16
[] = {
641 "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
643 static char *names8
[] = {
644 "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
646 static char *names_seg
[] = {
647 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
650 struct dis386 grps
[][8] = {
768 { "imulS", eAX
, Ev
},
770 { "idivS", eAX
, Ev
},
788 { "lcall", indirEv
},
829 #define PREFIX_REPZ 1
830 #define PREFIX_REPNZ 2
831 #define PREFIX_LOCK 4
833 #define PREFIX_SS 0x10
834 #define PREFIX_DS 0x20
835 #define PREFIX_ES 0x40
836 #define PREFIX_FS 0x80
837 #define PREFIX_GS 0x100
838 #define PREFIX_DATA 0x200
839 #define PREFIX_ADR 0x400
840 #define PREFIX_FWAIT 0x800
852 prefixes
|= PREFIX_REPZ
;
855 prefixes
|= PREFIX_REPNZ
;
858 prefixes
|= PREFIX_LOCK
;
861 prefixes
|= PREFIX_CS
;
864 prefixes
|= PREFIX_SS
;
867 prefixes
|= PREFIX_DS
;
870 prefixes
|= PREFIX_ES
;
873 prefixes
|= PREFIX_FS
;
876 prefixes
|= PREFIX_GS
;
879 prefixes
|= PREFIX_DATA
;
882 prefixes
|= PREFIX_ADR
;
885 prefixes
|= PREFIX_FWAIT
;
897 static char op1out
[100], op2out
[100], op3out
[100];
898 static int op_address
[3], op_ad
, op_index
[3];
900 extern void fputs_filtered ();
903 * disassemble the first instruction in 'inbuf'. You have to make
904 * sure all of the bytes of the instruction are filled in.
905 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
906 * (see topic "Redundant prefixes" in the "Differences from 8086"
907 * section of the "Virtual 8086 Mode" chapter.)
908 * 'pc' should be the address of this instruction, it will
909 * be used to print the target address if this is a relative jump or call
910 * 'outbuf' gets filled in with the disassembled instruction. it should
911 * be long enough to hold the longest disassembled instruction.
912 * 100 bytes is certainly enough, unless symbol printing is added later
913 * The function returns the length of this instruction in bytes.
915 i386dis (pc
, inbuf
, stream
)
917 unsigned char *inbuf
;
923 int enter_instruction
;
924 char *first
, *second
, *third
;
932 op_index
[0] = op_index
[1] = op_index
[2] = -1;
941 enter_instruction
= 1;
943 enter_instruction
= 0;
947 if (prefixes
& PREFIX_REPZ
)
949 if (prefixes
& PREFIX_REPNZ
)
951 if (prefixes
& PREFIX_LOCK
)
954 if ((prefixes
& PREFIX_FWAIT
)
955 && ((*codep
< 0xd8) || (*codep
> 0xdf)))
957 /* fwait not followed by floating point instruction */
958 fputs_filtered ("fwait", stream
);
962 /* these would be initialized to 0 if disassembling for 8086 or 286 */
966 if (prefixes
& PREFIX_DATA
)
969 if (prefixes
& PREFIX_ADR
)
976 dp
= &dis386_twobyte
[*++codep
];
978 dp
= &dis386
[*codep
];
980 mod
= (*codep
>> 6) & 3;
981 reg
= (*codep
>> 3) & 7;
984 if (dp
->name
== NULL
&& dp
->bytemode1
== FLOATCODE
)
990 if (dp
->name
== NULL
)
991 dp
= &grps
[dp
->bytemode1
][reg
];
998 (*dp
->op1
)(dp
->bytemode1
);
1003 (*dp
->op2
)(dp
->bytemode2
);
1008 (*dp
->op3
)(dp
->bytemode3
);
1011 obufp
= obuf
+ strlen (obuf
);
1012 for (i
= strlen (obuf
); i
< 6; i
++)
1015 fputs_filtered (obuf
, stream
);
1017 /* enter instruction is printed with operands in the
1018 * same order as the intel book; everything else
1019 * is printed in reverse order
1021 if (enter_instruction
)
1026 op_ad
= op_index
[0];
1027 op_index
[0] = op_index
[2];
1028 op_index
[2] = op_ad
;
1039 if (op_index
[0] != -1)
1040 print_address (op_address
[op_index
[0]], stream
);
1042 fputs_filtered (first
, stream
);
1048 fputs_filtered (",", stream
);
1049 if (op_index
[1] != -1)
1050 print_address (op_address
[op_index
[1]], stream
);
1052 fputs_filtered (second
, stream
);
1058 fputs_filtered (",", stream
);
1059 if (op_index
[2] != -1)
1060 print_address (op_address
[op_index
[2]], stream
);
1062 fputs_filtered (third
, stream
);
1064 return (codep
- inbuf
);
1067 char *float_mem
[] = {
1143 #define STi OP_STi, 0
1144 int OP_ST(), OP_STi();
1146 #define FGRPd9_2 NULL, NULL, 0
1147 #define FGRPd9_4 NULL, NULL, 1
1148 #define FGRPd9_5 NULL, NULL, 2
1149 #define FGRPd9_6 NULL, NULL, 3
1150 #define FGRPd9_7 NULL, NULL, 4
1151 #define FGRPda_5 NULL, NULL, 5
1152 #define FGRPdb_4 NULL, NULL, 6
1153 #define FGRPde_3 NULL, NULL, 7
1154 #define FGRPdf_4 NULL, NULL, 8
1156 struct dis386 float_reg
[][8] = {
1159 { "fadd", ST
, STi
},
1160 { "fmul", ST
, STi
},
1163 { "fsub", ST
, STi
},
1164 { "fsubr", ST
, STi
},
1165 { "fdiv", ST
, STi
},
1166 { "fdivr", ST
, STi
},
1203 { "fadd", STi
, ST
},
1204 { "fmul", STi
, ST
},
1207 { "fsub", STi
, ST
},
1208 { "fsubr", STi
, ST
},
1209 { "fdiv", STi
, ST
},
1210 { "fdivr", STi
, ST
},
1225 { "faddp", STi
, ST
},
1226 { "fmulp", STi
, ST
},
1229 { "fsubp", STi
, ST
},
1230 { "fsubrp", STi
, ST
},
1231 { "fdivp", STi
, ST
},
1232 { "fdivrp", STi
, ST
},
1248 char *fgrps
[][8] = {
1251 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1256 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
1261 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
1266 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
1271 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
1276 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1281 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
1282 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
1287 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1292 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
1300 unsigned char floatop
;
1302 floatop
= codep
[-1];
1306 putop (float_mem
[(floatop
- 0xd8) * 8 + reg
]);
1313 dp
= &float_reg
[floatop
- 0xd8][reg
];
1314 if (dp
->name
== NULL
)
1316 putop (fgrps
[dp
->bytemode1
][rm
]);
1317 /* instruction fnstsw is only one with strange arg */
1318 if (floatop
== 0xdf && *codep
== 0xe0)
1319 strcpy (op1out
, "%eax");
1326 (*dp
->op1
)(dp
->bytemode1
);
1329 (*dp
->op2
)(dp
->bytemode2
);
1342 sprintf (scratchbuf
, "%%st(%d)", rm
);
1343 oappend (scratchbuf
);
1347 /* capital letters in template are macros */
1353 for (p
= template; *p
; p
++)
1360 case 'C': /* For jcxz/jecxz */
1365 if ((prefixes
& PREFIX_FWAIT
) == 0)
1369 /* operand size flag */
1385 obufp
+= strlen (s
);
1391 if (prefixes
& PREFIX_CS
)
1393 if (prefixes
& PREFIX_DS
)
1395 if (prefixes
& PREFIX_SS
)
1397 if (prefixes
& PREFIX_ES
)
1399 if (prefixes
& PREFIX_FS
)
1401 if (prefixes
& PREFIX_GS
)
1405 OP_indirE (bytemode
)
1421 /* skip mod/rm byte */
1433 oappend (names8
[rm
]);
1436 oappend (names16
[rm
]);
1440 oappend (names32
[rm
]);
1442 oappend (names16
[rm
]);
1445 oappend ("<bad dis table>");
1456 scale
= (*codep
>> 6) & 3;
1457 index
= (*codep
>> 3) & 7;
1468 /* implies havesib and havebase */
1484 disp
= *(char *)codep
++;
1501 if (mod
!= 0 || rm
== 5 || (havesib
&& base
== 5))
1503 sprintf (scratchbuf
, "%d", disp
);
1504 oappend (scratchbuf
);
1507 if (havebase
|| havesib
)
1511 oappend (names32
[base
]);
1516 sprintf (scratchbuf
, ",%s", names32
[index
]);
1517 oappend (scratchbuf
);
1519 sprintf (scratchbuf
, ",%d", 1 << scale
);
1520 oappend (scratchbuf
);
1531 oappend (names8
[reg
]);
1534 oappend (names16
[reg
]);
1537 oappend (names32
[reg
]);
1541 oappend (names32
[reg
]);
1543 oappend (names16
[reg
]);
1546 oappend ("<internal disassembler error>");
1555 x
= *codep
++ & 0xff;
1556 x
|= (*codep
++ & 0xff) << 8;
1557 x
|= (*codep
++ & 0xff) << 16;
1558 x
|= (*codep
++ & 0xff) << 24;
1566 x
= *codep
++ & 0xff;
1567 x
|= (*codep
++ & 0xff) << 8;
1574 op_index
[op_ad
] = op_ad
;
1575 op_address
[op_ad
] = op
;
1584 case indir_dx_reg
: s
= "(%dx)"; break;
1585 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
1586 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
1587 s
= names16
[code
- ax_reg
];
1589 case es_reg
: case ss_reg
: case cs_reg
:
1590 case ds_reg
: case fs_reg
: case gs_reg
:
1591 s
= names_seg
[code
- es_reg
];
1593 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
1594 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
1595 s
= names8
[code
- al_reg
];
1597 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
1598 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
1600 s
= names32
[code
- eAX_reg
];
1602 s
= names16
[code
- eAX_reg
];
1605 s
= "<internal disassembler error>";
1618 op
= *codep
++ & 0xff;
1630 oappend ("<internal disassembler error>");
1633 sprintf (scratchbuf
, "$0x%x", op
);
1634 oappend (scratchbuf
);
1644 op
= *(char *)codep
++;
1650 op
= (short)get16();
1653 op
= (short)get16 ();
1656 oappend ("<internal disassembler error>");
1659 sprintf (scratchbuf
, "$0x%x", op
);
1660 oappend (scratchbuf
);
1671 disp
= *(char *)codep
++;
1678 disp
= (short)get16 ();
1679 /* for some reason, a data16 prefix on a jump instruction
1680 means that the pc is masked to 16 bits after the
1681 displacement is added! */
1686 oappend ("<internal disassembler error>");
1689 disp
= (start_pc
+ codep
- start_codep
+ disp
) & mask
;
1691 sprintf (scratchbuf
, "0x%x", disp
);
1692 oappend (scratchbuf
);
1698 static char *sreg
[] = {
1699 "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
1702 oappend (sreg
[reg
]);
1722 sprintf (scratchbuf
, "0x%x,0x%x", seg
, offset
);
1723 oappend (scratchbuf
);
1729 offset
= (short)get16 ();
1731 offset
= start_pc
+ codep
- start_codep
+ offset
;
1733 sprintf (scratchbuf
, "0x%x", offset
);
1734 oappend (scratchbuf
);
1737 oappend ("<internal disassembler error>");
1752 sprintf (scratchbuf
, "0x%x", off
);
1753 oappend (scratchbuf
);
1760 oappend (aflag
? "%edi" : "%di");
1768 oappend (aflag
? "%esi" : "%si");
1781 codep
++; /* skip mod/rm */
1782 sprintf (scratchbuf
, "%%cr%d", reg
);
1783 oappend (scratchbuf
);
1789 codep
++; /* skip mod/rm */
1790 sprintf (scratchbuf
, "%%db%d", reg
);
1791 oappend (scratchbuf
);
1797 codep
++; /* skip mod/rm */
1798 sprintf (scratchbuf
, "%%tr%d", reg
);
1799 oappend (scratchbuf
);
1807 oappend (names32
[rm
]);
1810 oappend (names16
[rm
]);
1820 #include "inferior.h"
1821 #include "gdbcore.h"
1824 print_insn (memaddr
, stream
)
1828 unsigned char buffer
[MAXLEN
];
1830 read_memory (memaddr
, buffer
, MAXLEN
);
1832 return (i386dis ((int)memaddr
, buffer
, stream
));