1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
54 #include "record-full.h"
55 #include "target-descriptions.h"
56 #include "arch/i386.h"
61 #include "stap-probe.h"
62 #include "user-regs.h"
63 #include "cli/cli-utils.h"
64 #include "expression.h"
65 #include "parser-defs.h"
68 #include <unordered_set>
73 static const char * const i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char * const i386_zmm_names
[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char * const i386_zmmh_names
[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char * const i386_k_names
[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char * const i386_ymm_names
[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char * const i386_ymmh_names
[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char * const i386_mpx_names
[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 static const char * const i386_pkeys_names
[] =
128 /* Register names for MPX pseudo-registers. */
130 static const char * const i386_bnd_names
[] =
132 "bnd0", "bnd1", "bnd2", "bnd3"
135 /* Register names for MMX pseudo-registers. */
137 static const char * const i386_mmx_names
[] =
139 "mm0", "mm1", "mm2", "mm3",
140 "mm4", "mm5", "mm6", "mm7"
143 /* Register names for byte pseudo-registers. */
145 static const char * const i386_byte_names
[] =
147 "al", "cl", "dl", "bl",
148 "ah", "ch", "dh", "bh"
151 /* Register names for word pseudo-registers. */
153 static const char * const i386_word_names
[] =
155 "ax", "cx", "dx", "bx",
159 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
160 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
161 we have 16 upper ZMM regs that have to be handled differently. */
163 const int num_lower_zmm_regs
= 16;
168 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
170 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
171 int mm0_regnum
= tdep
->mm0_regnum
;
176 regnum
-= mm0_regnum
;
177 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
183 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
185 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
187 regnum
-= tdep
->al_regnum
;
188 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
194 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
196 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
198 regnum
-= tdep
->ax_regnum
;
199 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
202 /* Dword register? */
205 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
207 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
208 int eax_regnum
= tdep
->eax_regnum
;
213 regnum
-= eax_regnum
;
214 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
217 /* AVX512 register? */
220 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
223 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
225 if (zmm0h_regnum
< 0)
228 regnum
-= zmm0h_regnum
;
229 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
233 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
236 int zmm0_regnum
= tdep
->zmm0_regnum
;
241 regnum
-= zmm0_regnum
;
242 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
246 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
248 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
249 int k0_regnum
= tdep
->k0_regnum
;
255 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
259 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
261 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
262 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
264 if (ymm0h_regnum
< 0)
267 regnum
-= ymm0h_regnum
;
268 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
274 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
276 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
277 int ymm0_regnum
= tdep
->ymm0_regnum
;
282 regnum
-= ymm0_regnum
;
283 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
287 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
289 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
290 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
292 if (ymm16h_regnum
< 0)
295 regnum
-= ymm16h_regnum
;
296 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
300 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
302 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
303 int ymm16_regnum
= tdep
->ymm16_regnum
;
305 if (ymm16_regnum
< 0)
308 regnum
-= ymm16_regnum
;
309 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
315 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
317 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
318 int bnd0_regnum
= tdep
->bnd0_regnum
;
323 regnum
-= bnd0_regnum
;
324 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
330 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
332 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
333 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
335 if (num_xmm_regs
== 0)
338 regnum
-= I387_XMM0_REGNUM (tdep
);
339 return regnum
>= 0 && regnum
< num_xmm_regs
;
342 /* XMM_512 register? */
345 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
347 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
348 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
350 if (num_xmm_avx512_regs
== 0)
353 regnum
-= I387_XMM16_REGNUM (tdep
);
354 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
358 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
360 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
362 if (I387_NUM_XMM_REGS (tdep
) == 0)
365 return (regnum
== I387_MXCSR_REGNUM (tdep
));
371 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
373 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
375 if (I387_ST0_REGNUM (tdep
) < 0)
378 return (I387_ST0_REGNUM (tdep
) <= regnum
379 && regnum
< I387_FCTRL_REGNUM (tdep
));
383 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
385 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
387 if (I387_ST0_REGNUM (tdep
) < 0)
390 return (I387_FCTRL_REGNUM (tdep
) <= regnum
391 && regnum
< I387_XMM0_REGNUM (tdep
));
394 /* BNDr (raw) register? */
397 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
399 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
401 if (I387_BND0R_REGNUM (tdep
) < 0)
404 regnum
-= tdep
->bnd0r_regnum
;
405 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
408 /* BND control register? */
411 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
413 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
415 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
418 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
419 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
425 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
427 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
428 int pkru_regnum
= tdep
->pkru_regnum
;
433 regnum
-= pkru_regnum
;
434 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
437 /* Return the name of register REGNUM, or the empty string if it is
438 an anonymous register. */
441 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
443 /* Hide the upper YMM registers. */
444 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
447 /* Hide the upper YMM16-31 registers. */
448 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
451 /* Hide the upper ZMM registers. */
452 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
455 return tdesc_register_name (gdbarch
, regnum
);
458 /* Return the name of register REGNUM. */
461 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
463 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
464 if (i386_bnd_regnum_p (gdbarch
, regnum
))
465 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
466 if (i386_mmx_regnum_p (gdbarch
, regnum
))
467 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
468 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
469 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
470 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
471 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
472 else if (i386_byte_regnum_p (gdbarch
, regnum
))
473 return i386_byte_names
[regnum
- tdep
->al_regnum
];
474 else if (i386_word_regnum_p (gdbarch
, regnum
))
475 return i386_word_names
[regnum
- tdep
->ax_regnum
];
477 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
480 /* Convert a dbx register number REG to the appropriate register
481 number used by GDB. */
484 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
486 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
488 /* This implements what GCC calls the "default" register map
489 (dbx_register_map[]). */
491 if (reg
>= 0 && reg
<= 7)
493 /* General-purpose registers. The debug info calls %ebp
494 register 4, and %esp register 5. */
501 else if (reg
>= 12 && reg
<= 19)
503 /* Floating-point registers. */
504 return reg
- 12 + I387_ST0_REGNUM (tdep
);
506 else if (reg
>= 21 && reg
<= 28)
509 int ymm0_regnum
= tdep
->ymm0_regnum
;
512 && i386_xmm_regnum_p (gdbarch
, reg
))
513 return reg
- 21 + ymm0_regnum
;
515 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
517 else if (reg
>= 29 && reg
<= 36)
520 return reg
- 29 + I387_MM0_REGNUM (tdep
);
523 /* This will hopefully provoke a warning. */
524 return gdbarch_num_cooked_regs (gdbarch
);
527 /* Convert SVR4 DWARF register number REG to the appropriate register number
531 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
533 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
535 /* This implements the GCC register map that tries to be compatible
536 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
538 /* The SVR4 register numbering includes %eip and %eflags, and
539 numbers the floating point registers differently. */
540 if (reg
>= 0 && reg
<= 9)
542 /* General-purpose registers. */
545 else if (reg
>= 11 && reg
<= 18)
547 /* Floating-point registers. */
548 return reg
- 11 + I387_ST0_REGNUM (tdep
);
550 else if (reg
>= 21 && reg
<= 36)
552 /* The SSE and MMX registers have the same numbers as with dbx. */
553 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
558 case 37: return I387_FCTRL_REGNUM (tdep
);
559 case 38: return I387_FSTAT_REGNUM (tdep
);
560 case 39: return I387_MXCSR_REGNUM (tdep
);
561 case 40: return I386_ES_REGNUM
;
562 case 41: return I386_CS_REGNUM
;
563 case 42: return I386_SS_REGNUM
;
564 case 43: return I386_DS_REGNUM
;
565 case 44: return I386_FS_REGNUM
;
566 case 45: return I386_GS_REGNUM
;
572 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
573 num_regs + num_pseudo_regs for other debug formats. */
576 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
578 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
581 return gdbarch_num_cooked_regs (gdbarch
);
587 /* This is the variable that is set with "set disassembly-flavor", and
588 its legitimate values. */
589 static const char att_flavor
[] = "att";
590 static const char intel_flavor
[] = "intel";
591 static const char *const valid_flavors
[] =
597 static const char *disassembly_flavor
= att_flavor
;
600 /* Use the program counter to determine the contents and size of a
601 breakpoint instruction. Return a pointer to a string of bytes that
602 encode a breakpoint instruction, store the length of the string in
603 *LEN and optionally adjust *PC to point to the correct memory
604 location for inserting the breakpoint.
606 On the i386 we have a single breakpoint that fits in a single byte
607 and can be inserted anywhere.
609 This function is 64-bit safe. */
611 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
613 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
616 /* Displaced instruction handling. */
618 /* Skip the legacy instruction prefixes in INSN.
619 Not all prefixes are valid for any particular insn
620 but we needn't care, the insn will fault if it's invalid.
621 The result is a pointer to the first opcode byte,
622 or NULL if we run off the end of the buffer. */
625 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
627 gdb_byte
*end
= insn
+ max_len
;
633 case DATA_PREFIX_OPCODE
:
634 case ADDR_PREFIX_OPCODE
:
635 case CS_PREFIX_OPCODE
:
636 case DS_PREFIX_OPCODE
:
637 case ES_PREFIX_OPCODE
:
638 case FS_PREFIX_OPCODE
:
639 case GS_PREFIX_OPCODE
:
640 case SS_PREFIX_OPCODE
:
641 case LOCK_PREFIX_OPCODE
:
642 case REPE_PREFIX_OPCODE
:
643 case REPNE_PREFIX_OPCODE
:
655 i386_absolute_jmp_p (const gdb_byte
*insn
)
657 /* jmp far (absolute address in operand). */
663 /* jump near, absolute indirect (/4). */
664 if ((insn
[1] & 0x38) == 0x20)
667 /* jump far, absolute indirect (/5). */
668 if ((insn
[1] & 0x38) == 0x28)
675 /* Return non-zero if INSN is a jump, zero otherwise. */
678 i386_jmp_p (const gdb_byte
*insn
)
680 /* jump short, relative. */
684 /* jump near, relative. */
688 return i386_absolute_jmp_p (insn
);
692 i386_absolute_call_p (const gdb_byte
*insn
)
694 /* call far, absolute. */
700 /* Call near, absolute indirect (/2). */
701 if ((insn
[1] & 0x38) == 0x10)
704 /* Call far, absolute indirect (/3). */
705 if ((insn
[1] & 0x38) == 0x18)
713 i386_ret_p (const gdb_byte
*insn
)
717 case 0xc2: /* ret near, pop N bytes. */
718 case 0xc3: /* ret near */
719 case 0xca: /* ret far, pop N bytes. */
720 case 0xcb: /* ret far */
721 case 0xcf: /* iret */
730 i386_call_p (const gdb_byte
*insn
)
732 if (i386_absolute_call_p (insn
))
735 /* call near, relative. */
742 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
743 length in bytes. Otherwise, return zero. */
746 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
748 /* Is it 'int $0x80'? */
749 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
750 /* Or is it 'sysenter'? */
751 || (insn
[0] == 0x0f && insn
[1] == 0x34)
752 /* Or is it 'syscall'? */
753 || (insn
[0] == 0x0f && insn
[1] == 0x05))
762 /* The gdbarch insn_is_call method. */
765 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
767 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
769 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
770 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
772 return i386_call_p (insn
);
775 /* The gdbarch insn_is_ret method. */
778 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
780 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
782 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
783 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
785 return i386_ret_p (insn
);
788 /* The gdbarch insn_is_jump method. */
791 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
793 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
795 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
796 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
798 return i386_jmp_p (insn
);
801 /* Some kernels may run one past a syscall insn, so we have to cope. */
803 displaced_step_copy_insn_closure_up
804 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
805 CORE_ADDR from
, CORE_ADDR to
,
806 struct regcache
*regs
)
808 size_t len
= gdbarch_max_insn_length (gdbarch
);
809 std::unique_ptr
<i386_displaced_step_copy_insn_closure
> closure
810 (new i386_displaced_step_copy_insn_closure (len
));
811 gdb_byte
*buf
= closure
->buf
.data ();
813 read_memory (from
, buf
, len
);
815 /* GDB may get control back after the insn after the syscall.
816 Presumably this is a kernel bug.
817 If this is a syscall, make sure there's a nop afterwards. */
822 insn
= i386_skip_prefixes (buf
, len
);
823 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
824 insn
[syscall_length
] = NOP_OPCODE
;
827 write_memory (to
, buf
, len
);
829 displaced_debug_printf ("%s->%s: %s",
830 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
831 displaced_step_dump_bytes (buf
, len
).c_str ());
833 /* This is a work around for a problem with g++ 4.8. */
834 return displaced_step_copy_insn_closure_up (closure
.release ());
837 /* Fix up the state of registers and memory after having single-stepped
838 a displaced instruction. */
841 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
842 struct displaced_step_copy_insn_closure
*closure_
,
843 CORE_ADDR from
, CORE_ADDR to
,
844 struct regcache
*regs
)
846 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
848 /* The offset we applied to the instruction's address.
849 This could well be negative (when viewed as a signed 32-bit
850 value), but ULONGEST won't reflect that, so take care when
852 ULONGEST insn_offset
= to
- from
;
854 i386_displaced_step_copy_insn_closure
*closure
855 = (i386_displaced_step_copy_insn_closure
*) closure_
;
856 gdb_byte
*insn
= closure
->buf
.data ();
857 /* The start of the insn, needed in case we see some prefixes. */
858 gdb_byte
*insn_start
= insn
;
860 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
861 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
864 /* The list of issues to contend with here is taken from
865 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
866 Yay for Free Software! */
868 /* Relocate the %eip, if necessary. */
870 /* The instruction recognizers we use assume any leading prefixes
871 have been skipped. */
873 /* This is the size of the buffer in closure. */
874 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
875 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
876 /* If there are too many prefixes, just ignore the insn.
877 It will fault when run. */
882 /* Except in the case of absolute or indirect jump or call
883 instructions, or a return instruction, the new eip is relative to
884 the displaced instruction; make it relative. Well, signal
885 handler returns don't need relocation either, but we use the
886 value of %eip to recognize those; see below. */
887 if (! i386_absolute_jmp_p (insn
)
888 && ! i386_absolute_call_p (insn
)
889 && ! i386_ret_p (insn
))
894 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
896 /* A signal trampoline system call changes the %eip, resuming
897 execution of the main program after the signal handler has
898 returned. That makes them like 'return' instructions; we
899 shouldn't relocate %eip.
901 But most system calls don't, and we do need to relocate %eip.
903 Our heuristic for distinguishing these cases: if stepping
904 over the system call instruction left control directly after
905 the instruction, the we relocate --- control almost certainly
906 doesn't belong in the displaced copy. Otherwise, we assume
907 the instruction has put control where it belongs, and leave
908 it unrelocated. Goodness help us if there are PC-relative
910 if (i386_syscall_p (insn
, &insn_len
)
911 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
912 /* GDB can get control back after the insn after the syscall.
913 Presumably this is a kernel bug.
914 i386_displaced_step_copy_insn ensures its a nop,
915 we add one to the length for it. */
916 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
917 displaced_debug_printf ("syscall changed %%eip; not relocating");
920 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
922 /* If we just stepped over a breakpoint insn, we don't backup
923 the pc on purpose; this is to match behaviour without
926 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
928 displaced_debug_printf ("relocated %%eip from %s to %s",
929 paddress (gdbarch
, orig_eip
),
930 paddress (gdbarch
, eip
));
934 /* If the instruction was PUSHFL, then the TF bit will be set in the
935 pushed value, and should be cleared. We'll leave this for later,
936 since GDB already messes up the TF flag when stepping over a
939 /* If the instruction was a call, the return address now atop the
940 stack is the address following the copied instruction. We need
941 to make it the address following the original instruction. */
942 if (i386_call_p (insn
))
946 const ULONGEST retaddr_len
= 4;
948 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
949 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
950 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
951 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
953 displaced_debug_printf ("relocated return addr at %s to %s",
954 paddress (gdbarch
, esp
),
955 paddress (gdbarch
, retaddr
));
960 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
962 target_write_memory (*to
, buf
, len
);
967 i386_relocate_instruction (struct gdbarch
*gdbarch
,
968 CORE_ADDR
*to
, CORE_ADDR oldloc
)
970 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
971 gdb_byte buf
[I386_MAX_INSN_LEN
];
972 int offset
= 0, rel32
, newrel
;
974 gdb_byte
*insn
= buf
;
976 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
978 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
979 I386_MAX_INSN_LEN
, oldloc
);
981 /* Get past the prefixes. */
982 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
984 /* Adjust calls with 32-bit relative addresses as push/jump, with
985 the address pushed being the location where the original call in
986 the user program would return to. */
989 gdb_byte push_buf
[16];
990 unsigned int ret_addr
;
992 /* Where "ret" in the original code will return to. */
993 ret_addr
= oldloc
+ insn_length
;
994 push_buf
[0] = 0x68; /* pushq $... */
995 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
997 append_insns (to
, 5, push_buf
);
999 /* Convert the relative call to a relative jump. */
1002 /* Adjust the destination offset. */
1003 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1004 newrel
= (oldloc
- *to
) + rel32
;
1005 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1007 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1008 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1009 hex_string (newrel
), paddress (gdbarch
, *to
));
1011 /* Write the adjusted jump into its displaced location. */
1012 append_insns (to
, 5, insn
);
1016 /* Adjust jumps with 32-bit relative addresses. Calls are already
1018 if (insn
[0] == 0xe9)
1020 /* Adjust conditional jumps. */
1021 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1026 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1027 newrel
= (oldloc
- *to
) + rel32
;
1028 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1029 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1030 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1031 hex_string (newrel
), paddress (gdbarch
, *to
));
1034 /* Write the adjusted instructions into their displaced
1036 append_insns (to
, insn_length
, buf
);
1040 #ifdef I386_REGNO_TO_SYMMETRY
1041 #error "The Sequent Symmetry is no longer supported."
1044 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1045 and %esp "belong" to the calling function. Therefore these
1046 registers should be saved if they're going to be modified. */
1048 /* The maximum number of saved registers. This should include all
1049 registers mentioned above, and %eip. */
1050 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1052 struct i386_frame_cache
1060 /* Saved registers. */
1061 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1066 /* Stack space reserved for local variables. */
1070 /* Allocate and initialize a frame cache. */
1072 static struct i386_frame_cache
*
1073 i386_alloc_frame_cache (void)
1075 struct i386_frame_cache
*cache
;
1078 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1083 cache
->sp_offset
= -4;
1086 /* Saved registers. We initialize these to -1 since zero is a valid
1087 offset (that's where %ebp is supposed to be stored). */
1088 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1089 cache
->saved_regs
[i
] = -1;
1090 cache
->saved_sp
= 0;
1091 cache
->saved_sp_reg
= -1;
1092 cache
->pc_in_eax
= 0;
1094 /* Frameless until proven otherwise. */
1100 /* If the instruction at PC is a jump, return the address of its
1101 target. Otherwise, return PC. */
1104 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1106 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1111 if (target_read_code (pc
, &op
, 1))
1118 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1124 /* Relative jump: if data16 == 0, disp32, else disp16. */
1127 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1129 /* Include the size of the jmp instruction (including the
1135 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1137 /* Include the size of the jmp instruction. */
1142 /* Relative jump, disp8 (ignore data16). */
1143 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1145 delta
+= data16
+ 2;
1152 /* Check whether PC points at a prologue for a function returning a
1153 structure or union. If so, it updates CACHE and returns the
1154 address of the first instruction after the code sequence that
1155 removes the "hidden" argument from the stack or CURRENT_PC,
1156 whichever is smaller. Otherwise, return PC. */
1159 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1160 struct i386_frame_cache
*cache
)
1162 /* Functions that return a structure or union start with:
1165 xchgl %eax, (%esp) 0x87 0x04 0x24
1166 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1168 (the System V compiler puts out the second `xchg' instruction,
1169 and the assembler doesn't try to optimize it, so the 'sib' form
1170 gets generated). This sequence is used to get the address of the
1171 return buffer for a function that returns a structure. */
1172 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1173 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1177 if (current_pc
<= pc
)
1180 if (target_read_code (pc
, &op
, 1))
1183 if (op
!= 0x58) /* popl %eax */
1186 if (target_read_code (pc
+ 1, buf
, 4))
1189 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1192 if (current_pc
== pc
)
1194 cache
->sp_offset
+= 4;
1198 if (current_pc
== pc
+ 1)
1200 cache
->pc_in_eax
= 1;
1204 if (buf
[1] == proto1
[1])
1211 i386_skip_probe (CORE_ADDR pc
)
1213 /* A function may start with
1227 if (target_read_code (pc
, &op
, 1))
1230 if (op
== 0x68 || op
== 0x6a)
1234 /* Skip past the `pushl' instruction; it has either a one-byte or a
1235 four-byte operand, depending on the opcode. */
1241 /* Read the following 8 bytes, which should be `call _probe' (6
1242 bytes) followed by `addl $4,%esp' (2 bytes). */
1243 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1244 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1245 pc
+= delta
+ sizeof (buf
);
1251 /* GCC 4.1 and later, can put code in the prologue to realign the
1252 stack pointer. Check whether PC points to such code, and update
1253 CACHE accordingly. Return the first instruction after the code
1254 sequence or CURRENT_PC, whichever is smaller. If we don't
1255 recognize the code, return PC. */
1258 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1259 struct i386_frame_cache
*cache
)
1261 /* There are 2 code sequences to re-align stack before the frame
1264 1. Use a caller-saved saved register:
1270 2. Use a callee-saved saved register:
1277 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1279 0x83 0xe4 0xf0 andl $-16, %esp
1280 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1285 int offset
, offset_and
;
1286 static int regnums
[8] = {
1287 I386_EAX_REGNUM
, /* %eax */
1288 I386_ECX_REGNUM
, /* %ecx */
1289 I386_EDX_REGNUM
, /* %edx */
1290 I386_EBX_REGNUM
, /* %ebx */
1291 I386_ESP_REGNUM
, /* %esp */
1292 I386_EBP_REGNUM
, /* %ebp */
1293 I386_ESI_REGNUM
, /* %esi */
1294 I386_EDI_REGNUM
/* %edi */
1297 if (target_read_code (pc
, buf
, sizeof buf
))
1300 /* Check caller-saved saved register. The first instruction has
1301 to be "leal 4(%esp), %reg". */
1302 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1304 /* MOD must be binary 10 and R/M must be binary 100. */
1305 if ((buf
[1] & 0xc7) != 0x44)
1308 /* REG has register number. */
1309 reg
= (buf
[1] >> 3) & 7;
1314 /* Check callee-saved saved register. The first instruction
1315 has to be "pushl %reg". */
1316 if ((buf
[0] & 0xf8) != 0x50)
1322 /* The next instruction has to be "leal 8(%esp), %reg". */
1323 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1326 /* MOD must be binary 10 and R/M must be binary 100. */
1327 if ((buf
[2] & 0xc7) != 0x44)
1330 /* REG has register number. Registers in pushl and leal have to
1332 if (reg
!= ((buf
[2] >> 3) & 7))
1338 /* Rigister can't be %esp nor %ebp. */
1339 if (reg
== 4 || reg
== 5)
1342 /* The next instruction has to be "andl $-XXX, %esp". */
1343 if (buf
[offset
+ 1] != 0xe4
1344 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1347 offset_and
= offset
;
1348 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1350 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1351 0xfc. REG must be binary 110 and MOD must be binary 01. */
1352 if (buf
[offset
] != 0xff
1353 || buf
[offset
+ 2] != 0xfc
1354 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1357 /* R/M has register. Registers in leal and pushl have to be the
1359 if (reg
!= (buf
[offset
+ 1] & 7))
1362 if (current_pc
> pc
+ offset_and
)
1363 cache
->saved_sp_reg
= regnums
[reg
];
1365 return std::min (pc
+ offset
+ 3, current_pc
);
1368 /* Maximum instruction length we need to handle. */
1369 #define I386_MAX_MATCHED_INSN_LEN 6
1371 /* Instruction description. */
1375 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1376 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1379 /* Return whether instruction at PC matches PATTERN. */
1382 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1386 if (target_read_code (pc
, &op
, 1))
1389 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1391 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1392 int insn_matched
= 1;
1395 gdb_assert (pattern
.len
> 1);
1396 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1398 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1401 for (i
= 1; i
< pattern
.len
; i
++)
1403 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1406 return insn_matched
;
1411 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1412 the first instruction description that matches. Otherwise, return
1415 static struct i386_insn
*
1416 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1418 struct i386_insn
*pattern
;
1420 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1422 if (i386_match_pattern (pc
, *pattern
))
1429 /* Return whether PC points inside a sequence of instructions that
1430 matches INSN_PATTERNS. */
1433 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1435 CORE_ADDR current_pc
;
1437 struct i386_insn
*insn
;
1439 insn
= i386_match_insn (pc
, insn_patterns
);
1444 ix
= insn
- insn_patterns
;
1445 for (i
= ix
- 1; i
>= 0; i
--)
1447 current_pc
-= insn_patterns
[i
].len
;
1449 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1453 current_pc
= pc
+ insn
->len
;
1454 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1456 if (!i386_match_pattern (current_pc
, *insn
))
1459 current_pc
+= insn
->len
;
1465 /* Some special instructions that might be migrated by GCC into the
1466 part of the prologue that sets up the new stack frame. Because the
1467 stack frame hasn't been setup yet, no registers have been saved
1468 yet, and only the scratch registers %eax, %ecx and %edx can be
1471 static i386_insn i386_frame_setup_skip_insns
[] =
1473 /* Check for `movb imm8, r' and `movl imm32, r'.
1475 ??? Should we handle 16-bit operand-sizes here? */
1477 /* `movb imm8, %al' and `movb imm8, %ah' */
1478 /* `movb imm8, %cl' and `movb imm8, %ch' */
1479 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1480 /* `movb imm8, %dl' and `movb imm8, %dh' */
1481 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1482 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1483 { 5, { 0xb8 }, { 0xfe } },
1484 /* `movl imm32, %edx' */
1485 { 5, { 0xba }, { 0xff } },
1487 /* Check for `mov imm32, r32'. Note that there is an alternative
1488 encoding for `mov m32, %eax'.
1490 ??? Should we handle SIB addressing here?
1491 ??? Should we handle 16-bit operand-sizes here? */
1493 /* `movl m32, %eax' */
1494 { 5, { 0xa1 }, { 0xff } },
1495 /* `movl m32, %eax' and `mov; m32, %ecx' */
1496 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1497 /* `movl m32, %edx' */
1498 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1500 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1501 Because of the symmetry, there are actually two ways to encode
1502 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1503 opcode bytes 0x31 and 0x33 for `xorl'. */
1505 /* `subl %eax, %eax' */
1506 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1507 /* `subl %ecx, %ecx' */
1508 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1509 /* `subl %edx, %edx' */
1510 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1511 /* `xorl %eax, %eax' */
1512 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1513 /* `xorl %ecx, %ecx' */
1514 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1515 /* `xorl %edx, %edx' */
1516 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1520 /* Check whether PC points to an endbr32 instruction. */
1522 i386_skip_endbr (CORE_ADDR pc
)
1524 static const gdb_byte endbr32
[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1526 gdb_byte buf
[sizeof (endbr32
)];
1528 /* Stop there if we can't read the code */
1529 if (target_read_code (pc
, buf
, sizeof (endbr32
)))
1532 /* If the instruction isn't an endbr32, stop */
1533 if (memcmp (buf
, endbr32
, sizeof (endbr32
)) != 0)
1536 return pc
+ sizeof (endbr32
);
1539 /* Check whether PC points to a no-op instruction. */
1541 i386_skip_noop (CORE_ADDR pc
)
1546 if (target_read_code (pc
, &op
, 1))
1552 /* Ignore `nop' instruction. */
1556 if (target_read_code (pc
, &op
, 1))
1560 /* Ignore no-op instruction `mov %edi, %edi'.
1561 Microsoft system dlls often start with
1562 a `mov %edi,%edi' instruction.
1563 The 5 bytes before the function start are
1564 filled with `nop' instructions.
1565 This pattern can be used for hot-patching:
1566 The `mov %edi, %edi' instruction can be replaced by a
1567 near jump to the location of the 5 `nop' instructions
1568 which can be replaced by a 32-bit jump to anywhere
1569 in the 32-bit address space. */
1571 else if (op
== 0x8b)
1573 if (target_read_code (pc
+ 1, &op
, 1))
1579 if (target_read_code (pc
, &op
, 1))
1589 /* Check whether PC points at a code that sets up a new stack frame.
1590 If so, it updates CACHE and returns the address of the first
1591 instruction after the sequence that sets up the frame or LIMIT,
1592 whichever is smaller. If we don't recognize the code, return PC. */
1595 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1596 CORE_ADDR pc
, CORE_ADDR limit
,
1597 struct i386_frame_cache
*cache
)
1599 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1600 struct i386_insn
*insn
;
1607 if (target_read_code (pc
, &op
, 1))
1610 if (op
== 0x55) /* pushl %ebp */
1612 /* Take into account that we've executed the `pushl %ebp' that
1613 starts this instruction sequence. */
1614 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1615 cache
->sp_offset
+= 4;
1618 /* If that's all, return now. */
1622 /* Check for some special instructions that might be migrated by
1623 GCC into the prologue and skip them. At this point in the
1624 prologue, code should only touch the scratch registers %eax,
1625 %ecx and %edx, so while the number of possibilities is sheer,
1628 Make sure we only skip these instructions if we later see the
1629 `movl %esp, %ebp' that actually sets up the frame. */
1630 while (pc
+ skip
< limit
)
1632 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1639 /* If that's all, return now. */
1640 if (limit
<= pc
+ skip
)
1643 if (target_read_code (pc
+ skip
, &op
, 1))
1646 /* The i386 prologue looks like
1652 and a different prologue can be generated for atom.
1656 lea -0x10(%esp),%esp
1658 We handle both of them here. */
1662 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1664 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1670 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1675 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1676 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1685 /* OK, we actually have a frame. We just don't know how large
1686 it is yet. Set its size to zero. We'll adjust it if
1687 necessary. We also now commit to skipping the special
1688 instructions mentioned before. */
1691 /* If that's all, return now. */
1695 /* Check for stack adjustment
1701 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1702 reg, so we don't have to worry about a data16 prefix. */
1703 if (target_read_code (pc
, &op
, 1))
1707 /* `subl' with 8-bit immediate. */
1708 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1709 /* Some instruction starting with 0x83 other than `subl'. */
1712 /* `subl' with signed 8-bit immediate (though it wouldn't
1713 make sense to be negative). */
1714 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1717 else if (op
== 0x81)
1719 /* Maybe it is `subl' with a 32-bit immediate. */
1720 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1721 /* Some instruction starting with 0x81 other than `subl'. */
1724 /* It is `subl' with a 32-bit immediate. */
1725 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1728 else if (op
== 0x8d)
1730 /* The ModR/M byte is 0x64. */
1731 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1733 /* 'lea' with 8-bit displacement. */
1734 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1739 /* Some instruction other than `subl' nor 'lea'. */
1743 else if (op
== 0xc8) /* enter */
1745 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1752 /* Check whether PC points at code that saves registers on the stack.
1753 If so, it updates CACHE and returns the address of the first
1754 instruction after the register saves or CURRENT_PC, whichever is
1755 smaller. Otherwise, return PC. */
1758 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1759 struct i386_frame_cache
*cache
)
1761 CORE_ADDR offset
= 0;
1765 if (cache
->locals
> 0)
1766 offset
-= cache
->locals
;
1767 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1769 if (target_read_code (pc
, &op
, 1))
1771 if (op
< 0x50 || op
> 0x57)
1775 cache
->saved_regs
[op
- 0x50] = offset
;
1776 cache
->sp_offset
+= 4;
1783 /* Do a full analysis of the prologue at PC and update CACHE
1784 accordingly. Bail out early if CURRENT_PC is reached. Return the
1785 address where the analysis stopped.
1787 We handle these cases:
1789 The startup sequence can be at the start of the function, or the
1790 function can start with a branch to startup code at the end.
1792 %ebp can be set up with either the 'enter' instruction, or "pushl
1793 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1794 once used in the System V compiler).
1796 Local space is allocated just below the saved %ebp by either the
1797 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1798 16-bit unsigned argument for space to allocate, and the 'addl'
1799 instruction could have either a signed byte, or 32-bit immediate.
1801 Next, the registers used by this function are pushed. With the
1802 System V compiler they will always be in the order: %edi, %esi,
1803 %ebx (and sometimes a harmless bug causes it to also save but not
1804 restore %eax); however, the code below is willing to see the pushes
1805 in any order, and will handle up to 8 of them.
1807 If the setup sequence is at the end of the function, then the next
1808 instruction will be a branch back to the start. */
1811 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1812 CORE_ADDR pc
, CORE_ADDR current_pc
,
1813 struct i386_frame_cache
*cache
)
1815 pc
= i386_skip_endbr (pc
);
1816 pc
= i386_skip_noop (pc
);
1817 pc
= i386_follow_jump (gdbarch
, pc
);
1818 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1819 pc
= i386_skip_probe (pc
);
1820 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1821 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1822 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1825 /* Return PC of first real instruction. */
1828 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1830 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1832 static gdb_byte pic_pat
[6] =
1834 0xe8, 0, 0, 0, 0, /* call 0x0 */
1835 0x5b, /* popl %ebx */
1837 struct i386_frame_cache cache
;
1841 CORE_ADDR func_addr
;
1843 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1845 CORE_ADDR post_prologue_pc
1846 = skip_prologue_using_sal (gdbarch
, func_addr
);
1847 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1849 /* LLVM backend (Clang/Flang) always emits a line note before the
1850 prologue and another one after. We trust clang and newer Intel
1851 compilers to emit usable line notes. */
1852 if (post_prologue_pc
1854 && COMPUNIT_PRODUCER (cust
) != NULL
1855 && (producer_is_llvm (COMPUNIT_PRODUCER (cust
))
1856 || producer_is_icc_ge_19 (COMPUNIT_PRODUCER (cust
)))))
1857 return std::max (start_pc
, post_prologue_pc
);
1861 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1862 if (cache
.locals
< 0)
1865 /* Found valid frame setup. */
1867 /* The native cc on SVR4 in -K PIC mode inserts the following code
1868 to get the address of the global offset table (GOT) into register
1873 movl %ebx,x(%ebp) (optional)
1876 This code is with the rest of the prologue (at the end of the
1877 function), so we have to skip it to get to the first real
1878 instruction at the start of the function. */
1880 for (i
= 0; i
< 6; i
++)
1882 if (target_read_code (pc
+ i
, &op
, 1))
1885 if (pic_pat
[i
] != op
)
1892 if (target_read_code (pc
+ delta
, &op
, 1))
1895 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1897 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1899 if (op
== 0x5d) /* One byte offset from %ebp. */
1901 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1903 else /* Unexpected instruction. */
1906 if (target_read_code (pc
+ delta
, &op
, 1))
1911 if (delta
> 0 && op
== 0x81
1912 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1919 /* If the function starts with a branch (to startup code at the end)
1920 the last instruction should bring us back to the first
1921 instruction of the real code. */
1922 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1923 pc
= i386_follow_jump (gdbarch
, pc
);
1928 /* Check that the code pointed to by PC corresponds to a call to
1929 __main, skip it if so. Return PC otherwise. */
1932 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1937 if (target_read_code (pc
, &op
, 1))
1943 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1945 /* Make sure address is computed correctly as a 32bit
1946 integer even if CORE_ADDR is 64 bit wide. */
1947 struct bound_minimal_symbol s
;
1948 CORE_ADDR call_dest
;
1950 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1951 call_dest
= call_dest
& 0xffffffffU
;
1952 s
= lookup_minimal_symbol_by_pc (call_dest
);
1953 if (s
.minsym
!= NULL
1954 && s
.minsym
->linkage_name () != NULL
1955 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1963 /* This function is 64-bit safe. */
1966 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1970 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1971 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1975 /* Normal frames. */
1978 i386_frame_cache_1 (struct frame_info
*this_frame
,
1979 struct i386_frame_cache
*cache
)
1981 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1982 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1986 cache
->pc
= get_frame_func (this_frame
);
1988 /* In principle, for normal frames, %ebp holds the frame pointer,
1989 which holds the base address for the current stack frame.
1990 However, for functions that don't need it, the frame pointer is
1991 optional. For these "frameless" functions the frame pointer is
1992 actually the frame pointer of the calling frame. Signal
1993 trampolines are just a special case of a "frameless" function.
1994 They (usually) share their frame pointer with the frame that was
1995 in progress when the signal occurred. */
1997 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1998 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1999 if (cache
->base
== 0)
2005 /* For normal frames, %eip is stored at 4(%ebp). */
2006 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2009 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2012 if (cache
->locals
< 0)
2014 /* We didn't find a valid frame, which means that CACHE->base
2015 currently holds the frame pointer for our calling frame. If
2016 we're at the start of a function, or somewhere half-way its
2017 prologue, the function's frame probably hasn't been fully
2018 setup yet. Try to reconstruct the base address for the stack
2019 frame by looking at the stack pointer. For truly "frameless"
2020 functions this might work too. */
2022 if (cache
->saved_sp_reg
!= -1)
2024 /* Saved stack pointer has been saved. */
2025 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2026 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2028 /* We're halfway aligning the stack. */
2029 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2030 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2032 /* This will be added back below. */
2033 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2035 else if (cache
->pc
!= 0
2036 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2038 /* We're in a known function, but did not find a frame
2039 setup. Assume that the function does not use %ebp.
2040 Alternatively, we may have jumped to an invalid
2041 address; in that case there is definitely no new
2043 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2044 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2048 /* We're in an unknown function. We could not find the start
2049 of the function to analyze the prologue; our best option is
2050 to assume a typical frame layout with the caller's %ebp
2052 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2055 if (cache
->saved_sp_reg
!= -1)
2057 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2058 register may be unavailable). */
2059 if (cache
->saved_sp
== 0
2060 && deprecated_frame_register_read (this_frame
,
2061 cache
->saved_sp_reg
, buf
))
2062 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2064 /* Now that we have the base address for the stack frame we can
2065 calculate the value of %esp in the calling frame. */
2066 else if (cache
->saved_sp
== 0)
2067 cache
->saved_sp
= cache
->base
+ 8;
2069 /* Adjust all the saved registers such that they contain addresses
2070 instead of offsets. */
2071 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2072 if (cache
->saved_regs
[i
] != -1)
2073 cache
->saved_regs
[i
] += cache
->base
;
2078 static struct i386_frame_cache
*
2079 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2081 struct i386_frame_cache
*cache
;
2084 return (struct i386_frame_cache
*) *this_cache
;
2086 cache
= i386_alloc_frame_cache ();
2087 *this_cache
= cache
;
2091 i386_frame_cache_1 (this_frame
, cache
);
2093 catch (const gdb_exception_error
&ex
)
2095 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2103 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2104 struct frame_id
*this_id
)
2106 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2109 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2110 else if (cache
->base
== 0)
2112 /* This marks the outermost frame. */
2116 /* See the end of i386_push_dummy_call. */
2117 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2121 static enum unwind_stop_reason
2122 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2125 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2128 return UNWIND_UNAVAILABLE
;
2130 /* This marks the outermost frame. */
2131 if (cache
->base
== 0)
2132 return UNWIND_OUTERMOST
;
2134 return UNWIND_NO_REASON
;
2137 static struct value
*
2138 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2141 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2143 gdb_assert (regnum
>= 0);
2145 /* The System V ABI says that:
2147 "The flags register contains the system flags, such as the
2148 direction flag and the carry flag. The direction flag must be
2149 set to the forward (that is, zero) direction before entry and
2150 upon exit from a function. Other user flags have no specified
2151 role in the standard calling sequence and are not preserved."
2153 To guarantee the "upon exit" part of that statement we fake a
2154 saved flags register that has its direction flag cleared.
2156 Note that GCC doesn't seem to rely on the fact that the direction
2157 flag is cleared after a function return; it always explicitly
2158 clears the flag before operations where it matters.
2160 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2161 right thing to do. The way we fake the flags register here makes
2162 it impossible to change it. */
2164 if (regnum
== I386_EFLAGS_REGNUM
)
2168 val
= get_frame_register_unsigned (this_frame
, regnum
);
2170 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2173 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2174 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2176 if (regnum
== I386_ESP_REGNUM
2177 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2179 /* If the SP has been saved, but we don't know where, then this
2180 means that SAVED_SP_REG register was found unavailable back
2181 when we built the cache. */
2182 if (cache
->saved_sp
== 0)
2183 return frame_unwind_got_register (this_frame
, regnum
,
2184 cache
->saved_sp_reg
);
2186 return frame_unwind_got_constant (this_frame
, regnum
,
2190 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2191 return frame_unwind_got_memory (this_frame
, regnum
,
2192 cache
->saved_regs
[regnum
]);
2194 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2197 static const struct frame_unwind i386_frame_unwind
=
2201 i386_frame_unwind_stop_reason
,
2203 i386_frame_prev_register
,
2205 default_frame_sniffer
2208 /* Normal frames, but in a function epilogue. */
2210 /* Implement the stack_frame_destroyed_p gdbarch method.
2212 The epilogue is defined here as the 'ret' instruction, which will
2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2214 the function's stack frame. */
2217 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2220 struct compunit_symtab
*cust
;
2222 cust
= find_pc_compunit_symtab (pc
);
2223 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2226 if (target_read_memory (pc
, &insn
, 1))
2227 return 0; /* Can't read memory at pc. */
2229 if (insn
!= 0xc3) /* 'ret' instruction. */
2236 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2237 struct frame_info
*this_frame
,
2238 void **this_prologue_cache
)
2240 if (frame_relative_level (this_frame
) == 0)
2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2242 get_frame_pc (this_frame
));
2247 static struct i386_frame_cache
*
2248 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2250 struct i386_frame_cache
*cache
;
2254 return (struct i386_frame_cache
*) *this_cache
;
2256 cache
= i386_alloc_frame_cache ();
2257 *this_cache
= cache
;
2261 cache
->pc
= get_frame_func (this_frame
);
2263 /* At this point the stack looks as if we just entered the
2264 function, with the return address at the top of the
2266 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2267 cache
->base
= sp
+ cache
->sp_offset
;
2268 cache
->saved_sp
= cache
->base
+ 8;
2269 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2273 catch (const gdb_exception_error
&ex
)
2275 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2282 static enum unwind_stop_reason
2283 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2286 struct i386_frame_cache
*cache
=
2287 i386_epilogue_frame_cache (this_frame
, this_cache
);
2290 return UNWIND_UNAVAILABLE
;
2292 return UNWIND_NO_REASON
;
2296 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2298 struct frame_id
*this_id
)
2300 struct i386_frame_cache
*cache
=
2301 i386_epilogue_frame_cache (this_frame
, this_cache
);
2304 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2306 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2309 static struct value
*
2310 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2311 void **this_cache
, int regnum
)
2313 /* Make sure we've initialized the cache. */
2314 i386_epilogue_frame_cache (this_frame
, this_cache
);
2316 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2319 static const struct frame_unwind i386_epilogue_frame_unwind
=
2323 i386_epilogue_frame_unwind_stop_reason
,
2324 i386_epilogue_frame_this_id
,
2325 i386_epilogue_frame_prev_register
,
2327 i386_epilogue_frame_sniffer
2331 /* Stack-based trampolines. */
2333 /* These trampolines are used on cross x86 targets, when taking the
2334 address of a nested function. When executing these trampolines,
2335 no stack frame is set up, so we are in a similar situation as in
2336 epilogues and i386_epilogue_frame_this_id can be re-used. */
2338 /* Static chain passed in register. */
2340 static i386_insn i386_tramp_chain_in_reg_insns
[] =
2342 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2343 { 5, { 0xb8 }, { 0xfe } },
2346 { 5, { 0xe9 }, { 0xff } },
2351 /* Static chain passed on stack (when regparm=3). */
2353 static i386_insn i386_tramp_chain_on_stack_insns
[] =
2356 { 5, { 0x68 }, { 0xff } },
2359 { 5, { 0xe9 }, { 0xff } },
2364 /* Return whether PC points inside a stack trampoline. */
2367 i386_in_stack_tramp_p (CORE_ADDR pc
)
2372 /* A stack trampoline is detected if no name is associated
2373 to the current pc and if it points inside a trampoline
2376 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2380 if (target_read_memory (pc
, &insn
, 1))
2383 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2384 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2391 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2392 struct frame_info
*this_frame
,
2395 if (frame_relative_level (this_frame
) == 0)
2396 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2401 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2405 i386_epilogue_frame_unwind_stop_reason
,
2406 i386_epilogue_frame_this_id
,
2407 i386_epilogue_frame_prev_register
,
2409 i386_stack_tramp_frame_sniffer
2412 /* Generate a bytecode expression to get the value of the saved PC. */
2415 i386_gen_return_address (struct gdbarch
*gdbarch
,
2416 struct agent_expr
*ax
, struct axs_value
*value
,
2419 /* The following sequence assumes the traditional use of the base
2421 ax_reg (ax
, I386_EBP_REGNUM
);
2423 ax_simple (ax
, aop_add
);
2424 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2425 value
->kind
= axs_lvalue_memory
;
2429 /* Signal trampolines. */
2431 static struct i386_frame_cache
*
2432 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2434 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2435 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2436 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2437 struct i386_frame_cache
*cache
;
2442 return (struct i386_frame_cache
*) *this_cache
;
2444 cache
= i386_alloc_frame_cache ();
2448 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2449 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2451 addr
= tdep
->sigcontext_addr (this_frame
);
2452 if (tdep
->sc_reg_offset
)
2456 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2458 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2459 if (tdep
->sc_reg_offset
[i
] != -1)
2460 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2464 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2465 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2470 catch (const gdb_exception_error
&ex
)
2472 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2476 *this_cache
= cache
;
2480 static enum unwind_stop_reason
2481 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2484 struct i386_frame_cache
*cache
=
2485 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2488 return UNWIND_UNAVAILABLE
;
2490 return UNWIND_NO_REASON
;
2494 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2495 struct frame_id
*this_id
)
2497 struct i386_frame_cache
*cache
=
2498 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2501 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2504 /* See the end of i386_push_dummy_call. */
2505 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2509 static struct value
*
2510 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2511 void **this_cache
, int regnum
)
2513 /* Make sure we've initialized the cache. */
2514 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2516 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2520 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2521 struct frame_info
*this_frame
,
2522 void **this_prologue_cache
)
2524 gdbarch
*arch
= get_frame_arch (this_frame
);
2525 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (arch
);
2527 /* We shouldn't even bother if we don't have a sigcontext_addr
2529 if (tdep
->sigcontext_addr
== NULL
)
2532 if (tdep
->sigtramp_p
!= NULL
)
2534 if (tdep
->sigtramp_p (this_frame
))
2538 if (tdep
->sigtramp_start
!= 0)
2540 CORE_ADDR pc
= get_frame_pc (this_frame
);
2542 gdb_assert (tdep
->sigtramp_end
!= 0);
2543 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2550 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2554 i386_sigtramp_frame_unwind_stop_reason
,
2555 i386_sigtramp_frame_this_id
,
2556 i386_sigtramp_frame_prev_register
,
2558 i386_sigtramp_frame_sniffer
2563 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2565 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2570 static const struct frame_base i386_frame_base
=
2573 i386_frame_base_address
,
2574 i386_frame_base_address
,
2575 i386_frame_base_address
2578 static struct frame_id
2579 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2583 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2585 /* See the end of i386_push_dummy_call. */
2586 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2589 /* _Decimal128 function return values need 16-byte alignment on the
2593 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2595 return sp
& -(CORE_ADDR
)16;
2599 /* Figure out where the longjmp will land. Slurp the args out of the
2600 stack. We expect the first arg to be a pointer to the jmp_buf
2601 structure from which we extract the address that we will land at.
2602 This address is copied into PC. This routine returns non-zero on
2606 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2609 CORE_ADDR sp
, jb_addr
;
2610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2611 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2612 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2613 int jb_pc_offset
= tdep
->jb_pc_offset
;
2615 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2616 longjmp will land. */
2617 if (jb_pc_offset
== -1)
2620 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2621 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2622 if (target_read_memory (sp
+ 4, buf
, 4))
2625 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2626 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2629 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2634 /* Check whether TYPE must be 16-byte-aligned when passed as a
2635 function argument. 16-byte vectors, _Decimal128 and structures or
2636 unions containing such types must be 16-byte-aligned; other
2637 arguments are 4-byte-aligned. */
2640 i386_16_byte_align_p (struct type
*type
)
2642 type
= check_typedef (type
);
2643 if ((type
->code () == TYPE_CODE_DECFLOAT
2644 || (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ()))
2645 && TYPE_LENGTH (type
) == 16)
2647 if (type
->code () == TYPE_CODE_ARRAY
)
2648 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2649 if (type
->code () == TYPE_CODE_STRUCT
2650 || type
->code () == TYPE_CODE_UNION
)
2653 for (i
= 0; i
< type
->num_fields (); i
++)
2655 if (field_is_static (&type
->field (i
)))
2657 if (i386_16_byte_align_p (type
->field (i
).type ()))
2664 /* Implementation for set_gdbarch_push_dummy_code. */
2667 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2668 struct value
**args
, int nargs
, struct type
*value_type
,
2669 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2670 struct regcache
*regcache
)
2672 /* Use 0xcc breakpoint - 1 byte. */
2676 /* Keep the stack aligned. */
2680 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2681 calling convention. */
2684 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2685 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2686 int nargs
, struct value
**args
, CORE_ADDR sp
,
2687 function_call_return_method return_method
,
2688 CORE_ADDR struct_addr
, bool thiscall
)
2690 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2696 /* BND registers can be in arbitrary values at the moment of the
2697 inferior call. This can cause boundary violations that are not
2698 due to a real bug or even desired by the user. The best to be done
2699 is set the BND registers to allow access to the whole memory, INIT
2700 state, before pushing the inferior call. */
2701 i387_reset_bnd_regs (gdbarch
, regcache
);
2703 /* Determine the total space required for arguments and struct
2704 return address in a first pass (allowing for 16-byte-aligned
2705 arguments), then push arguments in a second pass. */
2707 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2709 int args_space_used
= 0;
2711 if (return_method
== return_method_struct
)
2715 /* Push value address. */
2716 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2717 write_memory (sp
, buf
, 4);
2718 args_space_used
+= 4;
2724 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2726 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2730 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2731 args_space_used
= align_up (args_space_used
, 16);
2733 write_memory (sp
+ args_space_used
,
2734 value_contents_all (args
[i
]).data (), len
);
2735 /* The System V ABI says that:
2737 "An argument's size is increased, if necessary, to make it a
2738 multiple of [32-bit] words. This may require tail padding,
2739 depending on the size of the argument."
2741 This makes sure the stack stays word-aligned. */
2742 args_space_used
+= align_up (len
, 4);
2746 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2747 args_space
= align_up (args_space
, 16);
2748 args_space
+= align_up (len
, 4);
2756 /* The original System V ABI only requires word alignment,
2757 but modern incarnations need 16-byte alignment in order
2758 to support SSE. Since wasting a few bytes here isn't
2759 harmful we unconditionally enforce 16-byte alignment. */
2764 /* Store return address. */
2766 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2767 write_memory (sp
, buf
, 4);
2769 /* Finally, update the stack pointer... */
2770 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2771 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2773 /* ...and fake a frame pointer. */
2774 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2776 /* The 'this' pointer needs to be in ECX. */
2778 regcache
->cooked_write (I386_ECX_REGNUM
,
2779 value_contents_all (args
[0]).data ());
2781 /* MarkK wrote: This "+ 8" is all over the place:
2782 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2783 i386_dummy_id). It's there, since all frame unwinders for
2784 a given target have to agree (within a certain margin) on the
2785 definition of the stack address of a frame. Otherwise frame id
2786 comparison might not work correctly. Since DWARF2/GCC uses the
2787 stack address *before* the function call as a frame's CFA. On
2788 the i386, when %ebp is used as a frame pointer, the offset
2789 between the contents %ebp and the CFA as defined by GCC. */
2793 /* Implement the "push_dummy_call" gdbarch method. */
2796 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2797 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2798 struct value
**args
, CORE_ADDR sp
,
2799 function_call_return_method return_method
,
2800 CORE_ADDR struct_addr
)
2802 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2803 nargs
, args
, sp
, return_method
,
2804 struct_addr
, false);
2807 /* These registers are used for returning integers (and on some
2808 targets also for returning `struct' and `union' values when their
2809 size and alignment match an integer type). */
2810 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2811 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2813 /* Read, for architecture GDBARCH, a function return value of TYPE
2814 from REGCACHE, and copy that into VALBUF. */
2817 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2818 struct regcache
*regcache
, gdb_byte
*valbuf
)
2820 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2821 int len
= TYPE_LENGTH (type
);
2822 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2824 /* _Float16 and _Float16 _Complex values are returned via xmm0. */
2825 if (((type
->code () == TYPE_CODE_FLT
) && len
== 2)
2826 || ((type
->code () == TYPE_CODE_COMPLEX
) && len
== 4))
2828 regcache
->raw_read (I387_XMM0_REGNUM (tdep
), valbuf
);
2831 else if (type
->code () == TYPE_CODE_FLT
)
2833 if (tdep
->st0_regnum
< 0)
2835 warning (_("Cannot find floating-point return value."));
2836 memset (valbuf
, 0, len
);
2840 /* Floating-point return values can be found in %st(0). Convert
2841 its contents to the desired type. This is probably not
2842 exactly how it would happen on the target itself, but it is
2843 the best we can do. */
2844 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2845 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2849 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2850 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2852 if (len
<= low_size
)
2854 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2855 memcpy (valbuf
, buf
, len
);
2857 else if (len
<= (low_size
+ high_size
))
2859 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2860 memcpy (valbuf
, buf
, low_size
);
2861 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2862 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2865 internal_error (__FILE__
, __LINE__
,
2866 _("Cannot extract return value of %d bytes long."),
2871 /* Write, for architecture GDBARCH, a function return value of TYPE
2872 from VALBUF into REGCACHE. */
2875 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2876 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2878 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2879 int len
= TYPE_LENGTH (type
);
2881 if (type
->code () == TYPE_CODE_FLT
)
2884 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2886 if (tdep
->st0_regnum
< 0)
2888 warning (_("Cannot set floating-point return value."));
2892 /* Returning floating-point values is a bit tricky. Apart from
2893 storing the return value in %st(0), we have to simulate the
2894 state of the FPU at function return point. */
2896 /* Convert the value found in VALBUF to the extended
2897 floating-point format used by the FPU. This is probably
2898 not exactly how it would happen on the target itself, but
2899 it is the best we can do. */
2900 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2901 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2903 /* Set the top of the floating-point register stack to 7. The
2904 actual value doesn't really matter, but 7 is what a normal
2905 function return would end up with if the program started out
2906 with a freshly initialized FPU. */
2907 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2909 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2911 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2912 the floating-point register stack to 7, the appropriate value
2913 for the tag word is 0x3fff. */
2914 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2918 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2919 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2921 if (len
<= low_size
)
2922 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2923 else if (len
<= (low_size
+ high_size
))
2925 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2926 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2930 internal_error (__FILE__
, __LINE__
,
2931 _("Cannot store return value of %d bytes long."), len
);
2936 /* This is the variable that is set with "set struct-convention", and
2937 its legitimate values. */
2938 static const char default_struct_convention
[] = "default";
2939 static const char pcc_struct_convention
[] = "pcc";
2940 static const char reg_struct_convention
[] = "reg";
2941 static const char *const valid_conventions
[] =
2943 default_struct_convention
,
2944 pcc_struct_convention
,
2945 reg_struct_convention
,
2948 static const char *struct_convention
= default_struct_convention
;
2950 /* Return non-zero if TYPE, which is assumed to be a structure,
2951 a union type, or an array type, should be returned in registers
2952 for architecture GDBARCH. */
2955 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2957 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
2958 enum type_code code
= type
->code ();
2959 int len
= TYPE_LENGTH (type
);
2961 gdb_assert (code
== TYPE_CODE_STRUCT
2962 || code
== TYPE_CODE_UNION
2963 || code
== TYPE_CODE_ARRAY
);
2965 if (struct_convention
== pcc_struct_convention
2966 || (struct_convention
== default_struct_convention
2967 && tdep
->struct_return
== pcc_struct_return
))
2970 /* Structures consisting of a single `float', `double' or 'long
2971 double' member are returned in %st(0). */
2972 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
2974 type
= check_typedef (type
->field (0).type ());
2975 if (type
->code () == TYPE_CODE_FLT
)
2976 return (len
== 4 || len
== 8 || len
== 12);
2979 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2982 /* Determine, for architecture GDBARCH, how a return value of TYPE
2983 should be returned. If it is supposed to be returned in registers,
2984 and READBUF is non-zero, read the appropriate value from REGCACHE,
2985 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2986 from WRITEBUF into REGCACHE. */
2988 static enum return_value_convention
2989 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2990 struct type
*type
, struct regcache
*regcache
,
2991 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2993 enum type_code code
= type
->code ();
2995 if (((code
== TYPE_CODE_STRUCT
2996 || code
== TYPE_CODE_UNION
2997 || code
== TYPE_CODE_ARRAY
)
2998 && !i386_reg_struct_return_p (gdbarch
, type
))
2999 /* Complex double and long double uses the struct return convention. */
3000 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
3001 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
3002 /* 128-bit decimal float uses the struct return convention. */
3003 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
3005 /* The System V ABI says that:
3007 "A function that returns a structure or union also sets %eax
3008 to the value of the original address of the caller's area
3009 before it returns. Thus when the caller receives control
3010 again, the address of the returned object resides in register
3011 %eax and can be used to access the object."
3013 So the ABI guarantees that we can always find the return
3014 value just after the function has returned. */
3016 /* Note that the ABI doesn't mention functions returning arrays,
3017 which is something possible in certain languages such as Ada.
3018 In this case, the value is returned as if it was wrapped in
3019 a record, so the convention applied to records also applies
3026 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3027 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
3030 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3033 /* This special case is for structures consisting of a single
3034 `float', `double' or 'long double' member. These structures are
3035 returned in %st(0). For these structures, we call ourselves
3036 recursively, changing TYPE into the type of the first member of
3037 the structure. Since that should work for all structures that
3038 have only one member, we don't bother to check the member's type
3040 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3042 type
= check_typedef (type
->field (0).type ());
3043 return i386_return_value (gdbarch
, function
, type
, regcache
,
3048 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3050 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3052 return RETURN_VALUE_REGISTER_CONVENTION
;
3057 i387_ext_type (struct gdbarch
*gdbarch
)
3059 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3061 if (!tdep
->i387_ext_type
)
3063 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3064 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3067 return tdep
->i387_ext_type
;
3070 /* Construct type for pseudo BND registers. We can't use
3071 tdesc_find_type since a complement of one value has to be used
3072 to describe the upper bound. */
3074 static struct type
*
3075 i386_bnd_type (struct gdbarch
*gdbarch
)
3077 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3080 if (!tdep
->i386_bnd_type
)
3083 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3085 /* The type we're building is described bellow: */
3090 void *ubound
; /* One complement of raw ubound field. */
3094 t
= arch_composite_type (gdbarch
,
3095 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3097 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3098 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3100 t
->set_name ("builtin_type_bound128");
3101 tdep
->i386_bnd_type
= t
;
3104 return tdep
->i386_bnd_type
;
3107 /* Construct vector type for pseudo ZMM registers. We can't use
3108 tdesc_find_type since ZMM isn't described in target description. */
3110 static struct type
*
3111 i386_zmm_type (struct gdbarch
*gdbarch
)
3113 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3115 if (!tdep
->i386_zmm_type
)
3117 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3119 /* The type we're building is this: */
3121 union __gdb_builtin_type_vec512i
3123 int128_t v4_int128
[4];
3124 int64_t v8_int64
[8];
3125 int32_t v16_int32
[16];
3126 int16_t v32_int16
[32];
3127 int8_t v64_int8
[64];
3128 double v8_double
[8];
3129 float v16_float
[16];
3130 float16_t v32_half
[32];
3131 bfloat16_t v32_bfloat16
[32];
3137 t
= arch_composite_type (gdbarch
,
3138 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3139 append_composite_type_field (t
, "v32_bfloat16",
3140 init_vector_type (bt
->builtin_bfloat16
, 32));
3141 append_composite_type_field (t
, "v32_half",
3142 init_vector_type (bt
->builtin_half
, 32));
3143 append_composite_type_field (t
, "v16_float",
3144 init_vector_type (bt
->builtin_float
, 16));
3145 append_composite_type_field (t
, "v8_double",
3146 init_vector_type (bt
->builtin_double
, 8));
3147 append_composite_type_field (t
, "v64_int8",
3148 init_vector_type (bt
->builtin_int8
, 64));
3149 append_composite_type_field (t
, "v32_int16",
3150 init_vector_type (bt
->builtin_int16
, 32));
3151 append_composite_type_field (t
, "v16_int32",
3152 init_vector_type (bt
->builtin_int32
, 16));
3153 append_composite_type_field (t
, "v8_int64",
3154 init_vector_type (bt
->builtin_int64
, 8));
3155 append_composite_type_field (t
, "v4_int128",
3156 init_vector_type (bt
->builtin_int128
, 4));
3158 t
->set_is_vector (true);
3159 t
->set_name ("builtin_type_vec512i");
3160 tdep
->i386_zmm_type
= t
;
3163 return tdep
->i386_zmm_type
;
3166 /* Construct vector type for pseudo YMM registers. We can't use
3167 tdesc_find_type since YMM isn't described in target description. */
3169 static struct type
*
3170 i386_ymm_type (struct gdbarch
*gdbarch
)
3172 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3174 if (!tdep
->i386_ymm_type
)
3176 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3178 /* The type we're building is this: */
3180 union __gdb_builtin_type_vec256i
3182 int128_t v2_int128
[2];
3183 int64_t v4_int64
[4];
3184 int32_t v8_int32
[8];
3185 int16_t v16_int16
[16];
3186 int8_t v32_int8
[32];
3187 double v4_double
[4];
3189 float16_t v16_half
[16];
3190 bfloat16_t v16_bfloat16
[16];
3196 t
= arch_composite_type (gdbarch
,
3197 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3198 append_composite_type_field (t
, "v16_bfloat16",
3199 init_vector_type (bt
->builtin_bfloat16
, 16));
3200 append_composite_type_field (t
, "v16_half",
3201 init_vector_type (bt
->builtin_half
, 16));
3202 append_composite_type_field (t
, "v8_float",
3203 init_vector_type (bt
->builtin_float
, 8));
3204 append_composite_type_field (t
, "v4_double",
3205 init_vector_type (bt
->builtin_double
, 4));
3206 append_composite_type_field (t
, "v32_int8",
3207 init_vector_type (bt
->builtin_int8
, 32));
3208 append_composite_type_field (t
, "v16_int16",
3209 init_vector_type (bt
->builtin_int16
, 16));
3210 append_composite_type_field (t
, "v8_int32",
3211 init_vector_type (bt
->builtin_int32
, 8));
3212 append_composite_type_field (t
, "v4_int64",
3213 init_vector_type (bt
->builtin_int64
, 4));
3214 append_composite_type_field (t
, "v2_int128",
3215 init_vector_type (bt
->builtin_int128
, 2));
3217 t
->set_is_vector (true);
3218 t
->set_name ("builtin_type_vec256i");
3219 tdep
->i386_ymm_type
= t
;
3222 return tdep
->i386_ymm_type
;
3225 /* Construct vector type for MMX registers. */
3226 static struct type
*
3227 i386_mmx_type (struct gdbarch
*gdbarch
)
3229 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3231 if (!tdep
->i386_mmx_type
)
3233 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3235 /* The type we're building is this: */
3237 union __gdb_builtin_type_vec64i
3240 int32_t v2_int32
[2];
3241 int16_t v4_int16
[4];
3248 t
= arch_composite_type (gdbarch
,
3249 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3251 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3252 append_composite_type_field (t
, "v2_int32",
3253 init_vector_type (bt
->builtin_int32
, 2));
3254 append_composite_type_field (t
, "v4_int16",
3255 init_vector_type (bt
->builtin_int16
, 4));
3256 append_composite_type_field (t
, "v8_int8",
3257 init_vector_type (bt
->builtin_int8
, 8));
3259 t
->set_is_vector (true);
3260 t
->set_name ("builtin_type_vec64i");
3261 tdep
->i386_mmx_type
= t
;
3264 return tdep
->i386_mmx_type
;
3267 /* Return the GDB type object for the "standard" data type of data in
3271 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3273 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3274 return i386_bnd_type (gdbarch
);
3275 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3276 return i386_mmx_type (gdbarch
);
3277 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3278 return i386_ymm_type (gdbarch
);
3279 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3280 return i386_ymm_type (gdbarch
);
3281 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3282 return i386_zmm_type (gdbarch
);
3285 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3286 if (i386_byte_regnum_p (gdbarch
, regnum
))
3287 return bt
->builtin_int8
;
3288 else if (i386_word_regnum_p (gdbarch
, regnum
))
3289 return bt
->builtin_int16
;
3290 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3291 return bt
->builtin_int32
;
3292 else if (i386_k_regnum_p (gdbarch
, regnum
))
3293 return bt
->builtin_int64
;
3296 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3299 /* Map a cooked register onto a raw register or memory. For the i386,
3300 the MMX registers need to be mapped onto floating point registers. */
3303 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3305 gdbarch
*arch
= regcache
->arch ();
3306 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (arch
);
3311 mmxreg
= regnum
- tdep
->mm0_regnum
;
3312 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3313 tos
= (fstat
>> 11) & 0x7;
3314 fpreg
= (mmxreg
+ tos
) % 8;
3316 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3319 /* A helper function for us by i386_pseudo_register_read_value and
3320 amd64_pseudo_register_read_value. It does all the work but reads
3321 the data into an already-allocated value. */
3324 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3325 readable_regcache
*regcache
,
3327 struct value
*result_value
)
3329 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3330 enum register_status status
;
3331 gdb_byte
*buf
= value_contents_raw (result_value
).data ();
3333 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3335 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3337 /* Extract (always little endian). */
3338 status
= regcache
->raw_read (fpnum
, raw_buf
);
3339 if (status
!= REG_VALID
)
3340 mark_value_bytes_unavailable (result_value
, 0,
3341 TYPE_LENGTH (value_type (result_value
)));
3343 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3347 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3348 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3350 regnum
-= tdep
->bnd0_regnum
;
3352 /* Extract (always little endian). Read lower 128bits. */
3353 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3355 if (status
!= REG_VALID
)
3356 mark_value_bytes_unavailable (result_value
, 0, 16);
3359 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3360 LONGEST upper
, lower
;
3361 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3363 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3364 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3367 memcpy (buf
, &lower
, size
);
3368 memcpy (buf
+ size
, &upper
, size
);
3371 else if (i386_k_regnum_p (gdbarch
, regnum
))
3373 regnum
-= tdep
->k0_regnum
;
3375 /* Extract (always little endian). */
3376 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3377 if (status
!= REG_VALID
)
3378 mark_value_bytes_unavailable (result_value
, 0, 8);
3380 memcpy (buf
, raw_buf
, 8);
3382 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3384 regnum
-= tdep
->zmm0_regnum
;
3386 if (regnum
< num_lower_zmm_regs
)
3388 /* Extract (always little endian). Read lower 128bits. */
3389 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3391 if (status
!= REG_VALID
)
3392 mark_value_bytes_unavailable (result_value
, 0, 16);
3394 memcpy (buf
, raw_buf
, 16);
3396 /* Extract (always little endian). Read upper 128bits. */
3397 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3399 if (status
!= REG_VALID
)
3400 mark_value_bytes_unavailable (result_value
, 16, 16);
3402 memcpy (buf
+ 16, raw_buf
, 16);
3406 /* Extract (always little endian). Read lower 128bits. */
3407 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3408 - num_lower_zmm_regs
,
3410 if (status
!= REG_VALID
)
3411 mark_value_bytes_unavailable (result_value
, 0, 16);
3413 memcpy (buf
, raw_buf
, 16);
3415 /* Extract (always little endian). Read upper 128bits. */
3416 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3417 - num_lower_zmm_regs
,
3419 if (status
!= REG_VALID
)
3420 mark_value_bytes_unavailable (result_value
, 16, 16);
3422 memcpy (buf
+ 16, raw_buf
, 16);
3425 /* Read upper 256bits. */
3426 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3428 if (status
!= REG_VALID
)
3429 mark_value_bytes_unavailable (result_value
, 32, 32);
3431 memcpy (buf
+ 32, raw_buf
, 32);
3433 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3435 regnum
-= tdep
->ymm0_regnum
;
3437 /* Extract (always little endian). Read lower 128bits. */
3438 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3440 if (status
!= REG_VALID
)
3441 mark_value_bytes_unavailable (result_value
, 0, 16);
3443 memcpy (buf
, raw_buf
, 16);
3444 /* Read upper 128bits. */
3445 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3447 if (status
!= REG_VALID
)
3448 mark_value_bytes_unavailable (result_value
, 16, 32);
3450 memcpy (buf
+ 16, raw_buf
, 16);
3452 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3454 regnum
-= tdep
->ymm16_regnum
;
3455 /* Extract (always little endian). Read lower 128bits. */
3456 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3458 if (status
!= REG_VALID
)
3459 mark_value_bytes_unavailable (result_value
, 0, 16);
3461 memcpy (buf
, raw_buf
, 16);
3462 /* Read upper 128bits. */
3463 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3465 if (status
!= REG_VALID
)
3466 mark_value_bytes_unavailable (result_value
, 16, 16);
3468 memcpy (buf
+ 16, raw_buf
, 16);
3470 else if (i386_word_regnum_p (gdbarch
, regnum
))
3472 int gpnum
= regnum
- tdep
->ax_regnum
;
3474 /* Extract (always little endian). */
3475 status
= regcache
->raw_read (gpnum
, raw_buf
);
3476 if (status
!= REG_VALID
)
3477 mark_value_bytes_unavailable (result_value
, 0,
3478 TYPE_LENGTH (value_type (result_value
)));
3480 memcpy (buf
, raw_buf
, 2);
3482 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3484 int gpnum
= regnum
- tdep
->al_regnum
;
3486 /* Extract (always little endian). We read both lower and
3488 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3489 if (status
!= REG_VALID
)
3490 mark_value_bytes_unavailable (result_value
, 0,
3491 TYPE_LENGTH (value_type (result_value
)));
3492 else if (gpnum
>= 4)
3493 memcpy (buf
, raw_buf
+ 1, 1);
3495 memcpy (buf
, raw_buf
, 1);
3498 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3502 static struct value
*
3503 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3504 readable_regcache
*regcache
,
3507 struct value
*result
;
3509 result
= allocate_value (register_type (gdbarch
, regnum
));
3510 VALUE_LVAL (result
) = lval_register
;
3511 VALUE_REGNUM (result
) = regnum
;
3513 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3519 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3520 int regnum
, const gdb_byte
*buf
)
3522 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3524 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3526 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3529 regcache
->raw_read (fpnum
, raw_buf
);
3530 /* ... Modify ... (always little endian). */
3531 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3533 regcache
->raw_write (fpnum
, raw_buf
);
3537 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3539 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3541 ULONGEST upper
, lower
;
3542 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3543 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3545 /* New values from input value. */
3546 regnum
-= tdep
->bnd0_regnum
;
3547 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3548 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3550 /* Fetching register buffer. */
3551 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3556 /* Set register bits. */
3557 memcpy (raw_buf
, &lower
, 8);
3558 memcpy (raw_buf
+ 8, &upper
, 8);
3560 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3562 else if (i386_k_regnum_p (gdbarch
, regnum
))
3564 regnum
-= tdep
->k0_regnum
;
3566 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3568 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3570 regnum
-= tdep
->zmm0_regnum
;
3572 if (regnum
< num_lower_zmm_regs
)
3574 /* Write lower 128bits. */
3575 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3576 /* Write upper 128bits. */
3577 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3581 /* Write lower 128bits. */
3582 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3583 - num_lower_zmm_regs
, buf
);
3584 /* Write upper 128bits. */
3585 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3586 - num_lower_zmm_regs
, buf
+ 16);
3588 /* Write upper 256bits. */
3589 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3591 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3593 regnum
-= tdep
->ymm0_regnum
;
3595 /* ... Write lower 128bits. */
3596 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3597 /* ... Write upper 128bits. */
3598 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3600 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3602 regnum
-= tdep
->ymm16_regnum
;
3604 /* ... Write lower 128bits. */
3605 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3606 /* ... Write upper 128bits. */
3607 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3609 else if (i386_word_regnum_p (gdbarch
, regnum
))
3611 int gpnum
= regnum
- tdep
->ax_regnum
;
3614 regcache
->raw_read (gpnum
, raw_buf
);
3615 /* ... Modify ... (always little endian). */
3616 memcpy (raw_buf
, buf
, 2);
3618 regcache
->raw_write (gpnum
, raw_buf
);
3620 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3622 int gpnum
= regnum
- tdep
->al_regnum
;
3624 /* Read ... We read both lower and upper registers. */
3625 regcache
->raw_read (gpnum
% 4, raw_buf
);
3626 /* ... Modify ... (always little endian). */
3628 memcpy (raw_buf
+ 1, buf
, 1);
3630 memcpy (raw_buf
, buf
, 1);
3632 regcache
->raw_write (gpnum
% 4, raw_buf
);
3635 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3639 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3642 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3643 struct agent_expr
*ax
, int regnum
)
3645 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3647 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3649 /* MMX to FPU register mapping depends on current TOS. Let's just
3650 not care and collect everything... */
3653 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3654 for (i
= 0; i
< 8; i
++)
3655 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3658 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3660 regnum
-= tdep
->bnd0_regnum
;
3661 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3664 else if (i386_k_regnum_p (gdbarch
, regnum
))
3666 regnum
-= tdep
->k0_regnum
;
3667 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3670 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3672 regnum
-= tdep
->zmm0_regnum
;
3673 if (regnum
< num_lower_zmm_regs
)
3675 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3676 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3680 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3681 - num_lower_zmm_regs
);
3682 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3683 - num_lower_zmm_regs
);
3685 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3688 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3690 regnum
-= tdep
->ymm0_regnum
;
3691 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3692 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3695 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3697 regnum
-= tdep
->ymm16_regnum
;
3698 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3699 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3702 else if (i386_word_regnum_p (gdbarch
, regnum
))
3704 int gpnum
= regnum
- tdep
->ax_regnum
;
3706 ax_reg_mask (ax
, gpnum
);
3709 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3711 int gpnum
= regnum
- tdep
->al_regnum
;
3713 ax_reg_mask (ax
, gpnum
% 4);
3717 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3722 /* Return the register number of the register allocated by GCC after
3723 REGNUM, or -1 if there is no such register. */
3726 i386_next_regnum (int regnum
)
3728 /* GCC allocates the registers in the order:
3730 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3732 Since storing a variable in %esp doesn't make any sense we return
3733 -1 for %ebp and for %esp itself. */
3734 static int next_regnum
[] =
3736 I386_EDX_REGNUM
, /* Slot for %eax. */
3737 I386_EBX_REGNUM
, /* Slot for %ecx. */
3738 I386_ECX_REGNUM
, /* Slot for %edx. */
3739 I386_ESI_REGNUM
, /* Slot for %ebx. */
3740 -1, -1, /* Slots for %esp and %ebp. */
3741 I386_EDI_REGNUM
, /* Slot for %esi. */
3742 I386_EBP_REGNUM
/* Slot for %edi. */
3745 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3746 return next_regnum
[regnum
];
3751 /* Return nonzero if a value of type TYPE stored in register REGNUM
3752 needs any special handling. */
3755 i386_convert_register_p (struct gdbarch
*gdbarch
,
3756 int regnum
, struct type
*type
)
3758 int len
= TYPE_LENGTH (type
);
3760 /* Values may be spread across multiple registers. Most debugging
3761 formats aren't expressive enough to specify the locations, so
3762 some heuristics is involved. Right now we only handle types that
3763 have a length that is a multiple of the word size, since GCC
3764 doesn't seem to put any other types into registers. */
3765 if (len
> 4 && len
% 4 == 0)
3767 int last_regnum
= regnum
;
3771 last_regnum
= i386_next_regnum (last_regnum
);
3775 if (last_regnum
!= -1)
3779 return i387_convert_register_p (gdbarch
, regnum
, type
);
3782 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3783 return its contents in TO. */
3786 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3787 struct type
*type
, gdb_byte
*to
,
3788 int *optimizedp
, int *unavailablep
)
3790 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3791 int len
= TYPE_LENGTH (type
);
3793 if (i386_fp_regnum_p (gdbarch
, regnum
))
3794 return i387_register_to_value (frame
, regnum
, type
, to
,
3795 optimizedp
, unavailablep
);
3797 /* Read a value spread across multiple registers. */
3799 gdb_assert (len
> 4 && len
% 4 == 0);
3803 gdb_assert (regnum
!= -1);
3804 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3806 if (!get_frame_register_bytes (frame
, regnum
, 0,
3807 gdb::make_array_view (to
,
3808 register_size (gdbarch
,
3810 optimizedp
, unavailablep
))
3813 regnum
= i386_next_regnum (regnum
);
3818 *optimizedp
= *unavailablep
= 0;
3822 /* Write the contents FROM of a value of type TYPE into register
3823 REGNUM in frame FRAME. */
3826 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3827 struct type
*type
, const gdb_byte
*from
)
3829 int len
= TYPE_LENGTH (type
);
3831 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3833 i387_value_to_register (frame
, regnum
, type
, from
);
3837 /* Write a value spread across multiple registers. */
3839 gdb_assert (len
> 4 && len
% 4 == 0);
3843 gdb_assert (regnum
!= -1);
3844 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3846 put_frame_register (frame
, regnum
, from
);
3847 regnum
= i386_next_regnum (regnum
);
3853 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3854 in the general-purpose register set REGSET to register cache
3855 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3858 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3859 int regnum
, const void *gregs
, size_t len
)
3861 struct gdbarch
*gdbarch
= regcache
->arch ();
3862 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3863 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3866 gdb_assert (len
>= tdep
->sizeof_gregset
);
3868 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3870 if ((regnum
== i
|| regnum
== -1)
3871 && tdep
->gregset_reg_offset
[i
] != -1)
3872 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3876 /* Collect register REGNUM from the register cache REGCACHE and store
3877 it in the buffer specified by GREGS and LEN as described by the
3878 general-purpose register set REGSET. If REGNUM is -1, do this for
3879 all registers in REGSET. */
3882 i386_collect_gregset (const struct regset
*regset
,
3883 const struct regcache
*regcache
,
3884 int regnum
, void *gregs
, size_t len
)
3886 struct gdbarch
*gdbarch
= regcache
->arch ();
3887 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3888 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3891 gdb_assert (len
>= tdep
->sizeof_gregset
);
3893 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3895 if ((regnum
== i
|| regnum
== -1)
3896 && tdep
->gregset_reg_offset
[i
] != -1)
3897 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3901 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3902 in the floating-point register set REGSET to register cache
3903 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3906 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3907 int regnum
, const void *fpregs
, size_t len
)
3909 struct gdbarch
*gdbarch
= regcache
->arch ();
3910 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3912 if (len
== I387_SIZEOF_FXSAVE
)
3914 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3918 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3919 i387_supply_fsave (regcache
, regnum
, fpregs
);
3922 /* Collect register REGNUM from the register cache REGCACHE and store
3923 it in the buffer specified by FPREGS and LEN as described by the
3924 floating-point register set REGSET. If REGNUM is -1, do this for
3925 all registers in REGSET. */
3928 i386_collect_fpregset (const struct regset
*regset
,
3929 const struct regcache
*regcache
,
3930 int regnum
, void *fpregs
, size_t len
)
3932 struct gdbarch
*gdbarch
= regcache
->arch ();
3933 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3935 if (len
== I387_SIZEOF_FXSAVE
)
3937 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3941 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3942 i387_collect_fsave (regcache
, regnum
, fpregs
);
3945 /* Register set definitions. */
3947 const struct regset i386_gregset
=
3949 NULL
, i386_supply_gregset
, i386_collect_gregset
3952 const struct regset i386_fpregset
=
3954 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3957 /* Default iterator over core file register note sections. */
3960 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3961 iterate_over_regset_sections_cb
*cb
,
3963 const struct regcache
*regcache
)
3965 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3967 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3969 if (tdep
->sizeof_fpregset
)
3970 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3975 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3978 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3979 CORE_ADDR pc
, char *name
)
3981 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3982 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3985 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3987 unsigned long indirect
=
3988 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3989 struct minimal_symbol
*indsym
=
3990 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3991 const char *symname
= indsym
? indsym
->linkage_name () : 0;
3995 if (startswith (symname
, "__imp_")
3996 || startswith (symname
, "_imp_"))
3998 read_memory_unsigned_integer (indirect
, 4, byte_order
);
4001 return 0; /* Not a trampoline. */
4005 /* Return whether the THIS_FRAME corresponds to a sigtramp
4009 i386_sigtramp_p (struct frame_info
*this_frame
)
4011 CORE_ADDR pc
= get_frame_pc (this_frame
);
4014 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4015 return (name
&& strcmp ("_sigtramp", name
) == 0);
4019 /* We have two flavours of disassembly. The machinery on this page
4020 deals with switching between those. */
4023 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4025 gdb_assert (disassembly_flavor
== att_flavor
4026 || disassembly_flavor
== intel_flavor
);
4028 info
->disassembler_options
= disassembly_flavor
;
4030 return default_print_insn (pc
, info
);
4034 /* There are a few i386 architecture variants that differ only
4035 slightly from the generic i386 target. For now, we don't give them
4036 their own source file, but include them here. As a consequence,
4037 they'll always be included. */
4039 /* System V Release 4 (SVR4). */
4041 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4045 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4047 CORE_ADDR pc
= get_frame_pc (this_frame
);
4050 /* The origin of these symbols is currently unknown. */
4051 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4052 return (name
&& (strcmp ("_sigreturn", name
) == 0
4053 || strcmp ("sigvechandler", name
) == 0));
4056 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4057 address of the associated sigcontext (ucontext) structure. */
4060 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4062 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4063 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4067 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4068 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4070 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4075 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4079 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4081 return (*s
== '$' /* Literal number. */
4082 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4083 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4084 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4087 /* Helper function for i386_stap_parse_special_token.
4089 This function parses operands of the form `-8+3+1(%rbp)', which
4090 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4092 Return true if the operand was parsed successfully, false
4095 static expr::operation_up
4096 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4097 struct stap_parse_info
*p
)
4099 const char *s
= p
->arg
;
4101 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4105 long displacements
[3];
4110 got_minus
[0] = false;
4116 got_minus
[0] = true;
4119 if (!isdigit ((unsigned char) *s
))
4122 displacements
[0] = strtol (s
, &endp
, 10);
4125 if (*s
!= '+' && *s
!= '-')
4127 /* We are not dealing with a triplet. */
4131 got_minus
[1] = false;
4137 got_minus
[1] = true;
4140 if (!isdigit ((unsigned char) *s
))
4143 displacements
[1] = strtol (s
, &endp
, 10);
4146 if (*s
!= '+' && *s
!= '-')
4148 /* We are not dealing with a triplet. */
4152 got_minus
[2] = false;
4158 got_minus
[2] = true;
4161 if (!isdigit ((unsigned char) *s
))
4164 displacements
[2] = strtol (s
, &endp
, 10);
4167 if (*s
!= '(' || s
[1] != '%')
4173 while (isalnum (*s
))
4179 len
= s
- start
- 1;
4180 std::string
regname (start
, len
);
4182 if (user_reg_map_name_to_regnum (gdbarch
, regname
.c_str (), len
) == -1)
4183 error (_("Invalid register name `%s' on expression `%s'."),
4184 regname
.c_str (), p
->saved_arg
);
4187 for (i
= 0; i
< 3; i
++)
4189 LONGEST this_val
= displacements
[i
];
4191 this_val
= -this_val
;
4197 using namespace expr
;
4199 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4201 = make_operation
<long_const_operation
> (long_type
, value
);
4204 = make_operation
<register_operation
> (std::move (regname
));
4205 struct type
*void_ptr
= builtin_type (gdbarch
)->builtin_data_ptr
;
4206 reg
= make_operation
<unop_cast_operation
> (std::move (reg
), void_ptr
);
4209 = make_operation
<add_operation
> (std::move (reg
), std::move (offset
));
4210 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4211 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4213 return make_operation
<unop_ind_operation
> (std::move (sum
));
4219 /* Helper function for i386_stap_parse_special_token.
4221 This function parses operands of the form `register base +
4222 (register index * size) + offset', as represented in
4223 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4225 Return true if the operand was parsed successfully, false
4228 static expr::operation_up
4229 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4230 struct stap_parse_info
*p
)
4232 const char *s
= p
->arg
;
4234 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4236 bool offset_minus
= false;
4238 bool size_minus
= false;
4249 offset_minus
= true;
4252 if (offset_minus
&& !isdigit (*s
))
4259 offset
= strtol (s
, &endp
, 10);
4263 if (*s
!= '(' || s
[1] != '%')
4269 while (isalnum (*s
))
4272 if (*s
!= ',' || s
[1] != '%')
4275 len_base
= s
- start
;
4276 std::string
base (start
, len_base
);
4278 if (user_reg_map_name_to_regnum (gdbarch
, base
.c_str (), len_base
) == -1)
4279 error (_("Invalid register name `%s' on expression `%s'."),
4280 base
.c_str (), p
->saved_arg
);
4285 while (isalnum (*s
))
4288 len_index
= s
- start
;
4289 std::string
index (start
, len_index
);
4291 if (user_reg_map_name_to_regnum (gdbarch
, index
.c_str (),
4293 error (_("Invalid register name `%s' on expression `%s'."),
4294 index
.c_str (), p
->saved_arg
);
4296 if (*s
!= ',' && *s
!= ')')
4312 size
= strtol (s
, &endp
, 10);
4322 using namespace expr
;
4324 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4325 operation_up reg
= make_operation
<register_operation
> (std::move (base
));
4332 = make_operation
<long_const_operation
> (long_type
, offset
);
4333 reg
= make_operation
<add_operation
> (std::move (reg
),
4337 operation_up ind_reg
4338 = make_operation
<register_operation
> (std::move (index
));
4345 = make_operation
<long_const_operation
> (long_type
, size
);
4346 ind_reg
= make_operation
<mul_operation
> (std::move (ind_reg
),
4351 = make_operation
<add_operation
> (std::move (reg
),
4352 std::move (ind_reg
));
4354 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4355 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4357 return make_operation
<unop_ind_operation
> (std::move (sum
));
4363 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4367 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4368 struct stap_parse_info
*p
)
4370 /* The special tokens to be parsed here are:
4372 - `register base + (register index * size) + offset', as represented
4373 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4375 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4376 `*(-8 + 3 - 1 + (void *) $eax)'. */
4378 expr::operation_up result
4379 = i386_stap_parse_special_token_triplet (gdbarch
, p
);
4381 if (result
== nullptr)
4382 result
= i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
);
4387 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4391 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4392 const std::string
®name
, int regnum
)
4394 static const std::unordered_set
<std::string
> reg_assoc
4395 = { "ax", "bx", "cx", "dx",
4396 "si", "di", "bp", "sp" };
4398 /* If we are dealing with a register whose size is less than the size
4399 specified by the "[-]N@" prefix, and it is one of the registers that
4400 we know has an extended variant available, then use the extended
4401 version of the register instead. */
4402 if (register_size (gdbarch
, regnum
) < TYPE_LENGTH (p
->arg_type
)
4403 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4404 return "e" + regname
;
4406 /* Otherwise, just use the requested register. */
4412 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4413 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4416 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4418 return "(x86_64|i.86)";
4423 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4426 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4428 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4429 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4435 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4437 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4438 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4439 static const char *const stap_register_indirection_prefixes
[] = { "(",
4441 static const char *const stap_register_indirection_suffixes
[] = { ")",
4444 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4445 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4447 /* Registering SystemTap handlers. */
4448 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4449 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4450 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4451 stap_register_indirection_prefixes
);
4452 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4453 stap_register_indirection_suffixes
);
4454 set_gdbarch_stap_is_single_operand (gdbarch
,
4455 i386_stap_is_single_operand
);
4456 set_gdbarch_stap_parse_special_token (gdbarch
,
4457 i386_stap_parse_special_token
);
4458 set_gdbarch_stap_adjust_register (gdbarch
,
4459 i386_stap_adjust_register
);
4461 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4462 i386_in_indirect_branch_thunk
);
4465 /* System V Release 4 (SVR4). */
4468 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4470 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4472 /* System V Release 4 uses ELF. */
4473 i386_elf_init_abi (info
, gdbarch
);
4475 /* System V Release 4 has shared libraries. */
4476 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4478 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4479 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4480 tdep
->sc_pc_offset
= 36 + 14 * 4;
4481 tdep
->sc_sp_offset
= 36 + 17 * 4;
4483 tdep
->jb_pc_offset
= 20;
4488 /* i386 register groups. In addition to the normal groups, add "mmx"
4491 static struct reggroup
*i386_sse_reggroup
;
4492 static struct reggroup
*i386_mmx_reggroup
;
4495 i386_init_reggroups (void)
4497 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4498 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4502 i386_add_reggroups (struct gdbarch
*gdbarch
)
4504 reggroup_add (gdbarch
, i386_sse_reggroup
);
4505 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4506 reggroup_add (gdbarch
, general_reggroup
);
4507 reggroup_add (gdbarch
, float_reggroup
);
4508 reggroup_add (gdbarch
, all_reggroup
);
4509 reggroup_add (gdbarch
, save_reggroup
);
4510 reggroup_add (gdbarch
, restore_reggroup
);
4511 reggroup_add (gdbarch
, vector_reggroup
);
4512 reggroup_add (gdbarch
, system_reggroup
);
4516 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4517 struct reggroup
*group
)
4519 const i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4520 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4521 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4522 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4523 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4524 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4526 /* Don't include pseudo registers, except for MMX, in any register
4528 if (i386_byte_regnum_p (gdbarch
, regnum
))
4531 if (i386_word_regnum_p (gdbarch
, regnum
))
4534 if (i386_dword_regnum_p (gdbarch
, regnum
))
4537 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4538 if (group
== i386_mmx_reggroup
)
4539 return mmx_regnum_p
;
4541 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4542 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4543 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4544 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4545 if (group
== i386_sse_reggroup
)
4546 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4548 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4549 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4550 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4552 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4553 == X86_XSTATE_AVX_AVX512_MASK
);
4554 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4555 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4556 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4557 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4559 if (group
== vector_reggroup
)
4560 return (mmx_regnum_p
4561 || (zmm_regnum_p
&& avx512_p
)
4562 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4563 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4566 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4567 || i386_fpc_regnum_p (gdbarch
, regnum
));
4568 if (group
== float_reggroup
)
4571 /* For "info reg all", don't include upper YMM registers nor XMM
4572 registers when AVX is supported. */
4573 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4574 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4575 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4576 if (group
== all_reggroup
4577 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4578 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4580 || ymmh_avx512_regnum_p
4584 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4585 if (group
== all_reggroup
4586 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4587 return bnd_regnum_p
;
4589 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4590 if (group
== all_reggroup
4591 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4594 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4595 if (group
== all_reggroup
4596 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4597 return mpx_ctrl_regnum_p
;
4599 if (group
== general_reggroup
)
4600 return (!fp_regnum_p
4604 && !xmm_avx512_regnum_p
4607 && !ymm_avx512_regnum_p
4608 && !ymmh_avx512_regnum_p
4611 && !mpx_ctrl_regnum_p
4616 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4620 /* Get the ARGIth function argument for the current function. */
4623 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4626 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4627 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4628 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4629 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4632 #define PREFIX_REPZ 0x01
4633 #define PREFIX_REPNZ 0x02
4634 #define PREFIX_LOCK 0x04
4635 #define PREFIX_DATA 0x08
4636 #define PREFIX_ADDR 0x10
4648 /* i386 arith/logic operations */
4661 struct i386_record_s
4663 struct gdbarch
*gdbarch
;
4664 struct regcache
*regcache
;
4665 CORE_ADDR orig_addr
;
4671 uint8_t mod
, reg
, rm
;
4680 /* Parse the "modrm" part of the memory address irp->addr points at.
4681 Returns -1 if something goes wrong, 0 otherwise. */
4684 i386_record_modrm (struct i386_record_s
*irp
)
4686 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4688 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4692 irp
->mod
= (irp
->modrm
>> 6) & 3;
4693 irp
->reg
= (irp
->modrm
>> 3) & 7;
4694 irp
->rm
= irp
->modrm
& 7;
4699 /* Extract the memory address that the current instruction writes to,
4700 and return it in *ADDR. Return -1 if something goes wrong. */
4703 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4705 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4706 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4711 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4718 uint8_t base
= irp
->rm
;
4723 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4726 scale
= (byte
>> 6) & 3;
4727 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4735 if ((base
& 7) == 5)
4738 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4741 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4742 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4743 *addr
+= irp
->addr
+ irp
->rip_offset
;
4747 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4750 *addr
= (int8_t) buf
[0];
4753 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4755 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4763 if (base
== 4 && irp
->popl_esp_hack
)
4764 *addr
+= irp
->popl_esp_hack
;
4765 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4768 if (irp
->aflag
== 2)
4773 *addr
= (uint32_t) (offset64
+ *addr
);
4775 if (havesib
&& (index
!= 4 || scale
!= 0))
4777 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4779 if (irp
->aflag
== 2)
4780 *addr
+= offset64
<< scale
;
4782 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4787 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4788 address from 32-bit to 64-bit. */
4789 *addr
= (uint32_t) *addr
;
4800 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4803 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4809 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4812 *addr
= (int8_t) buf
[0];
4815 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4818 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4825 regcache_raw_read_unsigned (irp
->regcache
,
4826 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4828 *addr
= (uint32_t) (*addr
+ offset64
);
4829 regcache_raw_read_unsigned (irp
->regcache
,
4830 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4832 *addr
= (uint32_t) (*addr
+ offset64
);
4835 regcache_raw_read_unsigned (irp
->regcache
,
4836 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4838 *addr
= (uint32_t) (*addr
+ offset64
);
4839 regcache_raw_read_unsigned (irp
->regcache
,
4840 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4842 *addr
= (uint32_t) (*addr
+ offset64
);
4845 regcache_raw_read_unsigned (irp
->regcache
,
4846 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4848 *addr
= (uint32_t) (*addr
+ offset64
);
4849 regcache_raw_read_unsigned (irp
->regcache
,
4850 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4852 *addr
= (uint32_t) (*addr
+ offset64
);
4855 regcache_raw_read_unsigned (irp
->regcache
,
4856 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4858 *addr
= (uint32_t) (*addr
+ offset64
);
4859 regcache_raw_read_unsigned (irp
->regcache
,
4860 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4862 *addr
= (uint32_t) (*addr
+ offset64
);
4865 regcache_raw_read_unsigned (irp
->regcache
,
4866 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4868 *addr
= (uint32_t) (*addr
+ offset64
);
4871 regcache_raw_read_unsigned (irp
->regcache
,
4872 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4874 *addr
= (uint32_t) (*addr
+ offset64
);
4877 regcache_raw_read_unsigned (irp
->regcache
,
4878 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4880 *addr
= (uint32_t) (*addr
+ offset64
);
4883 regcache_raw_read_unsigned (irp
->regcache
,
4884 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4886 *addr
= (uint32_t) (*addr
+ offset64
);
4896 /* Record the address and contents of the memory that will be changed
4897 by the current instruction. Return -1 if something goes wrong, 0
4901 i386_record_lea_modrm (struct i386_record_s
*irp
)
4903 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4906 if (irp
->override
>= 0)
4908 if (record_full_memory_query
)
4911 Process record ignores the memory change of instruction at address %s\n\
4912 because it can't get the value of the segment register.\n\
4913 Do you want to stop the program?"),
4914 paddress (gdbarch
, irp
->orig_addr
)))
4921 if (i386_record_lea_modrm_addr (irp
, &addr
))
4924 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4930 /* Record the effects of a push operation. Return -1 if something
4931 goes wrong, 0 otherwise. */
4934 i386_record_push (struct i386_record_s
*irp
, int size
)
4938 if (record_full_arch_list_add_reg (irp
->regcache
,
4939 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4941 regcache_raw_read_unsigned (irp
->regcache
,
4942 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4944 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4951 /* Defines contents to record. */
4952 #define I386_SAVE_FPU_REGS 0xfffd
4953 #define I386_SAVE_FPU_ENV 0xfffe
4954 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4956 /* Record the values of the floating point registers which will be
4957 changed by the current instruction. Returns -1 if something is
4958 wrong, 0 otherwise. */
4960 static int i386_record_floats (struct gdbarch
*gdbarch
,
4961 struct i386_record_s
*ir
,
4964 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4967 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4968 happen. Currently we store st0-st7 registers, but we need not store all
4969 registers all the time, in future we use ftag register and record only
4970 those who are not marked as an empty. */
4972 if (I386_SAVE_FPU_REGS
== iregnum
)
4974 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4976 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4980 else if (I386_SAVE_FPU_ENV
== iregnum
)
4982 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4984 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4988 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4990 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4991 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4994 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4995 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4997 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5002 /* Parameter error. */
5005 if(I386_SAVE_FPU_ENV
!= iregnum
)
5007 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5009 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5016 /* Parse the current instruction, and record the values of the
5017 registers and memory that will be changed by the current
5018 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5020 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5021 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5024 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5025 CORE_ADDR input_addr
)
5027 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5033 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5034 struct i386_record_s ir
;
5035 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5039 memset (&ir
, 0, sizeof (struct i386_record_s
));
5040 ir
.regcache
= regcache
;
5041 ir
.addr
= input_addr
;
5042 ir
.orig_addr
= input_addr
;
5046 ir
.popl_esp_hack
= 0;
5047 ir
.regmap
= tdep
->record_regmap
;
5048 ir
.gdbarch
= gdbarch
;
5050 if (record_debug
> 1)
5051 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5053 paddress (gdbarch
, ir
.addr
));
5058 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5061 switch (opcode8
) /* Instruction prefixes */
5063 case REPE_PREFIX_OPCODE
:
5064 prefixes
|= PREFIX_REPZ
;
5066 case REPNE_PREFIX_OPCODE
:
5067 prefixes
|= PREFIX_REPNZ
;
5069 case LOCK_PREFIX_OPCODE
:
5070 prefixes
|= PREFIX_LOCK
;
5072 case CS_PREFIX_OPCODE
:
5073 ir
.override
= X86_RECORD_CS_REGNUM
;
5075 case SS_PREFIX_OPCODE
:
5076 ir
.override
= X86_RECORD_SS_REGNUM
;
5078 case DS_PREFIX_OPCODE
:
5079 ir
.override
= X86_RECORD_DS_REGNUM
;
5081 case ES_PREFIX_OPCODE
:
5082 ir
.override
= X86_RECORD_ES_REGNUM
;
5084 case FS_PREFIX_OPCODE
:
5085 ir
.override
= X86_RECORD_FS_REGNUM
;
5087 case GS_PREFIX_OPCODE
:
5088 ir
.override
= X86_RECORD_GS_REGNUM
;
5090 case DATA_PREFIX_OPCODE
:
5091 prefixes
|= PREFIX_DATA
;
5093 case ADDR_PREFIX_OPCODE
:
5094 prefixes
|= PREFIX_ADDR
;
5096 case 0x40: /* i386 inc %eax */
5097 case 0x41: /* i386 inc %ecx */
5098 case 0x42: /* i386 inc %edx */
5099 case 0x43: /* i386 inc %ebx */
5100 case 0x44: /* i386 inc %esp */
5101 case 0x45: /* i386 inc %ebp */
5102 case 0x46: /* i386 inc %esi */
5103 case 0x47: /* i386 inc %edi */
5104 case 0x48: /* i386 dec %eax */
5105 case 0x49: /* i386 dec %ecx */
5106 case 0x4a: /* i386 dec %edx */
5107 case 0x4b: /* i386 dec %ebx */
5108 case 0x4c: /* i386 dec %esp */
5109 case 0x4d: /* i386 dec %ebp */
5110 case 0x4e: /* i386 dec %esi */
5111 case 0x4f: /* i386 dec %edi */
5112 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5115 rex_w
= (opcode8
>> 3) & 1;
5116 rex_r
= (opcode8
& 0x4) << 1;
5117 ir
.rex_x
= (opcode8
& 0x2) << 2;
5118 ir
.rex_b
= (opcode8
& 0x1) << 3;
5120 else /* 32 bit target */
5129 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5135 if (prefixes
& PREFIX_DATA
)
5138 if (prefixes
& PREFIX_ADDR
)
5140 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5143 /* Now check op code. */
5144 opcode
= (uint32_t) opcode8
;
5149 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5152 opcode
= (uint32_t) opcode8
| 0x0f00;
5156 case 0x00: /* arith & logic */
5204 if (((opcode
>> 3) & 7) != OP_CMPL
)
5206 if ((opcode
& 1) == 0)
5209 ir
.ot
= ir
.dflag
+ OT_WORD
;
5211 switch ((opcode
>> 1) & 3)
5213 case 0: /* OP Ev, Gv */
5214 if (i386_record_modrm (&ir
))
5218 if (i386_record_lea_modrm (&ir
))
5224 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5226 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5229 case 1: /* OP Gv, Ev */
5230 if (i386_record_modrm (&ir
))
5233 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5235 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5237 case 2: /* OP A, Iv */
5238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5245 case 0x80: /* GRP1 */
5249 if (i386_record_modrm (&ir
))
5252 if (ir
.reg
!= OP_CMPL
)
5254 if ((opcode
& 1) == 0)
5257 ir
.ot
= ir
.dflag
+ OT_WORD
;
5264 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5265 if (i386_record_lea_modrm (&ir
))
5269 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5271 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5274 case 0x40: /* inc */
5283 case 0x48: /* dec */
5292 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5293 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5296 case 0xf6: /* GRP3 */
5298 if ((opcode
& 1) == 0)
5301 ir
.ot
= ir
.dflag
+ OT_WORD
;
5302 if (i386_record_modrm (&ir
))
5305 if (ir
.mod
!= 3 && ir
.reg
== 0)
5306 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5311 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5317 if (i386_record_lea_modrm (&ir
))
5323 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5327 if (ir
.reg
== 3) /* neg */
5328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5334 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5335 if (ir
.ot
!= OT_BYTE
)
5336 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5337 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5341 opcode
= opcode
<< 8 | ir
.modrm
;
5347 case 0xfe: /* GRP4 */
5348 case 0xff: /* GRP5 */
5349 if (i386_record_modrm (&ir
))
5351 if (ir
.reg
>= 2 && opcode
== 0xfe)
5354 opcode
= opcode
<< 8 | ir
.modrm
;
5361 if ((opcode
& 1) == 0)
5364 ir
.ot
= ir
.dflag
+ OT_WORD
;
5367 if (i386_record_lea_modrm (&ir
))
5373 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5380 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5382 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5388 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5390 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5397 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5399 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5404 opcode
= opcode
<< 8 | ir
.modrm
;
5410 case 0x84: /* test */
5414 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5417 case 0x98: /* CWDE/CBW */
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5421 case 0x99: /* CDQ/CWD */
5422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5423 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5426 case 0x0faf: /* imul */
5429 ir
.ot
= ir
.dflag
+ OT_WORD
;
5430 if (i386_record_modrm (&ir
))
5433 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5434 else if (opcode
== 0x6b)
5437 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5439 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5440 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5443 case 0x0fc0: /* xadd */
5445 if ((opcode
& 1) == 0)
5448 ir
.ot
= ir
.dflag
+ OT_WORD
;
5449 if (i386_record_modrm (&ir
))
5454 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5457 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5459 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5463 if (i386_record_lea_modrm (&ir
))
5465 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5472 case 0x0fb0: /* cmpxchg */
5474 if ((opcode
& 1) == 0)
5477 ir
.ot
= ir
.dflag
+ OT_WORD
;
5478 if (i386_record_modrm (&ir
))
5483 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5484 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5486 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5491 if (i386_record_lea_modrm (&ir
))
5494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5497 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5498 if (i386_record_modrm (&ir
))
5502 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5503 an extended opcode. rdrand has bits 110 (/6) and rdseed
5504 has bits 111 (/7). */
5505 if (ir
.reg
== 6 || ir
.reg
== 7)
5507 /* The storage register is described by the 3 R/M bits, but the
5508 REX.B prefix may be used to give access to registers
5509 R8~R15. In this case ir.rex_b + R/M will give us the register
5510 in the range R8~R15.
5512 REX.W may also be used to access 64-bit registers, but we
5513 already record entire registers and not just partial bits
5515 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5516 /* These instructions also set conditional bits. */
5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5522 /* We don't handle this particular instruction yet. */
5524 opcode
= opcode
<< 8 | ir
.modrm
;
5528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5530 if (i386_record_lea_modrm (&ir
))
5532 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5535 case 0x50: /* push */
5545 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5547 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5551 case 0x06: /* push es */
5552 case 0x0e: /* push cs */
5553 case 0x16: /* push ss */
5554 case 0x1e: /* push ds */
5555 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5560 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5564 case 0x0fa0: /* push fs */
5565 case 0x0fa8: /* push gs */
5566 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5571 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5575 case 0x60: /* pusha */
5576 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5581 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5585 case 0x58: /* pop */
5593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5594 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5597 case 0x61: /* popa */
5598 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5603 for (regnum
= X86_RECORD_REAX_REGNUM
;
5604 regnum
<= X86_RECORD_REDI_REGNUM
;
5606 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5609 case 0x8f: /* pop */
5610 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5611 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5613 ir
.ot
= ir
.dflag
+ OT_WORD
;
5614 if (i386_record_modrm (&ir
))
5617 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5620 ir
.popl_esp_hack
= 1 << ir
.ot
;
5621 if (i386_record_lea_modrm (&ir
))
5624 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5627 case 0xc8: /* enter */
5628 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5629 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5631 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5635 case 0xc9: /* leave */
5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5640 case 0x07: /* pop es */
5641 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5648 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5651 case 0x17: /* pop ss */
5652 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5662 case 0x1f: /* pop ds */
5663 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5668 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5673 case 0x0fa1: /* pop fs */
5674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5675 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5676 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5679 case 0x0fa9: /* pop gs */
5680 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5685 case 0x88: /* mov */
5689 if ((opcode
& 1) == 0)
5692 ir
.ot
= ir
.dflag
+ OT_WORD
;
5694 if (i386_record_modrm (&ir
))
5699 if (opcode
== 0xc6 || opcode
== 0xc7)
5700 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5701 if (i386_record_lea_modrm (&ir
))
5706 if (opcode
== 0xc6 || opcode
== 0xc7)
5708 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5714 case 0x8a: /* mov */
5716 if ((opcode
& 1) == 0)
5719 ir
.ot
= ir
.dflag
+ OT_WORD
;
5720 if (i386_record_modrm (&ir
))
5723 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5725 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5728 case 0x8c: /* mov seg */
5729 if (i386_record_modrm (&ir
))
5734 opcode
= opcode
<< 8 | ir
.modrm
;
5739 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5743 if (i386_record_lea_modrm (&ir
))
5748 case 0x8e: /* mov seg */
5749 if (i386_record_modrm (&ir
))
5754 regnum
= X86_RECORD_ES_REGNUM
;
5757 regnum
= X86_RECORD_SS_REGNUM
;
5760 regnum
= X86_RECORD_DS_REGNUM
;
5763 regnum
= X86_RECORD_FS_REGNUM
;
5766 regnum
= X86_RECORD_GS_REGNUM
;
5770 opcode
= opcode
<< 8 | ir
.modrm
;
5774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5778 case 0x0fb6: /* movzbS */
5779 case 0x0fb7: /* movzwS */
5780 case 0x0fbe: /* movsbS */
5781 case 0x0fbf: /* movswS */
5782 if (i386_record_modrm (&ir
))
5784 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5787 case 0x8d: /* lea */
5788 if (i386_record_modrm (&ir
))
5793 opcode
= opcode
<< 8 | ir
.modrm
;
5798 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5800 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5803 case 0xa0: /* mov EAX */
5806 case 0xd7: /* xlat */
5807 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5810 case 0xa2: /* mov EAX */
5812 if (ir
.override
>= 0)
5814 if (record_full_memory_query
)
5817 Process record ignores the memory change of instruction at address %s\n\
5818 because it can't get the value of the segment register.\n\
5819 Do you want to stop the program?"),
5820 paddress (gdbarch
, ir
.orig_addr
)))
5826 if ((opcode
& 1) == 0)
5829 ir
.ot
= ir
.dflag
+ OT_WORD
;
5832 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5835 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5839 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5842 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5846 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5849 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5851 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5856 case 0xb0: /* mov R, Ib */
5864 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5865 ? ((opcode
& 0x7) | ir
.rex_b
)
5866 : ((opcode
& 0x7) & 0x3));
5869 case 0xb8: /* mov R, Iv */
5877 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5880 case 0x91: /* xchg R, EAX */
5887 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5888 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5891 case 0x86: /* xchg Ev, Gv */
5893 if ((opcode
& 1) == 0)
5896 ir
.ot
= ir
.dflag
+ OT_WORD
;
5897 if (i386_record_modrm (&ir
))
5902 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5904 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5908 if (i386_record_lea_modrm (&ir
))
5912 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5914 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5917 case 0xc4: /* les Gv */
5918 case 0xc5: /* lds Gv */
5919 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5925 case 0x0fb2: /* lss Gv */
5926 case 0x0fb4: /* lfs Gv */
5927 case 0x0fb5: /* lgs Gv */
5928 if (i386_record_modrm (&ir
))
5936 opcode
= opcode
<< 8 | ir
.modrm
;
5941 case 0xc4: /* les Gv */
5942 regnum
= X86_RECORD_ES_REGNUM
;
5944 case 0xc5: /* lds Gv */
5945 regnum
= X86_RECORD_DS_REGNUM
;
5947 case 0x0fb2: /* lss Gv */
5948 regnum
= X86_RECORD_SS_REGNUM
;
5950 case 0x0fb4: /* lfs Gv */
5951 regnum
= X86_RECORD_FS_REGNUM
;
5953 case 0x0fb5: /* lgs Gv */
5954 regnum
= X86_RECORD_GS_REGNUM
;
5957 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5958 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5959 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5962 case 0xc0: /* shifts */
5968 if ((opcode
& 1) == 0)
5971 ir
.ot
= ir
.dflag
+ OT_WORD
;
5972 if (i386_record_modrm (&ir
))
5974 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5976 if (i386_record_lea_modrm (&ir
))
5982 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5986 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5993 if (i386_record_modrm (&ir
))
5997 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6002 if (i386_record_lea_modrm (&ir
))
6007 case 0xd8: /* Floats. */
6015 if (i386_record_modrm (&ir
))
6017 ir
.reg
|= ((opcode
& 7) << 3);
6023 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6031 /* For fcom, ficom nothing to do. */
6037 /* For fcomp, ficomp pop FPU stack, store all. */
6038 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6065 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6066 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6067 of code, always affects st(0) register. */
6068 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6092 /* Handling fld, fild. */
6093 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6097 switch (ir
.reg
>> 4)
6100 if (record_full_arch_list_add_mem (addr64
, 4))
6104 if (record_full_arch_list_add_mem (addr64
, 8))
6110 if (record_full_arch_list_add_mem (addr64
, 2))
6116 switch (ir
.reg
>> 4)
6119 if (record_full_arch_list_add_mem (addr64
, 4))
6121 if (3 == (ir
.reg
& 7))
6123 /* For fstp m32fp. */
6124 if (i386_record_floats (gdbarch
, &ir
,
6125 I386_SAVE_FPU_REGS
))
6130 if (record_full_arch_list_add_mem (addr64
, 4))
6132 if ((3 == (ir
.reg
& 7))
6133 || (5 == (ir
.reg
& 7))
6134 || (7 == (ir
.reg
& 7)))
6136 /* For fstp insn. */
6137 if (i386_record_floats (gdbarch
, &ir
,
6138 I386_SAVE_FPU_REGS
))
6143 if (record_full_arch_list_add_mem (addr64
, 8))
6145 if (3 == (ir
.reg
& 7))
6147 /* For fstp m64fp. */
6148 if (i386_record_floats (gdbarch
, &ir
,
6149 I386_SAVE_FPU_REGS
))
6154 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6156 /* For fistp, fbld, fild, fbstp. */
6157 if (i386_record_floats (gdbarch
, &ir
,
6158 I386_SAVE_FPU_REGS
))
6163 if (record_full_arch_list_add_mem (addr64
, 2))
6172 if (i386_record_floats (gdbarch
, &ir
,
6173 I386_SAVE_FPU_ENV_REG_STACK
))
6178 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6183 if (i386_record_floats (gdbarch
, &ir
,
6184 I386_SAVE_FPU_ENV_REG_STACK
))
6190 if (record_full_arch_list_add_mem (addr64
, 28))
6195 if (record_full_arch_list_add_mem (addr64
, 14))
6201 if (record_full_arch_list_add_mem (addr64
, 2))
6203 /* Insn fstp, fbstp. */
6204 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6209 if (record_full_arch_list_add_mem (addr64
, 10))
6215 if (record_full_arch_list_add_mem (addr64
, 28))
6221 if (record_full_arch_list_add_mem (addr64
, 14))
6225 if (record_full_arch_list_add_mem (addr64
, 80))
6228 if (i386_record_floats (gdbarch
, &ir
,
6229 I386_SAVE_FPU_ENV_REG_STACK
))
6233 if (record_full_arch_list_add_mem (addr64
, 8))
6236 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6241 opcode
= opcode
<< 8 | ir
.modrm
;
6246 /* Opcode is an extension of modR/M byte. */
6252 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6256 if (0x0c == (ir
.modrm
>> 4))
6258 if ((ir
.modrm
& 0x0f) <= 7)
6260 if (i386_record_floats (gdbarch
, &ir
,
6261 I386_SAVE_FPU_REGS
))
6266 if (i386_record_floats (gdbarch
, &ir
,
6267 I387_ST0_REGNUM (tdep
)))
6269 /* If only st(0) is changing, then we have already
6271 if ((ir
.modrm
& 0x0f) - 0x08)
6273 if (i386_record_floats (gdbarch
, &ir
,
6274 I387_ST0_REGNUM (tdep
) +
6275 ((ir
.modrm
& 0x0f) - 0x08)))
6293 if (i386_record_floats (gdbarch
, &ir
,
6294 I387_ST0_REGNUM (tdep
)))
6312 if (i386_record_floats (gdbarch
, &ir
,
6313 I386_SAVE_FPU_REGS
))
6317 if (i386_record_floats (gdbarch
, &ir
,
6318 I387_ST0_REGNUM (tdep
)))
6320 if (i386_record_floats (gdbarch
, &ir
,
6321 I387_ST0_REGNUM (tdep
) + 1))
6328 if (0xe9 == ir
.modrm
)
6330 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6333 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6335 if (i386_record_floats (gdbarch
, &ir
,
6336 I387_ST0_REGNUM (tdep
)))
6338 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6340 if (i386_record_floats (gdbarch
, &ir
,
6341 I387_ST0_REGNUM (tdep
) +
6345 else if ((ir
.modrm
& 0x0f) - 0x08)
6347 if (i386_record_floats (gdbarch
, &ir
,
6348 I387_ST0_REGNUM (tdep
) +
6349 ((ir
.modrm
& 0x0f) - 0x08)))
6355 if (0xe3 == ir
.modrm
)
6357 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6360 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6362 if (i386_record_floats (gdbarch
, &ir
,
6363 I387_ST0_REGNUM (tdep
)))
6365 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6367 if (i386_record_floats (gdbarch
, &ir
,
6368 I387_ST0_REGNUM (tdep
) +
6372 else if ((ir
.modrm
& 0x0f) - 0x08)
6374 if (i386_record_floats (gdbarch
, &ir
,
6375 I387_ST0_REGNUM (tdep
) +
6376 ((ir
.modrm
& 0x0f) - 0x08)))
6382 if ((0x0c == ir
.modrm
>> 4)
6383 || (0x0d == ir
.modrm
>> 4)
6384 || (0x0f == ir
.modrm
>> 4))
6386 if ((ir
.modrm
& 0x0f) <= 7)
6388 if (i386_record_floats (gdbarch
, &ir
,
6389 I387_ST0_REGNUM (tdep
) +
6395 if (i386_record_floats (gdbarch
, &ir
,
6396 I387_ST0_REGNUM (tdep
) +
6397 ((ir
.modrm
& 0x0f) - 0x08)))
6403 if (0x0c == ir
.modrm
>> 4)
6405 if (i386_record_floats (gdbarch
, &ir
,
6406 I387_FTAG_REGNUM (tdep
)))
6409 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6411 if ((ir
.modrm
& 0x0f) <= 7)
6413 if (i386_record_floats (gdbarch
, &ir
,
6414 I387_ST0_REGNUM (tdep
) +
6420 if (i386_record_floats (gdbarch
, &ir
,
6421 I386_SAVE_FPU_REGS
))
6427 if ((0x0c == ir
.modrm
>> 4)
6428 || (0x0e == ir
.modrm
>> 4)
6429 || (0x0f == ir
.modrm
>> 4)
6430 || (0xd9 == ir
.modrm
))
6432 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6437 if (0xe0 == ir
.modrm
)
6439 if (record_full_arch_list_add_reg (ir
.regcache
,
6443 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6445 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6453 case 0xa4: /* movsS */
6455 case 0xaa: /* stosS */
6457 case 0x6c: /* insS */
6459 regcache_raw_read_unsigned (ir
.regcache
,
6460 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6466 if ((opcode
& 1) == 0)
6469 ir
.ot
= ir
.dflag
+ OT_WORD
;
6470 regcache_raw_read_unsigned (ir
.regcache
,
6471 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6474 regcache_raw_read_unsigned (ir
.regcache
,
6475 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6477 regcache_raw_read_unsigned (ir
.regcache
,
6478 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6480 if (ir
.aflag
&& (es
!= ds
))
6482 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6483 if (record_full_memory_query
)
6486 Process record ignores the memory change of instruction at address %s\n\
6487 because it can't get the value of the segment register.\n\
6488 Do you want to stop the program?"),
6489 paddress (gdbarch
, ir
.orig_addr
)))
6495 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6499 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6501 if (opcode
== 0xa4 || opcode
== 0xa5)
6502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6503 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6508 case 0xa6: /* cmpsS */
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6512 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6517 case 0xac: /* lodsS */
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6521 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6522 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6523 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6526 case 0xae: /* scasS */
6528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6529 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6531 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6534 case 0x6e: /* outsS */
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6537 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6542 case 0xe4: /* port I/O */
6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6557 case 0xc2: /* ret im */
6558 case 0xc3: /* ret */
6559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6560 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6563 case 0xca: /* lret im */
6564 case 0xcb: /* lret */
6565 case 0xcf: /* iret */
6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6568 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6571 case 0xe8: /* call im */
6572 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6574 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6578 case 0x9a: /* lcall im */
6579 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6585 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6589 case 0xe9: /* jmp im */
6590 case 0xea: /* ljmp im */
6591 case 0xeb: /* jmp Jb */
6592 case 0x70: /* jcc Jb */
6608 case 0x0f80: /* jcc Jv */
6626 case 0x0f90: /* setcc Gv */
6642 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6644 if (i386_record_modrm (&ir
))
6647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6651 if (i386_record_lea_modrm (&ir
))
6656 case 0x0f40: /* cmov Gv, Ev */
6672 if (i386_record_modrm (&ir
))
6675 if (ir
.dflag
== OT_BYTE
)
6677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6681 case 0x9c: /* pushf */
6682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6683 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6685 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6689 case 0x9d: /* popf */
6690 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6691 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6694 case 0x9e: /* sahf */
6695 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6701 case 0xf5: /* cmc */
6702 case 0xf8: /* clc */
6703 case 0xf9: /* stc */
6704 case 0xfc: /* cld */
6705 case 0xfd: /* std */
6706 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6709 case 0x9f: /* lahf */
6710 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6719 /* bit operations */
6720 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6721 ir
.ot
= ir
.dflag
+ OT_WORD
;
6722 if (i386_record_modrm (&ir
))
6727 opcode
= opcode
<< 8 | ir
.modrm
;
6733 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6736 if (i386_record_lea_modrm (&ir
))
6740 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6743 case 0x0fa3: /* bt Gv, Ev */
6744 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6747 case 0x0fab: /* bts */
6748 case 0x0fb3: /* btr */
6749 case 0x0fbb: /* btc */
6750 ir
.ot
= ir
.dflag
+ OT_WORD
;
6751 if (i386_record_modrm (&ir
))
6754 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6758 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6760 regcache_raw_read_unsigned (ir
.regcache
,
6761 ir
.regmap
[ir
.reg
| rex_r
],
6766 addr64
+= ((int16_t) addr
>> 4) << 4;
6769 addr64
+= ((int32_t) addr
>> 5) << 5;
6772 addr64
+= ((int64_t) addr
>> 6) << 6;
6775 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6777 if (i386_record_lea_modrm (&ir
))
6780 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6783 case 0x0fbc: /* bsf */
6784 case 0x0fbd: /* bsr */
6785 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6786 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6790 case 0x27: /* daa */
6791 case 0x2f: /* das */
6792 case 0x37: /* aaa */
6793 case 0x3f: /* aas */
6794 case 0xd4: /* aam */
6795 case 0xd5: /* aad */
6796 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6801 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6802 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6806 case 0x90: /* nop */
6807 if (prefixes
& PREFIX_LOCK
)
6814 case 0x9b: /* fwait */
6815 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6817 opcode
= (uint32_t) opcode8
;
6823 case 0xcc: /* int3 */
6824 printf_unfiltered (_("Process record does not support instruction "
6831 case 0xcd: /* int */
6835 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6838 if (interrupt
!= 0x80
6839 || tdep
->i386_intx80_record
== NULL
)
6841 printf_unfiltered (_("Process record does not support "
6842 "instruction int 0x%02x.\n"),
6847 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6854 case 0xce: /* into */
6855 printf_unfiltered (_("Process record does not support "
6856 "instruction into.\n"));
6861 case 0xfa: /* cli */
6862 case 0xfb: /* sti */
6865 case 0x62: /* bound */
6866 printf_unfiltered (_("Process record does not support "
6867 "instruction bound.\n"));
6872 case 0x0fc8: /* bswap reg */
6880 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6883 case 0xd6: /* salc */
6884 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6889 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6893 case 0xe0: /* loopnz */
6894 case 0xe1: /* loopz */
6895 case 0xe2: /* loop */
6896 case 0xe3: /* jecxz */
6897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6898 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6901 case 0x0f30: /* wrmsr */
6902 printf_unfiltered (_("Process record does not support "
6903 "instruction wrmsr.\n"));
6908 case 0x0f32: /* rdmsr */
6909 printf_unfiltered (_("Process record does not support "
6910 "instruction rdmsr.\n"));
6915 case 0x0f31: /* rdtsc */
6916 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6917 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6920 case 0x0f34: /* sysenter */
6923 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6928 if (tdep
->i386_sysenter_record
== NULL
)
6930 printf_unfiltered (_("Process record does not support "
6931 "instruction sysenter.\n"));
6935 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6941 case 0x0f35: /* sysexit */
6942 printf_unfiltered (_("Process record does not support "
6943 "instruction sysexit.\n"));
6948 case 0x0f05: /* syscall */
6951 if (tdep
->i386_syscall_record
== NULL
)
6953 printf_unfiltered (_("Process record does not support "
6954 "instruction syscall.\n"));
6958 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6964 case 0x0f07: /* sysret */
6965 printf_unfiltered (_("Process record does not support "
6966 "instruction sysret.\n"));
6971 case 0x0fa2: /* cpuid */
6972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6973 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6975 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6978 case 0xf4: /* hlt */
6979 printf_unfiltered (_("Process record does not support "
6980 "instruction hlt.\n"));
6986 if (i386_record_modrm (&ir
))
6993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6997 if (i386_record_lea_modrm (&ir
))
7006 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7010 opcode
= opcode
<< 8 | ir
.modrm
;
7017 if (i386_record_modrm (&ir
))
7028 opcode
= opcode
<< 8 | ir
.modrm
;
7031 if (ir
.override
>= 0)
7033 if (record_full_memory_query
)
7036 Process record ignores the memory change of instruction at address %s\n\
7037 because it can't get the value of the segment register.\n\
7038 Do you want to stop the program?"),
7039 paddress (gdbarch
, ir
.orig_addr
)))
7045 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7047 if (record_full_arch_list_add_mem (addr64
, 2))
7050 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7052 if (record_full_arch_list_add_mem (addr64
, 8))
7057 if (record_full_arch_list_add_mem (addr64
, 4))
7068 case 0: /* monitor */
7071 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7075 opcode
= opcode
<< 8 | ir
.modrm
;
7083 if (ir
.override
>= 0)
7085 if (record_full_memory_query
)
7088 Process record ignores the memory change of instruction at address %s\n\
7089 because it can't get the value of the segment register.\n\
7090 Do you want to stop the program?"),
7091 paddress (gdbarch
, ir
.orig_addr
)))
7099 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7101 if (record_full_arch_list_add_mem (addr64
, 2))
7104 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7106 if (record_full_arch_list_add_mem (addr64
, 8))
7111 if (record_full_arch_list_add_mem (addr64
, 4))
7123 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7124 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7128 else if (ir
.rm
== 1)
7136 opcode
= opcode
<< 8 | ir
.modrm
;
7143 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7149 if (i386_record_lea_modrm (&ir
))
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7155 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7157 case 7: /* invlpg */
7160 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7161 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7165 opcode
= opcode
<< 8 | ir
.modrm
;
7170 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7174 opcode
= opcode
<< 8 | ir
.modrm
;
7180 case 0x0f08: /* invd */
7181 case 0x0f09: /* wbinvd */
7184 case 0x63: /* arpl */
7185 if (i386_record_modrm (&ir
))
7187 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7189 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7190 ? (ir
.reg
| rex_r
) : ir
.rm
);
7194 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7195 if (i386_record_lea_modrm (&ir
))
7198 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7199 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7202 case 0x0f02: /* lar */
7203 case 0x0f03: /* lsl */
7204 if (i386_record_modrm (&ir
))
7206 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7207 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7211 if (i386_record_modrm (&ir
))
7213 if (ir
.mod
== 3 && ir
.reg
== 3)
7216 opcode
= opcode
<< 8 | ir
.modrm
;
7228 /* nop (multi byte) */
7231 case 0x0f20: /* mov reg, crN */
7232 case 0x0f22: /* mov crN, reg */
7233 if (i386_record_modrm (&ir
))
7235 if ((ir
.modrm
& 0xc0) != 0xc0)
7238 opcode
= opcode
<< 8 | ir
.modrm
;
7249 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7251 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7255 opcode
= opcode
<< 8 | ir
.modrm
;
7261 case 0x0f21: /* mov reg, drN */
7262 case 0x0f23: /* mov drN, reg */
7263 if (i386_record_modrm (&ir
))
7265 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7266 || ir
.reg
== 5 || ir
.reg
>= 8)
7269 opcode
= opcode
<< 8 | ir
.modrm
;
7273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7275 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7278 case 0x0f06: /* clts */
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7282 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7284 case 0x0f0d: /* 3DNow! prefetch */
7287 case 0x0f0e: /* 3DNow! femms */
7288 case 0x0f77: /* emms */
7289 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7291 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7294 case 0x0f0f: /* 3DNow! data */
7295 if (i386_record_modrm (&ir
))
7297 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7302 case 0x0c: /* 3DNow! pi2fw */
7303 case 0x0d: /* 3DNow! pi2fd */
7304 case 0x1c: /* 3DNow! pf2iw */
7305 case 0x1d: /* 3DNow! pf2id */
7306 case 0x8a: /* 3DNow! pfnacc */
7307 case 0x8e: /* 3DNow! pfpnacc */
7308 case 0x90: /* 3DNow! pfcmpge */
7309 case 0x94: /* 3DNow! pfmin */
7310 case 0x96: /* 3DNow! pfrcp */
7311 case 0x97: /* 3DNow! pfrsqrt */
7312 case 0x9a: /* 3DNow! pfsub */
7313 case 0x9e: /* 3DNow! pfadd */
7314 case 0xa0: /* 3DNow! pfcmpgt */
7315 case 0xa4: /* 3DNow! pfmax */
7316 case 0xa6: /* 3DNow! pfrcpit1 */
7317 case 0xa7: /* 3DNow! pfrsqit1 */
7318 case 0xaa: /* 3DNow! pfsubr */
7319 case 0xae: /* 3DNow! pfacc */
7320 case 0xb0: /* 3DNow! pfcmpeq */
7321 case 0xb4: /* 3DNow! pfmul */
7322 case 0xb6: /* 3DNow! pfrcpit2 */
7323 case 0xb7: /* 3DNow! pmulhrw */
7324 case 0xbb: /* 3DNow! pswapd */
7325 case 0xbf: /* 3DNow! pavgusb */
7326 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7327 goto no_support_3dnow_data
;
7328 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7332 no_support_3dnow_data
:
7333 opcode
= (opcode
<< 8) | opcode8
;
7339 case 0x0faa: /* rsm */
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7348 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7352 if (i386_record_modrm (&ir
))
7356 case 0: /* fxsave */
7360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7361 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7363 if (record_full_arch_list_add_mem (tmpu64
, 512))
7368 case 1: /* fxrstor */
7372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7374 for (i
= I387_MM0_REGNUM (tdep
);
7375 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7376 record_full_arch_list_add_reg (ir
.regcache
, i
);
7378 for (i
= I387_XMM0_REGNUM (tdep
);
7379 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7380 record_full_arch_list_add_reg (ir
.regcache
, i
);
7382 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7383 record_full_arch_list_add_reg (ir
.regcache
,
7384 I387_MXCSR_REGNUM(tdep
));
7386 for (i
= I387_ST0_REGNUM (tdep
);
7387 i386_fp_regnum_p (gdbarch
, i
); i
++)
7388 record_full_arch_list_add_reg (ir
.regcache
, i
);
7390 for (i
= I387_FCTRL_REGNUM (tdep
);
7391 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7392 record_full_arch_list_add_reg (ir
.regcache
, i
);
7396 case 2: /* ldmxcsr */
7397 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7399 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7402 case 3: /* stmxcsr */
7404 if (i386_record_lea_modrm (&ir
))
7408 case 5: /* lfence */
7409 case 6: /* mfence */
7410 case 7: /* sfence clflush */
7414 opcode
= (opcode
<< 8) | ir
.modrm
;
7420 case 0x0fc3: /* movnti */
7421 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7422 if (i386_record_modrm (&ir
))
7427 if (i386_record_lea_modrm (&ir
))
7431 /* Add prefix to opcode. */
7546 /* Mask out PREFIX_ADDR. */
7547 switch ((prefixes
& ~PREFIX_ADDR
))
7559 reswitch_prefix_add
:
7567 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7570 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7571 goto reswitch_prefix_add
;
7574 case 0x0f10: /* movups */
7575 case 0x660f10: /* movupd */
7576 case 0xf30f10: /* movss */
7577 case 0xf20f10: /* movsd */
7578 case 0x0f12: /* movlps */
7579 case 0x660f12: /* movlpd */
7580 case 0xf30f12: /* movsldup */
7581 case 0xf20f12: /* movddup */
7582 case 0x0f14: /* unpcklps */
7583 case 0x660f14: /* unpcklpd */
7584 case 0x0f15: /* unpckhps */
7585 case 0x660f15: /* unpckhpd */
7586 case 0x0f16: /* movhps */
7587 case 0x660f16: /* movhpd */
7588 case 0xf30f16: /* movshdup */
7589 case 0x0f28: /* movaps */
7590 case 0x660f28: /* movapd */
7591 case 0x0f2a: /* cvtpi2ps */
7592 case 0x660f2a: /* cvtpi2pd */
7593 case 0xf30f2a: /* cvtsi2ss */
7594 case 0xf20f2a: /* cvtsi2sd */
7595 case 0x0f2c: /* cvttps2pi */
7596 case 0x660f2c: /* cvttpd2pi */
7597 case 0x0f2d: /* cvtps2pi */
7598 case 0x660f2d: /* cvtpd2pi */
7599 case 0x660f3800: /* pshufb */
7600 case 0x660f3801: /* phaddw */
7601 case 0x660f3802: /* phaddd */
7602 case 0x660f3803: /* phaddsw */
7603 case 0x660f3804: /* pmaddubsw */
7604 case 0x660f3805: /* phsubw */
7605 case 0x660f3806: /* phsubd */
7606 case 0x660f3807: /* phsubsw */
7607 case 0x660f3808: /* psignb */
7608 case 0x660f3809: /* psignw */
7609 case 0x660f380a: /* psignd */
7610 case 0x660f380b: /* pmulhrsw */
7611 case 0x660f3810: /* pblendvb */
7612 case 0x660f3814: /* blendvps */
7613 case 0x660f3815: /* blendvpd */
7614 case 0x660f381c: /* pabsb */
7615 case 0x660f381d: /* pabsw */
7616 case 0x660f381e: /* pabsd */
7617 case 0x660f3820: /* pmovsxbw */
7618 case 0x660f3821: /* pmovsxbd */
7619 case 0x660f3822: /* pmovsxbq */
7620 case 0x660f3823: /* pmovsxwd */
7621 case 0x660f3824: /* pmovsxwq */
7622 case 0x660f3825: /* pmovsxdq */
7623 case 0x660f3828: /* pmuldq */
7624 case 0x660f3829: /* pcmpeqq */
7625 case 0x660f382a: /* movntdqa */
7626 case 0x660f3a08: /* roundps */
7627 case 0x660f3a09: /* roundpd */
7628 case 0x660f3a0a: /* roundss */
7629 case 0x660f3a0b: /* roundsd */
7630 case 0x660f3a0c: /* blendps */
7631 case 0x660f3a0d: /* blendpd */
7632 case 0x660f3a0e: /* pblendw */
7633 case 0x660f3a0f: /* palignr */
7634 case 0x660f3a20: /* pinsrb */
7635 case 0x660f3a21: /* insertps */
7636 case 0x660f3a22: /* pinsrd pinsrq */
7637 case 0x660f3a40: /* dpps */
7638 case 0x660f3a41: /* dppd */
7639 case 0x660f3a42: /* mpsadbw */
7640 case 0x660f3a60: /* pcmpestrm */
7641 case 0x660f3a61: /* pcmpestri */
7642 case 0x660f3a62: /* pcmpistrm */
7643 case 0x660f3a63: /* pcmpistri */
7644 case 0x0f51: /* sqrtps */
7645 case 0x660f51: /* sqrtpd */
7646 case 0xf20f51: /* sqrtsd */
7647 case 0xf30f51: /* sqrtss */
7648 case 0x0f52: /* rsqrtps */
7649 case 0xf30f52: /* rsqrtss */
7650 case 0x0f53: /* rcpps */
7651 case 0xf30f53: /* rcpss */
7652 case 0x0f54: /* andps */
7653 case 0x660f54: /* andpd */
7654 case 0x0f55: /* andnps */
7655 case 0x660f55: /* andnpd */
7656 case 0x0f56: /* orps */
7657 case 0x660f56: /* orpd */
7658 case 0x0f57: /* xorps */
7659 case 0x660f57: /* xorpd */
7660 case 0x0f58: /* addps */
7661 case 0x660f58: /* addpd */
7662 case 0xf20f58: /* addsd */
7663 case 0xf30f58: /* addss */
7664 case 0x0f59: /* mulps */
7665 case 0x660f59: /* mulpd */
7666 case 0xf20f59: /* mulsd */
7667 case 0xf30f59: /* mulss */
7668 case 0x0f5a: /* cvtps2pd */
7669 case 0x660f5a: /* cvtpd2ps */
7670 case 0xf20f5a: /* cvtsd2ss */
7671 case 0xf30f5a: /* cvtss2sd */
7672 case 0x0f5b: /* cvtdq2ps */
7673 case 0x660f5b: /* cvtps2dq */
7674 case 0xf30f5b: /* cvttps2dq */
7675 case 0x0f5c: /* subps */
7676 case 0x660f5c: /* subpd */
7677 case 0xf20f5c: /* subsd */
7678 case 0xf30f5c: /* subss */
7679 case 0x0f5d: /* minps */
7680 case 0x660f5d: /* minpd */
7681 case 0xf20f5d: /* minsd */
7682 case 0xf30f5d: /* minss */
7683 case 0x0f5e: /* divps */
7684 case 0x660f5e: /* divpd */
7685 case 0xf20f5e: /* divsd */
7686 case 0xf30f5e: /* divss */
7687 case 0x0f5f: /* maxps */
7688 case 0x660f5f: /* maxpd */
7689 case 0xf20f5f: /* maxsd */
7690 case 0xf30f5f: /* maxss */
7691 case 0x660f60: /* punpcklbw */
7692 case 0x660f61: /* punpcklwd */
7693 case 0x660f62: /* punpckldq */
7694 case 0x660f63: /* packsswb */
7695 case 0x660f64: /* pcmpgtb */
7696 case 0x660f65: /* pcmpgtw */
7697 case 0x660f66: /* pcmpgtd */
7698 case 0x660f67: /* packuswb */
7699 case 0x660f68: /* punpckhbw */
7700 case 0x660f69: /* punpckhwd */
7701 case 0x660f6a: /* punpckhdq */
7702 case 0x660f6b: /* packssdw */
7703 case 0x660f6c: /* punpcklqdq */
7704 case 0x660f6d: /* punpckhqdq */
7705 case 0x660f6e: /* movd */
7706 case 0x660f6f: /* movdqa */
7707 case 0xf30f6f: /* movdqu */
7708 case 0x660f70: /* pshufd */
7709 case 0xf20f70: /* pshuflw */
7710 case 0xf30f70: /* pshufhw */
7711 case 0x660f74: /* pcmpeqb */
7712 case 0x660f75: /* pcmpeqw */
7713 case 0x660f76: /* pcmpeqd */
7714 case 0x660f7c: /* haddpd */
7715 case 0xf20f7c: /* haddps */
7716 case 0x660f7d: /* hsubpd */
7717 case 0xf20f7d: /* hsubps */
7718 case 0xf30f7e: /* movq */
7719 case 0x0fc2: /* cmpps */
7720 case 0x660fc2: /* cmppd */
7721 case 0xf20fc2: /* cmpsd */
7722 case 0xf30fc2: /* cmpss */
7723 case 0x660fc4: /* pinsrw */
7724 case 0x0fc6: /* shufps */
7725 case 0x660fc6: /* shufpd */
7726 case 0x660fd0: /* addsubpd */
7727 case 0xf20fd0: /* addsubps */
7728 case 0x660fd1: /* psrlw */
7729 case 0x660fd2: /* psrld */
7730 case 0x660fd3: /* psrlq */
7731 case 0x660fd4: /* paddq */
7732 case 0x660fd5: /* pmullw */
7733 case 0xf30fd6: /* movq2dq */
7734 case 0x660fd8: /* psubusb */
7735 case 0x660fd9: /* psubusw */
7736 case 0x660fda: /* pminub */
7737 case 0x660fdb: /* pand */
7738 case 0x660fdc: /* paddusb */
7739 case 0x660fdd: /* paddusw */
7740 case 0x660fde: /* pmaxub */
7741 case 0x660fdf: /* pandn */
7742 case 0x660fe0: /* pavgb */
7743 case 0x660fe1: /* psraw */
7744 case 0x660fe2: /* psrad */
7745 case 0x660fe3: /* pavgw */
7746 case 0x660fe4: /* pmulhuw */
7747 case 0x660fe5: /* pmulhw */
7748 case 0x660fe6: /* cvttpd2dq */
7749 case 0xf20fe6: /* cvtpd2dq */
7750 case 0xf30fe6: /* cvtdq2pd */
7751 case 0x660fe8: /* psubsb */
7752 case 0x660fe9: /* psubsw */
7753 case 0x660fea: /* pminsw */
7754 case 0x660feb: /* por */
7755 case 0x660fec: /* paddsb */
7756 case 0x660fed: /* paddsw */
7757 case 0x660fee: /* pmaxsw */
7758 case 0x660fef: /* pxor */
7759 case 0xf20ff0: /* lddqu */
7760 case 0x660ff1: /* psllw */
7761 case 0x660ff2: /* pslld */
7762 case 0x660ff3: /* psllq */
7763 case 0x660ff4: /* pmuludq */
7764 case 0x660ff5: /* pmaddwd */
7765 case 0x660ff6: /* psadbw */
7766 case 0x660ff8: /* psubb */
7767 case 0x660ff9: /* psubw */
7768 case 0x660ffa: /* psubd */
7769 case 0x660ffb: /* psubq */
7770 case 0x660ffc: /* paddb */
7771 case 0x660ffd: /* paddw */
7772 case 0x660ffe: /* paddd */
7773 if (i386_record_modrm (&ir
))
7776 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7778 record_full_arch_list_add_reg (ir
.regcache
,
7779 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7780 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7784 case 0x0f11: /* movups */
7785 case 0x660f11: /* movupd */
7786 case 0xf30f11: /* movss */
7787 case 0xf20f11: /* movsd */
7788 case 0x0f13: /* movlps */
7789 case 0x660f13: /* movlpd */
7790 case 0x0f17: /* movhps */
7791 case 0x660f17: /* movhpd */
7792 case 0x0f29: /* movaps */
7793 case 0x660f29: /* movapd */
7794 case 0x660f3a14: /* pextrb */
7795 case 0x660f3a15: /* pextrw */
7796 case 0x660f3a16: /* pextrd pextrq */
7797 case 0x660f3a17: /* extractps */
7798 case 0x660f7f: /* movdqa */
7799 case 0xf30f7f: /* movdqu */
7800 if (i386_record_modrm (&ir
))
7804 if (opcode
== 0x0f13 || opcode
== 0x660f13
7805 || opcode
== 0x0f17 || opcode
== 0x660f17)
7808 if (!i386_xmm_regnum_p (gdbarch
,
7809 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7811 record_full_arch_list_add_reg (ir
.regcache
,
7812 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7834 if (i386_record_lea_modrm (&ir
))
7839 case 0x0f2b: /* movntps */
7840 case 0x660f2b: /* movntpd */
7841 case 0x0fe7: /* movntq */
7842 case 0x660fe7: /* movntdq */
7845 if (opcode
== 0x0fe7)
7849 if (i386_record_lea_modrm (&ir
))
7853 case 0xf30f2c: /* cvttss2si */
7854 case 0xf20f2c: /* cvttsd2si */
7855 case 0xf30f2d: /* cvtss2si */
7856 case 0xf20f2d: /* cvtsd2si */
7857 case 0xf20f38f0: /* crc32 */
7858 case 0xf20f38f1: /* crc32 */
7859 case 0x0f50: /* movmskps */
7860 case 0x660f50: /* movmskpd */
7861 case 0x0fc5: /* pextrw */
7862 case 0x660fc5: /* pextrw */
7863 case 0x0fd7: /* pmovmskb */
7864 case 0x660fd7: /* pmovmskb */
7865 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7868 case 0x0f3800: /* pshufb */
7869 case 0x0f3801: /* phaddw */
7870 case 0x0f3802: /* phaddd */
7871 case 0x0f3803: /* phaddsw */
7872 case 0x0f3804: /* pmaddubsw */
7873 case 0x0f3805: /* phsubw */
7874 case 0x0f3806: /* phsubd */
7875 case 0x0f3807: /* phsubsw */
7876 case 0x0f3808: /* psignb */
7877 case 0x0f3809: /* psignw */
7878 case 0x0f380a: /* psignd */
7879 case 0x0f380b: /* pmulhrsw */
7880 case 0x0f381c: /* pabsb */
7881 case 0x0f381d: /* pabsw */
7882 case 0x0f381e: /* pabsd */
7883 case 0x0f382b: /* packusdw */
7884 case 0x0f3830: /* pmovzxbw */
7885 case 0x0f3831: /* pmovzxbd */
7886 case 0x0f3832: /* pmovzxbq */
7887 case 0x0f3833: /* pmovzxwd */
7888 case 0x0f3834: /* pmovzxwq */
7889 case 0x0f3835: /* pmovzxdq */
7890 case 0x0f3837: /* pcmpgtq */
7891 case 0x0f3838: /* pminsb */
7892 case 0x0f3839: /* pminsd */
7893 case 0x0f383a: /* pminuw */
7894 case 0x0f383b: /* pminud */
7895 case 0x0f383c: /* pmaxsb */
7896 case 0x0f383d: /* pmaxsd */
7897 case 0x0f383e: /* pmaxuw */
7898 case 0x0f383f: /* pmaxud */
7899 case 0x0f3840: /* pmulld */
7900 case 0x0f3841: /* phminposuw */
7901 case 0x0f3a0f: /* palignr */
7902 case 0x0f60: /* punpcklbw */
7903 case 0x0f61: /* punpcklwd */
7904 case 0x0f62: /* punpckldq */
7905 case 0x0f63: /* packsswb */
7906 case 0x0f64: /* pcmpgtb */
7907 case 0x0f65: /* pcmpgtw */
7908 case 0x0f66: /* pcmpgtd */
7909 case 0x0f67: /* packuswb */
7910 case 0x0f68: /* punpckhbw */
7911 case 0x0f69: /* punpckhwd */
7912 case 0x0f6a: /* punpckhdq */
7913 case 0x0f6b: /* packssdw */
7914 case 0x0f6e: /* movd */
7915 case 0x0f6f: /* movq */
7916 case 0x0f70: /* pshufw */
7917 case 0x0f74: /* pcmpeqb */
7918 case 0x0f75: /* pcmpeqw */
7919 case 0x0f76: /* pcmpeqd */
7920 case 0x0fc4: /* pinsrw */
7921 case 0x0fd1: /* psrlw */
7922 case 0x0fd2: /* psrld */
7923 case 0x0fd3: /* psrlq */
7924 case 0x0fd4: /* paddq */
7925 case 0x0fd5: /* pmullw */
7926 case 0xf20fd6: /* movdq2q */
7927 case 0x0fd8: /* psubusb */
7928 case 0x0fd9: /* psubusw */
7929 case 0x0fda: /* pminub */
7930 case 0x0fdb: /* pand */
7931 case 0x0fdc: /* paddusb */
7932 case 0x0fdd: /* paddusw */
7933 case 0x0fde: /* pmaxub */
7934 case 0x0fdf: /* pandn */
7935 case 0x0fe0: /* pavgb */
7936 case 0x0fe1: /* psraw */
7937 case 0x0fe2: /* psrad */
7938 case 0x0fe3: /* pavgw */
7939 case 0x0fe4: /* pmulhuw */
7940 case 0x0fe5: /* pmulhw */
7941 case 0x0fe8: /* psubsb */
7942 case 0x0fe9: /* psubsw */
7943 case 0x0fea: /* pminsw */
7944 case 0x0feb: /* por */
7945 case 0x0fec: /* paddsb */
7946 case 0x0fed: /* paddsw */
7947 case 0x0fee: /* pmaxsw */
7948 case 0x0fef: /* pxor */
7949 case 0x0ff1: /* psllw */
7950 case 0x0ff2: /* pslld */
7951 case 0x0ff3: /* psllq */
7952 case 0x0ff4: /* pmuludq */
7953 case 0x0ff5: /* pmaddwd */
7954 case 0x0ff6: /* psadbw */
7955 case 0x0ff8: /* psubb */
7956 case 0x0ff9: /* psubw */
7957 case 0x0ffa: /* psubd */
7958 case 0x0ffb: /* psubq */
7959 case 0x0ffc: /* paddb */
7960 case 0x0ffd: /* paddw */
7961 case 0x0ffe: /* paddd */
7962 if (i386_record_modrm (&ir
))
7964 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7966 record_full_arch_list_add_reg (ir
.regcache
,
7967 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7970 case 0x0f71: /* psllw */
7971 case 0x0f72: /* pslld */
7972 case 0x0f73: /* psllq */
7973 if (i386_record_modrm (&ir
))
7975 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7977 record_full_arch_list_add_reg (ir
.regcache
,
7978 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7981 case 0x660f71: /* psllw */
7982 case 0x660f72: /* pslld */
7983 case 0x660f73: /* psllq */
7984 if (i386_record_modrm (&ir
))
7987 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7989 record_full_arch_list_add_reg (ir
.regcache
,
7990 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7993 case 0x0f7e: /* movd */
7994 case 0x660f7e: /* movd */
7995 if (i386_record_modrm (&ir
))
7998 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8005 if (i386_record_lea_modrm (&ir
))
8010 case 0x0f7f: /* movq */
8011 if (i386_record_modrm (&ir
))
8015 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8017 record_full_arch_list_add_reg (ir
.regcache
,
8018 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8023 if (i386_record_lea_modrm (&ir
))
8028 case 0xf30fb8: /* popcnt */
8029 if (i386_record_modrm (&ir
))
8031 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8032 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8035 case 0x660fd6: /* movq */
8036 if (i386_record_modrm (&ir
))
8041 if (!i386_xmm_regnum_p (gdbarch
,
8042 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8044 record_full_arch_list_add_reg (ir
.regcache
,
8045 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8050 if (i386_record_lea_modrm (&ir
))
8055 case 0x660f3817: /* ptest */
8056 case 0x0f2e: /* ucomiss */
8057 case 0x660f2e: /* ucomisd */
8058 case 0x0f2f: /* comiss */
8059 case 0x660f2f: /* comisd */
8060 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8063 case 0x0ff7: /* maskmovq */
8064 regcache_raw_read_unsigned (ir
.regcache
,
8065 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8067 if (record_full_arch_list_add_mem (addr
, 64))
8071 case 0x660ff7: /* maskmovdqu */
8072 regcache_raw_read_unsigned (ir
.regcache
,
8073 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8075 if (record_full_arch_list_add_mem (addr
, 128))
8090 /* In the future, maybe still need to deal with need_dasm. */
8091 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8092 if (record_full_arch_list_add_end ())
8098 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8099 "at address %s.\n"),
8100 (unsigned int) (opcode
),
8101 paddress (gdbarch
, ir
.orig_addr
));
8105 static const int i386_record_regmap
[] =
8107 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8108 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8109 0, 0, 0, 0, 0, 0, 0, 0,
8110 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8111 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8114 /* Check that the given address appears suitable for a fast
8115 tracepoint, which on x86-64 means that we need an instruction of at
8116 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8117 jump and not have to worry about program jumps to an address in the
8118 middle of the tracepoint jump. On x86, it may be possible to use
8119 4-byte jumps with a 2-byte offset to a trampoline located in the
8120 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8121 of instruction to replace, and 0 if not, plus an explanatory
8125 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8130 /* Ask the target for the minimum instruction length supported. */
8131 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8135 /* If the target does not support the get_min_fast_tracepoint_insn_len
8136 operation, assume that fast tracepoints will always be implemented
8137 using 4-byte relative jumps on both x86 and x86-64. */
8140 else if (jumplen
== 0)
8142 /* If the target does support get_min_fast_tracepoint_insn_len but
8143 returns zero, then the IPA has not loaded yet. In this case,
8144 we optimistically assume that truncated 2-byte relative jumps
8145 will be available on x86, and compensate later if this assumption
8146 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8147 jumps will always be used. */
8148 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8151 /* Check for fit. */
8152 len
= gdb_insn_length (gdbarch
, addr
);
8156 /* Return a bit of target-specific detail to add to the caller's
8157 generic failure message. */
8159 *msg
= string_printf (_("; instruction is only %d bytes long, "
8160 "need at least %d bytes for the jump"),
8172 /* Return a floating-point format for a floating-point variable of
8173 length LEN in bits. If non-NULL, NAME is the name of its type.
8174 If no suitable type is found, return NULL. */
8176 static const struct floatformat
**
8177 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8178 const char *name
, int len
)
8180 if (len
== 128 && name
)
8181 if (strcmp (name
, "__float128") == 0
8182 || strcmp (name
, "_Float128") == 0
8183 || strcmp (name
, "complex _Float128") == 0
8184 || strcmp (name
, "complex(kind=16)") == 0
8185 || strcmp (name
, "complex*32") == 0
8186 || strcmp (name
, "COMPLEX*32") == 0
8187 || strcmp (name
, "quad complex") == 0
8188 || strcmp (name
, "real(kind=16)") == 0
8189 || strcmp (name
, "real*16") == 0
8190 || strcmp (name
, "REAL*16") == 0)
8191 return floatformats_ia64_quad
;
8193 return default_floatformat_for_type (gdbarch
, name
, len
);
8197 i386_validate_tdesc_p (i386_gdbarch_tdep
*tdep
,
8198 struct tdesc_arch_data
*tdesc_data
)
8200 const struct target_desc
*tdesc
= tdep
->tdesc
;
8201 const struct tdesc_feature
*feature_core
;
8203 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8204 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8205 int i
, num_regs
, valid_p
;
8207 if (! tdesc_has_registers (tdesc
))
8210 /* Get core registers. */
8211 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8212 if (feature_core
== NULL
)
8215 /* Get SSE registers. */
8216 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8218 /* Try AVX registers. */
8219 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8221 /* Try MPX registers. */
8222 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8224 /* Try AVX512 registers. */
8225 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8227 /* Try segment base registers. */
8228 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8231 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8235 /* The XCR0 bits. */
8238 /* AVX512 register description requires AVX register description. */
8242 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8244 /* It may have been set by OSABI initialization function. */
8245 if (tdep
->k0_regnum
< 0)
8247 tdep
->k_register_names
= i386_k_names
;
8248 tdep
->k0_regnum
= I386_K0_REGNUM
;
8251 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8252 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8253 tdep
->k0_regnum
+ i
,
8256 if (tdep
->num_zmm_regs
== 0)
8258 tdep
->zmmh_register_names
= i386_zmmh_names
;
8259 tdep
->num_zmm_regs
= 8;
8260 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8263 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8264 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8265 tdep
->zmm0h_regnum
+ i
,
8266 tdep
->zmmh_register_names
[i
]);
8268 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8269 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8270 tdep
->xmm16_regnum
+ i
,
8271 tdep
->xmm_avx512_register_names
[i
]);
8273 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8274 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8275 tdep
->ymm16h_regnum
+ i
,
8276 tdep
->ymm16h_register_names
[i
]);
8280 /* AVX register description requires SSE register description. */
8284 if (!feature_avx512
)
8285 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8287 /* It may have been set by OSABI initialization function. */
8288 if (tdep
->num_ymm_regs
== 0)
8290 tdep
->ymmh_register_names
= i386_ymmh_names
;
8291 tdep
->num_ymm_regs
= 8;
8292 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8295 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8296 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8297 tdep
->ymm0h_regnum
+ i
,
8298 tdep
->ymmh_register_names
[i
]);
8300 else if (feature_sse
)
8301 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8304 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8305 tdep
->num_xmm_regs
= 0;
8308 num_regs
= tdep
->num_core_regs
;
8309 for (i
= 0; i
< num_regs
; i
++)
8310 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8311 tdep
->register_names
[i
]);
8315 /* Need to include %mxcsr, so add one. */
8316 num_regs
+= tdep
->num_xmm_regs
+ 1;
8317 for (; i
< num_regs
; i
++)
8318 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8319 tdep
->register_names
[i
]);
8324 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8326 if (tdep
->bnd0r_regnum
< 0)
8328 tdep
->mpx_register_names
= i386_mpx_names
;
8329 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8330 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8333 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8334 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8335 I387_BND0R_REGNUM (tdep
) + i
,
8336 tdep
->mpx_register_names
[i
]);
8339 if (feature_segments
)
8341 if (tdep
->fsbase_regnum
< 0)
8342 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8343 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8344 tdep
->fsbase_regnum
, "fs_base");
8345 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8346 tdep
->fsbase_regnum
+ 1, "gs_base");
8351 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8352 if (tdep
->pkru_regnum
< 0)
8354 tdep
->pkeys_register_names
= i386_pkeys_names
;
8355 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8356 tdep
->num_pkeys_regs
= 1;
8359 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8360 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8361 I387_PKRU_REGNUM (tdep
) + i
,
8362 tdep
->pkeys_register_names
[i
]);
8370 /* Implement the type_align gdbarch function. */
8373 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8375 type
= check_typedef (type
);
8377 if (gdbarch_ptr_bit (gdbarch
) == 32)
8379 if ((type
->code () == TYPE_CODE_INT
8380 || type
->code () == TYPE_CODE_FLT
)
8381 && TYPE_LENGTH (type
) > 4)
8384 /* Handle x86's funny long double. */
8385 if (type
->code () == TYPE_CODE_FLT
8386 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8394 /* Note: This is called for both i386 and amd64. */
8396 static struct gdbarch
*
8397 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8399 struct gdbarch
*gdbarch
;
8400 const struct target_desc
*tdesc
;
8406 /* If there is already a candidate, use it. */
8407 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8409 return arches
->gdbarch
;
8411 /* Allocate space for the new architecture. Assume i386 for now. */
8412 i386_gdbarch_tdep
*tdep
= new i386_gdbarch_tdep
;
8413 gdbarch
= gdbarch_alloc (&info
, tdep
);
8415 /* General-purpose registers. */
8416 tdep
->gregset_reg_offset
= NULL
;
8417 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8418 tdep
->sizeof_gregset
= 0;
8420 /* Floating-point registers. */
8421 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8422 tdep
->fpregset
= &i386_fpregset
;
8424 /* The default settings include the FPU registers, the MMX registers
8425 and the SSE registers. This can be overridden for a specific ABI
8426 by adjusting the members `st0_regnum', `mm0_regnum' and
8427 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8428 will show up in the output of "info all-registers". */
8430 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8432 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8433 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8435 tdep
->jb_pc_offset
= -1;
8436 tdep
->struct_return
= pcc_struct_return
;
8437 tdep
->sigtramp_start
= 0;
8438 tdep
->sigtramp_end
= 0;
8439 tdep
->sigtramp_p
= i386_sigtramp_p
;
8440 tdep
->sigcontext_addr
= NULL
;
8441 tdep
->sc_reg_offset
= NULL
;
8442 tdep
->sc_pc_offset
= -1;
8443 tdep
->sc_sp_offset
= -1;
8445 tdep
->xsave_xcr0_offset
= -1;
8447 tdep
->record_regmap
= i386_record_regmap
;
8449 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8451 /* The format used for `long double' on almost all i386 targets is
8452 the i387 extended floating-point format. In fact, of all targets
8453 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8454 on having a `long double' that's not `long' at all. */
8455 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8457 /* Although the i387 extended floating-point has only 80 significant
8458 bits, a `long double' actually takes up 96, probably to enforce
8460 set_gdbarch_long_double_bit (gdbarch
, 96);
8462 /* Support of bfloat16 format. */
8463 set_gdbarch_bfloat16_format (gdbarch
, floatformats_bfloat16
);
8465 /* Support for floating-point data type variants. */
8466 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8468 /* Register numbers of various important registers. */
8469 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8470 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8471 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8472 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8474 /* NOTE: kettenis/20040418: GCC does have two possible register
8475 numbering schemes on the i386: dbx and SVR4. These schemes
8476 differ in how they number %ebp, %esp, %eflags, and the
8477 floating-point registers, and are implemented by the arrays
8478 dbx_register_map[] and svr4_dbx_register_map in
8479 gcc/config/i386.c. GCC also defines a third numbering scheme in
8480 gcc/config/i386.c, which it designates as the "default" register
8481 map used in 64bit mode. This last register numbering scheme is
8482 implemented in dbx64_register_map, and is used for AMD64; see
8485 Currently, each GCC i386 target always uses the same register
8486 numbering scheme across all its supported debugging formats
8487 i.e. SDB (COFF), stabs and DWARF 2. This is because
8488 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8489 DBX_REGISTER_NUMBER macro which is defined by each target's
8490 respective config header in a manner independent of the requested
8491 output debugging format.
8493 This does not match the arrangement below, which presumes that
8494 the SDB and stabs numbering schemes differ from the DWARF and
8495 DWARF 2 ones. The reason for this arrangement is that it is
8496 likely to get the numbering scheme for the target's
8497 default/native debug format right. For targets where GCC is the
8498 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8499 targets where the native toolchain uses a different numbering
8500 scheme for a particular debug format (stabs-in-ELF on Solaris)
8501 the defaults below will have to be overridden, like
8502 i386_elf_init_abi() does. */
8504 /* Use the dbx register numbering scheme for stabs and COFF. */
8505 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8506 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8508 /* Use the SVR4 register numbering scheme for DWARF 2. */
8509 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8511 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8512 be in use on any of the supported i386 targets. */
8514 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8516 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8518 /* Call dummy code. */
8519 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8520 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8521 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8522 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8524 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8525 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8526 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8528 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8530 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8532 /* Stack grows downward. */
8533 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8535 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8536 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8538 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8539 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8541 set_gdbarch_frame_args_skip (gdbarch
, 8);
8543 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8545 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8547 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8549 /* Add the i386 register groups. */
8550 i386_add_reggroups (gdbarch
);
8551 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8553 /* Helper for function argument information. */
8554 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8556 /* Hook the function epilogue frame unwinder. This unwinder is
8557 appended to the list first, so that it supercedes the DWARF
8558 unwinder in function epilogues (where the DWARF unwinder
8559 currently fails). */
8560 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8562 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8563 to the list before the prologue-based unwinders, so that DWARF
8564 CFI info will be used if it is available. */
8565 dwarf2_append_unwinders (gdbarch
);
8567 frame_base_set_default (gdbarch
, &i386_frame_base
);
8569 /* Pseudo registers may be changed by amd64_init_abi. */
8570 set_gdbarch_pseudo_register_read_value (gdbarch
,
8571 i386_pseudo_register_read_value
);
8572 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8573 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8574 i386_ax_pseudo_register_collect
);
8576 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8577 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8579 /* Override the normal target description method to make the AVX
8580 upper halves anonymous. */
8581 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8583 /* Even though the default ABI only includes general-purpose registers,
8584 floating-point registers and the SSE registers, we have to leave a
8585 gap for the upper AVX, MPX and AVX512 registers. */
8586 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8588 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8590 /* Get the x86 target description from INFO. */
8591 tdesc
= info
.target_desc
;
8592 if (! tdesc_has_registers (tdesc
))
8593 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8594 tdep
->tdesc
= tdesc
;
8596 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8597 tdep
->register_names
= i386_register_names
;
8599 /* No upper YMM registers. */
8600 tdep
->ymmh_register_names
= NULL
;
8601 tdep
->ymm0h_regnum
= -1;
8603 /* No upper ZMM registers. */
8604 tdep
->zmmh_register_names
= NULL
;
8605 tdep
->zmm0h_regnum
= -1;
8607 /* No high XMM registers. */
8608 tdep
->xmm_avx512_register_names
= NULL
;
8609 tdep
->xmm16_regnum
= -1;
8611 /* No upper YMM16-31 registers. */
8612 tdep
->ymm16h_register_names
= NULL
;
8613 tdep
->ymm16h_regnum
= -1;
8615 tdep
->num_byte_regs
= 8;
8616 tdep
->num_word_regs
= 8;
8617 tdep
->num_dword_regs
= 0;
8618 tdep
->num_mmx_regs
= 8;
8619 tdep
->num_ymm_regs
= 0;
8621 /* No MPX registers. */
8622 tdep
->bnd0r_regnum
= -1;
8623 tdep
->bndcfgu_regnum
= -1;
8625 /* No AVX512 registers. */
8626 tdep
->k0_regnum
= -1;
8627 tdep
->num_zmm_regs
= 0;
8628 tdep
->num_ymm_avx512_regs
= 0;
8629 tdep
->num_xmm_avx512_regs
= 0;
8631 /* No PKEYS registers */
8632 tdep
->pkru_regnum
= -1;
8633 tdep
->num_pkeys_regs
= 0;
8635 /* No segment base registers. */
8636 tdep
->fsbase_regnum
= -1;
8638 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
8640 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8642 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8644 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8645 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8646 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8648 /* Hook in ABI-specific overrides, if they have been registered.
8649 Note: If INFO specifies a 64 bit arch, this is where we turn
8650 a 32-bit i386 into a 64-bit amd64. */
8651 info
.tdesc_data
= tdesc_data
.get ();
8652 gdbarch_init_osabi (info
, gdbarch
);
8654 if (!i386_validate_tdesc_p (tdep
, tdesc_data
.get ()))
8657 gdbarch_free (gdbarch
);
8661 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8663 /* Wire in pseudo registers. Number of pseudo registers may be
8665 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8666 + tdep
->num_word_regs
8667 + tdep
->num_dword_regs
8668 + tdep
->num_mmx_regs
8669 + tdep
->num_ymm_regs
8671 + tdep
->num_ymm_avx512_regs
8672 + tdep
->num_zmm_regs
));
8674 /* Target description may be changed. */
8675 tdesc
= tdep
->tdesc
;
8677 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8679 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8680 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8682 /* Make %al the first pseudo-register. */
8683 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8684 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8686 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8687 if (tdep
->num_dword_regs
)
8689 /* Support dword pseudo-register if it hasn't been disabled. */
8690 tdep
->eax_regnum
= ymm0_regnum
;
8691 ymm0_regnum
+= tdep
->num_dword_regs
;
8694 tdep
->eax_regnum
= -1;
8696 mm0_regnum
= ymm0_regnum
;
8697 if (tdep
->num_ymm_regs
)
8699 /* Support YMM pseudo-register if it is available. */
8700 tdep
->ymm0_regnum
= ymm0_regnum
;
8701 mm0_regnum
+= tdep
->num_ymm_regs
;
8704 tdep
->ymm0_regnum
= -1;
8706 if (tdep
->num_ymm_avx512_regs
)
8708 /* Support YMM16-31 pseudo registers if available. */
8709 tdep
->ymm16_regnum
= mm0_regnum
;
8710 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8713 tdep
->ymm16_regnum
= -1;
8715 if (tdep
->num_zmm_regs
)
8717 /* Support ZMM pseudo-register if it is available. */
8718 tdep
->zmm0_regnum
= mm0_regnum
;
8719 mm0_regnum
+= tdep
->num_zmm_regs
;
8722 tdep
->zmm0_regnum
= -1;
8724 bnd0_regnum
= mm0_regnum
;
8725 if (tdep
->num_mmx_regs
!= 0)
8727 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8728 tdep
->mm0_regnum
= mm0_regnum
;
8729 bnd0_regnum
+= tdep
->num_mmx_regs
;
8732 tdep
->mm0_regnum
= -1;
8734 if (tdep
->bnd0r_regnum
> 0)
8735 tdep
->bnd0_regnum
= bnd0_regnum
;
8737 tdep
-> bnd0_regnum
= -1;
8739 /* Hook in the legacy prologue-based unwinders last (fallback). */
8740 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8741 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8742 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8744 /* If we have a register mapping, enable the generic core file
8745 support, unless it has already been enabled. */
8746 if (tdep
->gregset_reg_offset
8747 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8748 set_gdbarch_iterate_over_regset_sections
8749 (gdbarch
, i386_iterate_over_regset_sections
);
8751 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8752 i386_fast_tracepoint_valid_at
);
8759 /* Return the target description for a specified XSAVE feature mask. */
8761 const struct target_desc
*
8762 i386_target_description (uint64_t xcr0
, bool segments
)
8764 static target_desc
*i386_tdescs \
8765 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8766 target_desc
**tdesc
;
8768 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8769 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8770 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8771 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8772 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8776 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8781 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8783 /* Find the bound directory base address. */
8785 static unsigned long
8786 i386_mpx_bd_base (void)
8788 struct regcache
*rcache
;
8790 enum register_status regstatus
;
8792 rcache
= get_current_regcache ();
8793 gdbarch
*arch
= rcache
->arch ();
8794 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (arch
);
8796 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8798 if (regstatus
!= REG_VALID
)
8799 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8801 return ret
& MPX_BASE_MASK
;
8805 i386_mpx_enabled (void)
8807 gdbarch
*arch
= get_current_arch ();
8808 i386_gdbarch_tdep
*tdep
= (i386_gdbarch_tdep
*) gdbarch_tdep (arch
);
8809 const struct target_desc
*tdesc
= tdep
->tdesc
;
8811 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8814 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8815 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8816 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8817 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8819 /* Find the bound table entry given the pointer location and the base
8820 address of the table. */
8823 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8827 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8828 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8829 CORE_ADDR bd_entry_addr
;
8832 struct gdbarch
*gdbarch
= get_current_arch ();
8833 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8836 if (gdbarch_ptr_bit (gdbarch
) == 64)
8838 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8839 bd_ptr_r_shift
= 20;
8841 bt_select_r_shift
= 3;
8842 bt_select_l_shift
= 5;
8843 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8845 if ( sizeof (CORE_ADDR
) == 4)
8846 error (_("bound table examination not supported\
8847 for 64-bit process with 32-bit GDB"));
8851 mpx_bd_mask
= MPX_BD_MASK_32
;
8852 bd_ptr_r_shift
= 12;
8854 bt_select_r_shift
= 2;
8855 bt_select_l_shift
= 4;
8856 bt_mask
= MPX_BT_MASK_32
;
8859 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8860 bd_entry_addr
= bd_base
+ offset1
;
8861 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8863 if ((bd_entry
& 0x1) == 0)
8864 error (_("Invalid bounds directory entry at %s."),
8865 paddress (get_current_arch (), bd_entry_addr
));
8867 /* Clearing status bit. */
8869 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8870 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8872 return bt_addr
+ offset2
;
8875 /* Print routine for the mpx bounds. */
8878 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8880 struct ui_out
*uiout
= current_uiout
;
8882 struct gdbarch
*gdbarch
= get_current_arch ();
8883 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8884 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8886 if (bounds_in_map
== 1)
8888 uiout
->text ("Null bounds on map:");
8889 uiout
->text (" pointer value = ");
8890 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8896 uiout
->text ("{lbound = ");
8897 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8898 uiout
->text (", ubound = ");
8900 /* The upper bound is stored in 1's complement. */
8901 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8902 uiout
->text ("}: pointer value = ");
8903 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8905 if (gdbarch_ptr_bit (gdbarch
) == 64)
8906 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8908 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8910 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8911 -1 represents in this sense full memory access, and there is no need
8914 size
= (size
> -1 ? size
+ 1 : size
);
8915 uiout
->text (", size = ");
8916 uiout
->field_string ("size", plongest (size
));
8918 uiout
->text (", metadata = ");
8919 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8924 /* Implement the command "show mpx bound". */
8927 i386_mpx_info_bounds (const char *args
, int from_tty
)
8929 CORE_ADDR bd_base
= 0;
8931 CORE_ADDR bt_entry_addr
= 0;
8932 CORE_ADDR bt_entry
[4];
8934 struct gdbarch
*gdbarch
= get_current_arch ();
8935 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8937 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8938 || !i386_mpx_enabled ())
8940 printf_unfiltered (_("Intel Memory Protection Extensions not "
8941 "supported on this target.\n"));
8947 printf_unfiltered (_("Address of pointer variable expected.\n"));
8951 addr
= parse_and_eval_address (args
);
8953 bd_base
= i386_mpx_bd_base ();
8954 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8956 memset (bt_entry
, 0, sizeof (bt_entry
));
8958 for (i
= 0; i
< 4; i
++)
8959 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8960 + i
* TYPE_LENGTH (data_ptr_type
),
8963 i386_mpx_print_bounds (bt_entry
);
8966 /* Implement the command "set mpx bound". */
8969 i386_mpx_set_bounds (const char *args
, int from_tty
)
8971 CORE_ADDR bd_base
= 0;
8972 CORE_ADDR addr
, lower
, upper
;
8973 CORE_ADDR bt_entry_addr
= 0;
8974 CORE_ADDR bt_entry
[2];
8975 const char *input
= args
;
8977 struct gdbarch
*gdbarch
= get_current_arch ();
8978 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8979 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8981 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8982 || !i386_mpx_enabled ())
8983 error (_("Intel Memory Protection Extensions not supported\
8987 error (_("Pointer value expected."));
8989 addr
= value_as_address (parse_to_comma_and_eval (&input
));
8991 if (input
[0] == ',')
8993 if (input
[0] == '\0')
8994 error (_("wrong number of arguments: missing lower and upper bound."));
8995 lower
= value_as_address (parse_to_comma_and_eval (&input
));
8997 if (input
[0] == ',')
8999 if (input
[0] == '\0')
9000 error (_("Wrong number of arguments; Missing upper bound."));
9001 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9003 bd_base
= i386_mpx_bd_base ();
9004 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9005 for (i
= 0; i
< 2; i
++)
9006 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9007 + i
* TYPE_LENGTH (data_ptr_type
),
9009 bt_entry
[0] = (uint64_t) lower
;
9010 bt_entry
[1] = ~(uint64_t) upper
;
9012 for (i
= 0; i
< 2; i
++)
9013 write_memory_unsigned_integer (bt_entry_addr
9014 + i
* TYPE_LENGTH (data_ptr_type
),
9015 TYPE_LENGTH (data_ptr_type
), byte_order
,
9019 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9021 void _initialize_i386_tdep ();
9023 _initialize_i386_tdep ()
9025 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
9027 /* Add the variable that controls the disassembly flavor. */
9028 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9029 &disassembly_flavor
, _("\
9030 Set the disassembly flavor."), _("\
9031 Show the disassembly flavor."), _("\
9032 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9034 NULL
, /* FIXME: i18n: */
9035 &setlist
, &showlist
);
9037 /* Add the variable that controls the convention for returning
9039 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9040 &struct_convention
, _("\
9041 Set the convention for returning small structs."), _("\
9042 Show the convention for returning small structs."), _("\
9043 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9046 NULL
, /* FIXME: i18n: */
9047 &setlist
, &showlist
);
9049 /* Add "mpx" prefix for the set and show commands. */
9051 add_setshow_prefix_cmd
9052 ("mpx", class_support
,
9053 _("Set Intel Memory Protection Extensions specific variables."),
9054 _("Show Intel Memory Protection Extensions specific variables."),
9055 &mpx_set_cmdlist
, &mpx_show_cmdlist
, &setlist
, &showlist
);
9057 /* Add "bound" command for the show mpx commands list. */
9059 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9060 "Show the memory bounds for a given array/pointer storage\
9061 in the bound table.",
9064 /* Add "bound" command for the set mpx commands list. */
9066 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9067 "Set the memory bounds for a given array/pointer storage\
9068 in the bound table.",
9071 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9072 i386_svr4_init_abi
);
9074 /* Initialize the i386-specific register groups. */
9075 i386_init_reggroups ();
9077 /* Tell remote stub that we support XML target description. */
9078 register_remote_support_xml ("i386");