1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
54 #include "record-full.h"
55 #include "target-descriptions.h"
56 #include "arch/i386.h"
61 #include "stap-probe.h"
62 #include "user-regs.h"
63 #include "cli/cli-utils.h"
64 #include "expression.h"
65 #include "parser-defs.h"
68 #include <unordered_set>
73 static const char * const i386_register_names
[] =
75 "eax", "ecx", "edx", "ebx",
76 "esp", "ebp", "esi", "edi",
77 "eip", "eflags", "cs", "ss",
78 "ds", "es", "fs", "gs",
79 "st0", "st1", "st2", "st3",
80 "st4", "st5", "st6", "st7",
81 "fctrl", "fstat", "ftag", "fiseg",
82 "fioff", "foseg", "fooff", "fop",
83 "xmm0", "xmm1", "xmm2", "xmm3",
84 "xmm4", "xmm5", "xmm6", "xmm7",
88 static const char * const i386_zmm_names
[] =
90 "zmm0", "zmm1", "zmm2", "zmm3",
91 "zmm4", "zmm5", "zmm6", "zmm7"
94 static const char * const i386_zmmh_names
[] =
96 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
97 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
100 static const char * const i386_k_names
[] =
102 "k0", "k1", "k2", "k3",
103 "k4", "k5", "k6", "k7"
106 static const char * const i386_ymm_names
[] =
108 "ymm0", "ymm1", "ymm2", "ymm3",
109 "ymm4", "ymm5", "ymm6", "ymm7",
112 static const char * const i386_ymmh_names
[] =
114 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
115 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
118 static const char * const i386_mpx_names
[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 static const char * const i386_pkeys_names
[] =
128 /* Register names for MPX pseudo-registers. */
130 static const char * const i386_bnd_names
[] =
132 "bnd0", "bnd1", "bnd2", "bnd3"
135 /* Register names for MMX pseudo-registers. */
137 static const char * const i386_mmx_names
[] =
139 "mm0", "mm1", "mm2", "mm3",
140 "mm4", "mm5", "mm6", "mm7"
143 /* Register names for byte pseudo-registers. */
145 static const char * const i386_byte_names
[] =
147 "al", "cl", "dl", "bl",
148 "ah", "ch", "dh", "bh"
151 /* Register names for word pseudo-registers. */
153 static const char * const i386_word_names
[] =
155 "ax", "cx", "dx", "bx",
159 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
160 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
161 we have 16 upper ZMM regs that have to be handled differently. */
163 const int num_lower_zmm_regs
= 16;
168 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 int mm0_regnum
= tdep
->mm0_regnum
;
176 regnum
-= mm0_regnum
;
177 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
183 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 regnum
-= tdep
->al_regnum
;
188 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
194 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
196 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
198 regnum
-= tdep
->ax_regnum
;
199 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
202 /* Dword register? */
205 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
208 int eax_regnum
= tdep
->eax_regnum
;
213 regnum
-= eax_regnum
;
214 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
217 /* AVX512 register? */
220 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
223 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
225 if (zmm0h_regnum
< 0)
228 regnum
-= zmm0h_regnum
;
229 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
233 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
236 int zmm0_regnum
= tdep
->zmm0_regnum
;
241 regnum
-= zmm0_regnum
;
242 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
246 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 int k0_regnum
= tdep
->k0_regnum
;
255 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
259 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
261 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
262 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
264 if (ymm0h_regnum
< 0)
267 regnum
-= ymm0h_regnum
;
268 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
274 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
277 int ymm0_regnum
= tdep
->ymm0_regnum
;
282 regnum
-= ymm0_regnum
;
283 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
287 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
290 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
292 if (ymm16h_regnum
< 0)
295 regnum
-= ymm16h_regnum
;
296 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
300 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
303 int ymm16_regnum
= tdep
->ymm16_regnum
;
305 if (ymm16_regnum
< 0)
308 regnum
-= ymm16_regnum
;
309 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
315 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
318 int bnd0_regnum
= tdep
->bnd0_regnum
;
323 regnum
-= bnd0_regnum
;
324 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
330 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
333 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
335 if (num_xmm_regs
== 0)
338 regnum
-= I387_XMM0_REGNUM (tdep
);
339 return regnum
>= 0 && regnum
< num_xmm_regs
;
342 /* XMM_512 register? */
345 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
348 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
350 if (num_xmm_avx512_regs
== 0)
353 regnum
-= I387_XMM16_REGNUM (tdep
);
354 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
358 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
360 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
362 if (I387_NUM_XMM_REGS (tdep
) == 0)
365 return (regnum
== I387_MXCSR_REGNUM (tdep
));
371 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
373 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
375 if (I387_ST0_REGNUM (tdep
) < 0)
378 return (I387_ST0_REGNUM (tdep
) <= regnum
379 && regnum
< I387_FCTRL_REGNUM (tdep
));
383 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
385 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
387 if (I387_ST0_REGNUM (tdep
) < 0)
390 return (I387_FCTRL_REGNUM (tdep
) <= regnum
391 && regnum
< I387_XMM0_REGNUM (tdep
));
394 /* BNDr (raw) register? */
397 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
401 if (I387_BND0R_REGNUM (tdep
) < 0)
404 regnum
-= tdep
->bnd0r_regnum
;
405 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
408 /* BND control register? */
411 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
415 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
418 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
419 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
425 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
427 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
428 int pkru_regnum
= tdep
->pkru_regnum
;
433 regnum
-= pkru_regnum
;
434 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
437 /* Return the name of register REGNUM, or the empty string if it is
438 an anonymous register. */
441 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
443 /* Hide the upper YMM registers. */
444 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
447 /* Hide the upper YMM16-31 registers. */
448 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
451 /* Hide the upper ZMM registers. */
452 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
455 return tdesc_register_name (gdbarch
, regnum
);
458 /* Return the name of register REGNUM. */
461 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
464 if (i386_bnd_regnum_p (gdbarch
, regnum
))
465 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
466 if (i386_mmx_regnum_p (gdbarch
, regnum
))
467 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
468 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
469 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
470 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
471 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
472 else if (i386_byte_regnum_p (gdbarch
, regnum
))
473 return i386_byte_names
[regnum
- tdep
->al_regnum
];
474 else if (i386_word_regnum_p (gdbarch
, regnum
))
475 return i386_word_names
[regnum
- tdep
->ax_regnum
];
477 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
480 /* Convert a dbx register number REG to the appropriate register
481 number used by GDB. */
484 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
486 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
488 /* This implements what GCC calls the "default" register map
489 (dbx_register_map[]). */
491 if (reg
>= 0 && reg
<= 7)
493 /* General-purpose registers. The debug info calls %ebp
494 register 4, and %esp register 5. */
501 else if (reg
>= 12 && reg
<= 19)
503 /* Floating-point registers. */
504 return reg
- 12 + I387_ST0_REGNUM (tdep
);
506 else if (reg
>= 21 && reg
<= 28)
509 int ymm0_regnum
= tdep
->ymm0_regnum
;
512 && i386_xmm_regnum_p (gdbarch
, reg
))
513 return reg
- 21 + ymm0_regnum
;
515 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
517 else if (reg
>= 29 && reg
<= 36)
520 return reg
- 29 + I387_MM0_REGNUM (tdep
);
523 /* This will hopefully provoke a warning. */
524 return gdbarch_num_cooked_regs (gdbarch
);
527 /* Convert SVR4 DWARF register number REG to the appropriate register number
531 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
535 /* This implements the GCC register map that tries to be compatible
536 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
538 /* The SVR4 register numbering includes %eip and %eflags, and
539 numbers the floating point registers differently. */
540 if (reg
>= 0 && reg
<= 9)
542 /* General-purpose registers. */
545 else if (reg
>= 11 && reg
<= 18)
547 /* Floating-point registers. */
548 return reg
- 11 + I387_ST0_REGNUM (tdep
);
550 else if (reg
>= 21 && reg
<= 36)
552 /* The SSE and MMX registers have the same numbers as with dbx. */
553 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
558 case 37: return I387_FCTRL_REGNUM (tdep
);
559 case 38: return I387_FSTAT_REGNUM (tdep
);
560 case 39: return I387_MXCSR_REGNUM (tdep
);
561 case 40: return I386_ES_REGNUM
;
562 case 41: return I386_CS_REGNUM
;
563 case 42: return I386_SS_REGNUM
;
564 case 43: return I386_DS_REGNUM
;
565 case 44: return I386_FS_REGNUM
;
566 case 45: return I386_GS_REGNUM
;
572 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
573 num_regs + num_pseudo_regs for other debug formats. */
576 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
578 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
581 return gdbarch_num_cooked_regs (gdbarch
);
587 /* This is the variable that is set with "set disassembly-flavor", and
588 its legitimate values. */
589 static const char att_flavor
[] = "att";
590 static const char intel_flavor
[] = "intel";
591 static const char *const valid_flavors
[] =
597 static const char *disassembly_flavor
= att_flavor
;
600 /* Use the program counter to determine the contents and size of a
601 breakpoint instruction. Return a pointer to a string of bytes that
602 encode a breakpoint instruction, store the length of the string in
603 *LEN and optionally adjust *PC to point to the correct memory
604 location for inserting the breakpoint.
606 On the i386 we have a single breakpoint that fits in a single byte
607 and can be inserted anywhere.
609 This function is 64-bit safe. */
611 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
613 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
616 /* Displaced instruction handling. */
618 /* Skip the legacy instruction prefixes in INSN.
619 Not all prefixes are valid for any particular insn
620 but we needn't care, the insn will fault if it's invalid.
621 The result is a pointer to the first opcode byte,
622 or NULL if we run off the end of the buffer. */
625 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
627 gdb_byte
*end
= insn
+ max_len
;
633 case DATA_PREFIX_OPCODE
:
634 case ADDR_PREFIX_OPCODE
:
635 case CS_PREFIX_OPCODE
:
636 case DS_PREFIX_OPCODE
:
637 case ES_PREFIX_OPCODE
:
638 case FS_PREFIX_OPCODE
:
639 case GS_PREFIX_OPCODE
:
640 case SS_PREFIX_OPCODE
:
641 case LOCK_PREFIX_OPCODE
:
642 case REPE_PREFIX_OPCODE
:
643 case REPNE_PREFIX_OPCODE
:
655 i386_absolute_jmp_p (const gdb_byte
*insn
)
657 /* jmp far (absolute address in operand). */
663 /* jump near, absolute indirect (/4). */
664 if ((insn
[1] & 0x38) == 0x20)
667 /* jump far, absolute indirect (/5). */
668 if ((insn
[1] & 0x38) == 0x28)
675 /* Return non-zero if INSN is a jump, zero otherwise. */
678 i386_jmp_p (const gdb_byte
*insn
)
680 /* jump short, relative. */
684 /* jump near, relative. */
688 return i386_absolute_jmp_p (insn
);
692 i386_absolute_call_p (const gdb_byte
*insn
)
694 /* call far, absolute. */
700 /* Call near, absolute indirect (/2). */
701 if ((insn
[1] & 0x38) == 0x10)
704 /* Call far, absolute indirect (/3). */
705 if ((insn
[1] & 0x38) == 0x18)
713 i386_ret_p (const gdb_byte
*insn
)
717 case 0xc2: /* ret near, pop N bytes. */
718 case 0xc3: /* ret near */
719 case 0xca: /* ret far, pop N bytes. */
720 case 0xcb: /* ret far */
721 case 0xcf: /* iret */
730 i386_call_p (const gdb_byte
*insn
)
732 if (i386_absolute_call_p (insn
))
735 /* call near, relative. */
742 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
743 length in bytes. Otherwise, return zero. */
746 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
748 /* Is it 'int $0x80'? */
749 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
750 /* Or is it 'sysenter'? */
751 || (insn
[0] == 0x0f && insn
[1] == 0x34)
752 /* Or is it 'syscall'? */
753 || (insn
[0] == 0x0f && insn
[1] == 0x05))
762 /* The gdbarch insn_is_call method. */
765 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
767 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
769 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
770 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
772 return i386_call_p (insn
);
775 /* The gdbarch insn_is_ret method. */
778 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
780 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
782 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
783 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
785 return i386_ret_p (insn
);
788 /* The gdbarch insn_is_jump method. */
791 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
793 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
795 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
796 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
798 return i386_jmp_p (insn
);
801 /* Some kernels may run one past a syscall insn, so we have to cope. */
803 displaced_step_copy_insn_closure_up
804 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
805 CORE_ADDR from
, CORE_ADDR to
,
806 struct regcache
*regs
)
808 size_t len
= gdbarch_max_insn_length (gdbarch
);
809 std::unique_ptr
<i386_displaced_step_copy_insn_closure
> closure
810 (new i386_displaced_step_copy_insn_closure (len
));
811 gdb_byte
*buf
= closure
->buf
.data ();
813 read_memory (from
, buf
, len
);
815 /* GDB may get control back after the insn after the syscall.
816 Presumably this is a kernel bug.
817 If this is a syscall, make sure there's a nop afterwards. */
822 insn
= i386_skip_prefixes (buf
, len
);
823 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
824 insn
[syscall_length
] = NOP_OPCODE
;
827 write_memory (to
, buf
, len
);
829 displaced_debug_printf ("%s->%s: %s",
830 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
831 displaced_step_dump_bytes (buf
, len
).c_str ());
833 /* This is a work around for a problem with g++ 4.8. */
834 return displaced_step_copy_insn_closure_up (closure
.release ());
837 /* Fix up the state of registers and memory after having single-stepped
838 a displaced instruction. */
841 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
842 struct displaced_step_copy_insn_closure
*closure_
,
843 CORE_ADDR from
, CORE_ADDR to
,
844 struct regcache
*regs
)
846 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
848 /* The offset we applied to the instruction's address.
849 This could well be negative (when viewed as a signed 32-bit
850 value), but ULONGEST won't reflect that, so take care when
852 ULONGEST insn_offset
= to
- from
;
854 i386_displaced_step_copy_insn_closure
*closure
855 = (i386_displaced_step_copy_insn_closure
*) closure_
;
856 gdb_byte
*insn
= closure
->buf
.data ();
857 /* The start of the insn, needed in case we see some prefixes. */
858 gdb_byte
*insn_start
= insn
;
860 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
861 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
864 /* The list of issues to contend with here is taken from
865 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
866 Yay for Free Software! */
868 /* Relocate the %eip, if necessary. */
870 /* The instruction recognizers we use assume any leading prefixes
871 have been skipped. */
873 /* This is the size of the buffer in closure. */
874 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
875 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
876 /* If there are too many prefixes, just ignore the insn.
877 It will fault when run. */
882 /* Except in the case of absolute or indirect jump or call
883 instructions, or a return instruction, the new eip is relative to
884 the displaced instruction; make it relative. Well, signal
885 handler returns don't need relocation either, but we use the
886 value of %eip to recognize those; see below. */
887 if (! i386_absolute_jmp_p (insn
)
888 && ! i386_absolute_call_p (insn
)
889 && ! i386_ret_p (insn
))
894 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
896 /* A signal trampoline system call changes the %eip, resuming
897 execution of the main program after the signal handler has
898 returned. That makes them like 'return' instructions; we
899 shouldn't relocate %eip.
901 But most system calls don't, and we do need to relocate %eip.
903 Our heuristic for distinguishing these cases: if stepping
904 over the system call instruction left control directly after
905 the instruction, the we relocate --- control almost certainly
906 doesn't belong in the displaced copy. Otherwise, we assume
907 the instruction has put control where it belongs, and leave
908 it unrelocated. Goodness help us if there are PC-relative
910 if (i386_syscall_p (insn
, &insn_len
)
911 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
912 /* GDB can get control back after the insn after the syscall.
913 Presumably this is a kernel bug.
914 i386_displaced_step_copy_insn ensures its a nop,
915 we add one to the length for it. */
916 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
917 displaced_debug_printf ("syscall changed %%eip; not relocating");
920 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
922 /* If we just stepped over a breakpoint insn, we don't backup
923 the pc on purpose; this is to match behaviour without
926 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
928 displaced_debug_printf ("relocated %%eip from %s to %s",
929 paddress (gdbarch
, orig_eip
),
930 paddress (gdbarch
, eip
));
934 /* If the instruction was PUSHFL, then the TF bit will be set in the
935 pushed value, and should be cleared. We'll leave this for later,
936 since GDB already messes up the TF flag when stepping over a
939 /* If the instruction was a call, the return address now atop the
940 stack is the address following the copied instruction. We need
941 to make it the address following the original instruction. */
942 if (i386_call_p (insn
))
946 const ULONGEST retaddr_len
= 4;
948 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
949 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
950 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
951 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
953 displaced_debug_printf ("relocated return addr at %s to %s",
954 paddress (gdbarch
, esp
),
955 paddress (gdbarch
, retaddr
));
960 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
962 target_write_memory (*to
, buf
, len
);
967 i386_relocate_instruction (struct gdbarch
*gdbarch
,
968 CORE_ADDR
*to
, CORE_ADDR oldloc
)
970 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
971 gdb_byte buf
[I386_MAX_INSN_LEN
];
972 int offset
= 0, rel32
, newrel
;
974 gdb_byte
*insn
= buf
;
976 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
978 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
979 I386_MAX_INSN_LEN
, oldloc
);
981 /* Get past the prefixes. */
982 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
984 /* Adjust calls with 32-bit relative addresses as push/jump, with
985 the address pushed being the location where the original call in
986 the user program would return to. */
989 gdb_byte push_buf
[16];
990 unsigned int ret_addr
;
992 /* Where "ret" in the original code will return to. */
993 ret_addr
= oldloc
+ insn_length
;
994 push_buf
[0] = 0x68; /* pushq $... */
995 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
997 append_insns (to
, 5, push_buf
);
999 /* Convert the relative call to a relative jump. */
1002 /* Adjust the destination offset. */
1003 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1004 newrel
= (oldloc
- *to
) + rel32
;
1005 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1007 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1008 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1009 hex_string (newrel
), paddress (gdbarch
, *to
));
1011 /* Write the adjusted jump into its displaced location. */
1012 append_insns (to
, 5, insn
);
1016 /* Adjust jumps with 32-bit relative addresses. Calls are already
1018 if (insn
[0] == 0xe9)
1020 /* Adjust conditional jumps. */
1021 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1026 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1027 newrel
= (oldloc
- *to
) + rel32
;
1028 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1029 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1030 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1031 hex_string (newrel
), paddress (gdbarch
, *to
));
1034 /* Write the adjusted instructions into their displaced
1036 append_insns (to
, insn_length
, buf
);
1040 #ifdef I386_REGNO_TO_SYMMETRY
1041 #error "The Sequent Symmetry is no longer supported."
1044 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1045 and %esp "belong" to the calling function. Therefore these
1046 registers should be saved if they're going to be modified. */
1048 /* The maximum number of saved registers. This should include all
1049 registers mentioned above, and %eip. */
1050 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1052 struct i386_frame_cache
1060 /* Saved registers. */
1061 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1066 /* Stack space reserved for local variables. */
1070 /* Allocate and initialize a frame cache. */
1072 static struct i386_frame_cache
*
1073 i386_alloc_frame_cache (void)
1075 struct i386_frame_cache
*cache
;
1078 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1083 cache
->sp_offset
= -4;
1086 /* Saved registers. We initialize these to -1 since zero is a valid
1087 offset (that's where %ebp is supposed to be stored). */
1088 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1089 cache
->saved_regs
[i
] = -1;
1090 cache
->saved_sp
= 0;
1091 cache
->saved_sp_reg
= -1;
1092 cache
->pc_in_eax
= 0;
1094 /* Frameless until proven otherwise. */
1100 /* If the instruction at PC is a jump, return the address of its
1101 target. Otherwise, return PC. */
1104 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1106 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1111 if (target_read_code (pc
, &op
, 1))
1118 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1124 /* Relative jump: if data16 == 0, disp32, else disp16. */
1127 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1129 /* Include the size of the jmp instruction (including the
1135 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1137 /* Include the size of the jmp instruction. */
1142 /* Relative jump, disp8 (ignore data16). */
1143 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1145 delta
+= data16
+ 2;
1152 /* Check whether PC points at a prologue for a function returning a
1153 structure or union. If so, it updates CACHE and returns the
1154 address of the first instruction after the code sequence that
1155 removes the "hidden" argument from the stack or CURRENT_PC,
1156 whichever is smaller. Otherwise, return PC. */
1159 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1160 struct i386_frame_cache
*cache
)
1162 /* Functions that return a structure or union start with:
1165 xchgl %eax, (%esp) 0x87 0x04 0x24
1166 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1168 (the System V compiler puts out the second `xchg' instruction,
1169 and the assembler doesn't try to optimize it, so the 'sib' form
1170 gets generated). This sequence is used to get the address of the
1171 return buffer for a function that returns a structure. */
1172 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1173 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1177 if (current_pc
<= pc
)
1180 if (target_read_code (pc
, &op
, 1))
1183 if (op
!= 0x58) /* popl %eax */
1186 if (target_read_code (pc
+ 1, buf
, 4))
1189 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1192 if (current_pc
== pc
)
1194 cache
->sp_offset
+= 4;
1198 if (current_pc
== pc
+ 1)
1200 cache
->pc_in_eax
= 1;
1204 if (buf
[1] == proto1
[1])
1211 i386_skip_probe (CORE_ADDR pc
)
1213 /* A function may start with
1227 if (target_read_code (pc
, &op
, 1))
1230 if (op
== 0x68 || op
== 0x6a)
1234 /* Skip past the `pushl' instruction; it has either a one-byte or a
1235 four-byte operand, depending on the opcode. */
1241 /* Read the following 8 bytes, which should be `call _probe' (6
1242 bytes) followed by `addl $4,%esp' (2 bytes). */
1243 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1244 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1245 pc
+= delta
+ sizeof (buf
);
1251 /* GCC 4.1 and later, can put code in the prologue to realign the
1252 stack pointer. Check whether PC points to such code, and update
1253 CACHE accordingly. Return the first instruction after the code
1254 sequence or CURRENT_PC, whichever is smaller. If we don't
1255 recognize the code, return PC. */
1258 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1259 struct i386_frame_cache
*cache
)
1261 /* There are 2 code sequences to re-align stack before the frame
1264 1. Use a caller-saved saved register:
1270 2. Use a callee-saved saved register:
1277 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1279 0x83 0xe4 0xf0 andl $-16, %esp
1280 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1285 int offset
, offset_and
;
1286 static int regnums
[8] = {
1287 I386_EAX_REGNUM
, /* %eax */
1288 I386_ECX_REGNUM
, /* %ecx */
1289 I386_EDX_REGNUM
, /* %edx */
1290 I386_EBX_REGNUM
, /* %ebx */
1291 I386_ESP_REGNUM
, /* %esp */
1292 I386_EBP_REGNUM
, /* %ebp */
1293 I386_ESI_REGNUM
, /* %esi */
1294 I386_EDI_REGNUM
/* %edi */
1297 if (target_read_code (pc
, buf
, sizeof buf
))
1300 /* Check caller-saved saved register. The first instruction has
1301 to be "leal 4(%esp), %reg". */
1302 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1304 /* MOD must be binary 10 and R/M must be binary 100. */
1305 if ((buf
[1] & 0xc7) != 0x44)
1308 /* REG has register number. */
1309 reg
= (buf
[1] >> 3) & 7;
1314 /* Check callee-saved saved register. The first instruction
1315 has to be "pushl %reg". */
1316 if ((buf
[0] & 0xf8) != 0x50)
1322 /* The next instruction has to be "leal 8(%esp), %reg". */
1323 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1326 /* MOD must be binary 10 and R/M must be binary 100. */
1327 if ((buf
[2] & 0xc7) != 0x44)
1330 /* REG has register number. Registers in pushl and leal have to
1332 if (reg
!= ((buf
[2] >> 3) & 7))
1338 /* Rigister can't be %esp nor %ebp. */
1339 if (reg
== 4 || reg
== 5)
1342 /* The next instruction has to be "andl $-XXX, %esp". */
1343 if (buf
[offset
+ 1] != 0xe4
1344 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1347 offset_and
= offset
;
1348 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1350 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1351 0xfc. REG must be binary 110 and MOD must be binary 01. */
1352 if (buf
[offset
] != 0xff
1353 || buf
[offset
+ 2] != 0xfc
1354 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1357 /* R/M has register. Registers in leal and pushl have to be the
1359 if (reg
!= (buf
[offset
+ 1] & 7))
1362 if (current_pc
> pc
+ offset_and
)
1363 cache
->saved_sp_reg
= regnums
[reg
];
1365 return std::min (pc
+ offset
+ 3, current_pc
);
1368 /* Maximum instruction length we need to handle. */
1369 #define I386_MAX_MATCHED_INSN_LEN 6
1371 /* Instruction description. */
1375 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1376 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1379 /* Return whether instruction at PC matches PATTERN. */
1382 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1386 if (target_read_code (pc
, &op
, 1))
1389 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1391 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1392 int insn_matched
= 1;
1395 gdb_assert (pattern
.len
> 1);
1396 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1398 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1401 for (i
= 1; i
< pattern
.len
; i
++)
1403 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1406 return insn_matched
;
1411 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1412 the first instruction description that matches. Otherwise, return
1415 static struct i386_insn
*
1416 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1418 struct i386_insn
*pattern
;
1420 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1422 if (i386_match_pattern (pc
, *pattern
))
1429 /* Return whether PC points inside a sequence of instructions that
1430 matches INSN_PATTERNS. */
1433 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1435 CORE_ADDR current_pc
;
1437 struct i386_insn
*insn
;
1439 insn
= i386_match_insn (pc
, insn_patterns
);
1444 ix
= insn
- insn_patterns
;
1445 for (i
= ix
- 1; i
>= 0; i
--)
1447 current_pc
-= insn_patterns
[i
].len
;
1449 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1453 current_pc
= pc
+ insn
->len
;
1454 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1456 if (!i386_match_pattern (current_pc
, *insn
))
1459 current_pc
+= insn
->len
;
1465 /* Some special instructions that might be migrated by GCC into the
1466 part of the prologue that sets up the new stack frame. Because the
1467 stack frame hasn't been setup yet, no registers have been saved
1468 yet, and only the scratch registers %eax, %ecx and %edx can be
1471 static i386_insn i386_frame_setup_skip_insns
[] =
1473 /* Check for `movb imm8, r' and `movl imm32, r'.
1475 ??? Should we handle 16-bit operand-sizes here? */
1477 /* `movb imm8, %al' and `movb imm8, %ah' */
1478 /* `movb imm8, %cl' and `movb imm8, %ch' */
1479 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1480 /* `movb imm8, %dl' and `movb imm8, %dh' */
1481 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1482 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1483 { 5, { 0xb8 }, { 0xfe } },
1484 /* `movl imm32, %edx' */
1485 { 5, { 0xba }, { 0xff } },
1487 /* Check for `mov imm32, r32'. Note that there is an alternative
1488 encoding for `mov m32, %eax'.
1490 ??? Should we handle SIB addressing here?
1491 ??? Should we handle 16-bit operand-sizes here? */
1493 /* `movl m32, %eax' */
1494 { 5, { 0xa1 }, { 0xff } },
1495 /* `movl m32, %eax' and `mov; m32, %ecx' */
1496 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1497 /* `movl m32, %edx' */
1498 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1500 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1501 Because of the symmetry, there are actually two ways to encode
1502 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1503 opcode bytes 0x31 and 0x33 for `xorl'. */
1505 /* `subl %eax, %eax' */
1506 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1507 /* `subl %ecx, %ecx' */
1508 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1509 /* `subl %edx, %edx' */
1510 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1511 /* `xorl %eax, %eax' */
1512 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1513 /* `xorl %ecx, %ecx' */
1514 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1515 /* `xorl %edx, %edx' */
1516 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1520 /* Check whether PC points to an endbr32 instruction. */
1522 i386_skip_endbr (CORE_ADDR pc
)
1524 static const gdb_byte endbr32
[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1526 gdb_byte buf
[sizeof (endbr32
)];
1528 /* Stop there if we can't read the code */
1529 if (target_read_code (pc
, buf
, sizeof (endbr32
)))
1532 /* If the instruction isn't an endbr32, stop */
1533 if (memcmp (buf
, endbr32
, sizeof (endbr32
)) != 0)
1536 return pc
+ sizeof (endbr32
);
1539 /* Check whether PC points to a no-op instruction. */
1541 i386_skip_noop (CORE_ADDR pc
)
1546 if (target_read_code (pc
, &op
, 1))
1552 /* Ignore `nop' instruction. */
1556 if (target_read_code (pc
, &op
, 1))
1560 /* Ignore no-op instruction `mov %edi, %edi'.
1561 Microsoft system dlls often start with
1562 a `mov %edi,%edi' instruction.
1563 The 5 bytes before the function start are
1564 filled with `nop' instructions.
1565 This pattern can be used for hot-patching:
1566 The `mov %edi, %edi' instruction can be replaced by a
1567 near jump to the location of the 5 `nop' instructions
1568 which can be replaced by a 32-bit jump to anywhere
1569 in the 32-bit address space. */
1571 else if (op
== 0x8b)
1573 if (target_read_code (pc
+ 1, &op
, 1))
1579 if (target_read_code (pc
, &op
, 1))
1589 /* Check whether PC points at a code that sets up a new stack frame.
1590 If so, it updates CACHE and returns the address of the first
1591 instruction after the sequence that sets up the frame or LIMIT,
1592 whichever is smaller. If we don't recognize the code, return PC. */
1595 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1596 CORE_ADDR pc
, CORE_ADDR limit
,
1597 struct i386_frame_cache
*cache
)
1599 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1600 struct i386_insn
*insn
;
1607 if (target_read_code (pc
, &op
, 1))
1610 if (op
== 0x55) /* pushl %ebp */
1612 /* Take into account that we've executed the `pushl %ebp' that
1613 starts this instruction sequence. */
1614 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1615 cache
->sp_offset
+= 4;
1618 /* If that's all, return now. */
1622 /* Check for some special instructions that might be migrated by
1623 GCC into the prologue and skip them. At this point in the
1624 prologue, code should only touch the scratch registers %eax,
1625 %ecx and %edx, so while the number of possibilities is sheer,
1628 Make sure we only skip these instructions if we later see the
1629 `movl %esp, %ebp' that actually sets up the frame. */
1630 while (pc
+ skip
< limit
)
1632 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1639 /* If that's all, return now. */
1640 if (limit
<= pc
+ skip
)
1643 if (target_read_code (pc
+ skip
, &op
, 1))
1646 /* The i386 prologue looks like
1652 and a different prologue can be generated for atom.
1656 lea -0x10(%esp),%esp
1658 We handle both of them here. */
1662 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1664 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1670 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1675 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1676 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1685 /* OK, we actually have a frame. We just don't know how large
1686 it is yet. Set its size to zero. We'll adjust it if
1687 necessary. We also now commit to skipping the special
1688 instructions mentioned before. */
1691 /* If that's all, return now. */
1695 /* Check for stack adjustment
1701 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1702 reg, so we don't have to worry about a data16 prefix. */
1703 if (target_read_code (pc
, &op
, 1))
1707 /* `subl' with 8-bit immediate. */
1708 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1709 /* Some instruction starting with 0x83 other than `subl'. */
1712 /* `subl' with signed 8-bit immediate (though it wouldn't
1713 make sense to be negative). */
1714 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1717 else if (op
== 0x81)
1719 /* Maybe it is `subl' with a 32-bit immediate. */
1720 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1721 /* Some instruction starting with 0x81 other than `subl'. */
1724 /* It is `subl' with a 32-bit immediate. */
1725 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1728 else if (op
== 0x8d)
1730 /* The ModR/M byte is 0x64. */
1731 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1733 /* 'lea' with 8-bit displacement. */
1734 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1739 /* Some instruction other than `subl' nor 'lea'. */
1743 else if (op
== 0xc8) /* enter */
1745 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1752 /* Check whether PC points at code that saves registers on the stack.
1753 If so, it updates CACHE and returns the address of the first
1754 instruction after the register saves or CURRENT_PC, whichever is
1755 smaller. Otherwise, return PC. */
1758 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1759 struct i386_frame_cache
*cache
)
1761 CORE_ADDR offset
= 0;
1765 if (cache
->locals
> 0)
1766 offset
-= cache
->locals
;
1767 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1769 if (target_read_code (pc
, &op
, 1))
1771 if (op
< 0x50 || op
> 0x57)
1775 cache
->saved_regs
[op
- 0x50] = offset
;
1776 cache
->sp_offset
+= 4;
1783 /* Do a full analysis of the prologue at PC and update CACHE
1784 accordingly. Bail out early if CURRENT_PC is reached. Return the
1785 address where the analysis stopped.
1787 We handle these cases:
1789 The startup sequence can be at the start of the function, or the
1790 function can start with a branch to startup code at the end.
1792 %ebp can be set up with either the 'enter' instruction, or "pushl
1793 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1794 once used in the System V compiler).
1796 Local space is allocated just below the saved %ebp by either the
1797 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1798 16-bit unsigned argument for space to allocate, and the 'addl'
1799 instruction could have either a signed byte, or 32-bit immediate.
1801 Next, the registers used by this function are pushed. With the
1802 System V compiler they will always be in the order: %edi, %esi,
1803 %ebx (and sometimes a harmless bug causes it to also save but not
1804 restore %eax); however, the code below is willing to see the pushes
1805 in any order, and will handle up to 8 of them.
1807 If the setup sequence is at the end of the function, then the next
1808 instruction will be a branch back to the start. */
1811 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1812 CORE_ADDR pc
, CORE_ADDR current_pc
,
1813 struct i386_frame_cache
*cache
)
1815 pc
= i386_skip_endbr (pc
);
1816 pc
= i386_skip_noop (pc
);
1817 pc
= i386_follow_jump (gdbarch
, pc
);
1818 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1819 pc
= i386_skip_probe (pc
);
1820 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1821 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1822 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1825 /* Return PC of first real instruction. */
1828 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1830 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1832 static gdb_byte pic_pat
[6] =
1834 0xe8, 0, 0, 0, 0, /* call 0x0 */
1835 0x5b, /* popl %ebx */
1837 struct i386_frame_cache cache
;
1841 CORE_ADDR func_addr
;
1843 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1845 CORE_ADDR post_prologue_pc
1846 = skip_prologue_using_sal (gdbarch
, func_addr
);
1847 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1849 /* LLVM backend (Clang/Flang) always emits a line note before the
1850 prologue and another one after. We trust clang and newer Intel
1851 compilers to emit usable line notes. */
1852 if (post_prologue_pc
1854 && COMPUNIT_PRODUCER (cust
) != NULL
1855 && (producer_is_llvm (COMPUNIT_PRODUCER (cust
))
1856 || producer_is_icc_ge_19 (COMPUNIT_PRODUCER (cust
)))))
1857 return std::max (start_pc
, post_prologue_pc
);
1861 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1862 if (cache
.locals
< 0)
1865 /* Found valid frame setup. */
1867 /* The native cc on SVR4 in -K PIC mode inserts the following code
1868 to get the address of the global offset table (GOT) into register
1873 movl %ebx,x(%ebp) (optional)
1876 This code is with the rest of the prologue (at the end of the
1877 function), so we have to skip it to get to the first real
1878 instruction at the start of the function. */
1880 for (i
= 0; i
< 6; i
++)
1882 if (target_read_code (pc
+ i
, &op
, 1))
1885 if (pic_pat
[i
] != op
)
1892 if (target_read_code (pc
+ delta
, &op
, 1))
1895 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1897 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1899 if (op
== 0x5d) /* One byte offset from %ebp. */
1901 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1903 else /* Unexpected instruction. */
1906 if (target_read_code (pc
+ delta
, &op
, 1))
1911 if (delta
> 0 && op
== 0x81
1912 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1919 /* If the function starts with a branch (to startup code at the end)
1920 the last instruction should bring us back to the first
1921 instruction of the real code. */
1922 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1923 pc
= i386_follow_jump (gdbarch
, pc
);
1928 /* Check that the code pointed to by PC corresponds to a call to
1929 __main, skip it if so. Return PC otherwise. */
1932 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1937 if (target_read_code (pc
, &op
, 1))
1943 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1945 /* Make sure address is computed correctly as a 32bit
1946 integer even if CORE_ADDR is 64 bit wide. */
1947 struct bound_minimal_symbol s
;
1948 CORE_ADDR call_dest
;
1950 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1951 call_dest
= call_dest
& 0xffffffffU
;
1952 s
= lookup_minimal_symbol_by_pc (call_dest
);
1953 if (s
.minsym
!= NULL
1954 && s
.minsym
->linkage_name () != NULL
1955 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1963 /* This function is 64-bit safe. */
1966 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1970 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1971 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1975 /* Normal frames. */
1978 i386_frame_cache_1 (struct frame_info
*this_frame
,
1979 struct i386_frame_cache
*cache
)
1981 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1982 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1986 cache
->pc
= get_frame_func (this_frame
);
1988 /* In principle, for normal frames, %ebp holds the frame pointer,
1989 which holds the base address for the current stack frame.
1990 However, for functions that don't need it, the frame pointer is
1991 optional. For these "frameless" functions the frame pointer is
1992 actually the frame pointer of the calling frame. Signal
1993 trampolines are just a special case of a "frameless" function.
1994 They (usually) share their frame pointer with the frame that was
1995 in progress when the signal occurred. */
1997 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1998 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1999 if (cache
->base
== 0)
2005 /* For normal frames, %eip is stored at 4(%ebp). */
2006 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2009 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2012 if (cache
->locals
< 0)
2014 /* We didn't find a valid frame, which means that CACHE->base
2015 currently holds the frame pointer for our calling frame. If
2016 we're at the start of a function, or somewhere half-way its
2017 prologue, the function's frame probably hasn't been fully
2018 setup yet. Try to reconstruct the base address for the stack
2019 frame by looking at the stack pointer. For truly "frameless"
2020 functions this might work too. */
2022 if (cache
->saved_sp_reg
!= -1)
2024 /* Saved stack pointer has been saved. */
2025 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2026 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2028 /* We're halfway aligning the stack. */
2029 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2030 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2032 /* This will be added back below. */
2033 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2035 else if (cache
->pc
!= 0
2036 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2038 /* We're in a known function, but did not find a frame
2039 setup. Assume that the function does not use %ebp.
2040 Alternatively, we may have jumped to an invalid
2041 address; in that case there is definitely no new
2043 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2044 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2048 /* We're in an unknown function. We could not find the start
2049 of the function to analyze the prologue; our best option is
2050 to assume a typical frame layout with the caller's %ebp
2052 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2055 if (cache
->saved_sp_reg
!= -1)
2057 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2058 register may be unavailable). */
2059 if (cache
->saved_sp
== 0
2060 && deprecated_frame_register_read (this_frame
,
2061 cache
->saved_sp_reg
, buf
))
2062 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2064 /* Now that we have the base address for the stack frame we can
2065 calculate the value of %esp in the calling frame. */
2066 else if (cache
->saved_sp
== 0)
2067 cache
->saved_sp
= cache
->base
+ 8;
2069 /* Adjust all the saved registers such that they contain addresses
2070 instead of offsets. */
2071 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2072 if (cache
->saved_regs
[i
] != -1)
2073 cache
->saved_regs
[i
] += cache
->base
;
2078 static struct i386_frame_cache
*
2079 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2081 struct i386_frame_cache
*cache
;
2084 return (struct i386_frame_cache
*) *this_cache
;
2086 cache
= i386_alloc_frame_cache ();
2087 *this_cache
= cache
;
2091 i386_frame_cache_1 (this_frame
, cache
);
2093 catch (const gdb_exception_error
&ex
)
2095 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2103 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2104 struct frame_id
*this_id
)
2106 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2109 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2110 else if (cache
->base
== 0)
2112 /* This marks the outermost frame. */
2116 /* See the end of i386_push_dummy_call. */
2117 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2121 static enum unwind_stop_reason
2122 i386_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2125 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2128 return UNWIND_UNAVAILABLE
;
2130 /* This marks the outermost frame. */
2131 if (cache
->base
== 0)
2132 return UNWIND_OUTERMOST
;
2134 return UNWIND_NO_REASON
;
2137 static struct value
*
2138 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2141 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2143 gdb_assert (regnum
>= 0);
2145 /* The System V ABI says that:
2147 "The flags register contains the system flags, such as the
2148 direction flag and the carry flag. The direction flag must be
2149 set to the forward (that is, zero) direction before entry and
2150 upon exit from a function. Other user flags have no specified
2151 role in the standard calling sequence and are not preserved."
2153 To guarantee the "upon exit" part of that statement we fake a
2154 saved flags register that has its direction flag cleared.
2156 Note that GCC doesn't seem to rely on the fact that the direction
2157 flag is cleared after a function return; it always explicitly
2158 clears the flag before operations where it matters.
2160 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2161 right thing to do. The way we fake the flags register here makes
2162 it impossible to change it. */
2164 if (regnum
== I386_EFLAGS_REGNUM
)
2168 val
= get_frame_register_unsigned (this_frame
, regnum
);
2170 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2173 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2174 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2176 if (regnum
== I386_ESP_REGNUM
2177 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2179 /* If the SP has been saved, but we don't know where, then this
2180 means that SAVED_SP_REG register was found unavailable back
2181 when we built the cache. */
2182 if (cache
->saved_sp
== 0)
2183 return frame_unwind_got_register (this_frame
, regnum
,
2184 cache
->saved_sp_reg
);
2186 return frame_unwind_got_constant (this_frame
, regnum
,
2190 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2191 return frame_unwind_got_memory (this_frame
, regnum
,
2192 cache
->saved_regs
[regnum
]);
2194 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2197 static const struct frame_unwind i386_frame_unwind
=
2201 i386_frame_unwind_stop_reason
,
2203 i386_frame_prev_register
,
2205 default_frame_sniffer
2208 /* Normal frames, but in a function epilogue. */
2210 /* Implement the stack_frame_destroyed_p gdbarch method.
2212 The epilogue is defined here as the 'ret' instruction, which will
2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2214 the function's stack frame. */
2217 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2220 struct compunit_symtab
*cust
;
2222 cust
= find_pc_compunit_symtab (pc
);
2223 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2226 if (target_read_memory (pc
, &insn
, 1))
2227 return 0; /* Can't read memory at pc. */
2229 if (insn
!= 0xc3) /* 'ret' instruction. */
2236 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2237 struct frame_info
*this_frame
,
2238 void **this_prologue_cache
)
2240 if (frame_relative_level (this_frame
) == 0)
2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2242 get_frame_pc (this_frame
));
2247 static struct i386_frame_cache
*
2248 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2250 struct i386_frame_cache
*cache
;
2254 return (struct i386_frame_cache
*) *this_cache
;
2256 cache
= i386_alloc_frame_cache ();
2257 *this_cache
= cache
;
2261 cache
->pc
= get_frame_func (this_frame
);
2263 /* At this point the stack looks as if we just entered the
2264 function, with the return address at the top of the
2266 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2267 cache
->base
= sp
+ cache
->sp_offset
;
2268 cache
->saved_sp
= cache
->base
+ 8;
2269 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2273 catch (const gdb_exception_error
&ex
)
2275 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2282 static enum unwind_stop_reason
2283 i386_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2286 struct i386_frame_cache
*cache
=
2287 i386_epilogue_frame_cache (this_frame
, this_cache
);
2290 return UNWIND_UNAVAILABLE
;
2292 return UNWIND_NO_REASON
;
2296 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
2298 struct frame_id
*this_id
)
2300 struct i386_frame_cache
*cache
=
2301 i386_epilogue_frame_cache (this_frame
, this_cache
);
2304 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2306 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2309 static struct value
*
2310 i386_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2311 void **this_cache
, int regnum
)
2313 /* Make sure we've initialized the cache. */
2314 i386_epilogue_frame_cache (this_frame
, this_cache
);
2316 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2319 static const struct frame_unwind i386_epilogue_frame_unwind
=
2323 i386_epilogue_frame_unwind_stop_reason
,
2324 i386_epilogue_frame_this_id
,
2325 i386_epilogue_frame_prev_register
,
2327 i386_epilogue_frame_sniffer
2331 /* Stack-based trampolines. */
2333 /* These trampolines are used on cross x86 targets, when taking the
2334 address of a nested function. When executing these trampolines,
2335 no stack frame is set up, so we are in a similar situation as in
2336 epilogues and i386_epilogue_frame_this_id can be re-used. */
2338 /* Static chain passed in register. */
2340 static i386_insn i386_tramp_chain_in_reg_insns
[] =
2342 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2343 { 5, { 0xb8 }, { 0xfe } },
2346 { 5, { 0xe9 }, { 0xff } },
2351 /* Static chain passed on stack (when regparm=3). */
2353 static i386_insn i386_tramp_chain_on_stack_insns
[] =
2356 { 5, { 0x68 }, { 0xff } },
2359 { 5, { 0xe9 }, { 0xff } },
2364 /* Return whether PC points inside a stack trampoline. */
2367 i386_in_stack_tramp_p (CORE_ADDR pc
)
2372 /* A stack trampoline is detected if no name is associated
2373 to the current pc and if it points inside a trampoline
2376 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2380 if (target_read_memory (pc
, &insn
, 1))
2383 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2384 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2391 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2392 struct frame_info
*this_frame
,
2395 if (frame_relative_level (this_frame
) == 0)
2396 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2401 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2405 i386_epilogue_frame_unwind_stop_reason
,
2406 i386_epilogue_frame_this_id
,
2407 i386_epilogue_frame_prev_register
,
2409 i386_stack_tramp_frame_sniffer
2412 /* Generate a bytecode expression to get the value of the saved PC. */
2415 i386_gen_return_address (struct gdbarch
*gdbarch
,
2416 struct agent_expr
*ax
, struct axs_value
*value
,
2419 /* The following sequence assumes the traditional use of the base
2421 ax_reg (ax
, I386_EBP_REGNUM
);
2423 ax_simple (ax
, aop_add
);
2424 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2425 value
->kind
= axs_lvalue_memory
;
2429 /* Signal trampolines. */
2431 static struct i386_frame_cache
*
2432 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2434 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2436 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2437 struct i386_frame_cache
*cache
;
2442 return (struct i386_frame_cache
*) *this_cache
;
2444 cache
= i386_alloc_frame_cache ();
2448 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2449 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2451 addr
= tdep
->sigcontext_addr (this_frame
);
2452 if (tdep
->sc_reg_offset
)
2456 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2458 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2459 if (tdep
->sc_reg_offset
[i
] != -1)
2460 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2464 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2465 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2470 catch (const gdb_exception_error
&ex
)
2472 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2476 *this_cache
= cache
;
2480 static enum unwind_stop_reason
2481 i386_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2484 struct i386_frame_cache
*cache
=
2485 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2488 return UNWIND_UNAVAILABLE
;
2490 return UNWIND_NO_REASON
;
2494 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2495 struct frame_id
*this_id
)
2497 struct i386_frame_cache
*cache
=
2498 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2501 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2504 /* See the end of i386_push_dummy_call. */
2505 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2509 static struct value
*
2510 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2511 void **this_cache
, int regnum
)
2513 /* Make sure we've initialized the cache. */
2514 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2516 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2520 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2521 struct frame_info
*this_frame
,
2522 void **this_prologue_cache
)
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2526 /* We shouldn't even bother if we don't have a sigcontext_addr
2528 if (tdep
->sigcontext_addr
== NULL
)
2531 if (tdep
->sigtramp_p
!= NULL
)
2533 if (tdep
->sigtramp_p (this_frame
))
2537 if (tdep
->sigtramp_start
!= 0)
2539 CORE_ADDR pc
= get_frame_pc (this_frame
);
2541 gdb_assert (tdep
->sigtramp_end
!= 0);
2542 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2549 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2553 i386_sigtramp_frame_unwind_stop_reason
,
2554 i386_sigtramp_frame_this_id
,
2555 i386_sigtramp_frame_prev_register
,
2557 i386_sigtramp_frame_sniffer
2562 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2564 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2569 static const struct frame_base i386_frame_base
=
2572 i386_frame_base_address
,
2573 i386_frame_base_address
,
2574 i386_frame_base_address
2577 static struct frame_id
2578 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2582 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2584 /* See the end of i386_push_dummy_call. */
2585 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2588 /* _Decimal128 function return values need 16-byte alignment on the
2592 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2594 return sp
& -(CORE_ADDR
)16;
2598 /* Figure out where the longjmp will land. Slurp the args out of the
2599 stack. We expect the first arg to be a pointer to the jmp_buf
2600 structure from which we extract the address that we will land at.
2601 This address is copied into PC. This routine returns non-zero on
2605 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2608 CORE_ADDR sp
, jb_addr
;
2609 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2610 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2611 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2613 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2614 longjmp will land. */
2615 if (jb_pc_offset
== -1)
2618 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2619 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2620 if (target_read_memory (sp
+ 4, buf
, 4))
2623 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2624 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2627 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2632 /* Check whether TYPE must be 16-byte-aligned when passed as a
2633 function argument. 16-byte vectors, _Decimal128 and structures or
2634 unions containing such types must be 16-byte-aligned; other
2635 arguments are 4-byte-aligned. */
2638 i386_16_byte_align_p (struct type
*type
)
2640 type
= check_typedef (type
);
2641 if ((type
->code () == TYPE_CODE_DECFLOAT
2642 || (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ()))
2643 && TYPE_LENGTH (type
) == 16)
2645 if (type
->code () == TYPE_CODE_ARRAY
)
2646 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
2647 if (type
->code () == TYPE_CODE_STRUCT
2648 || type
->code () == TYPE_CODE_UNION
)
2651 for (i
= 0; i
< type
->num_fields (); i
++)
2653 if (field_is_static (&type
->field (i
)))
2655 if (i386_16_byte_align_p (type
->field (i
).type ()))
2662 /* Implementation for set_gdbarch_push_dummy_code. */
2665 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2666 struct value
**args
, int nargs
, struct type
*value_type
,
2667 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2668 struct regcache
*regcache
)
2670 /* Use 0xcc breakpoint - 1 byte. */
2674 /* Keep the stack aligned. */
2678 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2679 calling convention. */
2682 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2683 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2684 int nargs
, struct value
**args
, CORE_ADDR sp
,
2685 function_call_return_method return_method
,
2686 CORE_ADDR struct_addr
, bool thiscall
)
2688 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2694 /* BND registers can be in arbitrary values at the moment of the
2695 inferior call. This can cause boundary violations that are not
2696 due to a real bug or even desired by the user. The best to be done
2697 is set the BND registers to allow access to the whole memory, INIT
2698 state, before pushing the inferior call. */
2699 i387_reset_bnd_regs (gdbarch
, regcache
);
2701 /* Determine the total space required for arguments and struct
2702 return address in a first pass (allowing for 16-byte-aligned
2703 arguments), then push arguments in a second pass. */
2705 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2707 int args_space_used
= 0;
2709 if (return_method
== return_method_struct
)
2713 /* Push value address. */
2714 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2715 write_memory (sp
, buf
, 4);
2716 args_space_used
+= 4;
2722 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2724 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
2728 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2729 args_space_used
= align_up (args_space_used
, 16);
2731 write_memory (sp
+ args_space_used
,
2732 value_contents_all (args
[i
]).data (), len
);
2733 /* The System V ABI says that:
2735 "An argument's size is increased, if necessary, to make it a
2736 multiple of [32-bit] words. This may require tail padding,
2737 depending on the size of the argument."
2739 This makes sure the stack stays word-aligned. */
2740 args_space_used
+= align_up (len
, 4);
2744 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
2745 args_space
= align_up (args_space
, 16);
2746 args_space
+= align_up (len
, 4);
2754 /* The original System V ABI only requires word alignment,
2755 but modern incarnations need 16-byte alignment in order
2756 to support SSE. Since wasting a few bytes here isn't
2757 harmful we unconditionally enforce 16-byte alignment. */
2762 /* Store return address. */
2764 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2765 write_memory (sp
, buf
, 4);
2767 /* Finally, update the stack pointer... */
2768 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2769 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2771 /* ...and fake a frame pointer. */
2772 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2774 /* The 'this' pointer needs to be in ECX. */
2776 regcache
->cooked_write (I386_ECX_REGNUM
,
2777 value_contents_all (args
[0]).data ());
2779 /* MarkK wrote: This "+ 8" is all over the place:
2780 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2781 i386_dummy_id). It's there, since all frame unwinders for
2782 a given target have to agree (within a certain margin) on the
2783 definition of the stack address of a frame. Otherwise frame id
2784 comparison might not work correctly. Since DWARF2/GCC uses the
2785 stack address *before* the function call as a frame's CFA. On
2786 the i386, when %ebp is used as a frame pointer, the offset
2787 between the contents %ebp and the CFA as defined by GCC. */
2791 /* Implement the "push_dummy_call" gdbarch method. */
2794 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2795 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2796 struct value
**args
, CORE_ADDR sp
,
2797 function_call_return_method return_method
,
2798 CORE_ADDR struct_addr
)
2800 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2801 nargs
, args
, sp
, return_method
,
2802 struct_addr
, false);
2805 /* These registers are used for returning integers (and on some
2806 targets also for returning `struct' and `union' values when their
2807 size and alignment match an integer type). */
2808 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2809 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2811 /* Read, for architecture GDBARCH, a function return value of TYPE
2812 from REGCACHE, and copy that into VALBUF. */
2815 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2816 struct regcache
*regcache
, gdb_byte
*valbuf
)
2818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2819 int len
= TYPE_LENGTH (type
);
2820 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2822 /* _Float16 and _Float16 _Complex values are returned via xmm0. */
2823 if (((type
->code () == TYPE_CODE_FLT
) && len
== 2)
2824 || ((type
->code () == TYPE_CODE_COMPLEX
) && len
== 4))
2826 regcache
->raw_read (I387_XMM0_REGNUM (tdep
), valbuf
);
2829 else if (type
->code () == TYPE_CODE_FLT
)
2831 if (tdep
->st0_regnum
< 0)
2833 warning (_("Cannot find floating-point return value."));
2834 memset (valbuf
, 0, len
);
2838 /* Floating-point return values can be found in %st(0). Convert
2839 its contents to the desired type. This is probably not
2840 exactly how it would happen on the target itself, but it is
2841 the best we can do. */
2842 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2843 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2847 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2848 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2850 if (len
<= low_size
)
2852 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2853 memcpy (valbuf
, buf
, len
);
2855 else if (len
<= (low_size
+ high_size
))
2857 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2858 memcpy (valbuf
, buf
, low_size
);
2859 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2860 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2863 internal_error (__FILE__
, __LINE__
,
2864 _("Cannot extract return value of %d bytes long."),
2869 /* Write, for architecture GDBARCH, a function return value of TYPE
2870 from VALBUF into REGCACHE. */
2873 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2874 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2877 int len
= TYPE_LENGTH (type
);
2879 if (type
->code () == TYPE_CODE_FLT
)
2882 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2884 if (tdep
->st0_regnum
< 0)
2886 warning (_("Cannot set floating-point return value."));
2890 /* Returning floating-point values is a bit tricky. Apart from
2891 storing the return value in %st(0), we have to simulate the
2892 state of the FPU at function return point. */
2894 /* Convert the value found in VALBUF to the extended
2895 floating-point format used by the FPU. This is probably
2896 not exactly how it would happen on the target itself, but
2897 it is the best we can do. */
2898 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2899 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2901 /* Set the top of the floating-point register stack to 7. The
2902 actual value doesn't really matter, but 7 is what a normal
2903 function return would end up with if the program started out
2904 with a freshly initialized FPU. */
2905 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2907 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2909 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2910 the floating-point register stack to 7, the appropriate value
2911 for the tag word is 0x3fff. */
2912 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
2916 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2917 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2919 if (len
<= low_size
)
2920 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
2921 else if (len
<= (low_size
+ high_size
))
2923 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
2924 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
2928 internal_error (__FILE__
, __LINE__
,
2929 _("Cannot store return value of %d bytes long."), len
);
2934 /* This is the variable that is set with "set struct-convention", and
2935 its legitimate values. */
2936 static const char default_struct_convention
[] = "default";
2937 static const char pcc_struct_convention
[] = "pcc";
2938 static const char reg_struct_convention
[] = "reg";
2939 static const char *const valid_conventions
[] =
2941 default_struct_convention
,
2942 pcc_struct_convention
,
2943 reg_struct_convention
,
2946 static const char *struct_convention
= default_struct_convention
;
2948 /* Return non-zero if TYPE, which is assumed to be a structure,
2949 a union type, or an array type, should be returned in registers
2950 for architecture GDBARCH. */
2953 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2956 enum type_code code
= type
->code ();
2957 int len
= TYPE_LENGTH (type
);
2959 gdb_assert (code
== TYPE_CODE_STRUCT
2960 || code
== TYPE_CODE_UNION
2961 || code
== TYPE_CODE_ARRAY
);
2963 if (struct_convention
== pcc_struct_convention
2964 || (struct_convention
== default_struct_convention
2965 && tdep
->struct_return
== pcc_struct_return
))
2968 /* Structures consisting of a single `float', `double' or 'long
2969 double' member are returned in %st(0). */
2970 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
2972 type
= check_typedef (type
->field (0).type ());
2973 if (type
->code () == TYPE_CODE_FLT
)
2974 return (len
== 4 || len
== 8 || len
== 12);
2977 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2980 /* Determine, for architecture GDBARCH, how a return value of TYPE
2981 should be returned. If it is supposed to be returned in registers,
2982 and READBUF is non-zero, read the appropriate value from REGCACHE,
2983 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2984 from WRITEBUF into REGCACHE. */
2986 static enum return_value_convention
2987 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
2988 struct type
*type
, struct regcache
*regcache
,
2989 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2991 enum type_code code
= type
->code ();
2993 if (((code
== TYPE_CODE_STRUCT
2994 || code
== TYPE_CODE_UNION
2995 || code
== TYPE_CODE_ARRAY
)
2996 && !i386_reg_struct_return_p (gdbarch
, type
))
2997 /* Complex double and long double uses the struct return convention. */
2998 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 16)
2999 || (code
== TYPE_CODE_COMPLEX
&& TYPE_LENGTH (type
) == 24)
3000 /* 128-bit decimal float uses the struct return convention. */
3001 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
3003 /* The System V ABI says that:
3005 "A function that returns a structure or union also sets %eax
3006 to the value of the original address of the caller's area
3007 before it returns. Thus when the caller receives control
3008 again, the address of the returned object resides in register
3009 %eax and can be used to access the object."
3011 So the ABI guarantees that we can always find the return
3012 value just after the function has returned. */
3014 /* Note that the ABI doesn't mention functions returning arrays,
3015 which is something possible in certain languages such as Ada.
3016 In this case, the value is returned as if it was wrapped in
3017 a record, so the convention applied to records also applies
3024 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3025 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
3028 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3031 /* This special case is for structures consisting of a single
3032 `float', `double' or 'long double' member. These structures are
3033 returned in %st(0). For these structures, we call ourselves
3034 recursively, changing TYPE into the type of the first member of
3035 the structure. Since that should work for all structures that
3036 have only one member, we don't bother to check the member's type
3038 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3040 type
= check_typedef (type
->field (0).type ());
3041 return i386_return_value (gdbarch
, function
, type
, regcache
,
3046 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
3048 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3050 return RETURN_VALUE_REGISTER_CONVENTION
;
3055 i387_ext_type (struct gdbarch
*gdbarch
)
3057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3059 if (!tdep
->i387_ext_type
)
3061 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3062 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3065 return tdep
->i387_ext_type
;
3068 /* Construct type for pseudo BND registers. We can't use
3069 tdesc_find_type since a complement of one value has to be used
3070 to describe the upper bound. */
3072 static struct type
*
3073 i386_bnd_type (struct gdbarch
*gdbarch
)
3075 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3078 if (!tdep
->i386_bnd_type
)
3081 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3083 /* The type we're building is described bellow: */
3088 void *ubound
; /* One complement of raw ubound field. */
3092 t
= arch_composite_type (gdbarch
,
3093 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3095 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3096 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3098 t
->set_name ("builtin_type_bound128");
3099 tdep
->i386_bnd_type
= t
;
3102 return tdep
->i386_bnd_type
;
3105 /* Construct vector type for pseudo ZMM registers. We can't use
3106 tdesc_find_type since ZMM isn't described in target description. */
3108 static struct type
*
3109 i386_zmm_type (struct gdbarch
*gdbarch
)
3111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3113 if (!tdep
->i386_zmm_type
)
3115 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3117 /* The type we're building is this: */
3119 union __gdb_builtin_type_vec512i
3121 int128_t v4_int128
[4];
3122 int64_t v8_int64
[8];
3123 int32_t v16_int32
[16];
3124 int16_t v32_int16
[32];
3125 int8_t v64_int8
[64];
3126 double v8_double
[8];
3127 float v16_float
[16];
3128 float16_t v32_half
[32];
3129 bfloat16_t v32_bfloat16
[32];
3135 t
= arch_composite_type (gdbarch
,
3136 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3137 append_composite_type_field (t
, "v32_bfloat16",
3138 init_vector_type (bt
->builtin_bfloat16
, 32));
3139 append_composite_type_field (t
, "v32_half",
3140 init_vector_type (bt
->builtin_half
, 32));
3141 append_composite_type_field (t
, "v16_float",
3142 init_vector_type (bt
->builtin_float
, 16));
3143 append_composite_type_field (t
, "v8_double",
3144 init_vector_type (bt
->builtin_double
, 8));
3145 append_composite_type_field (t
, "v64_int8",
3146 init_vector_type (bt
->builtin_int8
, 64));
3147 append_composite_type_field (t
, "v32_int16",
3148 init_vector_type (bt
->builtin_int16
, 32));
3149 append_composite_type_field (t
, "v16_int32",
3150 init_vector_type (bt
->builtin_int32
, 16));
3151 append_composite_type_field (t
, "v8_int64",
3152 init_vector_type (bt
->builtin_int64
, 8));
3153 append_composite_type_field (t
, "v4_int128",
3154 init_vector_type (bt
->builtin_int128
, 4));
3156 t
->set_is_vector (true);
3157 t
->set_name ("builtin_type_vec512i");
3158 tdep
->i386_zmm_type
= t
;
3161 return tdep
->i386_zmm_type
;
3164 /* Construct vector type for pseudo YMM registers. We can't use
3165 tdesc_find_type since YMM isn't described in target description. */
3167 static struct type
*
3168 i386_ymm_type (struct gdbarch
*gdbarch
)
3170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3172 if (!tdep
->i386_ymm_type
)
3174 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3176 /* The type we're building is this: */
3178 union __gdb_builtin_type_vec256i
3180 int128_t v2_int128
[2];
3181 int64_t v4_int64
[4];
3182 int32_t v8_int32
[8];
3183 int16_t v16_int16
[16];
3184 int8_t v32_int8
[32];
3185 double v4_double
[4];
3187 float16_t v16_half
[16];
3188 bfloat16_t v16_bfloat16
[16];
3194 t
= arch_composite_type (gdbarch
,
3195 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3196 append_composite_type_field (t
, "v16_bfloat16",
3197 init_vector_type (bt
->builtin_bfloat16
, 16));
3198 append_composite_type_field (t
, "v16_half",
3199 init_vector_type (bt
->builtin_half
, 16));
3200 append_composite_type_field (t
, "v8_float",
3201 init_vector_type (bt
->builtin_float
, 8));
3202 append_composite_type_field (t
, "v4_double",
3203 init_vector_type (bt
->builtin_double
, 4));
3204 append_composite_type_field (t
, "v32_int8",
3205 init_vector_type (bt
->builtin_int8
, 32));
3206 append_composite_type_field (t
, "v16_int16",
3207 init_vector_type (bt
->builtin_int16
, 16));
3208 append_composite_type_field (t
, "v8_int32",
3209 init_vector_type (bt
->builtin_int32
, 8));
3210 append_composite_type_field (t
, "v4_int64",
3211 init_vector_type (bt
->builtin_int64
, 4));
3212 append_composite_type_field (t
, "v2_int128",
3213 init_vector_type (bt
->builtin_int128
, 2));
3215 t
->set_is_vector (true);
3216 t
->set_name ("builtin_type_vec256i");
3217 tdep
->i386_ymm_type
= t
;
3220 return tdep
->i386_ymm_type
;
3223 /* Construct vector type for MMX registers. */
3224 static struct type
*
3225 i386_mmx_type (struct gdbarch
*gdbarch
)
3227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3229 if (!tdep
->i386_mmx_type
)
3231 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3233 /* The type we're building is this: */
3235 union __gdb_builtin_type_vec64i
3238 int32_t v2_int32
[2];
3239 int16_t v4_int16
[4];
3246 t
= arch_composite_type (gdbarch
,
3247 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3249 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3250 append_composite_type_field (t
, "v2_int32",
3251 init_vector_type (bt
->builtin_int32
, 2));
3252 append_composite_type_field (t
, "v4_int16",
3253 init_vector_type (bt
->builtin_int16
, 4));
3254 append_composite_type_field (t
, "v8_int8",
3255 init_vector_type (bt
->builtin_int8
, 8));
3257 t
->set_is_vector (true);
3258 t
->set_name ("builtin_type_vec64i");
3259 tdep
->i386_mmx_type
= t
;
3262 return tdep
->i386_mmx_type
;
3265 /* Return the GDB type object for the "standard" data type of data in
3269 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3271 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3272 return i386_bnd_type (gdbarch
);
3273 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3274 return i386_mmx_type (gdbarch
);
3275 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3276 return i386_ymm_type (gdbarch
);
3277 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3278 return i386_ymm_type (gdbarch
);
3279 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3280 return i386_zmm_type (gdbarch
);
3283 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3284 if (i386_byte_regnum_p (gdbarch
, regnum
))
3285 return bt
->builtin_int8
;
3286 else if (i386_word_regnum_p (gdbarch
, regnum
))
3287 return bt
->builtin_int16
;
3288 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3289 return bt
->builtin_int32
;
3290 else if (i386_k_regnum_p (gdbarch
, regnum
))
3291 return bt
->builtin_int64
;
3294 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3297 /* Map a cooked register onto a raw register or memory. For the i386,
3298 the MMX registers need to be mapped onto floating point registers. */
3301 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3303 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
3308 mmxreg
= regnum
- tdep
->mm0_regnum
;
3309 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3310 tos
= (fstat
>> 11) & 0x7;
3311 fpreg
= (mmxreg
+ tos
) % 8;
3313 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3316 /* A helper function for us by i386_pseudo_register_read_value and
3317 amd64_pseudo_register_read_value. It does all the work but reads
3318 the data into an already-allocated value. */
3321 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3322 readable_regcache
*regcache
,
3324 struct value
*result_value
)
3326 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3327 enum register_status status
;
3328 gdb_byte
*buf
= value_contents_raw (result_value
).data ();
3330 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3332 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3334 /* Extract (always little endian). */
3335 status
= regcache
->raw_read (fpnum
, raw_buf
);
3336 if (status
!= REG_VALID
)
3337 mark_value_bytes_unavailable (result_value
, 0,
3338 TYPE_LENGTH (value_type (result_value
)));
3340 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3345 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3347 regnum
-= tdep
->bnd0_regnum
;
3349 /* Extract (always little endian). Read lower 128bits. */
3350 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3352 if (status
!= REG_VALID
)
3353 mark_value_bytes_unavailable (result_value
, 0, 16);
3356 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3357 LONGEST upper
, lower
;
3358 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3360 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3361 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3364 memcpy (buf
, &lower
, size
);
3365 memcpy (buf
+ size
, &upper
, size
);
3368 else if (i386_k_regnum_p (gdbarch
, regnum
))
3370 regnum
-= tdep
->k0_regnum
;
3372 /* Extract (always little endian). */
3373 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3374 if (status
!= REG_VALID
)
3375 mark_value_bytes_unavailable (result_value
, 0, 8);
3377 memcpy (buf
, raw_buf
, 8);
3379 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3381 regnum
-= tdep
->zmm0_regnum
;
3383 if (regnum
< num_lower_zmm_regs
)
3385 /* Extract (always little endian). Read lower 128bits. */
3386 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3388 if (status
!= REG_VALID
)
3389 mark_value_bytes_unavailable (result_value
, 0, 16);
3391 memcpy (buf
, raw_buf
, 16);
3393 /* Extract (always little endian). Read upper 128bits. */
3394 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3396 if (status
!= REG_VALID
)
3397 mark_value_bytes_unavailable (result_value
, 16, 16);
3399 memcpy (buf
+ 16, raw_buf
, 16);
3403 /* Extract (always little endian). Read lower 128bits. */
3404 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3405 - num_lower_zmm_regs
,
3407 if (status
!= REG_VALID
)
3408 mark_value_bytes_unavailable (result_value
, 0, 16);
3410 memcpy (buf
, raw_buf
, 16);
3412 /* Extract (always little endian). Read upper 128bits. */
3413 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3414 - num_lower_zmm_regs
,
3416 if (status
!= REG_VALID
)
3417 mark_value_bytes_unavailable (result_value
, 16, 16);
3419 memcpy (buf
+ 16, raw_buf
, 16);
3422 /* Read upper 256bits. */
3423 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3425 if (status
!= REG_VALID
)
3426 mark_value_bytes_unavailable (result_value
, 32, 32);
3428 memcpy (buf
+ 32, raw_buf
, 32);
3430 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3432 regnum
-= tdep
->ymm0_regnum
;
3434 /* Extract (always little endian). Read lower 128bits. */
3435 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3437 if (status
!= REG_VALID
)
3438 mark_value_bytes_unavailable (result_value
, 0, 16);
3440 memcpy (buf
, raw_buf
, 16);
3441 /* Read upper 128bits. */
3442 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3444 if (status
!= REG_VALID
)
3445 mark_value_bytes_unavailable (result_value
, 16, 32);
3447 memcpy (buf
+ 16, raw_buf
, 16);
3449 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3451 regnum
-= tdep
->ymm16_regnum
;
3452 /* Extract (always little endian). Read lower 128bits. */
3453 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3455 if (status
!= REG_VALID
)
3456 mark_value_bytes_unavailable (result_value
, 0, 16);
3458 memcpy (buf
, raw_buf
, 16);
3459 /* Read upper 128bits. */
3460 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3462 if (status
!= REG_VALID
)
3463 mark_value_bytes_unavailable (result_value
, 16, 16);
3465 memcpy (buf
+ 16, raw_buf
, 16);
3467 else if (i386_word_regnum_p (gdbarch
, regnum
))
3469 int gpnum
= regnum
- tdep
->ax_regnum
;
3471 /* Extract (always little endian). */
3472 status
= regcache
->raw_read (gpnum
, raw_buf
);
3473 if (status
!= REG_VALID
)
3474 mark_value_bytes_unavailable (result_value
, 0,
3475 TYPE_LENGTH (value_type (result_value
)));
3477 memcpy (buf
, raw_buf
, 2);
3479 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3481 int gpnum
= regnum
- tdep
->al_regnum
;
3483 /* Extract (always little endian). We read both lower and
3485 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3486 if (status
!= REG_VALID
)
3487 mark_value_bytes_unavailable (result_value
, 0,
3488 TYPE_LENGTH (value_type (result_value
)));
3489 else if (gpnum
>= 4)
3490 memcpy (buf
, raw_buf
+ 1, 1);
3492 memcpy (buf
, raw_buf
, 1);
3495 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3499 static struct value
*
3500 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3501 readable_regcache
*regcache
,
3504 struct value
*result
;
3506 result
= allocate_value (register_type (gdbarch
, regnum
));
3507 VALUE_LVAL (result
) = lval_register
;
3508 VALUE_REGNUM (result
) = regnum
;
3510 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3516 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3517 int regnum
, const gdb_byte
*buf
)
3519 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3521 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3523 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3526 regcache
->raw_read (fpnum
, raw_buf
);
3527 /* ... Modify ... (always little endian). */
3528 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3530 regcache
->raw_write (fpnum
, raw_buf
);
3534 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3536 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3538 ULONGEST upper
, lower
;
3539 int size
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
);
3540 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
3542 /* New values from input value. */
3543 regnum
-= tdep
->bnd0_regnum
;
3544 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3545 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3547 /* Fetching register buffer. */
3548 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3553 /* Set register bits. */
3554 memcpy (raw_buf
, &lower
, 8);
3555 memcpy (raw_buf
+ 8, &upper
, 8);
3557 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3559 else if (i386_k_regnum_p (gdbarch
, regnum
))
3561 regnum
-= tdep
->k0_regnum
;
3563 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3565 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3567 regnum
-= tdep
->zmm0_regnum
;
3569 if (regnum
< num_lower_zmm_regs
)
3571 /* Write lower 128bits. */
3572 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3573 /* Write upper 128bits. */
3574 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3578 /* Write lower 128bits. */
3579 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3580 - num_lower_zmm_regs
, buf
);
3581 /* Write upper 128bits. */
3582 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3583 - num_lower_zmm_regs
, buf
+ 16);
3585 /* Write upper 256bits. */
3586 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3588 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3590 regnum
-= tdep
->ymm0_regnum
;
3592 /* ... Write lower 128bits. */
3593 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3594 /* ... Write upper 128bits. */
3595 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3597 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3599 regnum
-= tdep
->ymm16_regnum
;
3601 /* ... Write lower 128bits. */
3602 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3603 /* ... Write upper 128bits. */
3604 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3606 else if (i386_word_regnum_p (gdbarch
, regnum
))
3608 int gpnum
= regnum
- tdep
->ax_regnum
;
3611 regcache
->raw_read (gpnum
, raw_buf
);
3612 /* ... Modify ... (always little endian). */
3613 memcpy (raw_buf
, buf
, 2);
3615 regcache
->raw_write (gpnum
, raw_buf
);
3617 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3619 int gpnum
= regnum
- tdep
->al_regnum
;
3621 /* Read ... We read both lower and upper registers. */
3622 regcache
->raw_read (gpnum
% 4, raw_buf
);
3623 /* ... Modify ... (always little endian). */
3625 memcpy (raw_buf
+ 1, buf
, 1);
3627 memcpy (raw_buf
, buf
, 1);
3629 regcache
->raw_write (gpnum
% 4, raw_buf
);
3632 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3636 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3639 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3640 struct agent_expr
*ax
, int regnum
)
3642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3644 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3646 /* MMX to FPU register mapping depends on current TOS. Let's just
3647 not care and collect everything... */
3650 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3651 for (i
= 0; i
< 8; i
++)
3652 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3655 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3657 regnum
-= tdep
->bnd0_regnum
;
3658 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3661 else if (i386_k_regnum_p (gdbarch
, regnum
))
3663 regnum
-= tdep
->k0_regnum
;
3664 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3667 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3669 regnum
-= tdep
->zmm0_regnum
;
3670 if (regnum
< num_lower_zmm_regs
)
3672 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3673 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3677 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3678 - num_lower_zmm_regs
);
3679 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3680 - num_lower_zmm_regs
);
3682 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3685 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3687 regnum
-= tdep
->ymm0_regnum
;
3688 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3689 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3692 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3694 regnum
-= tdep
->ymm16_regnum
;
3695 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3696 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3699 else if (i386_word_regnum_p (gdbarch
, regnum
))
3701 int gpnum
= regnum
- tdep
->ax_regnum
;
3703 ax_reg_mask (ax
, gpnum
);
3706 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3708 int gpnum
= regnum
- tdep
->al_regnum
;
3710 ax_reg_mask (ax
, gpnum
% 4);
3714 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
3719 /* Return the register number of the register allocated by GCC after
3720 REGNUM, or -1 if there is no such register. */
3723 i386_next_regnum (int regnum
)
3725 /* GCC allocates the registers in the order:
3727 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3729 Since storing a variable in %esp doesn't make any sense we return
3730 -1 for %ebp and for %esp itself. */
3731 static int next_regnum
[] =
3733 I386_EDX_REGNUM
, /* Slot for %eax. */
3734 I386_EBX_REGNUM
, /* Slot for %ecx. */
3735 I386_ECX_REGNUM
, /* Slot for %edx. */
3736 I386_ESI_REGNUM
, /* Slot for %ebx. */
3737 -1, -1, /* Slots for %esp and %ebp. */
3738 I386_EDI_REGNUM
, /* Slot for %esi. */
3739 I386_EBP_REGNUM
/* Slot for %edi. */
3742 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3743 return next_regnum
[regnum
];
3748 /* Return nonzero if a value of type TYPE stored in register REGNUM
3749 needs any special handling. */
3752 i386_convert_register_p (struct gdbarch
*gdbarch
,
3753 int regnum
, struct type
*type
)
3755 int len
= TYPE_LENGTH (type
);
3757 /* Values may be spread across multiple registers. Most debugging
3758 formats aren't expressive enough to specify the locations, so
3759 some heuristics is involved. Right now we only handle types that
3760 have a length that is a multiple of the word size, since GCC
3761 doesn't seem to put any other types into registers. */
3762 if (len
> 4 && len
% 4 == 0)
3764 int last_regnum
= regnum
;
3768 last_regnum
= i386_next_regnum (last_regnum
);
3772 if (last_regnum
!= -1)
3776 return i387_convert_register_p (gdbarch
, regnum
, type
);
3779 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3780 return its contents in TO. */
3783 i386_register_to_value (struct frame_info
*frame
, int regnum
,
3784 struct type
*type
, gdb_byte
*to
,
3785 int *optimizedp
, int *unavailablep
)
3787 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3788 int len
= TYPE_LENGTH (type
);
3790 if (i386_fp_regnum_p (gdbarch
, regnum
))
3791 return i387_register_to_value (frame
, regnum
, type
, to
,
3792 optimizedp
, unavailablep
);
3794 /* Read a value spread across multiple registers. */
3796 gdb_assert (len
> 4 && len
% 4 == 0);
3800 gdb_assert (regnum
!= -1);
3801 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3803 if (!get_frame_register_bytes (frame
, regnum
, 0,
3804 gdb::make_array_view (to
,
3805 register_size (gdbarch
,
3807 optimizedp
, unavailablep
))
3810 regnum
= i386_next_regnum (regnum
);
3815 *optimizedp
= *unavailablep
= 0;
3819 /* Write the contents FROM of a value of type TYPE into register
3820 REGNUM in frame FRAME. */
3823 i386_value_to_register (struct frame_info
*frame
, int regnum
,
3824 struct type
*type
, const gdb_byte
*from
)
3826 int len
= TYPE_LENGTH (type
);
3828 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3830 i387_value_to_register (frame
, regnum
, type
, from
);
3834 /* Write a value spread across multiple registers. */
3836 gdb_assert (len
> 4 && len
% 4 == 0);
3840 gdb_assert (regnum
!= -1);
3841 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3843 put_frame_register (frame
, regnum
, from
);
3844 regnum
= i386_next_regnum (regnum
);
3850 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3851 in the general-purpose register set REGSET to register cache
3852 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3855 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3856 int regnum
, const void *gregs
, size_t len
)
3858 struct gdbarch
*gdbarch
= regcache
->arch ();
3859 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3860 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3863 gdb_assert (len
>= tdep
->sizeof_gregset
);
3865 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3867 if ((regnum
== i
|| regnum
== -1)
3868 && tdep
->gregset_reg_offset
[i
] != -1)
3869 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3873 /* Collect register REGNUM from the register cache REGCACHE and store
3874 it in the buffer specified by GREGS and LEN as described by the
3875 general-purpose register set REGSET. If REGNUM is -1, do this for
3876 all registers in REGSET. */
3879 i386_collect_gregset (const struct regset
*regset
,
3880 const struct regcache
*regcache
,
3881 int regnum
, void *gregs
, size_t len
)
3883 struct gdbarch
*gdbarch
= regcache
->arch ();
3884 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3885 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3888 gdb_assert (len
>= tdep
->sizeof_gregset
);
3890 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3892 if ((regnum
== i
|| regnum
== -1)
3893 && tdep
->gregset_reg_offset
[i
] != -1)
3894 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3898 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3899 in the floating-point register set REGSET to register cache
3900 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3903 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3904 int regnum
, const void *fpregs
, size_t len
)
3906 struct gdbarch
*gdbarch
= regcache
->arch ();
3907 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3909 if (len
== I387_SIZEOF_FXSAVE
)
3911 i387_supply_fxsave (regcache
, regnum
, fpregs
);
3915 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3916 i387_supply_fsave (regcache
, regnum
, fpregs
);
3919 /* Collect register REGNUM from the register cache REGCACHE and store
3920 it in the buffer specified by FPREGS and LEN as described by the
3921 floating-point register set REGSET. If REGNUM is -1, do this for
3922 all registers in REGSET. */
3925 i386_collect_fpregset (const struct regset
*regset
,
3926 const struct regcache
*regcache
,
3927 int regnum
, void *fpregs
, size_t len
)
3929 struct gdbarch
*gdbarch
= regcache
->arch ();
3930 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3932 if (len
== I387_SIZEOF_FXSAVE
)
3934 i387_collect_fxsave (regcache
, regnum
, fpregs
);
3938 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3939 i387_collect_fsave (regcache
, regnum
, fpregs
);
3942 /* Register set definitions. */
3944 const struct regset i386_gregset
=
3946 NULL
, i386_supply_gregset
, i386_collect_gregset
3949 const struct regset i386_fpregset
=
3951 NULL
, i386_supply_fpregset
, i386_collect_fpregset
3954 /* Default iterator over core file register note sections. */
3957 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
3958 iterate_over_regset_sections_cb
*cb
,
3960 const struct regcache
*regcache
)
3962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3964 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
3966 if (tdep
->sizeof_fpregset
)
3967 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
3972 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
3975 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
3976 CORE_ADDR pc
, char *name
)
3978 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3979 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3982 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
3984 unsigned long indirect
=
3985 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
3986 struct minimal_symbol
*indsym
=
3987 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
3988 const char *symname
= indsym
? indsym
->linkage_name () : 0;
3992 if (startswith (symname
, "__imp_")
3993 || startswith (symname
, "_imp_"))
3995 read_memory_unsigned_integer (indirect
, 4, byte_order
);
3998 return 0; /* Not a trampoline. */
4002 /* Return whether the THIS_FRAME corresponds to a sigtramp
4006 i386_sigtramp_p (struct frame_info
*this_frame
)
4008 CORE_ADDR pc
= get_frame_pc (this_frame
);
4011 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4012 return (name
&& strcmp ("_sigtramp", name
) == 0);
4016 /* We have two flavours of disassembly. The machinery on this page
4017 deals with switching between those. */
4020 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4022 gdb_assert (disassembly_flavor
== att_flavor
4023 || disassembly_flavor
== intel_flavor
);
4025 info
->disassembler_options
= disassembly_flavor
;
4027 return default_print_insn (pc
, info
);
4031 /* There are a few i386 architecture variants that differ only
4032 slightly from the generic i386 target. For now, we don't give them
4033 their own source file, but include them here. As a consequence,
4034 they'll always be included. */
4036 /* System V Release 4 (SVR4). */
4038 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4042 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
4044 CORE_ADDR pc
= get_frame_pc (this_frame
);
4047 /* The origin of these symbols is currently unknown. */
4048 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4049 return (name
&& (strcmp ("_sigreturn", name
) == 0
4050 || strcmp ("sigvechandler", name
) == 0));
4053 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4054 address of the associated sigcontext (ucontext) structure. */
4057 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
4059 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4060 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4064 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4065 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4067 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4072 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4076 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4078 return (*s
== '$' /* Literal number. */
4079 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4080 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4081 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4084 /* Helper function for i386_stap_parse_special_token.
4086 This function parses operands of the form `-8+3+1(%rbp)', which
4087 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4089 Return true if the operand was parsed successfully, false
4092 static expr::operation_up
4093 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4094 struct stap_parse_info
*p
)
4096 const char *s
= p
->arg
;
4098 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4102 long displacements
[3];
4107 got_minus
[0] = false;
4113 got_minus
[0] = true;
4116 if (!isdigit ((unsigned char) *s
))
4119 displacements
[0] = strtol (s
, &endp
, 10);
4122 if (*s
!= '+' && *s
!= '-')
4124 /* We are not dealing with a triplet. */
4128 got_minus
[1] = false;
4134 got_minus
[1] = true;
4137 if (!isdigit ((unsigned char) *s
))
4140 displacements
[1] = strtol (s
, &endp
, 10);
4143 if (*s
!= '+' && *s
!= '-')
4145 /* We are not dealing with a triplet. */
4149 got_minus
[2] = false;
4155 got_minus
[2] = true;
4158 if (!isdigit ((unsigned char) *s
))
4161 displacements
[2] = strtol (s
, &endp
, 10);
4164 if (*s
!= '(' || s
[1] != '%')
4170 while (isalnum (*s
))
4176 len
= s
- start
- 1;
4177 std::string
regname (start
, len
);
4179 if (user_reg_map_name_to_regnum (gdbarch
, regname
.c_str (), len
) == -1)
4180 error (_("Invalid register name `%s' on expression `%s'."),
4181 regname
.c_str (), p
->saved_arg
);
4184 for (i
= 0; i
< 3; i
++)
4186 LONGEST this_val
= displacements
[i
];
4188 this_val
= -this_val
;
4194 using namespace expr
;
4196 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4198 = make_operation
<long_const_operation
> (long_type
, value
);
4201 = make_operation
<register_operation
> (std::move (regname
));
4202 struct type
*void_ptr
= builtin_type (gdbarch
)->builtin_data_ptr
;
4203 reg
= make_operation
<unop_cast_operation
> (std::move (reg
), void_ptr
);
4206 = make_operation
<add_operation
> (std::move (reg
), std::move (offset
));
4207 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4208 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4210 return make_operation
<unop_ind_operation
> (std::move (sum
));
4216 /* Helper function for i386_stap_parse_special_token.
4218 This function parses operands of the form `register base +
4219 (register index * size) + offset', as represented in
4220 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4222 Return true if the operand was parsed successfully, false
4225 static expr::operation_up
4226 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4227 struct stap_parse_info
*p
)
4229 const char *s
= p
->arg
;
4231 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4233 bool offset_minus
= false;
4235 bool size_minus
= false;
4246 offset_minus
= true;
4249 if (offset_minus
&& !isdigit (*s
))
4256 offset
= strtol (s
, &endp
, 10);
4260 if (*s
!= '(' || s
[1] != '%')
4266 while (isalnum (*s
))
4269 if (*s
!= ',' || s
[1] != '%')
4272 len_base
= s
- start
;
4273 std::string
base (start
, len_base
);
4275 if (user_reg_map_name_to_regnum (gdbarch
, base
.c_str (), len_base
) == -1)
4276 error (_("Invalid register name `%s' on expression `%s'."),
4277 base
.c_str (), p
->saved_arg
);
4282 while (isalnum (*s
))
4285 len_index
= s
- start
;
4286 std::string
index (start
, len_index
);
4288 if (user_reg_map_name_to_regnum (gdbarch
, index
.c_str (),
4290 error (_("Invalid register name `%s' on expression `%s'."),
4291 index
.c_str (), p
->saved_arg
);
4293 if (*s
!= ',' && *s
!= ')')
4309 size
= strtol (s
, &endp
, 10);
4319 using namespace expr
;
4321 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4322 operation_up reg
= make_operation
<register_operation
> (std::move (base
));
4329 = make_operation
<long_const_operation
> (long_type
, offset
);
4330 reg
= make_operation
<add_operation
> (std::move (reg
),
4334 operation_up ind_reg
4335 = make_operation
<register_operation
> (std::move (index
));
4342 = make_operation
<long_const_operation
> (long_type
, size
);
4343 ind_reg
= make_operation
<mul_operation
> (std::move (ind_reg
),
4348 = make_operation
<add_operation
> (std::move (reg
),
4349 std::move (ind_reg
));
4351 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4352 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4354 return make_operation
<unop_ind_operation
> (std::move (sum
));
4360 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4364 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4365 struct stap_parse_info
*p
)
4367 /* The special tokens to be parsed here are:
4369 - `register base + (register index * size) + offset', as represented
4370 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4372 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4373 `*(-8 + 3 - 1 + (void *) $eax)'. */
4375 expr::operation_up result
4376 = i386_stap_parse_special_token_triplet (gdbarch
, p
);
4378 if (result
== nullptr)
4379 result
= i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
);
4384 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4388 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4389 const std::string
®name
, int regnum
)
4391 static const std::unordered_set
<std::string
> reg_assoc
4392 = { "ax", "bx", "cx", "dx",
4393 "si", "di", "bp", "sp" };
4395 /* If we are dealing with a register whose size is less than the size
4396 specified by the "[-]N@" prefix, and it is one of the registers that
4397 we know has an extended variant available, then use the extended
4398 version of the register instead. */
4399 if (register_size (gdbarch
, regnum
) < TYPE_LENGTH (p
->arg_type
)
4400 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4401 return "e" + regname
;
4403 /* Otherwise, just use the requested register. */
4409 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4410 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4413 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4415 return "(x86_64|i.86)";
4420 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4423 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4425 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4426 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4432 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4434 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4435 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4436 static const char *const stap_register_indirection_prefixes
[] = { "(",
4438 static const char *const stap_register_indirection_suffixes
[] = { ")",
4441 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4442 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4444 /* Registering SystemTap handlers. */
4445 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4446 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4447 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4448 stap_register_indirection_prefixes
);
4449 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4450 stap_register_indirection_suffixes
);
4451 set_gdbarch_stap_is_single_operand (gdbarch
,
4452 i386_stap_is_single_operand
);
4453 set_gdbarch_stap_parse_special_token (gdbarch
,
4454 i386_stap_parse_special_token
);
4455 set_gdbarch_stap_adjust_register (gdbarch
,
4456 i386_stap_adjust_register
);
4458 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4459 i386_in_indirect_branch_thunk
);
4462 /* System V Release 4 (SVR4). */
4465 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4469 /* System V Release 4 uses ELF. */
4470 i386_elf_init_abi (info
, gdbarch
);
4472 /* System V Release 4 has shared libraries. */
4473 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4475 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4476 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4477 tdep
->sc_pc_offset
= 36 + 14 * 4;
4478 tdep
->sc_sp_offset
= 36 + 17 * 4;
4480 tdep
->jb_pc_offset
= 20;
4485 /* i386 register groups. In addition to the normal groups, add "mmx"
4488 static struct reggroup
*i386_sse_reggroup
;
4489 static struct reggroup
*i386_mmx_reggroup
;
4492 i386_init_reggroups (void)
4494 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4495 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4499 i386_add_reggroups (struct gdbarch
*gdbarch
)
4501 reggroup_add (gdbarch
, i386_sse_reggroup
);
4502 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4503 reggroup_add (gdbarch
, general_reggroup
);
4504 reggroup_add (gdbarch
, float_reggroup
);
4505 reggroup_add (gdbarch
, all_reggroup
);
4506 reggroup_add (gdbarch
, save_reggroup
);
4507 reggroup_add (gdbarch
, restore_reggroup
);
4508 reggroup_add (gdbarch
, vector_reggroup
);
4509 reggroup_add (gdbarch
, system_reggroup
);
4513 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4514 struct reggroup
*group
)
4516 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4517 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4518 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4519 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4520 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4521 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4523 /* Don't include pseudo registers, except for MMX, in any register
4525 if (i386_byte_regnum_p (gdbarch
, regnum
))
4528 if (i386_word_regnum_p (gdbarch
, regnum
))
4531 if (i386_dword_regnum_p (gdbarch
, regnum
))
4534 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4535 if (group
== i386_mmx_reggroup
)
4536 return mmx_regnum_p
;
4538 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4539 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4540 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4541 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4542 if (group
== i386_sse_reggroup
)
4543 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4545 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4546 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4547 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4549 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4550 == X86_XSTATE_AVX_AVX512_MASK
);
4551 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4552 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4553 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4554 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4556 if (group
== vector_reggroup
)
4557 return (mmx_regnum_p
4558 || (zmm_regnum_p
&& avx512_p
)
4559 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4560 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4563 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4564 || i386_fpc_regnum_p (gdbarch
, regnum
));
4565 if (group
== float_reggroup
)
4568 /* For "info reg all", don't include upper YMM registers nor XMM
4569 registers when AVX is supported. */
4570 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4571 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4572 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4573 if (group
== all_reggroup
4574 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4575 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4577 || ymmh_avx512_regnum_p
4581 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4582 if (group
== all_reggroup
4583 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4584 return bnd_regnum_p
;
4586 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4587 if (group
== all_reggroup
4588 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4591 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4592 if (group
== all_reggroup
4593 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4594 return mpx_ctrl_regnum_p
;
4596 if (group
== general_reggroup
)
4597 return (!fp_regnum_p
4601 && !xmm_avx512_regnum_p
4604 && !ymm_avx512_regnum_p
4605 && !ymmh_avx512_regnum_p
4608 && !mpx_ctrl_regnum_p
4613 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4617 /* Get the ARGIth function argument for the current function. */
4620 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
4623 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4624 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4625 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4626 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4629 #define PREFIX_REPZ 0x01
4630 #define PREFIX_REPNZ 0x02
4631 #define PREFIX_LOCK 0x04
4632 #define PREFIX_DATA 0x08
4633 #define PREFIX_ADDR 0x10
4645 /* i386 arith/logic operations */
4658 struct i386_record_s
4660 struct gdbarch
*gdbarch
;
4661 struct regcache
*regcache
;
4662 CORE_ADDR orig_addr
;
4668 uint8_t mod
, reg
, rm
;
4677 /* Parse the "modrm" part of the memory address irp->addr points at.
4678 Returns -1 if something goes wrong, 0 otherwise. */
4681 i386_record_modrm (struct i386_record_s
*irp
)
4683 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4685 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4689 irp
->mod
= (irp
->modrm
>> 6) & 3;
4690 irp
->reg
= (irp
->modrm
>> 3) & 7;
4691 irp
->rm
= irp
->modrm
& 7;
4696 /* Extract the memory address that the current instruction writes to,
4697 and return it in *ADDR. Return -1 if something goes wrong. */
4700 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4702 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4708 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4715 uint8_t base
= irp
->rm
;
4720 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4723 scale
= (byte
>> 6) & 3;
4724 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4732 if ((base
& 7) == 5)
4735 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4738 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4739 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4740 *addr
+= irp
->addr
+ irp
->rip_offset
;
4744 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4747 *addr
= (int8_t) buf
[0];
4750 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4752 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4760 if (base
== 4 && irp
->popl_esp_hack
)
4761 *addr
+= irp
->popl_esp_hack
;
4762 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4765 if (irp
->aflag
== 2)
4770 *addr
= (uint32_t) (offset64
+ *addr
);
4772 if (havesib
&& (index
!= 4 || scale
!= 0))
4774 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4776 if (irp
->aflag
== 2)
4777 *addr
+= offset64
<< scale
;
4779 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4784 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4785 address from 32-bit to 64-bit. */
4786 *addr
= (uint32_t) *addr
;
4797 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4800 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4806 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4809 *addr
= (int8_t) buf
[0];
4812 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4815 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4822 regcache_raw_read_unsigned (irp
->regcache
,
4823 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4825 *addr
= (uint32_t) (*addr
+ offset64
);
4826 regcache_raw_read_unsigned (irp
->regcache
,
4827 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4829 *addr
= (uint32_t) (*addr
+ offset64
);
4832 regcache_raw_read_unsigned (irp
->regcache
,
4833 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4835 *addr
= (uint32_t) (*addr
+ offset64
);
4836 regcache_raw_read_unsigned (irp
->regcache
,
4837 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4839 *addr
= (uint32_t) (*addr
+ offset64
);
4842 regcache_raw_read_unsigned (irp
->regcache
,
4843 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4845 *addr
= (uint32_t) (*addr
+ offset64
);
4846 regcache_raw_read_unsigned (irp
->regcache
,
4847 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4849 *addr
= (uint32_t) (*addr
+ offset64
);
4852 regcache_raw_read_unsigned (irp
->regcache
,
4853 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4855 *addr
= (uint32_t) (*addr
+ offset64
);
4856 regcache_raw_read_unsigned (irp
->regcache
,
4857 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4859 *addr
= (uint32_t) (*addr
+ offset64
);
4862 regcache_raw_read_unsigned (irp
->regcache
,
4863 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4865 *addr
= (uint32_t) (*addr
+ offset64
);
4868 regcache_raw_read_unsigned (irp
->regcache
,
4869 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4871 *addr
= (uint32_t) (*addr
+ offset64
);
4874 regcache_raw_read_unsigned (irp
->regcache
,
4875 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4877 *addr
= (uint32_t) (*addr
+ offset64
);
4880 regcache_raw_read_unsigned (irp
->regcache
,
4881 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4883 *addr
= (uint32_t) (*addr
+ offset64
);
4893 /* Record the address and contents of the memory that will be changed
4894 by the current instruction. Return -1 if something goes wrong, 0
4898 i386_record_lea_modrm (struct i386_record_s
*irp
)
4900 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4903 if (irp
->override
>= 0)
4905 if (record_full_memory_query
)
4908 Process record ignores the memory change of instruction at address %s\n\
4909 because it can't get the value of the segment register.\n\
4910 Do you want to stop the program?"),
4911 paddress (gdbarch
, irp
->orig_addr
)))
4918 if (i386_record_lea_modrm_addr (irp
, &addr
))
4921 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
4927 /* Record the effects of a push operation. Return -1 if something
4928 goes wrong, 0 otherwise. */
4931 i386_record_push (struct i386_record_s
*irp
, int size
)
4935 if (record_full_arch_list_add_reg (irp
->regcache
,
4936 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
4938 regcache_raw_read_unsigned (irp
->regcache
,
4939 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
4941 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
4948 /* Defines contents to record. */
4949 #define I386_SAVE_FPU_REGS 0xfffd
4950 #define I386_SAVE_FPU_ENV 0xfffe
4951 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
4953 /* Record the values of the floating point registers which will be
4954 changed by the current instruction. Returns -1 if something is
4955 wrong, 0 otherwise. */
4957 static int i386_record_floats (struct gdbarch
*gdbarch
,
4958 struct i386_record_s
*ir
,
4961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4964 /* Oza: Because of floating point insn push/pop of fpu stack is going to
4965 happen. Currently we store st0-st7 registers, but we need not store all
4966 registers all the time, in future we use ftag register and record only
4967 those who are not marked as an empty. */
4969 if (I386_SAVE_FPU_REGS
== iregnum
)
4971 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
4973 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4977 else if (I386_SAVE_FPU_ENV
== iregnum
)
4979 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4981 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4985 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
4987 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
4988 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
4991 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
4992 (iregnum
<= I387_FOP_REGNUM (tdep
)))
4994 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
4999 /* Parameter error. */
5002 if(I386_SAVE_FPU_ENV
!= iregnum
)
5004 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5006 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5013 /* Parse the current instruction, and record the values of the
5014 registers and memory that will be changed by the current
5015 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5017 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5018 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5021 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5022 CORE_ADDR input_addr
)
5024 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5030 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5031 struct i386_record_s ir
;
5032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5036 memset (&ir
, 0, sizeof (struct i386_record_s
));
5037 ir
.regcache
= regcache
;
5038 ir
.addr
= input_addr
;
5039 ir
.orig_addr
= input_addr
;
5043 ir
.popl_esp_hack
= 0;
5044 ir
.regmap
= tdep
->record_regmap
;
5045 ir
.gdbarch
= gdbarch
;
5047 if (record_debug
> 1)
5048 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
5050 paddress (gdbarch
, ir
.addr
));
5055 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5058 switch (opcode8
) /* Instruction prefixes */
5060 case REPE_PREFIX_OPCODE
:
5061 prefixes
|= PREFIX_REPZ
;
5063 case REPNE_PREFIX_OPCODE
:
5064 prefixes
|= PREFIX_REPNZ
;
5066 case LOCK_PREFIX_OPCODE
:
5067 prefixes
|= PREFIX_LOCK
;
5069 case CS_PREFIX_OPCODE
:
5070 ir
.override
= X86_RECORD_CS_REGNUM
;
5072 case SS_PREFIX_OPCODE
:
5073 ir
.override
= X86_RECORD_SS_REGNUM
;
5075 case DS_PREFIX_OPCODE
:
5076 ir
.override
= X86_RECORD_DS_REGNUM
;
5078 case ES_PREFIX_OPCODE
:
5079 ir
.override
= X86_RECORD_ES_REGNUM
;
5081 case FS_PREFIX_OPCODE
:
5082 ir
.override
= X86_RECORD_FS_REGNUM
;
5084 case GS_PREFIX_OPCODE
:
5085 ir
.override
= X86_RECORD_GS_REGNUM
;
5087 case DATA_PREFIX_OPCODE
:
5088 prefixes
|= PREFIX_DATA
;
5090 case ADDR_PREFIX_OPCODE
:
5091 prefixes
|= PREFIX_ADDR
;
5093 case 0x40: /* i386 inc %eax */
5094 case 0x41: /* i386 inc %ecx */
5095 case 0x42: /* i386 inc %edx */
5096 case 0x43: /* i386 inc %ebx */
5097 case 0x44: /* i386 inc %esp */
5098 case 0x45: /* i386 inc %ebp */
5099 case 0x46: /* i386 inc %esi */
5100 case 0x47: /* i386 inc %edi */
5101 case 0x48: /* i386 dec %eax */
5102 case 0x49: /* i386 dec %ecx */
5103 case 0x4a: /* i386 dec %edx */
5104 case 0x4b: /* i386 dec %ebx */
5105 case 0x4c: /* i386 dec %esp */
5106 case 0x4d: /* i386 dec %ebp */
5107 case 0x4e: /* i386 dec %esi */
5108 case 0x4f: /* i386 dec %edi */
5109 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5112 rex_w
= (opcode8
>> 3) & 1;
5113 rex_r
= (opcode8
& 0x4) << 1;
5114 ir
.rex_x
= (opcode8
& 0x2) << 2;
5115 ir
.rex_b
= (opcode8
& 0x1) << 3;
5117 else /* 32 bit target */
5126 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5132 if (prefixes
& PREFIX_DATA
)
5135 if (prefixes
& PREFIX_ADDR
)
5137 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5140 /* Now check op code. */
5141 opcode
= (uint32_t) opcode8
;
5146 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5149 opcode
= (uint32_t) opcode8
| 0x0f00;
5153 case 0x00: /* arith & logic */
5201 if (((opcode
>> 3) & 7) != OP_CMPL
)
5203 if ((opcode
& 1) == 0)
5206 ir
.ot
= ir
.dflag
+ OT_WORD
;
5208 switch ((opcode
>> 1) & 3)
5210 case 0: /* OP Ev, Gv */
5211 if (i386_record_modrm (&ir
))
5215 if (i386_record_lea_modrm (&ir
))
5221 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5223 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5226 case 1: /* OP Gv, Ev */
5227 if (i386_record_modrm (&ir
))
5230 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5232 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5234 case 2: /* OP A, Iv */
5235 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5239 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5242 case 0x80: /* GRP1 */
5246 if (i386_record_modrm (&ir
))
5249 if (ir
.reg
!= OP_CMPL
)
5251 if ((opcode
& 1) == 0)
5254 ir
.ot
= ir
.dflag
+ OT_WORD
;
5261 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5262 if (i386_record_lea_modrm (&ir
))
5266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5268 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5271 case 0x40: /* inc */
5280 case 0x48: /* dec */
5289 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5290 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5293 case 0xf6: /* GRP3 */
5295 if ((opcode
& 1) == 0)
5298 ir
.ot
= ir
.dflag
+ OT_WORD
;
5299 if (i386_record_modrm (&ir
))
5302 if (ir
.mod
!= 3 && ir
.reg
== 0)
5303 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5314 if (i386_record_lea_modrm (&ir
))
5320 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5322 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5324 if (ir
.reg
== 3) /* neg */
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5332 if (ir
.ot
!= OT_BYTE
)
5333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5334 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5338 opcode
= opcode
<< 8 | ir
.modrm
;
5344 case 0xfe: /* GRP4 */
5345 case 0xff: /* GRP5 */
5346 if (i386_record_modrm (&ir
))
5348 if (ir
.reg
>= 2 && opcode
== 0xfe)
5351 opcode
= opcode
<< 8 | ir
.modrm
;
5358 if ((opcode
& 1) == 0)
5361 ir
.ot
= ir
.dflag
+ OT_WORD
;
5364 if (i386_record_lea_modrm (&ir
))
5370 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5374 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5377 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5379 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5385 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5391 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5394 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5396 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5401 opcode
= opcode
<< 8 | ir
.modrm
;
5407 case 0x84: /* test */
5411 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5414 case 0x98: /* CWDE/CBW */
5415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5418 case 0x99: /* CDQ/CWD */
5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5420 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5423 case 0x0faf: /* imul */
5426 ir
.ot
= ir
.dflag
+ OT_WORD
;
5427 if (i386_record_modrm (&ir
))
5430 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5431 else if (opcode
== 0x6b)
5434 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5436 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5437 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5440 case 0x0fc0: /* xadd */
5442 if ((opcode
& 1) == 0)
5445 ir
.ot
= ir
.dflag
+ OT_WORD
;
5446 if (i386_record_modrm (&ir
))
5451 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5454 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5460 if (i386_record_lea_modrm (&ir
))
5462 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5464 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5469 case 0x0fb0: /* cmpxchg */
5471 if ((opcode
& 1) == 0)
5474 ir
.ot
= ir
.dflag
+ OT_WORD
;
5475 if (i386_record_modrm (&ir
))
5480 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5481 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5483 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5487 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5488 if (i386_record_lea_modrm (&ir
))
5491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5494 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5495 if (i386_record_modrm (&ir
))
5499 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5500 an extended opcode. rdrand has bits 110 (/6) and rdseed
5501 has bits 111 (/7). */
5502 if (ir
.reg
== 6 || ir
.reg
== 7)
5504 /* The storage register is described by the 3 R/M bits, but the
5505 REX.B prefix may be used to give access to registers
5506 R8~R15. In this case ir.rex_b + R/M will give us the register
5507 in the range R8~R15.
5509 REX.W may also be used to access 64-bit registers, but we
5510 already record entire registers and not just partial bits
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5513 /* These instructions also set conditional bits. */
5514 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5519 /* We don't handle this particular instruction yet. */
5521 opcode
= opcode
<< 8 | ir
.modrm
;
5525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5527 if (i386_record_lea_modrm (&ir
))
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5532 case 0x50: /* push */
5542 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5544 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5548 case 0x06: /* push es */
5549 case 0x0e: /* push cs */
5550 case 0x16: /* push ss */
5551 case 0x1e: /* push ds */
5552 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5557 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5561 case 0x0fa0: /* push fs */
5562 case 0x0fa8: /* push gs */
5563 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5568 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5572 case 0x60: /* pusha */
5573 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5578 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5582 case 0x58: /* pop */
5590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5591 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5594 case 0x61: /* popa */
5595 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5600 for (regnum
= X86_RECORD_REAX_REGNUM
;
5601 regnum
<= X86_RECORD_REDI_REGNUM
;
5603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5606 case 0x8f: /* pop */
5607 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5608 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5610 ir
.ot
= ir
.dflag
+ OT_WORD
;
5611 if (i386_record_modrm (&ir
))
5614 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5617 ir
.popl_esp_hack
= 1 << ir
.ot
;
5618 if (i386_record_lea_modrm (&ir
))
5621 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5624 case 0xc8: /* enter */
5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5626 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5628 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5632 case 0xc9: /* leave */
5633 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5637 case 0x07: /* pop es */
5638 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5643 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5648 case 0x17: /* pop ss */
5649 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5654 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5655 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5659 case 0x1f: /* pop ds */
5660 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5666 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5667 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5670 case 0x0fa1: /* pop fs */
5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5672 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5673 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5676 case 0x0fa9: /* pop gs */
5677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5682 case 0x88: /* mov */
5686 if ((opcode
& 1) == 0)
5689 ir
.ot
= ir
.dflag
+ OT_WORD
;
5691 if (i386_record_modrm (&ir
))
5696 if (opcode
== 0xc6 || opcode
== 0xc7)
5697 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5698 if (i386_record_lea_modrm (&ir
))
5703 if (opcode
== 0xc6 || opcode
== 0xc7)
5705 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5711 case 0x8a: /* mov */
5713 if ((opcode
& 1) == 0)
5716 ir
.ot
= ir
.dflag
+ OT_WORD
;
5717 if (i386_record_modrm (&ir
))
5720 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5722 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5725 case 0x8c: /* mov seg */
5726 if (i386_record_modrm (&ir
))
5731 opcode
= opcode
<< 8 | ir
.modrm
;
5736 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5740 if (i386_record_lea_modrm (&ir
))
5745 case 0x8e: /* mov seg */
5746 if (i386_record_modrm (&ir
))
5751 regnum
= X86_RECORD_ES_REGNUM
;
5754 regnum
= X86_RECORD_SS_REGNUM
;
5757 regnum
= X86_RECORD_DS_REGNUM
;
5760 regnum
= X86_RECORD_FS_REGNUM
;
5763 regnum
= X86_RECORD_GS_REGNUM
;
5767 opcode
= opcode
<< 8 | ir
.modrm
;
5771 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5775 case 0x0fb6: /* movzbS */
5776 case 0x0fb7: /* movzwS */
5777 case 0x0fbe: /* movsbS */
5778 case 0x0fbf: /* movswS */
5779 if (i386_record_modrm (&ir
))
5781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5784 case 0x8d: /* lea */
5785 if (i386_record_modrm (&ir
))
5790 opcode
= opcode
<< 8 | ir
.modrm
;
5795 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5797 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5800 case 0xa0: /* mov EAX */
5803 case 0xd7: /* xlat */
5804 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5807 case 0xa2: /* mov EAX */
5809 if (ir
.override
>= 0)
5811 if (record_full_memory_query
)
5814 Process record ignores the memory change of instruction at address %s\n\
5815 because it can't get the value of the segment register.\n\
5816 Do you want to stop the program?"),
5817 paddress (gdbarch
, ir
.orig_addr
)))
5823 if ((opcode
& 1) == 0)
5826 ir
.ot
= ir
.dflag
+ OT_WORD
;
5829 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5832 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5836 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5839 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5843 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5846 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5848 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5853 case 0xb0: /* mov R, Ib */
5861 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5862 ? ((opcode
& 0x7) | ir
.rex_b
)
5863 : ((opcode
& 0x7) & 0x3));
5866 case 0xb8: /* mov R, Iv */
5874 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5877 case 0x91: /* xchg R, EAX */
5884 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5885 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5888 case 0x86: /* xchg Ev, Gv */
5890 if ((opcode
& 1) == 0)
5893 ir
.ot
= ir
.dflag
+ OT_WORD
;
5894 if (i386_record_modrm (&ir
))
5899 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5901 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5905 if (i386_record_lea_modrm (&ir
))
5909 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5911 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5914 case 0xc4: /* les Gv */
5915 case 0xc5: /* lds Gv */
5916 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5922 case 0x0fb2: /* lss Gv */
5923 case 0x0fb4: /* lfs Gv */
5924 case 0x0fb5: /* lgs Gv */
5925 if (i386_record_modrm (&ir
))
5933 opcode
= opcode
<< 8 | ir
.modrm
;
5938 case 0xc4: /* les Gv */
5939 regnum
= X86_RECORD_ES_REGNUM
;
5941 case 0xc5: /* lds Gv */
5942 regnum
= X86_RECORD_DS_REGNUM
;
5944 case 0x0fb2: /* lss Gv */
5945 regnum
= X86_RECORD_SS_REGNUM
;
5947 case 0x0fb4: /* lfs Gv */
5948 regnum
= X86_RECORD_FS_REGNUM
;
5950 case 0x0fb5: /* lgs Gv */
5951 regnum
= X86_RECORD_GS_REGNUM
;
5954 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5955 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5956 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5959 case 0xc0: /* shifts */
5965 if ((opcode
& 1) == 0)
5968 ir
.ot
= ir
.dflag
+ OT_WORD
;
5969 if (i386_record_modrm (&ir
))
5971 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
5973 if (i386_record_lea_modrm (&ir
))
5979 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5990 if (i386_record_modrm (&ir
))
5994 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
5999 if (i386_record_lea_modrm (&ir
))
6004 case 0xd8: /* Floats. */
6012 if (i386_record_modrm (&ir
))
6014 ir
.reg
|= ((opcode
& 7) << 3);
6020 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6028 /* For fcom, ficom nothing to do. */
6034 /* For fcomp, ficomp pop FPU stack, store all. */
6035 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6062 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6063 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6064 of code, always affects st(0) register. */
6065 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6089 /* Handling fld, fild. */
6090 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6094 switch (ir
.reg
>> 4)
6097 if (record_full_arch_list_add_mem (addr64
, 4))
6101 if (record_full_arch_list_add_mem (addr64
, 8))
6107 if (record_full_arch_list_add_mem (addr64
, 2))
6113 switch (ir
.reg
>> 4)
6116 if (record_full_arch_list_add_mem (addr64
, 4))
6118 if (3 == (ir
.reg
& 7))
6120 /* For fstp m32fp. */
6121 if (i386_record_floats (gdbarch
, &ir
,
6122 I386_SAVE_FPU_REGS
))
6127 if (record_full_arch_list_add_mem (addr64
, 4))
6129 if ((3 == (ir
.reg
& 7))
6130 || (5 == (ir
.reg
& 7))
6131 || (7 == (ir
.reg
& 7)))
6133 /* For fstp insn. */
6134 if (i386_record_floats (gdbarch
, &ir
,
6135 I386_SAVE_FPU_REGS
))
6140 if (record_full_arch_list_add_mem (addr64
, 8))
6142 if (3 == (ir
.reg
& 7))
6144 /* For fstp m64fp. */
6145 if (i386_record_floats (gdbarch
, &ir
,
6146 I386_SAVE_FPU_REGS
))
6151 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6153 /* For fistp, fbld, fild, fbstp. */
6154 if (i386_record_floats (gdbarch
, &ir
,
6155 I386_SAVE_FPU_REGS
))
6160 if (record_full_arch_list_add_mem (addr64
, 2))
6169 if (i386_record_floats (gdbarch
, &ir
,
6170 I386_SAVE_FPU_ENV_REG_STACK
))
6175 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6180 if (i386_record_floats (gdbarch
, &ir
,
6181 I386_SAVE_FPU_ENV_REG_STACK
))
6187 if (record_full_arch_list_add_mem (addr64
, 28))
6192 if (record_full_arch_list_add_mem (addr64
, 14))
6198 if (record_full_arch_list_add_mem (addr64
, 2))
6200 /* Insn fstp, fbstp. */
6201 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6206 if (record_full_arch_list_add_mem (addr64
, 10))
6212 if (record_full_arch_list_add_mem (addr64
, 28))
6218 if (record_full_arch_list_add_mem (addr64
, 14))
6222 if (record_full_arch_list_add_mem (addr64
, 80))
6225 if (i386_record_floats (gdbarch
, &ir
,
6226 I386_SAVE_FPU_ENV_REG_STACK
))
6230 if (record_full_arch_list_add_mem (addr64
, 8))
6233 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6238 opcode
= opcode
<< 8 | ir
.modrm
;
6243 /* Opcode is an extension of modR/M byte. */
6249 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6253 if (0x0c == (ir
.modrm
>> 4))
6255 if ((ir
.modrm
& 0x0f) <= 7)
6257 if (i386_record_floats (gdbarch
, &ir
,
6258 I386_SAVE_FPU_REGS
))
6263 if (i386_record_floats (gdbarch
, &ir
,
6264 I387_ST0_REGNUM (tdep
)))
6266 /* If only st(0) is changing, then we have already
6268 if ((ir
.modrm
& 0x0f) - 0x08)
6270 if (i386_record_floats (gdbarch
, &ir
,
6271 I387_ST0_REGNUM (tdep
) +
6272 ((ir
.modrm
& 0x0f) - 0x08)))
6290 if (i386_record_floats (gdbarch
, &ir
,
6291 I387_ST0_REGNUM (tdep
)))
6309 if (i386_record_floats (gdbarch
, &ir
,
6310 I386_SAVE_FPU_REGS
))
6314 if (i386_record_floats (gdbarch
, &ir
,
6315 I387_ST0_REGNUM (tdep
)))
6317 if (i386_record_floats (gdbarch
, &ir
,
6318 I387_ST0_REGNUM (tdep
) + 1))
6325 if (0xe9 == ir
.modrm
)
6327 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6330 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6332 if (i386_record_floats (gdbarch
, &ir
,
6333 I387_ST0_REGNUM (tdep
)))
6335 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6337 if (i386_record_floats (gdbarch
, &ir
,
6338 I387_ST0_REGNUM (tdep
) +
6342 else if ((ir
.modrm
& 0x0f) - 0x08)
6344 if (i386_record_floats (gdbarch
, &ir
,
6345 I387_ST0_REGNUM (tdep
) +
6346 ((ir
.modrm
& 0x0f) - 0x08)))
6352 if (0xe3 == ir
.modrm
)
6354 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6357 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6359 if (i386_record_floats (gdbarch
, &ir
,
6360 I387_ST0_REGNUM (tdep
)))
6362 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6364 if (i386_record_floats (gdbarch
, &ir
,
6365 I387_ST0_REGNUM (tdep
) +
6369 else if ((ir
.modrm
& 0x0f) - 0x08)
6371 if (i386_record_floats (gdbarch
, &ir
,
6372 I387_ST0_REGNUM (tdep
) +
6373 ((ir
.modrm
& 0x0f) - 0x08)))
6379 if ((0x0c == ir
.modrm
>> 4)
6380 || (0x0d == ir
.modrm
>> 4)
6381 || (0x0f == ir
.modrm
>> 4))
6383 if ((ir
.modrm
& 0x0f) <= 7)
6385 if (i386_record_floats (gdbarch
, &ir
,
6386 I387_ST0_REGNUM (tdep
) +
6392 if (i386_record_floats (gdbarch
, &ir
,
6393 I387_ST0_REGNUM (tdep
) +
6394 ((ir
.modrm
& 0x0f) - 0x08)))
6400 if (0x0c == ir
.modrm
>> 4)
6402 if (i386_record_floats (gdbarch
, &ir
,
6403 I387_FTAG_REGNUM (tdep
)))
6406 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6408 if ((ir
.modrm
& 0x0f) <= 7)
6410 if (i386_record_floats (gdbarch
, &ir
,
6411 I387_ST0_REGNUM (tdep
) +
6417 if (i386_record_floats (gdbarch
, &ir
,
6418 I386_SAVE_FPU_REGS
))
6424 if ((0x0c == ir
.modrm
>> 4)
6425 || (0x0e == ir
.modrm
>> 4)
6426 || (0x0f == ir
.modrm
>> 4)
6427 || (0xd9 == ir
.modrm
))
6429 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6434 if (0xe0 == ir
.modrm
)
6436 if (record_full_arch_list_add_reg (ir
.regcache
,
6440 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6442 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6450 case 0xa4: /* movsS */
6452 case 0xaa: /* stosS */
6454 case 0x6c: /* insS */
6456 regcache_raw_read_unsigned (ir
.regcache
,
6457 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6463 if ((opcode
& 1) == 0)
6466 ir
.ot
= ir
.dflag
+ OT_WORD
;
6467 regcache_raw_read_unsigned (ir
.regcache
,
6468 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6471 regcache_raw_read_unsigned (ir
.regcache
,
6472 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6474 regcache_raw_read_unsigned (ir
.regcache
,
6475 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6477 if (ir
.aflag
&& (es
!= ds
))
6479 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6480 if (record_full_memory_query
)
6483 Process record ignores the memory change of instruction at address %s\n\
6484 because it can't get the value of the segment register.\n\
6485 Do you want to stop the program?"),
6486 paddress (gdbarch
, ir
.orig_addr
)))
6492 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6496 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6497 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6498 if (opcode
== 0xa4 || opcode
== 0xa5)
6499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6505 case 0xa6: /* cmpsS */
6507 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6509 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6514 case 0xac: /* lodsS */
6516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6518 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6523 case 0xae: /* scasS */
6525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6526 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6528 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6531 case 0x6e: /* outsS */
6533 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6534 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6536 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6539 case 0xe4: /* port I/O */
6543 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6544 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6554 case 0xc2: /* ret im */
6555 case 0xc3: /* ret */
6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6560 case 0xca: /* lret im */
6561 case 0xcb: /* lret */
6562 case 0xcf: /* iret */
6563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6568 case 0xe8: /* call im */
6569 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6571 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6575 case 0x9a: /* lcall im */
6576 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6582 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6586 case 0xe9: /* jmp im */
6587 case 0xea: /* ljmp im */
6588 case 0xeb: /* jmp Jb */
6589 case 0x70: /* jcc Jb */
6605 case 0x0f80: /* jcc Jv */
6623 case 0x0f90: /* setcc Gv */
6639 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6641 if (i386_record_modrm (&ir
))
6644 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6648 if (i386_record_lea_modrm (&ir
))
6653 case 0x0f40: /* cmov Gv, Ev */
6669 if (i386_record_modrm (&ir
))
6672 if (ir
.dflag
== OT_BYTE
)
6674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6678 case 0x9c: /* pushf */
6679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6680 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6682 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6686 case 0x9d: /* popf */
6687 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6688 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6691 case 0x9e: /* sahf */
6692 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6698 case 0xf5: /* cmc */
6699 case 0xf8: /* clc */
6700 case 0xf9: /* stc */
6701 case 0xfc: /* cld */
6702 case 0xfd: /* std */
6703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6706 case 0x9f: /* lahf */
6707 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6716 /* bit operations */
6717 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6718 ir
.ot
= ir
.dflag
+ OT_WORD
;
6719 if (i386_record_modrm (&ir
))
6724 opcode
= opcode
<< 8 | ir
.modrm
;
6730 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6733 if (i386_record_lea_modrm (&ir
))
6737 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6740 case 0x0fa3: /* bt Gv, Ev */
6741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6744 case 0x0fab: /* bts */
6745 case 0x0fb3: /* btr */
6746 case 0x0fbb: /* btc */
6747 ir
.ot
= ir
.dflag
+ OT_WORD
;
6748 if (i386_record_modrm (&ir
))
6751 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6755 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6757 regcache_raw_read_unsigned (ir
.regcache
,
6758 ir
.regmap
[ir
.reg
| rex_r
],
6763 addr64
+= ((int16_t) addr
>> 4) << 4;
6766 addr64
+= ((int32_t) addr
>> 5) << 5;
6769 addr64
+= ((int64_t) addr
>> 6) << 6;
6772 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6774 if (i386_record_lea_modrm (&ir
))
6777 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6780 case 0x0fbc: /* bsf */
6781 case 0x0fbd: /* bsr */
6782 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6783 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6787 case 0x27: /* daa */
6788 case 0x2f: /* das */
6789 case 0x37: /* aaa */
6790 case 0x3f: /* aas */
6791 case 0xd4: /* aam */
6792 case 0xd5: /* aad */
6793 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6798 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6799 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6803 case 0x90: /* nop */
6804 if (prefixes
& PREFIX_LOCK
)
6811 case 0x9b: /* fwait */
6812 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6814 opcode
= (uint32_t) opcode8
;
6820 case 0xcc: /* int3 */
6821 printf_unfiltered (_("Process record does not support instruction "
6828 case 0xcd: /* int */
6832 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6835 if (interrupt
!= 0x80
6836 || tdep
->i386_intx80_record
== NULL
)
6838 printf_unfiltered (_("Process record does not support "
6839 "instruction int 0x%02x.\n"),
6844 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6851 case 0xce: /* into */
6852 printf_unfiltered (_("Process record does not support "
6853 "instruction into.\n"));
6858 case 0xfa: /* cli */
6859 case 0xfb: /* sti */
6862 case 0x62: /* bound */
6863 printf_unfiltered (_("Process record does not support "
6864 "instruction bound.\n"));
6869 case 0x0fc8: /* bswap reg */
6877 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6880 case 0xd6: /* salc */
6881 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6887 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6890 case 0xe0: /* loopnz */
6891 case 0xe1: /* loopz */
6892 case 0xe2: /* loop */
6893 case 0xe3: /* jecxz */
6894 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6895 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6898 case 0x0f30: /* wrmsr */
6899 printf_unfiltered (_("Process record does not support "
6900 "instruction wrmsr.\n"));
6905 case 0x0f32: /* rdmsr */
6906 printf_unfiltered (_("Process record does not support "
6907 "instruction rdmsr.\n"));
6912 case 0x0f31: /* rdtsc */
6913 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6914 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6917 case 0x0f34: /* sysenter */
6920 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6925 if (tdep
->i386_sysenter_record
== NULL
)
6927 printf_unfiltered (_("Process record does not support "
6928 "instruction sysenter.\n"));
6932 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
6938 case 0x0f35: /* sysexit */
6939 printf_unfiltered (_("Process record does not support "
6940 "instruction sysexit.\n"));
6945 case 0x0f05: /* syscall */
6948 if (tdep
->i386_syscall_record
== NULL
)
6950 printf_unfiltered (_("Process record does not support "
6951 "instruction syscall.\n"));
6955 ret
= tdep
->i386_syscall_record (ir
.regcache
);
6961 case 0x0f07: /* sysret */
6962 printf_unfiltered (_("Process record does not support "
6963 "instruction sysret.\n"));
6968 case 0x0fa2: /* cpuid */
6969 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6970 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6971 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
6972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
6975 case 0xf4: /* hlt */
6976 printf_unfiltered (_("Process record does not support "
6977 "instruction hlt.\n"));
6983 if (i386_record_modrm (&ir
))
6990 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6994 if (i386_record_lea_modrm (&ir
))
7003 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7007 opcode
= opcode
<< 8 | ir
.modrm
;
7014 if (i386_record_modrm (&ir
))
7025 opcode
= opcode
<< 8 | ir
.modrm
;
7028 if (ir
.override
>= 0)
7030 if (record_full_memory_query
)
7033 Process record ignores the memory change of instruction at address %s\n\
7034 because it can't get the value of the segment register.\n\
7035 Do you want to stop the program?"),
7036 paddress (gdbarch
, ir
.orig_addr
)))
7042 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7044 if (record_full_arch_list_add_mem (addr64
, 2))
7047 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7049 if (record_full_arch_list_add_mem (addr64
, 8))
7054 if (record_full_arch_list_add_mem (addr64
, 4))
7065 case 0: /* monitor */
7068 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7072 opcode
= opcode
<< 8 | ir
.modrm
;
7080 if (ir
.override
>= 0)
7082 if (record_full_memory_query
)
7085 Process record ignores the memory change of instruction at address %s\n\
7086 because it can't get the value of the segment register.\n\
7087 Do you want to stop the program?"),
7088 paddress (gdbarch
, ir
.orig_addr
)))
7096 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7098 if (record_full_arch_list_add_mem (addr64
, 2))
7101 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7103 if (record_full_arch_list_add_mem (addr64
, 8))
7108 if (record_full_arch_list_add_mem (addr64
, 4))
7120 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7121 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7125 else if (ir
.rm
== 1)
7133 opcode
= opcode
<< 8 | ir
.modrm
;
7140 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7146 if (i386_record_lea_modrm (&ir
))
7149 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7152 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7154 case 7: /* invlpg */
7157 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7162 opcode
= opcode
<< 8 | ir
.modrm
;
7167 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7171 opcode
= opcode
<< 8 | ir
.modrm
;
7177 case 0x0f08: /* invd */
7178 case 0x0f09: /* wbinvd */
7181 case 0x63: /* arpl */
7182 if (i386_record_modrm (&ir
))
7184 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7187 ? (ir
.reg
| rex_r
) : ir
.rm
);
7191 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7192 if (i386_record_lea_modrm (&ir
))
7195 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7199 case 0x0f02: /* lar */
7200 case 0x0f03: /* lsl */
7201 if (i386_record_modrm (&ir
))
7203 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7204 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7208 if (i386_record_modrm (&ir
))
7210 if (ir
.mod
== 3 && ir
.reg
== 3)
7213 opcode
= opcode
<< 8 | ir
.modrm
;
7225 /* nop (multi byte) */
7228 case 0x0f20: /* mov reg, crN */
7229 case 0x0f22: /* mov crN, reg */
7230 if (i386_record_modrm (&ir
))
7232 if ((ir
.modrm
& 0xc0) != 0xc0)
7235 opcode
= opcode
<< 8 | ir
.modrm
;
7246 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7252 opcode
= opcode
<< 8 | ir
.modrm
;
7258 case 0x0f21: /* mov reg, drN */
7259 case 0x0f23: /* mov drN, reg */
7260 if (i386_record_modrm (&ir
))
7262 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7263 || ir
.reg
== 5 || ir
.reg
>= 8)
7266 opcode
= opcode
<< 8 | ir
.modrm
;
7270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7272 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7275 case 0x0f06: /* clts */
7276 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7279 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7281 case 0x0f0d: /* 3DNow! prefetch */
7284 case 0x0f0e: /* 3DNow! femms */
7285 case 0x0f77: /* emms */
7286 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7288 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7291 case 0x0f0f: /* 3DNow! data */
7292 if (i386_record_modrm (&ir
))
7294 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7299 case 0x0c: /* 3DNow! pi2fw */
7300 case 0x0d: /* 3DNow! pi2fd */
7301 case 0x1c: /* 3DNow! pf2iw */
7302 case 0x1d: /* 3DNow! pf2id */
7303 case 0x8a: /* 3DNow! pfnacc */
7304 case 0x8e: /* 3DNow! pfpnacc */
7305 case 0x90: /* 3DNow! pfcmpge */
7306 case 0x94: /* 3DNow! pfmin */
7307 case 0x96: /* 3DNow! pfrcp */
7308 case 0x97: /* 3DNow! pfrsqrt */
7309 case 0x9a: /* 3DNow! pfsub */
7310 case 0x9e: /* 3DNow! pfadd */
7311 case 0xa0: /* 3DNow! pfcmpgt */
7312 case 0xa4: /* 3DNow! pfmax */
7313 case 0xa6: /* 3DNow! pfrcpit1 */
7314 case 0xa7: /* 3DNow! pfrsqit1 */
7315 case 0xaa: /* 3DNow! pfsubr */
7316 case 0xae: /* 3DNow! pfacc */
7317 case 0xb0: /* 3DNow! pfcmpeq */
7318 case 0xb4: /* 3DNow! pfmul */
7319 case 0xb6: /* 3DNow! pfrcpit2 */
7320 case 0xb7: /* 3DNow! pmulhrw */
7321 case 0xbb: /* 3DNow! pswapd */
7322 case 0xbf: /* 3DNow! pavgusb */
7323 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7324 goto no_support_3dnow_data
;
7325 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7329 no_support_3dnow_data
:
7330 opcode
= (opcode
<< 8) | opcode8
;
7336 case 0x0faa: /* rsm */
7337 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7339 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7340 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7341 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7342 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7343 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7345 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7349 if (i386_record_modrm (&ir
))
7353 case 0: /* fxsave */
7357 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7358 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7360 if (record_full_arch_list_add_mem (tmpu64
, 512))
7365 case 1: /* fxrstor */
7369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7371 for (i
= I387_MM0_REGNUM (tdep
);
7372 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7373 record_full_arch_list_add_reg (ir
.regcache
, i
);
7375 for (i
= I387_XMM0_REGNUM (tdep
);
7376 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7377 record_full_arch_list_add_reg (ir
.regcache
, i
);
7379 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7380 record_full_arch_list_add_reg (ir
.regcache
,
7381 I387_MXCSR_REGNUM(tdep
));
7383 for (i
= I387_ST0_REGNUM (tdep
);
7384 i386_fp_regnum_p (gdbarch
, i
); i
++)
7385 record_full_arch_list_add_reg (ir
.regcache
, i
);
7387 for (i
= I387_FCTRL_REGNUM (tdep
);
7388 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7389 record_full_arch_list_add_reg (ir
.regcache
, i
);
7393 case 2: /* ldmxcsr */
7394 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7396 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7399 case 3: /* stmxcsr */
7401 if (i386_record_lea_modrm (&ir
))
7405 case 5: /* lfence */
7406 case 6: /* mfence */
7407 case 7: /* sfence clflush */
7411 opcode
= (opcode
<< 8) | ir
.modrm
;
7417 case 0x0fc3: /* movnti */
7418 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7419 if (i386_record_modrm (&ir
))
7424 if (i386_record_lea_modrm (&ir
))
7428 /* Add prefix to opcode. */
7543 /* Mask out PREFIX_ADDR. */
7544 switch ((prefixes
& ~PREFIX_ADDR
))
7556 reswitch_prefix_add
:
7564 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7567 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7568 goto reswitch_prefix_add
;
7571 case 0x0f10: /* movups */
7572 case 0x660f10: /* movupd */
7573 case 0xf30f10: /* movss */
7574 case 0xf20f10: /* movsd */
7575 case 0x0f12: /* movlps */
7576 case 0x660f12: /* movlpd */
7577 case 0xf30f12: /* movsldup */
7578 case 0xf20f12: /* movddup */
7579 case 0x0f14: /* unpcklps */
7580 case 0x660f14: /* unpcklpd */
7581 case 0x0f15: /* unpckhps */
7582 case 0x660f15: /* unpckhpd */
7583 case 0x0f16: /* movhps */
7584 case 0x660f16: /* movhpd */
7585 case 0xf30f16: /* movshdup */
7586 case 0x0f28: /* movaps */
7587 case 0x660f28: /* movapd */
7588 case 0x0f2a: /* cvtpi2ps */
7589 case 0x660f2a: /* cvtpi2pd */
7590 case 0xf30f2a: /* cvtsi2ss */
7591 case 0xf20f2a: /* cvtsi2sd */
7592 case 0x0f2c: /* cvttps2pi */
7593 case 0x660f2c: /* cvttpd2pi */
7594 case 0x0f2d: /* cvtps2pi */
7595 case 0x660f2d: /* cvtpd2pi */
7596 case 0x660f3800: /* pshufb */
7597 case 0x660f3801: /* phaddw */
7598 case 0x660f3802: /* phaddd */
7599 case 0x660f3803: /* phaddsw */
7600 case 0x660f3804: /* pmaddubsw */
7601 case 0x660f3805: /* phsubw */
7602 case 0x660f3806: /* phsubd */
7603 case 0x660f3807: /* phsubsw */
7604 case 0x660f3808: /* psignb */
7605 case 0x660f3809: /* psignw */
7606 case 0x660f380a: /* psignd */
7607 case 0x660f380b: /* pmulhrsw */
7608 case 0x660f3810: /* pblendvb */
7609 case 0x660f3814: /* blendvps */
7610 case 0x660f3815: /* blendvpd */
7611 case 0x660f381c: /* pabsb */
7612 case 0x660f381d: /* pabsw */
7613 case 0x660f381e: /* pabsd */
7614 case 0x660f3820: /* pmovsxbw */
7615 case 0x660f3821: /* pmovsxbd */
7616 case 0x660f3822: /* pmovsxbq */
7617 case 0x660f3823: /* pmovsxwd */
7618 case 0x660f3824: /* pmovsxwq */
7619 case 0x660f3825: /* pmovsxdq */
7620 case 0x660f3828: /* pmuldq */
7621 case 0x660f3829: /* pcmpeqq */
7622 case 0x660f382a: /* movntdqa */
7623 case 0x660f3a08: /* roundps */
7624 case 0x660f3a09: /* roundpd */
7625 case 0x660f3a0a: /* roundss */
7626 case 0x660f3a0b: /* roundsd */
7627 case 0x660f3a0c: /* blendps */
7628 case 0x660f3a0d: /* blendpd */
7629 case 0x660f3a0e: /* pblendw */
7630 case 0x660f3a0f: /* palignr */
7631 case 0x660f3a20: /* pinsrb */
7632 case 0x660f3a21: /* insertps */
7633 case 0x660f3a22: /* pinsrd pinsrq */
7634 case 0x660f3a40: /* dpps */
7635 case 0x660f3a41: /* dppd */
7636 case 0x660f3a42: /* mpsadbw */
7637 case 0x660f3a60: /* pcmpestrm */
7638 case 0x660f3a61: /* pcmpestri */
7639 case 0x660f3a62: /* pcmpistrm */
7640 case 0x660f3a63: /* pcmpistri */
7641 case 0x0f51: /* sqrtps */
7642 case 0x660f51: /* sqrtpd */
7643 case 0xf20f51: /* sqrtsd */
7644 case 0xf30f51: /* sqrtss */
7645 case 0x0f52: /* rsqrtps */
7646 case 0xf30f52: /* rsqrtss */
7647 case 0x0f53: /* rcpps */
7648 case 0xf30f53: /* rcpss */
7649 case 0x0f54: /* andps */
7650 case 0x660f54: /* andpd */
7651 case 0x0f55: /* andnps */
7652 case 0x660f55: /* andnpd */
7653 case 0x0f56: /* orps */
7654 case 0x660f56: /* orpd */
7655 case 0x0f57: /* xorps */
7656 case 0x660f57: /* xorpd */
7657 case 0x0f58: /* addps */
7658 case 0x660f58: /* addpd */
7659 case 0xf20f58: /* addsd */
7660 case 0xf30f58: /* addss */
7661 case 0x0f59: /* mulps */
7662 case 0x660f59: /* mulpd */
7663 case 0xf20f59: /* mulsd */
7664 case 0xf30f59: /* mulss */
7665 case 0x0f5a: /* cvtps2pd */
7666 case 0x660f5a: /* cvtpd2ps */
7667 case 0xf20f5a: /* cvtsd2ss */
7668 case 0xf30f5a: /* cvtss2sd */
7669 case 0x0f5b: /* cvtdq2ps */
7670 case 0x660f5b: /* cvtps2dq */
7671 case 0xf30f5b: /* cvttps2dq */
7672 case 0x0f5c: /* subps */
7673 case 0x660f5c: /* subpd */
7674 case 0xf20f5c: /* subsd */
7675 case 0xf30f5c: /* subss */
7676 case 0x0f5d: /* minps */
7677 case 0x660f5d: /* minpd */
7678 case 0xf20f5d: /* minsd */
7679 case 0xf30f5d: /* minss */
7680 case 0x0f5e: /* divps */
7681 case 0x660f5e: /* divpd */
7682 case 0xf20f5e: /* divsd */
7683 case 0xf30f5e: /* divss */
7684 case 0x0f5f: /* maxps */
7685 case 0x660f5f: /* maxpd */
7686 case 0xf20f5f: /* maxsd */
7687 case 0xf30f5f: /* maxss */
7688 case 0x660f60: /* punpcklbw */
7689 case 0x660f61: /* punpcklwd */
7690 case 0x660f62: /* punpckldq */
7691 case 0x660f63: /* packsswb */
7692 case 0x660f64: /* pcmpgtb */
7693 case 0x660f65: /* pcmpgtw */
7694 case 0x660f66: /* pcmpgtd */
7695 case 0x660f67: /* packuswb */
7696 case 0x660f68: /* punpckhbw */
7697 case 0x660f69: /* punpckhwd */
7698 case 0x660f6a: /* punpckhdq */
7699 case 0x660f6b: /* packssdw */
7700 case 0x660f6c: /* punpcklqdq */
7701 case 0x660f6d: /* punpckhqdq */
7702 case 0x660f6e: /* movd */
7703 case 0x660f6f: /* movdqa */
7704 case 0xf30f6f: /* movdqu */
7705 case 0x660f70: /* pshufd */
7706 case 0xf20f70: /* pshuflw */
7707 case 0xf30f70: /* pshufhw */
7708 case 0x660f74: /* pcmpeqb */
7709 case 0x660f75: /* pcmpeqw */
7710 case 0x660f76: /* pcmpeqd */
7711 case 0x660f7c: /* haddpd */
7712 case 0xf20f7c: /* haddps */
7713 case 0x660f7d: /* hsubpd */
7714 case 0xf20f7d: /* hsubps */
7715 case 0xf30f7e: /* movq */
7716 case 0x0fc2: /* cmpps */
7717 case 0x660fc2: /* cmppd */
7718 case 0xf20fc2: /* cmpsd */
7719 case 0xf30fc2: /* cmpss */
7720 case 0x660fc4: /* pinsrw */
7721 case 0x0fc6: /* shufps */
7722 case 0x660fc6: /* shufpd */
7723 case 0x660fd0: /* addsubpd */
7724 case 0xf20fd0: /* addsubps */
7725 case 0x660fd1: /* psrlw */
7726 case 0x660fd2: /* psrld */
7727 case 0x660fd3: /* psrlq */
7728 case 0x660fd4: /* paddq */
7729 case 0x660fd5: /* pmullw */
7730 case 0xf30fd6: /* movq2dq */
7731 case 0x660fd8: /* psubusb */
7732 case 0x660fd9: /* psubusw */
7733 case 0x660fda: /* pminub */
7734 case 0x660fdb: /* pand */
7735 case 0x660fdc: /* paddusb */
7736 case 0x660fdd: /* paddusw */
7737 case 0x660fde: /* pmaxub */
7738 case 0x660fdf: /* pandn */
7739 case 0x660fe0: /* pavgb */
7740 case 0x660fe1: /* psraw */
7741 case 0x660fe2: /* psrad */
7742 case 0x660fe3: /* pavgw */
7743 case 0x660fe4: /* pmulhuw */
7744 case 0x660fe5: /* pmulhw */
7745 case 0x660fe6: /* cvttpd2dq */
7746 case 0xf20fe6: /* cvtpd2dq */
7747 case 0xf30fe6: /* cvtdq2pd */
7748 case 0x660fe8: /* psubsb */
7749 case 0x660fe9: /* psubsw */
7750 case 0x660fea: /* pminsw */
7751 case 0x660feb: /* por */
7752 case 0x660fec: /* paddsb */
7753 case 0x660fed: /* paddsw */
7754 case 0x660fee: /* pmaxsw */
7755 case 0x660fef: /* pxor */
7756 case 0xf20ff0: /* lddqu */
7757 case 0x660ff1: /* psllw */
7758 case 0x660ff2: /* pslld */
7759 case 0x660ff3: /* psllq */
7760 case 0x660ff4: /* pmuludq */
7761 case 0x660ff5: /* pmaddwd */
7762 case 0x660ff6: /* psadbw */
7763 case 0x660ff8: /* psubb */
7764 case 0x660ff9: /* psubw */
7765 case 0x660ffa: /* psubd */
7766 case 0x660ffb: /* psubq */
7767 case 0x660ffc: /* paddb */
7768 case 0x660ffd: /* paddw */
7769 case 0x660ffe: /* paddd */
7770 if (i386_record_modrm (&ir
))
7773 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7775 record_full_arch_list_add_reg (ir
.regcache
,
7776 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7777 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7778 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7781 case 0x0f11: /* movups */
7782 case 0x660f11: /* movupd */
7783 case 0xf30f11: /* movss */
7784 case 0xf20f11: /* movsd */
7785 case 0x0f13: /* movlps */
7786 case 0x660f13: /* movlpd */
7787 case 0x0f17: /* movhps */
7788 case 0x660f17: /* movhpd */
7789 case 0x0f29: /* movaps */
7790 case 0x660f29: /* movapd */
7791 case 0x660f3a14: /* pextrb */
7792 case 0x660f3a15: /* pextrw */
7793 case 0x660f3a16: /* pextrd pextrq */
7794 case 0x660f3a17: /* extractps */
7795 case 0x660f7f: /* movdqa */
7796 case 0xf30f7f: /* movdqu */
7797 if (i386_record_modrm (&ir
))
7801 if (opcode
== 0x0f13 || opcode
== 0x660f13
7802 || opcode
== 0x0f17 || opcode
== 0x660f17)
7805 if (!i386_xmm_regnum_p (gdbarch
,
7806 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7808 record_full_arch_list_add_reg (ir
.regcache
,
7809 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7831 if (i386_record_lea_modrm (&ir
))
7836 case 0x0f2b: /* movntps */
7837 case 0x660f2b: /* movntpd */
7838 case 0x0fe7: /* movntq */
7839 case 0x660fe7: /* movntdq */
7842 if (opcode
== 0x0fe7)
7846 if (i386_record_lea_modrm (&ir
))
7850 case 0xf30f2c: /* cvttss2si */
7851 case 0xf20f2c: /* cvttsd2si */
7852 case 0xf30f2d: /* cvtss2si */
7853 case 0xf20f2d: /* cvtsd2si */
7854 case 0xf20f38f0: /* crc32 */
7855 case 0xf20f38f1: /* crc32 */
7856 case 0x0f50: /* movmskps */
7857 case 0x660f50: /* movmskpd */
7858 case 0x0fc5: /* pextrw */
7859 case 0x660fc5: /* pextrw */
7860 case 0x0fd7: /* pmovmskb */
7861 case 0x660fd7: /* pmovmskb */
7862 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7865 case 0x0f3800: /* pshufb */
7866 case 0x0f3801: /* phaddw */
7867 case 0x0f3802: /* phaddd */
7868 case 0x0f3803: /* phaddsw */
7869 case 0x0f3804: /* pmaddubsw */
7870 case 0x0f3805: /* phsubw */
7871 case 0x0f3806: /* phsubd */
7872 case 0x0f3807: /* phsubsw */
7873 case 0x0f3808: /* psignb */
7874 case 0x0f3809: /* psignw */
7875 case 0x0f380a: /* psignd */
7876 case 0x0f380b: /* pmulhrsw */
7877 case 0x0f381c: /* pabsb */
7878 case 0x0f381d: /* pabsw */
7879 case 0x0f381e: /* pabsd */
7880 case 0x0f382b: /* packusdw */
7881 case 0x0f3830: /* pmovzxbw */
7882 case 0x0f3831: /* pmovzxbd */
7883 case 0x0f3832: /* pmovzxbq */
7884 case 0x0f3833: /* pmovzxwd */
7885 case 0x0f3834: /* pmovzxwq */
7886 case 0x0f3835: /* pmovzxdq */
7887 case 0x0f3837: /* pcmpgtq */
7888 case 0x0f3838: /* pminsb */
7889 case 0x0f3839: /* pminsd */
7890 case 0x0f383a: /* pminuw */
7891 case 0x0f383b: /* pminud */
7892 case 0x0f383c: /* pmaxsb */
7893 case 0x0f383d: /* pmaxsd */
7894 case 0x0f383e: /* pmaxuw */
7895 case 0x0f383f: /* pmaxud */
7896 case 0x0f3840: /* pmulld */
7897 case 0x0f3841: /* phminposuw */
7898 case 0x0f3a0f: /* palignr */
7899 case 0x0f60: /* punpcklbw */
7900 case 0x0f61: /* punpcklwd */
7901 case 0x0f62: /* punpckldq */
7902 case 0x0f63: /* packsswb */
7903 case 0x0f64: /* pcmpgtb */
7904 case 0x0f65: /* pcmpgtw */
7905 case 0x0f66: /* pcmpgtd */
7906 case 0x0f67: /* packuswb */
7907 case 0x0f68: /* punpckhbw */
7908 case 0x0f69: /* punpckhwd */
7909 case 0x0f6a: /* punpckhdq */
7910 case 0x0f6b: /* packssdw */
7911 case 0x0f6e: /* movd */
7912 case 0x0f6f: /* movq */
7913 case 0x0f70: /* pshufw */
7914 case 0x0f74: /* pcmpeqb */
7915 case 0x0f75: /* pcmpeqw */
7916 case 0x0f76: /* pcmpeqd */
7917 case 0x0fc4: /* pinsrw */
7918 case 0x0fd1: /* psrlw */
7919 case 0x0fd2: /* psrld */
7920 case 0x0fd3: /* psrlq */
7921 case 0x0fd4: /* paddq */
7922 case 0x0fd5: /* pmullw */
7923 case 0xf20fd6: /* movdq2q */
7924 case 0x0fd8: /* psubusb */
7925 case 0x0fd9: /* psubusw */
7926 case 0x0fda: /* pminub */
7927 case 0x0fdb: /* pand */
7928 case 0x0fdc: /* paddusb */
7929 case 0x0fdd: /* paddusw */
7930 case 0x0fde: /* pmaxub */
7931 case 0x0fdf: /* pandn */
7932 case 0x0fe0: /* pavgb */
7933 case 0x0fe1: /* psraw */
7934 case 0x0fe2: /* psrad */
7935 case 0x0fe3: /* pavgw */
7936 case 0x0fe4: /* pmulhuw */
7937 case 0x0fe5: /* pmulhw */
7938 case 0x0fe8: /* psubsb */
7939 case 0x0fe9: /* psubsw */
7940 case 0x0fea: /* pminsw */
7941 case 0x0feb: /* por */
7942 case 0x0fec: /* paddsb */
7943 case 0x0fed: /* paddsw */
7944 case 0x0fee: /* pmaxsw */
7945 case 0x0fef: /* pxor */
7946 case 0x0ff1: /* psllw */
7947 case 0x0ff2: /* pslld */
7948 case 0x0ff3: /* psllq */
7949 case 0x0ff4: /* pmuludq */
7950 case 0x0ff5: /* pmaddwd */
7951 case 0x0ff6: /* psadbw */
7952 case 0x0ff8: /* psubb */
7953 case 0x0ff9: /* psubw */
7954 case 0x0ffa: /* psubd */
7955 case 0x0ffb: /* psubq */
7956 case 0x0ffc: /* paddb */
7957 case 0x0ffd: /* paddw */
7958 case 0x0ffe: /* paddd */
7959 if (i386_record_modrm (&ir
))
7961 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7963 record_full_arch_list_add_reg (ir
.regcache
,
7964 I387_MM0_REGNUM (tdep
) + ir
.reg
);
7967 case 0x0f71: /* psllw */
7968 case 0x0f72: /* pslld */
7969 case 0x0f73: /* psllq */
7970 if (i386_record_modrm (&ir
))
7972 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
7974 record_full_arch_list_add_reg (ir
.regcache
,
7975 I387_MM0_REGNUM (tdep
) + ir
.rm
);
7978 case 0x660f71: /* psllw */
7979 case 0x660f72: /* pslld */
7980 case 0x660f73: /* psllq */
7981 if (i386_record_modrm (&ir
))
7984 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7986 record_full_arch_list_add_reg (ir
.regcache
,
7987 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7990 case 0x0f7e: /* movd */
7991 case 0x660f7e: /* movd */
7992 if (i386_record_modrm (&ir
))
7995 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8002 if (i386_record_lea_modrm (&ir
))
8007 case 0x0f7f: /* movq */
8008 if (i386_record_modrm (&ir
))
8012 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8014 record_full_arch_list_add_reg (ir
.regcache
,
8015 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8020 if (i386_record_lea_modrm (&ir
))
8025 case 0xf30fb8: /* popcnt */
8026 if (i386_record_modrm (&ir
))
8028 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8029 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8032 case 0x660fd6: /* movq */
8033 if (i386_record_modrm (&ir
))
8038 if (!i386_xmm_regnum_p (gdbarch
,
8039 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8041 record_full_arch_list_add_reg (ir
.regcache
,
8042 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8047 if (i386_record_lea_modrm (&ir
))
8052 case 0x660f3817: /* ptest */
8053 case 0x0f2e: /* ucomiss */
8054 case 0x660f2e: /* ucomisd */
8055 case 0x0f2f: /* comiss */
8056 case 0x660f2f: /* comisd */
8057 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8060 case 0x0ff7: /* maskmovq */
8061 regcache_raw_read_unsigned (ir
.regcache
,
8062 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8064 if (record_full_arch_list_add_mem (addr
, 64))
8068 case 0x660ff7: /* maskmovdqu */
8069 regcache_raw_read_unsigned (ir
.regcache
,
8070 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8072 if (record_full_arch_list_add_mem (addr
, 128))
8087 /* In the future, maybe still need to deal with need_dasm. */
8088 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8089 if (record_full_arch_list_add_end ())
8095 printf_unfiltered (_("Process record does not support instruction 0x%02x "
8096 "at address %s.\n"),
8097 (unsigned int) (opcode
),
8098 paddress (gdbarch
, ir
.orig_addr
));
8102 static const int i386_record_regmap
[] =
8104 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8105 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8106 0, 0, 0, 0, 0, 0, 0, 0,
8107 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8108 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8111 /* Check that the given address appears suitable for a fast
8112 tracepoint, which on x86-64 means that we need an instruction of at
8113 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8114 jump and not have to worry about program jumps to an address in the
8115 middle of the tracepoint jump. On x86, it may be possible to use
8116 4-byte jumps with a 2-byte offset to a trampoline located in the
8117 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8118 of instruction to replace, and 0 if not, plus an explanatory
8122 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8127 /* Ask the target for the minimum instruction length supported. */
8128 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8132 /* If the target does not support the get_min_fast_tracepoint_insn_len
8133 operation, assume that fast tracepoints will always be implemented
8134 using 4-byte relative jumps on both x86 and x86-64. */
8137 else if (jumplen
== 0)
8139 /* If the target does support get_min_fast_tracepoint_insn_len but
8140 returns zero, then the IPA has not loaded yet. In this case,
8141 we optimistically assume that truncated 2-byte relative jumps
8142 will be available on x86, and compensate later if this assumption
8143 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8144 jumps will always be used. */
8145 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8148 /* Check for fit. */
8149 len
= gdb_insn_length (gdbarch
, addr
);
8153 /* Return a bit of target-specific detail to add to the caller's
8154 generic failure message. */
8156 *msg
= string_printf (_("; instruction is only %d bytes long, "
8157 "need at least %d bytes for the jump"),
8169 /* Return a floating-point format for a floating-point variable of
8170 length LEN in bits. If non-NULL, NAME is the name of its type.
8171 If no suitable type is found, return NULL. */
8173 static const struct floatformat
**
8174 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8175 const char *name
, int len
)
8177 if (len
== 128 && name
)
8178 if (strcmp (name
, "__float128") == 0
8179 || strcmp (name
, "_Float128") == 0
8180 || strcmp (name
, "complex _Float128") == 0
8181 || strcmp (name
, "complex(kind=16)") == 0
8182 || strcmp (name
, "complex*32") == 0
8183 || strcmp (name
, "COMPLEX*32") == 0
8184 || strcmp (name
, "quad complex") == 0
8185 || strcmp (name
, "real(kind=16)") == 0
8186 || strcmp (name
, "real*16") == 0
8187 || strcmp (name
, "REAL*16") == 0)
8188 return floatformats_ia64_quad
;
8190 return default_floatformat_for_type (gdbarch
, name
, len
);
8194 i386_validate_tdesc_p (struct gdbarch_tdep
*tdep
,
8195 struct tdesc_arch_data
*tdesc_data
)
8197 const struct target_desc
*tdesc
= tdep
->tdesc
;
8198 const struct tdesc_feature
*feature_core
;
8200 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8201 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8202 int i
, num_regs
, valid_p
;
8204 if (! tdesc_has_registers (tdesc
))
8207 /* Get core registers. */
8208 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8209 if (feature_core
== NULL
)
8212 /* Get SSE registers. */
8213 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8215 /* Try AVX registers. */
8216 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8218 /* Try MPX registers. */
8219 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8221 /* Try AVX512 registers. */
8222 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8224 /* Try segment base registers. */
8225 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8228 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8232 /* The XCR0 bits. */
8235 /* AVX512 register description requires AVX register description. */
8239 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8241 /* It may have been set by OSABI initialization function. */
8242 if (tdep
->k0_regnum
< 0)
8244 tdep
->k_register_names
= i386_k_names
;
8245 tdep
->k0_regnum
= I386_K0_REGNUM
;
8248 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8249 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8250 tdep
->k0_regnum
+ i
,
8253 if (tdep
->num_zmm_regs
== 0)
8255 tdep
->zmmh_register_names
= i386_zmmh_names
;
8256 tdep
->num_zmm_regs
= 8;
8257 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8260 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8261 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8262 tdep
->zmm0h_regnum
+ i
,
8263 tdep
->zmmh_register_names
[i
]);
8265 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8266 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8267 tdep
->xmm16_regnum
+ i
,
8268 tdep
->xmm_avx512_register_names
[i
]);
8270 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8271 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8272 tdep
->ymm16h_regnum
+ i
,
8273 tdep
->ymm16h_register_names
[i
]);
8277 /* AVX register description requires SSE register description. */
8281 if (!feature_avx512
)
8282 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8284 /* It may have been set by OSABI initialization function. */
8285 if (tdep
->num_ymm_regs
== 0)
8287 tdep
->ymmh_register_names
= i386_ymmh_names
;
8288 tdep
->num_ymm_regs
= 8;
8289 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8292 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8293 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8294 tdep
->ymm0h_regnum
+ i
,
8295 tdep
->ymmh_register_names
[i
]);
8297 else if (feature_sse
)
8298 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8301 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8302 tdep
->num_xmm_regs
= 0;
8305 num_regs
= tdep
->num_core_regs
;
8306 for (i
= 0; i
< num_regs
; i
++)
8307 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8308 tdep
->register_names
[i
]);
8312 /* Need to include %mxcsr, so add one. */
8313 num_regs
+= tdep
->num_xmm_regs
+ 1;
8314 for (; i
< num_regs
; i
++)
8315 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8316 tdep
->register_names
[i
]);
8321 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8323 if (tdep
->bnd0r_regnum
< 0)
8325 tdep
->mpx_register_names
= i386_mpx_names
;
8326 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8327 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8330 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8331 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8332 I387_BND0R_REGNUM (tdep
) + i
,
8333 tdep
->mpx_register_names
[i
]);
8336 if (feature_segments
)
8338 if (tdep
->fsbase_regnum
< 0)
8339 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8340 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8341 tdep
->fsbase_regnum
, "fs_base");
8342 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8343 tdep
->fsbase_regnum
+ 1, "gs_base");
8348 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8349 if (tdep
->pkru_regnum
< 0)
8351 tdep
->pkeys_register_names
= i386_pkeys_names
;
8352 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8353 tdep
->num_pkeys_regs
= 1;
8356 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8357 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8358 I387_PKRU_REGNUM (tdep
) + i
,
8359 tdep
->pkeys_register_names
[i
]);
8367 /* Implement the type_align gdbarch function. */
8370 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8372 type
= check_typedef (type
);
8374 if (gdbarch_ptr_bit (gdbarch
) == 32)
8376 if ((type
->code () == TYPE_CODE_INT
8377 || type
->code () == TYPE_CODE_FLT
)
8378 && TYPE_LENGTH (type
) > 4)
8381 /* Handle x86's funny long double. */
8382 if (type
->code () == TYPE_CODE_FLT
8383 && gdbarch_long_double_bit (gdbarch
) == TYPE_LENGTH (type
) * 8)
8391 /* Note: This is called for both i386 and amd64. */
8393 static struct gdbarch
*
8394 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8396 struct gdbarch_tdep
*tdep
;
8397 struct gdbarch
*gdbarch
;
8398 const struct target_desc
*tdesc
;
8404 /* If there is already a candidate, use it. */
8405 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8407 return arches
->gdbarch
;
8409 /* Allocate space for the new architecture. Assume i386 for now. */
8410 tdep
= XCNEW (struct gdbarch_tdep
);
8411 gdbarch
= gdbarch_alloc (&info
, tdep
);
8413 /* General-purpose registers. */
8414 tdep
->gregset_reg_offset
= NULL
;
8415 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8416 tdep
->sizeof_gregset
= 0;
8418 /* Floating-point registers. */
8419 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8420 tdep
->fpregset
= &i386_fpregset
;
8422 /* The default settings include the FPU registers, the MMX registers
8423 and the SSE registers. This can be overridden for a specific ABI
8424 by adjusting the members `st0_regnum', `mm0_regnum' and
8425 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8426 will show up in the output of "info all-registers". */
8428 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8430 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8431 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8433 tdep
->jb_pc_offset
= -1;
8434 tdep
->struct_return
= pcc_struct_return
;
8435 tdep
->sigtramp_start
= 0;
8436 tdep
->sigtramp_end
= 0;
8437 tdep
->sigtramp_p
= i386_sigtramp_p
;
8438 tdep
->sigcontext_addr
= NULL
;
8439 tdep
->sc_reg_offset
= NULL
;
8440 tdep
->sc_pc_offset
= -1;
8441 tdep
->sc_sp_offset
= -1;
8443 tdep
->xsave_xcr0_offset
= -1;
8445 tdep
->record_regmap
= i386_record_regmap
;
8447 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8449 /* The format used for `long double' on almost all i386 targets is
8450 the i387 extended floating-point format. In fact, of all targets
8451 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8452 on having a `long double' that's not `long' at all. */
8453 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8455 /* Although the i387 extended floating-point has only 80 significant
8456 bits, a `long double' actually takes up 96, probably to enforce
8458 set_gdbarch_long_double_bit (gdbarch
, 96);
8460 /* Support of bfloat16 format. */
8461 set_gdbarch_bfloat16_format (gdbarch
, floatformats_bfloat16
);
8463 /* Support for floating-point data type variants. */
8464 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8466 /* Register numbers of various important registers. */
8467 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8468 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8469 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8470 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8472 /* NOTE: kettenis/20040418: GCC does have two possible register
8473 numbering schemes on the i386: dbx and SVR4. These schemes
8474 differ in how they number %ebp, %esp, %eflags, and the
8475 floating-point registers, and are implemented by the arrays
8476 dbx_register_map[] and svr4_dbx_register_map in
8477 gcc/config/i386.c. GCC also defines a third numbering scheme in
8478 gcc/config/i386.c, which it designates as the "default" register
8479 map used in 64bit mode. This last register numbering scheme is
8480 implemented in dbx64_register_map, and is used for AMD64; see
8483 Currently, each GCC i386 target always uses the same register
8484 numbering scheme across all its supported debugging formats
8485 i.e. SDB (COFF), stabs and DWARF 2. This is because
8486 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8487 DBX_REGISTER_NUMBER macro which is defined by each target's
8488 respective config header in a manner independent of the requested
8489 output debugging format.
8491 This does not match the arrangement below, which presumes that
8492 the SDB and stabs numbering schemes differ from the DWARF and
8493 DWARF 2 ones. The reason for this arrangement is that it is
8494 likely to get the numbering scheme for the target's
8495 default/native debug format right. For targets where GCC is the
8496 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8497 targets where the native toolchain uses a different numbering
8498 scheme for a particular debug format (stabs-in-ELF on Solaris)
8499 the defaults below will have to be overridden, like
8500 i386_elf_init_abi() does. */
8502 /* Use the dbx register numbering scheme for stabs and COFF. */
8503 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8504 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8506 /* Use the SVR4 register numbering scheme for DWARF 2. */
8507 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8509 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8510 be in use on any of the supported i386 targets. */
8512 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8514 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8516 /* Call dummy code. */
8517 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8518 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8519 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8520 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8522 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8523 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8524 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8526 set_gdbarch_return_value (gdbarch
, i386_return_value
);
8528 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8530 /* Stack grows downward. */
8531 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8533 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8534 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8536 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8537 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8539 set_gdbarch_frame_args_skip (gdbarch
, 8);
8541 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8543 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8545 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8547 /* Add the i386 register groups. */
8548 i386_add_reggroups (gdbarch
);
8549 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8551 /* Helper for function argument information. */
8552 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8554 /* Hook the function epilogue frame unwinder. This unwinder is
8555 appended to the list first, so that it supercedes the DWARF
8556 unwinder in function epilogues (where the DWARF unwinder
8557 currently fails). */
8558 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8560 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8561 to the list before the prologue-based unwinders, so that DWARF
8562 CFI info will be used if it is available. */
8563 dwarf2_append_unwinders (gdbarch
);
8565 frame_base_set_default (gdbarch
, &i386_frame_base
);
8567 /* Pseudo registers may be changed by amd64_init_abi. */
8568 set_gdbarch_pseudo_register_read_value (gdbarch
,
8569 i386_pseudo_register_read_value
);
8570 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8571 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8572 i386_ax_pseudo_register_collect
);
8574 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8575 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8577 /* Override the normal target description method to make the AVX
8578 upper halves anonymous. */
8579 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8581 /* Even though the default ABI only includes general-purpose registers,
8582 floating-point registers and the SSE registers, we have to leave a
8583 gap for the upper AVX, MPX and AVX512 registers. */
8584 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8586 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8588 /* Get the x86 target description from INFO. */
8589 tdesc
= info
.target_desc
;
8590 if (! tdesc_has_registers (tdesc
))
8591 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8592 tdep
->tdesc
= tdesc
;
8594 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8595 tdep
->register_names
= i386_register_names
;
8597 /* No upper YMM registers. */
8598 tdep
->ymmh_register_names
= NULL
;
8599 tdep
->ymm0h_regnum
= -1;
8601 /* No upper ZMM registers. */
8602 tdep
->zmmh_register_names
= NULL
;
8603 tdep
->zmm0h_regnum
= -1;
8605 /* No high XMM registers. */
8606 tdep
->xmm_avx512_register_names
= NULL
;
8607 tdep
->xmm16_regnum
= -1;
8609 /* No upper YMM16-31 registers. */
8610 tdep
->ymm16h_register_names
= NULL
;
8611 tdep
->ymm16h_regnum
= -1;
8613 tdep
->num_byte_regs
= 8;
8614 tdep
->num_word_regs
= 8;
8615 tdep
->num_dword_regs
= 0;
8616 tdep
->num_mmx_regs
= 8;
8617 tdep
->num_ymm_regs
= 0;
8619 /* No MPX registers. */
8620 tdep
->bnd0r_regnum
= -1;
8621 tdep
->bndcfgu_regnum
= -1;
8623 /* No AVX512 registers. */
8624 tdep
->k0_regnum
= -1;
8625 tdep
->num_zmm_regs
= 0;
8626 tdep
->num_ymm_avx512_regs
= 0;
8627 tdep
->num_xmm_avx512_regs
= 0;
8629 /* No PKEYS registers */
8630 tdep
->pkru_regnum
= -1;
8631 tdep
->num_pkeys_regs
= 0;
8633 /* No segment base registers. */
8634 tdep
->fsbase_regnum
= -1;
8636 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
8638 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8640 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8642 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8643 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8644 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8646 /* Hook in ABI-specific overrides, if they have been registered.
8647 Note: If INFO specifies a 64 bit arch, this is where we turn
8648 a 32-bit i386 into a 64-bit amd64. */
8649 info
.tdesc_data
= tdesc_data
.get ();
8650 gdbarch_init_osabi (info
, gdbarch
);
8652 if (!i386_validate_tdesc_p (tdep
, tdesc_data
.get ()))
8655 gdbarch_free (gdbarch
);
8659 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8661 /* Wire in pseudo registers. Number of pseudo registers may be
8663 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8664 + tdep
->num_word_regs
8665 + tdep
->num_dword_regs
8666 + tdep
->num_mmx_regs
8667 + tdep
->num_ymm_regs
8669 + tdep
->num_ymm_avx512_regs
8670 + tdep
->num_zmm_regs
));
8672 /* Target description may be changed. */
8673 tdesc
= tdep
->tdesc
;
8675 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8677 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8678 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8680 /* Make %al the first pseudo-register. */
8681 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8682 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8684 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8685 if (tdep
->num_dword_regs
)
8687 /* Support dword pseudo-register if it hasn't been disabled. */
8688 tdep
->eax_regnum
= ymm0_regnum
;
8689 ymm0_regnum
+= tdep
->num_dword_regs
;
8692 tdep
->eax_regnum
= -1;
8694 mm0_regnum
= ymm0_regnum
;
8695 if (tdep
->num_ymm_regs
)
8697 /* Support YMM pseudo-register if it is available. */
8698 tdep
->ymm0_regnum
= ymm0_regnum
;
8699 mm0_regnum
+= tdep
->num_ymm_regs
;
8702 tdep
->ymm0_regnum
= -1;
8704 if (tdep
->num_ymm_avx512_regs
)
8706 /* Support YMM16-31 pseudo registers if available. */
8707 tdep
->ymm16_regnum
= mm0_regnum
;
8708 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8711 tdep
->ymm16_regnum
= -1;
8713 if (tdep
->num_zmm_regs
)
8715 /* Support ZMM pseudo-register if it is available. */
8716 tdep
->zmm0_regnum
= mm0_regnum
;
8717 mm0_regnum
+= tdep
->num_zmm_regs
;
8720 tdep
->zmm0_regnum
= -1;
8722 bnd0_regnum
= mm0_regnum
;
8723 if (tdep
->num_mmx_regs
!= 0)
8725 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8726 tdep
->mm0_regnum
= mm0_regnum
;
8727 bnd0_regnum
+= tdep
->num_mmx_regs
;
8730 tdep
->mm0_regnum
= -1;
8732 if (tdep
->bnd0r_regnum
> 0)
8733 tdep
->bnd0_regnum
= bnd0_regnum
;
8735 tdep
-> bnd0_regnum
= -1;
8737 /* Hook in the legacy prologue-based unwinders last (fallback). */
8738 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8739 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8740 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8742 /* If we have a register mapping, enable the generic core file
8743 support, unless it has already been enabled. */
8744 if (tdep
->gregset_reg_offset
8745 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8746 set_gdbarch_iterate_over_regset_sections
8747 (gdbarch
, i386_iterate_over_regset_sections
);
8749 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8750 i386_fast_tracepoint_valid_at
);
8757 /* Return the target description for a specified XSAVE feature mask. */
8759 const struct target_desc
*
8760 i386_target_description (uint64_t xcr0
, bool segments
)
8762 static target_desc
*i386_tdescs \
8763 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8764 target_desc
**tdesc
;
8766 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8767 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8768 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8769 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8770 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8774 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8779 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8781 /* Find the bound directory base address. */
8783 static unsigned long
8784 i386_mpx_bd_base (void)
8786 struct regcache
*rcache
;
8787 struct gdbarch_tdep
*tdep
;
8789 enum register_status regstatus
;
8791 rcache
= get_current_regcache ();
8792 tdep
= gdbarch_tdep (rcache
->arch ());
8794 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
8796 if (regstatus
!= REG_VALID
)
8797 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
8799 return ret
& MPX_BASE_MASK
;
8803 i386_mpx_enabled (void)
8805 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_current_arch ());
8806 const struct target_desc
*tdesc
= tdep
->tdesc
;
8808 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
8811 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
8812 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
8813 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
8814 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
8816 /* Find the bound table entry given the pointer location and the base
8817 address of the table. */
8820 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
8824 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
8825 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
8826 CORE_ADDR bd_entry_addr
;
8829 struct gdbarch
*gdbarch
= get_current_arch ();
8830 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8833 if (gdbarch_ptr_bit (gdbarch
) == 64)
8835 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
8836 bd_ptr_r_shift
= 20;
8838 bt_select_r_shift
= 3;
8839 bt_select_l_shift
= 5;
8840 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
8842 if ( sizeof (CORE_ADDR
) == 4)
8843 error (_("bound table examination not supported\
8844 for 64-bit process with 32-bit GDB"));
8848 mpx_bd_mask
= MPX_BD_MASK_32
;
8849 bd_ptr_r_shift
= 12;
8851 bt_select_r_shift
= 2;
8852 bt_select_l_shift
= 4;
8853 bt_mask
= MPX_BT_MASK_32
;
8856 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
8857 bd_entry_addr
= bd_base
+ offset1
;
8858 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
8860 if ((bd_entry
& 0x1) == 0)
8861 error (_("Invalid bounds directory entry at %s."),
8862 paddress (get_current_arch (), bd_entry_addr
));
8864 /* Clearing status bit. */
8866 bt_addr
= bd_entry
& ~bt_select_r_shift
;
8867 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
8869 return bt_addr
+ offset2
;
8872 /* Print routine for the mpx bounds. */
8875 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
8877 struct ui_out
*uiout
= current_uiout
;
8879 struct gdbarch
*gdbarch
= get_current_arch ();
8880 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
8881 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
8883 if (bounds_in_map
== 1)
8885 uiout
->text ("Null bounds on map:");
8886 uiout
->text (" pointer value = ");
8887 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8893 uiout
->text ("{lbound = ");
8894 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
8895 uiout
->text (", ubound = ");
8897 /* The upper bound is stored in 1's complement. */
8898 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
8899 uiout
->text ("}: pointer value = ");
8900 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
8902 if (gdbarch_ptr_bit (gdbarch
) == 64)
8903 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
8905 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
8907 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
8908 -1 represents in this sense full memory access, and there is no need
8911 size
= (size
> -1 ? size
+ 1 : size
);
8912 uiout
->text (", size = ");
8913 uiout
->field_string ("size", plongest (size
));
8915 uiout
->text (", metadata = ");
8916 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
8921 /* Implement the command "show mpx bound". */
8924 i386_mpx_info_bounds (const char *args
, int from_tty
)
8926 CORE_ADDR bd_base
= 0;
8928 CORE_ADDR bt_entry_addr
= 0;
8929 CORE_ADDR bt_entry
[4];
8931 struct gdbarch
*gdbarch
= get_current_arch ();
8932 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8934 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8935 || !i386_mpx_enabled ())
8937 printf_unfiltered (_("Intel Memory Protection Extensions not "
8938 "supported on this target.\n"));
8944 printf_unfiltered (_("Address of pointer variable expected.\n"));
8948 addr
= parse_and_eval_address (args
);
8950 bd_base
= i386_mpx_bd_base ();
8951 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
8953 memset (bt_entry
, 0, sizeof (bt_entry
));
8955 for (i
= 0; i
< 4; i
++)
8956 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
8957 + i
* TYPE_LENGTH (data_ptr_type
),
8960 i386_mpx_print_bounds (bt_entry
);
8963 /* Implement the command "set mpx bound". */
8966 i386_mpx_set_bounds (const char *args
, int from_tty
)
8968 CORE_ADDR bd_base
= 0;
8969 CORE_ADDR addr
, lower
, upper
;
8970 CORE_ADDR bt_entry_addr
= 0;
8971 CORE_ADDR bt_entry
[2];
8972 const char *input
= args
;
8974 struct gdbarch
*gdbarch
= get_current_arch ();
8975 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8976 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
8978 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
8979 || !i386_mpx_enabled ())
8980 error (_("Intel Memory Protection Extensions not supported\
8984 error (_("Pointer value expected."));
8986 addr
= value_as_address (parse_to_comma_and_eval (&input
));
8988 if (input
[0] == ',')
8990 if (input
[0] == '\0')
8991 error (_("wrong number of arguments: missing lower and upper bound."));
8992 lower
= value_as_address (parse_to_comma_and_eval (&input
));
8994 if (input
[0] == ',')
8996 if (input
[0] == '\0')
8997 error (_("Wrong number of arguments; Missing upper bound."));
8998 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9000 bd_base
= i386_mpx_bd_base ();
9001 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9002 for (i
= 0; i
< 2; i
++)
9003 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9004 + i
* TYPE_LENGTH (data_ptr_type
),
9006 bt_entry
[0] = (uint64_t) lower
;
9007 bt_entry
[1] = ~(uint64_t) upper
;
9009 for (i
= 0; i
< 2; i
++)
9010 write_memory_unsigned_integer (bt_entry_addr
9011 + i
* TYPE_LENGTH (data_ptr_type
),
9012 TYPE_LENGTH (data_ptr_type
), byte_order
,
9016 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9018 void _initialize_i386_tdep ();
9020 _initialize_i386_tdep ()
9022 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
9024 /* Add the variable that controls the disassembly flavor. */
9025 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9026 &disassembly_flavor
, _("\
9027 Set the disassembly flavor."), _("\
9028 Show the disassembly flavor."), _("\
9029 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9031 NULL
, /* FIXME: i18n: */
9032 &setlist
, &showlist
);
9034 /* Add the variable that controls the convention for returning
9036 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9037 &struct_convention
, _("\
9038 Set the convention for returning small structs."), _("\
9039 Show the convention for returning small structs."), _("\
9040 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9043 NULL
, /* FIXME: i18n: */
9044 &setlist
, &showlist
);
9046 /* Add "mpx" prefix for the set commands. */
9048 add_basic_prefix_cmd ("mpx", class_support
, _("\
9049 Set Intel Memory Protection Extensions specific variables."),
9051 0 /* allow-unknown */, &setlist
);
9053 /* Add "mpx" prefix for the show commands. */
9055 add_show_prefix_cmd ("mpx", class_support
, _("\
9056 Show Intel Memory Protection Extensions specific variables."),
9058 0 /* allow-unknown */, &showlist
);
9060 /* Add "bound" command for the show mpx commands list. */
9062 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9063 "Show the memory bounds for a given array/pointer storage\
9064 in the bound table.",
9067 /* Add "bound" command for the set mpx commands list. */
9069 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9070 "Set the memory bounds for a given array/pointer storage\
9071 in the bound table.",
9074 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9075 i386_svr4_init_abi
);
9077 /* Initialize the i386-specific register groups. */
9078 i386_init_reggroups ();
9080 /* Tell remote stub that we support XML target description. */
9081 register_remote_support_xml ("i386");