1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
27 #include "dwarf2-frame.h"
30 #include "frame-base.h"
31 #include "frame-unwind.h"
39 #include "reggroups.h"
47 #include "gdb_assert.h"
48 #include "gdb_string.h"
50 #include "i386-tdep.h"
51 #include "i387-tdep.h"
58 static char *i386_register_names
[] =
60 "eax", "ecx", "edx", "ebx",
61 "esp", "ebp", "esi", "edi",
62 "eip", "eflags", "cs", "ss",
63 "ds", "es", "fs", "gs",
64 "st0", "st1", "st2", "st3",
65 "st4", "st5", "st6", "st7",
66 "fctrl", "fstat", "ftag", "fiseg",
67 "fioff", "foseg", "fooff", "fop",
68 "xmm0", "xmm1", "xmm2", "xmm3",
69 "xmm4", "xmm5", "xmm6", "xmm7",
73 static const int i386_num_register_names
= ARRAY_SIZE (i386_register_names
);
75 /* Register names for MMX pseudo-registers. */
77 static char *i386_mmx_names
[] =
79 "mm0", "mm1", "mm2", "mm3",
80 "mm4", "mm5", "mm6", "mm7"
83 static const int i386_num_mmx_regs
= ARRAY_SIZE (i386_mmx_names
);
86 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
88 int mm0_regnum
= gdbarch_tdep (gdbarch
)->mm0_regnum
;
93 return (regnum
>= mm0_regnum
&& regnum
< mm0_regnum
+ i386_num_mmx_regs
);
99 i386_sse_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
103 if (I387_NUM_XMM_REGS (tdep
) == 0)
106 return (I387_XMM0_REGNUM (tdep
) <= regnum
107 && regnum
< I387_MXCSR_REGNUM (tdep
));
111 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
113 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
115 if (I387_NUM_XMM_REGS (tdep
) == 0)
118 return (regnum
== I387_MXCSR_REGNUM (tdep
));
124 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
128 if (I387_ST0_REGNUM (tdep
) < 0)
131 return (I387_ST0_REGNUM (tdep
) <= regnum
132 && regnum
< I387_FCTRL_REGNUM (tdep
));
136 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
140 if (I387_ST0_REGNUM (tdep
) < 0)
143 return (I387_FCTRL_REGNUM (tdep
) <= regnum
144 && regnum
< I387_XMM0_REGNUM (tdep
));
147 /* Return the name of register REGNUM. */
150 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
152 if (i386_mmx_regnum_p (gdbarch
, regnum
))
153 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (gdbarch_tdep (gdbarch
))];
155 if (regnum
>= 0 && regnum
< i386_num_register_names
)
156 return i386_register_names
[regnum
];
161 /* Convert a dbx register number REG to the appropriate register
162 number used by GDB. */
165 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
169 /* This implements what GCC calls the "default" register map
170 (dbx_register_map[]). */
172 if (reg
>= 0 && reg
<= 7)
174 /* General-purpose registers. The debug info calls %ebp
175 register 4, and %esp register 5. */
182 else if (reg
>= 12 && reg
<= 19)
184 /* Floating-point registers. */
185 return reg
- 12 + I387_ST0_REGNUM (tdep
);
187 else if (reg
>= 21 && reg
<= 28)
190 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
192 else if (reg
>= 29 && reg
<= 36)
195 return reg
- 29 + I387_MM0_REGNUM (tdep
);
198 /* This will hopefully provoke a warning. */
199 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
202 /* Convert SVR4 register number REG to the appropriate register number
206 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 /* This implements the GCC register map that tries to be compatible
211 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
213 /* The SVR4 register numbering includes %eip and %eflags, and
214 numbers the floating point registers differently. */
215 if (reg
>= 0 && reg
<= 9)
217 /* General-purpose registers. */
220 else if (reg
>= 11 && reg
<= 18)
222 /* Floating-point registers. */
223 return reg
- 11 + I387_ST0_REGNUM (tdep
);
225 else if (reg
>= 21 && reg
<= 36)
227 /* The SSE and MMX registers have the same numbers as with dbx. */
228 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
233 case 37: return I387_FCTRL_REGNUM (tdep
);
234 case 38: return I387_FSTAT_REGNUM (tdep
);
235 case 39: return I387_MXCSR_REGNUM (tdep
);
236 case 40: return I386_ES_REGNUM
;
237 case 41: return I386_CS_REGNUM
;
238 case 42: return I386_SS_REGNUM
;
239 case 43: return I386_DS_REGNUM
;
240 case 44: return I386_FS_REGNUM
;
241 case 45: return I386_GS_REGNUM
;
244 /* This will hopefully provoke a warning. */
245 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
250 /* This is the variable that is set with "set disassembly-flavor", and
251 its legitimate values. */
252 static const char att_flavor
[] = "att";
253 static const char intel_flavor
[] = "intel";
254 static const char *valid_flavors
[] =
260 static const char *disassembly_flavor
= att_flavor
;
263 /* Use the program counter to determine the contents and size of a
264 breakpoint instruction. Return a pointer to a string of bytes that
265 encode a breakpoint instruction, store the length of the string in
266 *LEN and optionally adjust *PC to point to the correct memory
267 location for inserting the breakpoint.
269 On the i386 we have a single breakpoint that fits in a single byte
270 and can be inserted anywhere.
272 This function is 64-bit safe. */
274 static const gdb_byte
*
275 i386_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
277 static gdb_byte break_insn
[] = { 0xcc }; /* int 3 */
279 *len
= sizeof (break_insn
);
283 /* Displaced instruction handling. */
285 /* Skip the legacy instruction prefixes in INSN.
286 Not all prefixes are valid for any particular insn
287 but we needn't care, the insn will fault if it's invalid.
288 The result is a pointer to the first opcode byte,
289 or NULL if we run off the end of the buffer. */
292 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
294 gdb_byte
*end
= insn
+ max_len
;
300 case DATA_PREFIX_OPCODE
:
301 case ADDR_PREFIX_OPCODE
:
302 case CS_PREFIX_OPCODE
:
303 case DS_PREFIX_OPCODE
:
304 case ES_PREFIX_OPCODE
:
305 case FS_PREFIX_OPCODE
:
306 case GS_PREFIX_OPCODE
:
307 case SS_PREFIX_OPCODE
:
308 case LOCK_PREFIX_OPCODE
:
309 case REPE_PREFIX_OPCODE
:
310 case REPNE_PREFIX_OPCODE
:
322 i386_absolute_jmp_p (const gdb_byte
*insn
)
324 /* jmp far (absolute address in operand) */
330 /* jump near, absolute indirect (/4) */
331 if ((insn
[1] & 0x38) == 0x20)
334 /* jump far, absolute indirect (/5) */
335 if ((insn
[1] & 0x38) == 0x28)
343 i386_absolute_call_p (const gdb_byte
*insn
)
345 /* call far, absolute */
351 /* Call near, absolute indirect (/2) */
352 if ((insn
[1] & 0x38) == 0x10)
355 /* Call far, absolute indirect (/3) */
356 if ((insn
[1] & 0x38) == 0x18)
364 i386_ret_p (const gdb_byte
*insn
)
368 case 0xc2: /* ret near, pop N bytes */
369 case 0xc3: /* ret near */
370 case 0xca: /* ret far, pop N bytes */
371 case 0xcb: /* ret far */
372 case 0xcf: /* iret */
381 i386_call_p (const gdb_byte
*insn
)
383 if (i386_absolute_call_p (insn
))
386 /* call near, relative */
393 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
394 length in bytes. Otherwise, return zero. */
397 i386_syscall_p (const gdb_byte
*insn
, ULONGEST
*lengthp
)
408 /* Fix up the state of registers and memory after having single-stepped
409 a displaced instruction. */
412 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
413 struct displaced_step_closure
*closure
,
414 CORE_ADDR from
, CORE_ADDR to
,
415 struct regcache
*regs
)
417 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
419 /* The offset we applied to the instruction's address.
420 This could well be negative (when viewed as a signed 32-bit
421 value), but ULONGEST won't reflect that, so take care when
423 ULONGEST insn_offset
= to
- from
;
425 /* Since we use simple_displaced_step_copy_insn, our closure is a
426 copy of the instruction. */
427 gdb_byte
*insn
= (gdb_byte
*) closure
;
428 /* The start of the insn, needed in case we see some prefixes. */
429 gdb_byte
*insn_start
= insn
;
432 fprintf_unfiltered (gdb_stdlog
,
433 "displaced: fixup (%s, %s), "
434 "insn = 0x%02x 0x%02x ...\n",
435 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
438 /* The list of issues to contend with here is taken from
439 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
440 Yay for Free Software! */
442 /* Relocate the %eip, if necessary. */
444 /* The instruction recognizers we use assume any leading prefixes
445 have been skipped. */
447 /* This is the size of the buffer in closure. */
448 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
449 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
450 /* If there are too many prefixes, just ignore the insn.
451 It will fault when run. */
456 /* Except in the case of absolute or indirect jump or call
457 instructions, or a return instruction, the new eip is relative to
458 the displaced instruction; make it relative. Well, signal
459 handler returns don't need relocation either, but we use the
460 value of %eip to recognize those; see below. */
461 if (! i386_absolute_jmp_p (insn
)
462 && ! i386_absolute_call_p (insn
)
463 && ! i386_ret_p (insn
))
468 regcache_cooked_read_unsigned (regs
, I386_EIP_REGNUM
, &orig_eip
);
470 /* A signal trampoline system call changes the %eip, resuming
471 execution of the main program after the signal handler has
472 returned. That makes them like 'return' instructions; we
473 shouldn't relocate %eip.
475 But most system calls don't, and we do need to relocate %eip.
477 Our heuristic for distinguishing these cases: if stepping
478 over the system call instruction left control directly after
479 the instruction, the we relocate --- control almost certainly
480 doesn't belong in the displaced copy. Otherwise, we assume
481 the instruction has put control where it belongs, and leave
482 it unrelocated. Goodness help us if there are PC-relative
484 if (i386_syscall_p (insn
, &insn_len
)
485 && orig_eip
!= to
+ (insn
- insn_start
) + insn_len
)
488 fprintf_unfiltered (gdb_stdlog
,
489 "displaced: syscall changed %%eip; "
494 ULONGEST eip
= (orig_eip
- insn_offset
) & 0xffffffffUL
;
496 /* If we just stepped over a breakpoint insn, we don't backup
497 the pc on purpose; this is to match behaviour without
500 regcache_cooked_write_unsigned (regs
, I386_EIP_REGNUM
, eip
);
503 fprintf_unfiltered (gdb_stdlog
,
505 "relocated %%eip from %s to %s\n",
506 paddress (gdbarch
, orig_eip
),
507 paddress (gdbarch
, eip
));
511 /* If the instruction was PUSHFL, then the TF bit will be set in the
512 pushed value, and should be cleared. We'll leave this for later,
513 since GDB already messes up the TF flag when stepping over a
516 /* If the instruction was a call, the return address now atop the
517 stack is the address following the copied instruction. We need
518 to make it the address following the original instruction. */
519 if (i386_call_p (insn
))
523 const ULONGEST retaddr_len
= 4;
525 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
526 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
527 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
528 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
531 fprintf_unfiltered (gdb_stdlog
,
532 "displaced: relocated return addr at %s to %s\n",
533 paddress (gdbarch
, esp
),
534 paddress (gdbarch
, retaddr
));
538 #ifdef I386_REGNO_TO_SYMMETRY
539 #error "The Sequent Symmetry is no longer supported."
542 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
543 and %esp "belong" to the calling function. Therefore these
544 registers should be saved if they're going to be modified. */
546 /* The maximum number of saved registers. This should include all
547 registers mentioned above, and %eip. */
548 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
550 struct i386_frame_cache
557 /* Saved registers. */
558 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
563 /* Stack space reserved for local variables. */
567 /* Allocate and initialize a frame cache. */
569 static struct i386_frame_cache
*
570 i386_alloc_frame_cache (void)
572 struct i386_frame_cache
*cache
;
575 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
579 cache
->sp_offset
= -4;
582 /* Saved registers. We initialize these to -1 since zero is a valid
583 offset (that's where %ebp is supposed to be stored). */
584 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
585 cache
->saved_regs
[i
] = -1;
587 cache
->saved_sp_reg
= -1;
588 cache
->pc_in_eax
= 0;
590 /* Frameless until proven otherwise. */
596 /* If the instruction at PC is a jump, return the address of its
597 target. Otherwise, return PC. */
600 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
607 target_read_memory (pc
, &op
, 1);
611 op
= read_memory_unsigned_integer (pc
+ 1, 1, byte_order
);
617 /* Relative jump: if data16 == 0, disp32, else disp16. */
620 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
622 /* Include the size of the jmp instruction (including the
628 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
630 /* Include the size of the jmp instruction. */
635 /* Relative jump, disp8 (ignore data16). */
636 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
645 /* Check whether PC points at a prologue for a function returning a
646 structure or union. If so, it updates CACHE and returns the
647 address of the first instruction after the code sequence that
648 removes the "hidden" argument from the stack or CURRENT_PC,
649 whichever is smaller. Otherwise, return PC. */
652 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
653 struct i386_frame_cache
*cache
)
655 /* Functions that return a structure or union start with:
658 xchgl %eax, (%esp) 0x87 0x04 0x24
659 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
661 (the System V compiler puts out the second `xchg' instruction,
662 and the assembler doesn't try to optimize it, so the 'sib' form
663 gets generated). This sequence is used to get the address of the
664 return buffer for a function that returns a structure. */
665 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
666 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
670 if (current_pc
<= pc
)
673 target_read_memory (pc
, &op
, 1);
675 if (op
!= 0x58) /* popl %eax */
678 target_read_memory (pc
+ 1, buf
, 4);
679 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
682 if (current_pc
== pc
)
684 cache
->sp_offset
+= 4;
688 if (current_pc
== pc
+ 1)
690 cache
->pc_in_eax
= 1;
694 if (buf
[1] == proto1
[1])
701 i386_skip_probe (CORE_ADDR pc
)
703 /* A function may start with
717 target_read_memory (pc
, &op
, 1);
719 if (op
== 0x68 || op
== 0x6a)
723 /* Skip past the `pushl' instruction; it has either a one-byte or a
724 four-byte operand, depending on the opcode. */
730 /* Read the following 8 bytes, which should be `call _probe' (6
731 bytes) followed by `addl $4,%esp' (2 bytes). */
732 read_memory (pc
+ delta
, buf
, sizeof (buf
));
733 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
734 pc
+= delta
+ sizeof (buf
);
740 /* GCC 4.1 and later, can put code in the prologue to realign the
741 stack pointer. Check whether PC points to such code, and update
742 CACHE accordingly. Return the first instruction after the code
743 sequence or CURRENT_PC, whichever is smaller. If we don't
744 recognize the code, return PC. */
747 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
748 struct i386_frame_cache
*cache
)
750 /* There are 2 code sequences to re-align stack before the frame
753 1. Use a caller-saved saved register:
759 2. Use a callee-saved saved register:
766 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
768 0x83 0xe4 0xf0 andl $-16, %esp
769 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
774 int offset
, offset_and
;
775 static int regnums
[8] = {
776 I386_EAX_REGNUM
, /* %eax */
777 I386_ECX_REGNUM
, /* %ecx */
778 I386_EDX_REGNUM
, /* %edx */
779 I386_EBX_REGNUM
, /* %ebx */
780 I386_ESP_REGNUM
, /* %esp */
781 I386_EBP_REGNUM
, /* %ebp */
782 I386_ESI_REGNUM
, /* %esi */
783 I386_EDI_REGNUM
/* %edi */
786 if (target_read_memory (pc
, buf
, sizeof buf
))
789 /* Check caller-saved saved register. The first instruction has
790 to be "leal 4(%esp), %reg". */
791 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
793 /* MOD must be binary 10 and R/M must be binary 100. */
794 if ((buf
[1] & 0xc7) != 0x44)
797 /* REG has register number. */
798 reg
= (buf
[1] >> 3) & 7;
803 /* Check callee-saved saved register. The first instruction
804 has to be "pushl %reg". */
805 if ((buf
[0] & 0xf8) != 0x50)
811 /* The next instruction has to be "leal 8(%esp), %reg". */
812 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
815 /* MOD must be binary 10 and R/M must be binary 100. */
816 if ((buf
[2] & 0xc7) != 0x44)
819 /* REG has register number. Registers in pushl and leal have to
821 if (reg
!= ((buf
[2] >> 3) & 7))
827 /* Rigister can't be %esp nor %ebp. */
828 if (reg
== 4 || reg
== 5)
831 /* The next instruction has to be "andl $-XXX, %esp". */
832 if (buf
[offset
+ 1] != 0xe4
833 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
837 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
839 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
840 0xfc. REG must be binary 110 and MOD must be binary 01. */
841 if (buf
[offset
] != 0xff
842 || buf
[offset
+ 2] != 0xfc
843 || (buf
[offset
+ 1] & 0xf8) != 0x70)
846 /* R/M has register. Registers in leal and pushl have to be the
848 if (reg
!= (buf
[offset
+ 1] & 7))
851 if (current_pc
> pc
+ offset_and
)
852 cache
->saved_sp_reg
= regnums
[reg
];
854 return min (pc
+ offset
+ 3, current_pc
);
857 /* Maximum instruction length we need to handle. */
858 #define I386_MAX_MATCHED_INSN_LEN 6
860 /* Instruction description. */
864 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
865 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
868 /* Search for the instruction at PC in the list SKIP_INSNS. Return
869 the first instruction description that matches. Otherwise, return
872 static struct i386_insn
*
873 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*skip_insns
)
875 struct i386_insn
*insn
;
878 target_read_memory (pc
, &op
, 1);
880 for (insn
= skip_insns
; insn
->len
> 0; insn
++)
882 if ((op
& insn
->mask
[0]) == insn
->insn
[0])
884 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
885 int insn_matched
= 1;
888 gdb_assert (insn
->len
> 1);
889 gdb_assert (insn
->len
<= I386_MAX_MATCHED_INSN_LEN
);
891 target_read_memory (pc
+ 1, buf
, insn
->len
- 1);
892 for (i
= 1; i
< insn
->len
; i
++)
894 if ((buf
[i
- 1] & insn
->mask
[i
]) != insn
->insn
[i
])
906 /* Some special instructions that might be migrated by GCC into the
907 part of the prologue that sets up the new stack frame. Because the
908 stack frame hasn't been setup yet, no registers have been saved
909 yet, and only the scratch registers %eax, %ecx and %edx can be
912 struct i386_insn i386_frame_setup_skip_insns
[] =
914 /* Check for `movb imm8, r' and `movl imm32, r'.
916 ??? Should we handle 16-bit operand-sizes here? */
918 /* `movb imm8, %al' and `movb imm8, %ah' */
919 /* `movb imm8, %cl' and `movb imm8, %ch' */
920 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
921 /* `movb imm8, %dl' and `movb imm8, %dh' */
922 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
923 /* `movl imm32, %eax' and `movl imm32, %ecx' */
924 { 5, { 0xb8 }, { 0xfe } },
925 /* `movl imm32, %edx' */
926 { 5, { 0xba }, { 0xff } },
928 /* Check for `mov imm32, r32'. Note that there is an alternative
929 encoding for `mov m32, %eax'.
931 ??? Should we handle SIB adressing here?
932 ??? Should we handle 16-bit operand-sizes here? */
934 /* `movl m32, %eax' */
935 { 5, { 0xa1 }, { 0xff } },
936 /* `movl m32, %eax' and `mov; m32, %ecx' */
937 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
938 /* `movl m32, %edx' */
939 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
941 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
942 Because of the symmetry, there are actually two ways to encode
943 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
944 opcode bytes 0x31 and 0x33 for `xorl'. */
946 /* `subl %eax, %eax' */
947 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
948 /* `subl %ecx, %ecx' */
949 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
950 /* `subl %edx, %edx' */
951 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
952 /* `xorl %eax, %eax' */
953 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
954 /* `xorl %ecx, %ecx' */
955 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
956 /* `xorl %edx, %edx' */
957 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
962 /* Check whether PC points to a no-op instruction. */
964 i386_skip_noop (CORE_ADDR pc
)
969 target_read_memory (pc
, &op
, 1);
974 /* Ignore `nop' instruction. */
978 target_read_memory (pc
, &op
, 1);
981 /* Ignore no-op instruction `mov %edi, %edi'.
982 Microsoft system dlls often start with
983 a `mov %edi,%edi' instruction.
984 The 5 bytes before the function start are
985 filled with `nop' instructions.
986 This pattern can be used for hot-patching:
987 The `mov %edi, %edi' instruction can be replaced by a
988 near jump to the location of the 5 `nop' instructions
989 which can be replaced by a 32-bit jump to anywhere
990 in the 32-bit address space. */
994 target_read_memory (pc
+ 1, &op
, 1);
998 target_read_memory (pc
, &op
, 1);
1006 /* Check whether PC points at a code that sets up a new stack frame.
1007 If so, it updates CACHE and returns the address of the first
1008 instruction after the sequence that sets up the frame or LIMIT,
1009 whichever is smaller. If we don't recognize the code, return PC. */
1012 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1013 CORE_ADDR pc
, CORE_ADDR limit
,
1014 struct i386_frame_cache
*cache
)
1016 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1017 struct i386_insn
*insn
;
1024 target_read_memory (pc
, &op
, 1);
1026 if (op
== 0x55) /* pushl %ebp */
1028 /* Take into account that we've executed the `pushl %ebp' that
1029 starts this instruction sequence. */
1030 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1031 cache
->sp_offset
+= 4;
1034 /* If that's all, return now. */
1038 /* Check for some special instructions that might be migrated by
1039 GCC into the prologue and skip them. At this point in the
1040 prologue, code should only touch the scratch registers %eax,
1041 %ecx and %edx, so while the number of posibilities is sheer,
1044 Make sure we only skip these instructions if we later see the
1045 `movl %esp, %ebp' that actually sets up the frame. */
1046 while (pc
+ skip
< limit
)
1048 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1055 /* If that's all, return now. */
1056 if (limit
<= pc
+ skip
)
1059 target_read_memory (pc
+ skip
, &op
, 1);
1061 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1065 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1070 if (read_memory_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1078 /* OK, we actually have a frame. We just don't know how large
1079 it is yet. Set its size to zero. We'll adjust it if
1080 necessary. We also now commit to skipping the special
1081 instructions mentioned before. */
1085 /* If that's all, return now. */
1089 /* Check for stack adjustment
1093 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1094 reg, so we don't have to worry about a data16 prefix. */
1095 target_read_memory (pc
, &op
, 1);
1098 /* `subl' with 8-bit immediate. */
1099 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1100 /* Some instruction starting with 0x83 other than `subl'. */
1103 /* `subl' with signed 8-bit immediate (though it wouldn't
1104 make sense to be negative). */
1105 cache
->locals
= read_memory_integer (pc
+ 2, 1, byte_order
);
1108 else if (op
== 0x81)
1110 /* Maybe it is `subl' with a 32-bit immediate. */
1111 if (read_memory_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1112 /* Some instruction starting with 0x81 other than `subl'. */
1115 /* It is `subl' with a 32-bit immediate. */
1116 cache
->locals
= read_memory_integer (pc
+ 2, 4, byte_order
);
1121 /* Some instruction other than `subl'. */
1125 else if (op
== 0xc8) /* enter */
1127 cache
->locals
= read_memory_unsigned_integer (pc
+ 1, 2, byte_order
);
1134 /* Check whether PC points at code that saves registers on the stack.
1135 If so, it updates CACHE and returns the address of the first
1136 instruction after the register saves or CURRENT_PC, whichever is
1137 smaller. Otherwise, return PC. */
1140 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1141 struct i386_frame_cache
*cache
)
1143 CORE_ADDR offset
= 0;
1147 if (cache
->locals
> 0)
1148 offset
-= cache
->locals
;
1149 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1151 target_read_memory (pc
, &op
, 1);
1152 if (op
< 0x50 || op
> 0x57)
1156 cache
->saved_regs
[op
- 0x50] = offset
;
1157 cache
->sp_offset
+= 4;
1164 /* Do a full analysis of the prologue at PC and update CACHE
1165 accordingly. Bail out early if CURRENT_PC is reached. Return the
1166 address where the analysis stopped.
1168 We handle these cases:
1170 The startup sequence can be at the start of the function, or the
1171 function can start with a branch to startup code at the end.
1173 %ebp can be set up with either the 'enter' instruction, or "pushl
1174 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1175 once used in the System V compiler).
1177 Local space is allocated just below the saved %ebp by either the
1178 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1179 16-bit unsigned argument for space to allocate, and the 'addl'
1180 instruction could have either a signed byte, or 32-bit immediate.
1182 Next, the registers used by this function are pushed. With the
1183 System V compiler they will always be in the order: %edi, %esi,
1184 %ebx (and sometimes a harmless bug causes it to also save but not
1185 restore %eax); however, the code below is willing to see the pushes
1186 in any order, and will handle up to 8 of them.
1188 If the setup sequence is at the end of the function, then the next
1189 instruction will be a branch back to the start. */
1192 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1193 CORE_ADDR pc
, CORE_ADDR current_pc
,
1194 struct i386_frame_cache
*cache
)
1196 pc
= i386_skip_noop (pc
);
1197 pc
= i386_follow_jump (gdbarch
, pc
);
1198 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1199 pc
= i386_skip_probe (pc
);
1200 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1201 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1202 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1205 /* Return PC of first real instruction. */
1208 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1210 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1212 static gdb_byte pic_pat
[6] =
1214 0xe8, 0, 0, 0, 0, /* call 0x0 */
1215 0x5b, /* popl %ebx */
1217 struct i386_frame_cache cache
;
1223 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1224 if (cache
.locals
< 0)
1227 /* Found valid frame setup. */
1229 /* The native cc on SVR4 in -K PIC mode inserts the following code
1230 to get the address of the global offset table (GOT) into register
1235 movl %ebx,x(%ebp) (optional)
1238 This code is with the rest of the prologue (at the end of the
1239 function), so we have to skip it to get to the first real
1240 instruction at the start of the function. */
1242 for (i
= 0; i
< 6; i
++)
1244 target_read_memory (pc
+ i
, &op
, 1);
1245 if (pic_pat
[i
] != op
)
1252 target_read_memory (pc
+ delta
, &op
, 1);
1254 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1256 op
= read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1258 if (op
== 0x5d) /* One byte offset from %ebp. */
1260 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1262 else /* Unexpected instruction. */
1265 target_read_memory (pc
+ delta
, &op
, 1);
1269 if (delta
> 0 && op
== 0x81
1270 && read_memory_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1277 /* If the function starts with a branch (to startup code at the end)
1278 the last instruction should bring us back to the first
1279 instruction of the real code. */
1280 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1281 pc
= i386_follow_jump (gdbarch
, pc
);
1286 /* Check that the code pointed to by PC corresponds to a call to
1287 __main, skip it if so. Return PC otherwise. */
1290 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1292 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1295 target_read_memory (pc
, &op
, 1);
1300 if (target_read_memory (pc
+ 1, buf
, sizeof buf
) == 0)
1302 /* Make sure address is computed correctly as a 32bit
1303 integer even if CORE_ADDR is 64 bit wide. */
1304 struct minimal_symbol
*s
;
1305 CORE_ADDR call_dest
;
1307 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1308 call_dest
= call_dest
& 0xffffffffU
;
1309 s
= lookup_minimal_symbol_by_pc (call_dest
);
1311 && SYMBOL_LINKAGE_NAME (s
) != NULL
1312 && strcmp (SYMBOL_LINKAGE_NAME (s
), "__main") == 0)
1320 /* This function is 64-bit safe. */
1323 i386_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1327 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1328 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1332 /* Normal frames. */
1334 static struct i386_frame_cache
*
1335 i386_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1337 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1338 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1339 struct i386_frame_cache
*cache
;
1346 cache
= i386_alloc_frame_cache ();
1347 *this_cache
= cache
;
1349 /* In principle, for normal frames, %ebp holds the frame pointer,
1350 which holds the base address for the current stack frame.
1351 However, for functions that don't need it, the frame pointer is
1352 optional. For these "frameless" functions the frame pointer is
1353 actually the frame pointer of the calling frame. Signal
1354 trampolines are just a special case of a "frameless" function.
1355 They (usually) share their frame pointer with the frame that was
1356 in progress when the signal occurred. */
1358 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
1359 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
1360 if (cache
->base
== 0)
1363 /* For normal frames, %eip is stored at 4(%ebp). */
1364 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
1366 cache
->pc
= get_frame_func (this_frame
);
1368 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
1371 if (cache
->saved_sp_reg
!= -1)
1373 /* Saved stack pointer has been saved. */
1374 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
1375 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1378 if (cache
->locals
< 0)
1380 /* We didn't find a valid frame, which means that CACHE->base
1381 currently holds the frame pointer for our calling frame. If
1382 we're at the start of a function, or somewhere half-way its
1383 prologue, the function's frame probably hasn't been fully
1384 setup yet. Try to reconstruct the base address for the stack
1385 frame by looking at the stack pointer. For truly "frameless"
1386 functions this might work too. */
1388 if (cache
->saved_sp_reg
!= -1)
1390 /* We're halfway aligning the stack. */
1391 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
1392 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
1394 /* This will be added back below. */
1395 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
1399 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1400 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
1405 /* Now that we have the base address for the stack frame we can
1406 calculate the value of %esp in the calling frame. */
1407 if (cache
->saved_sp
== 0)
1408 cache
->saved_sp
= cache
->base
+ 8;
1410 /* Adjust all the saved registers such that they contain addresses
1411 instead of offsets. */
1412 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1413 if (cache
->saved_regs
[i
] != -1)
1414 cache
->saved_regs
[i
] += cache
->base
;
1420 i386_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1421 struct frame_id
*this_id
)
1423 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1425 /* This marks the outermost frame. */
1426 if (cache
->base
== 0)
1429 /* See the end of i386_push_dummy_call. */
1430 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1433 static struct value
*
1434 i386_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1437 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1439 gdb_assert (regnum
>= 0);
1441 /* The System V ABI says that:
1443 "The flags register contains the system flags, such as the
1444 direction flag and the carry flag. The direction flag must be
1445 set to the forward (that is, zero) direction before entry and
1446 upon exit from a function. Other user flags have no specified
1447 role in the standard calling sequence and are not preserved."
1449 To guarantee the "upon exit" part of that statement we fake a
1450 saved flags register that has its direction flag cleared.
1452 Note that GCC doesn't seem to rely on the fact that the direction
1453 flag is cleared after a function return; it always explicitly
1454 clears the flag before operations where it matters.
1456 FIXME: kettenis/20030316: I'm not quite sure whether this is the
1457 right thing to do. The way we fake the flags register here makes
1458 it impossible to change it. */
1460 if (regnum
== I386_EFLAGS_REGNUM
)
1464 val
= get_frame_register_unsigned (this_frame
, regnum
);
1466 return frame_unwind_got_constant (this_frame
, regnum
, val
);
1469 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
1470 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
1472 if (regnum
== I386_ESP_REGNUM
&& cache
->saved_sp
)
1473 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1475 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
1476 return frame_unwind_got_memory (this_frame
, regnum
,
1477 cache
->saved_regs
[regnum
]);
1479 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1482 static const struct frame_unwind i386_frame_unwind
=
1486 i386_frame_prev_register
,
1488 default_frame_sniffer
1491 /* Normal frames, but in a function epilogue. */
1493 /* The epilogue is defined here as the 'ret' instruction, which will
1494 follow any instruction such as 'leave' or 'pop %ebp' that destroys
1495 the function's stack frame. */
1498 i386_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1502 if (target_read_memory (pc
, &insn
, 1))
1503 return 0; /* Can't read memory at pc. */
1505 if (insn
!= 0xc3) /* 'ret' instruction. */
1512 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
1513 struct frame_info
*this_frame
,
1514 void **this_prologue_cache
)
1516 if (frame_relative_level (this_frame
) == 0)
1517 return i386_in_function_epilogue_p (get_frame_arch (this_frame
),
1518 get_frame_pc (this_frame
));
1523 static struct i386_frame_cache
*
1524 i386_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1526 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1527 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1528 struct i386_frame_cache
*cache
;
1534 cache
= i386_alloc_frame_cache ();
1535 *this_cache
= cache
;
1537 /* Cache base will be %esp plus cache->sp_offset (-4). */
1538 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1539 cache
->base
= extract_unsigned_integer (buf
, 4,
1540 byte_order
) + cache
->sp_offset
;
1542 /* Cache pc will be the frame func. */
1543 cache
->pc
= get_frame_pc (this_frame
);
1545 /* The saved %esp will be at cache->base plus 8. */
1546 cache
->saved_sp
= cache
->base
+ 8;
1548 /* The saved %eip will be at cache->base plus 4. */
1549 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
1555 i386_epilogue_frame_this_id (struct frame_info
*this_frame
,
1557 struct frame_id
*this_id
)
1559 struct i386_frame_cache
*cache
= i386_epilogue_frame_cache (this_frame
,
1562 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
1565 static const struct frame_unwind i386_epilogue_frame_unwind
=
1568 i386_epilogue_frame_this_id
,
1569 i386_frame_prev_register
,
1571 i386_epilogue_frame_sniffer
1575 /* Signal trampolines. */
1577 static struct i386_frame_cache
*
1578 i386_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1580 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1582 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1583 struct i386_frame_cache
*cache
;
1590 cache
= i386_alloc_frame_cache ();
1592 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
1593 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
1595 addr
= tdep
->sigcontext_addr (this_frame
);
1596 if (tdep
->sc_reg_offset
)
1600 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
1602 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
1603 if (tdep
->sc_reg_offset
[i
] != -1)
1604 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
1608 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
1609 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
1612 *this_cache
= cache
;
1617 i386_sigtramp_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1618 struct frame_id
*this_id
)
1620 struct i386_frame_cache
*cache
=
1621 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1623 /* See the end of i386_push_dummy_call. */
1624 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
1627 static struct value
*
1628 i386_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
1629 void **this_cache
, int regnum
)
1631 /* Make sure we've initialized the cache. */
1632 i386_sigtramp_frame_cache (this_frame
, this_cache
);
1634 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
1638 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
1639 struct frame_info
*this_frame
,
1640 void **this_prologue_cache
)
1642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1644 /* We shouldn't even bother if we don't have a sigcontext_addr
1646 if (tdep
->sigcontext_addr
== NULL
)
1649 if (tdep
->sigtramp_p
!= NULL
)
1651 if (tdep
->sigtramp_p (this_frame
))
1655 if (tdep
->sigtramp_start
!= 0)
1657 CORE_ADDR pc
= get_frame_pc (this_frame
);
1659 gdb_assert (tdep
->sigtramp_end
!= 0);
1660 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
1667 static const struct frame_unwind i386_sigtramp_frame_unwind
=
1670 i386_sigtramp_frame_this_id
,
1671 i386_sigtramp_frame_prev_register
,
1673 i386_sigtramp_frame_sniffer
1678 i386_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1680 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
1685 static const struct frame_base i386_frame_base
=
1688 i386_frame_base_address
,
1689 i386_frame_base_address
,
1690 i386_frame_base_address
1693 static struct frame_id
1694 i386_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1698 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
1700 /* See the end of i386_push_dummy_call. */
1701 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
1705 /* Figure out where the longjmp will land. Slurp the args out of the
1706 stack. We expect the first arg to be a pointer to the jmp_buf
1707 structure from which we extract the address that we will land at.
1708 This address is copied into PC. This routine returns non-zero on
1712 i386_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1715 CORE_ADDR sp
, jb_addr
;
1716 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1717 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1718 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
1720 /* If JB_PC_OFFSET is -1, we have no way to find out where the
1721 longjmp will land. */
1722 if (jb_pc_offset
== -1)
1725 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
1726 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
1727 if (target_read_memory (sp
+ 4, buf
, 4))
1730 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
1731 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
1734 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1739 /* Check whether TYPE must be 16-byte-aligned when passed as a
1740 function argument. 16-byte vectors, _Decimal128 and structures or
1741 unions containing such types must be 16-byte-aligned; other
1742 arguments are 4-byte-aligned. */
1745 i386_16_byte_align_p (struct type
*type
)
1747 type
= check_typedef (type
);
1748 if ((TYPE_CODE (type
) == TYPE_CODE_DECFLOAT
1749 || (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)))
1750 && TYPE_LENGTH (type
) == 16)
1752 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1753 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type
));
1754 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
1755 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
1758 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1760 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type
, i
)))
1768 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1769 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1770 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1771 CORE_ADDR struct_addr
)
1773 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1779 /* Determine the total space required for arguments and struct
1780 return address in a first pass (allowing for 16-byte-aligned
1781 arguments), then push arguments in a second pass. */
1783 for (write_pass
= 0; write_pass
< 2; write_pass
++)
1785 int args_space_used
= 0;
1786 int have_16_byte_aligned_arg
= 0;
1792 /* Push value address. */
1793 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
1794 write_memory (sp
, buf
, 4);
1795 args_space_used
+= 4;
1801 for (i
= 0; i
< nargs
; i
++)
1803 int len
= TYPE_LENGTH (value_enclosing_type (args
[i
]));
1807 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1808 args_space_used
= align_up (args_space_used
, 16);
1810 write_memory (sp
+ args_space_used
,
1811 value_contents_all (args
[i
]), len
);
1812 /* The System V ABI says that:
1814 "An argument's size is increased, if necessary, to make it a
1815 multiple of [32-bit] words. This may require tail padding,
1816 depending on the size of the argument."
1818 This makes sure the stack stays word-aligned. */
1819 args_space_used
+= align_up (len
, 4);
1823 if (i386_16_byte_align_p (value_enclosing_type (args
[i
])))
1825 args_space
= align_up (args_space
, 16);
1826 have_16_byte_aligned_arg
= 1;
1828 args_space
+= align_up (len
, 4);
1834 if (have_16_byte_aligned_arg
)
1835 args_space
= align_up (args_space
, 16);
1840 /* Store return address. */
1842 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
1843 write_memory (sp
, buf
, 4);
1845 /* Finally, update the stack pointer... */
1846 store_unsigned_integer (buf
, 4, byte_order
, sp
);
1847 regcache_cooked_write (regcache
, I386_ESP_REGNUM
, buf
);
1849 /* ...and fake a frame pointer. */
1850 regcache_cooked_write (regcache
, I386_EBP_REGNUM
, buf
);
1852 /* MarkK wrote: This "+ 8" is all over the place:
1853 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1854 i386_dummy_id). It's there, since all frame unwinders for
1855 a given target have to agree (within a certain margin) on the
1856 definition of the stack address of a frame. Otherwise frame id
1857 comparison might not work correctly. Since DWARF2/GCC uses the
1858 stack address *before* the function call as a frame's CFA. On
1859 the i386, when %ebp is used as a frame pointer, the offset
1860 between the contents %ebp and the CFA as defined by GCC. */
1864 /* These registers are used for returning integers (and on some
1865 targets also for returning `struct' and `union' values when their
1866 size and alignment match an integer type). */
1867 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1868 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1870 /* Read, for architecture GDBARCH, a function return value of TYPE
1871 from REGCACHE, and copy that into VALBUF. */
1874 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1875 struct regcache
*regcache
, gdb_byte
*valbuf
)
1877 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1878 int len
= TYPE_LENGTH (type
);
1879 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1881 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1883 if (tdep
->st0_regnum
< 0)
1885 warning (_("Cannot find floating-point return value."));
1886 memset (valbuf
, 0, len
);
1890 /* Floating-point return values can be found in %st(0). Convert
1891 its contents to the desired type. This is probably not
1892 exactly how it would happen on the target itself, but it is
1893 the best we can do. */
1894 regcache_raw_read (regcache
, I386_ST0_REGNUM
, buf
);
1895 convert_typed_floating (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
1899 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1900 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1902 if (len
<= low_size
)
1904 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1905 memcpy (valbuf
, buf
, len
);
1907 else if (len
<= (low_size
+ high_size
))
1909 regcache_raw_read (regcache
, LOW_RETURN_REGNUM
, buf
);
1910 memcpy (valbuf
, buf
, low_size
);
1911 regcache_raw_read (regcache
, HIGH_RETURN_REGNUM
, buf
);
1912 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
1915 internal_error (__FILE__
, __LINE__
,
1916 _("Cannot extract return value of %d bytes long."), len
);
1920 /* Write, for architecture GDBARCH, a function return value of TYPE
1921 from VALBUF into REGCACHE. */
1924 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1925 struct regcache
*regcache
, const gdb_byte
*valbuf
)
1927 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1928 int len
= TYPE_LENGTH (type
);
1930 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1933 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
1935 if (tdep
->st0_regnum
< 0)
1937 warning (_("Cannot set floating-point return value."));
1941 /* Returning floating-point values is a bit tricky. Apart from
1942 storing the return value in %st(0), we have to simulate the
1943 state of the FPU at function return point. */
1945 /* Convert the value found in VALBUF to the extended
1946 floating-point format used by the FPU. This is probably
1947 not exactly how it would happen on the target itself, but
1948 it is the best we can do. */
1949 convert_typed_floating (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
1950 regcache_raw_write (regcache
, I386_ST0_REGNUM
, buf
);
1952 /* Set the top of the floating-point register stack to 7. The
1953 actual value doesn't really matter, but 7 is what a normal
1954 function return would end up with if the program started out
1955 with a freshly initialized FPU. */
1956 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1958 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1960 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1961 the floating-point register stack to 7, the appropriate value
1962 for the tag word is 0x3fff. */
1963 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
1967 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
1968 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
1970 if (len
<= low_size
)
1971 regcache_raw_write_part (regcache
, LOW_RETURN_REGNUM
, 0, len
, valbuf
);
1972 else if (len
<= (low_size
+ high_size
))
1974 regcache_raw_write (regcache
, LOW_RETURN_REGNUM
, valbuf
);
1975 regcache_raw_write_part (regcache
, HIGH_RETURN_REGNUM
, 0,
1976 len
- low_size
, valbuf
+ low_size
);
1979 internal_error (__FILE__
, __LINE__
,
1980 _("Cannot store return value of %d bytes long."), len
);
1985 /* This is the variable that is set with "set struct-convention", and
1986 its legitimate values. */
1987 static const char default_struct_convention
[] = "default";
1988 static const char pcc_struct_convention
[] = "pcc";
1989 static const char reg_struct_convention
[] = "reg";
1990 static const char *valid_conventions
[] =
1992 default_struct_convention
,
1993 pcc_struct_convention
,
1994 reg_struct_convention
,
1997 static const char *struct_convention
= default_struct_convention
;
1999 /* Return non-zero if TYPE, which is assumed to be a structure,
2000 a union type, or an array type, should be returned in registers
2001 for architecture GDBARCH. */
2004 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
2006 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2007 enum type_code code
= TYPE_CODE (type
);
2008 int len
= TYPE_LENGTH (type
);
2010 gdb_assert (code
== TYPE_CODE_STRUCT
2011 || code
== TYPE_CODE_UNION
2012 || code
== TYPE_CODE_ARRAY
);
2014 if (struct_convention
== pcc_struct_convention
2015 || (struct_convention
== default_struct_convention
2016 && tdep
->struct_return
== pcc_struct_return
))
2019 /* Structures consisting of a single `float', `double' or 'long
2020 double' member are returned in %st(0). */
2021 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2023 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2024 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2025 return (len
== 4 || len
== 8 || len
== 12);
2028 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
2031 /* Determine, for architecture GDBARCH, how a return value of TYPE
2032 should be returned. If it is supposed to be returned in registers,
2033 and READBUF is non-zero, read the appropriate value from REGCACHE,
2034 and copy it into READBUF. If WRITEBUF is non-zero, write the value
2035 from WRITEBUF into REGCACHE. */
2037 static enum return_value_convention
2038 i386_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2039 struct type
*type
, struct regcache
*regcache
,
2040 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2042 enum type_code code
= TYPE_CODE (type
);
2044 if (((code
== TYPE_CODE_STRUCT
2045 || code
== TYPE_CODE_UNION
2046 || code
== TYPE_CODE_ARRAY
)
2047 && !i386_reg_struct_return_p (gdbarch
, type
))
2048 /* 128-bit decimal float uses the struct return convention. */
2049 || (code
== TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type
) == 16))
2051 /* The System V ABI says that:
2053 "A function that returns a structure or union also sets %eax
2054 to the value of the original address of the caller's area
2055 before it returns. Thus when the caller receives control
2056 again, the address of the returned object resides in register
2057 %eax and can be used to access the object."
2059 So the ABI guarantees that we can always find the return
2060 value just after the function has returned. */
2062 /* Note that the ABI doesn't mention functions returning arrays,
2063 which is something possible in certain languages such as Ada.
2064 In this case, the value is returned as if it was wrapped in
2065 a record, so the convention applied to records also applies
2072 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
2073 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
2076 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2079 /* This special case is for structures consisting of a single
2080 `float', `double' or 'long double' member. These structures are
2081 returned in %st(0). For these structures, we call ourselves
2082 recursively, changing TYPE into the type of the first member of
2083 the structure. Since that should work for all structures that
2084 have only one member, we don't bother to check the member's type
2086 if (code
== TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type
) == 1)
2088 type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2089 return i386_return_value (gdbarch
, func_type
, type
, regcache
,
2094 i386_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
2096 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
2098 return RETURN_VALUE_REGISTER_CONVENTION
;
2102 /* Construct types for ISA-specific registers. */
2104 i386_eflags_type (struct gdbarch
*gdbarch
)
2106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2108 if (!tdep
->i386_eflags_type
)
2112 type
= arch_flags_type (gdbarch
, "builtin_type_i386_eflags", 4);
2113 append_flags_type_flag (type
, 0, "CF");
2114 append_flags_type_flag (type
, 1, NULL
);
2115 append_flags_type_flag (type
, 2, "PF");
2116 append_flags_type_flag (type
, 4, "AF");
2117 append_flags_type_flag (type
, 6, "ZF");
2118 append_flags_type_flag (type
, 7, "SF");
2119 append_flags_type_flag (type
, 8, "TF");
2120 append_flags_type_flag (type
, 9, "IF");
2121 append_flags_type_flag (type
, 10, "DF");
2122 append_flags_type_flag (type
, 11, "OF");
2123 append_flags_type_flag (type
, 14, "NT");
2124 append_flags_type_flag (type
, 16, "RF");
2125 append_flags_type_flag (type
, 17, "VM");
2126 append_flags_type_flag (type
, 18, "AC");
2127 append_flags_type_flag (type
, 19, "VIF");
2128 append_flags_type_flag (type
, 20, "VIP");
2129 append_flags_type_flag (type
, 21, "ID");
2131 tdep
->i386_eflags_type
= type
;
2134 return tdep
->i386_eflags_type
;
2138 i386_mxcsr_type (struct gdbarch
*gdbarch
)
2140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2142 if (!tdep
->i386_mxcsr_type
)
2146 type
= arch_flags_type (gdbarch
, "builtin_type_i386_mxcsr", 4);
2147 append_flags_type_flag (type
, 0, "IE");
2148 append_flags_type_flag (type
, 1, "DE");
2149 append_flags_type_flag (type
, 2, "ZE");
2150 append_flags_type_flag (type
, 3, "OE");
2151 append_flags_type_flag (type
, 4, "UE");
2152 append_flags_type_flag (type
, 5, "PE");
2153 append_flags_type_flag (type
, 6, "DAZ");
2154 append_flags_type_flag (type
, 7, "IM");
2155 append_flags_type_flag (type
, 8, "DM");
2156 append_flags_type_flag (type
, 9, "ZM");
2157 append_flags_type_flag (type
, 10, "OM");
2158 append_flags_type_flag (type
, 11, "UM");
2159 append_flags_type_flag (type
, 12, "PM");
2160 append_flags_type_flag (type
, 15, "FZ");
2162 tdep
->i386_mxcsr_type
= type
;
2165 return tdep
->i386_mxcsr_type
;
2169 i387_ext_type (struct gdbarch
*gdbarch
)
2171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2173 if (!tdep
->i387_ext_type
)
2175 = arch_float_type (gdbarch
, -1, "builtin_type_i387_ext",
2176 floatformats_i387_ext
);
2178 return tdep
->i387_ext_type
;
2181 /* Construct vector type for MMX registers. */
2183 i386_mmx_type (struct gdbarch
*gdbarch
)
2185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2187 if (!tdep
->i386_mmx_type
)
2189 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2191 /* The type we're building is this: */
2193 union __gdb_builtin_type_vec64i
2196 int32_t v2_int32
[2];
2197 int16_t v4_int16
[4];
2204 t
= arch_composite_type (gdbarch
,
2205 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
2207 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2208 append_composite_type_field (t
, "v2_int32",
2209 init_vector_type (bt
->builtin_int32
, 2));
2210 append_composite_type_field (t
, "v4_int16",
2211 init_vector_type (bt
->builtin_int16
, 4));
2212 append_composite_type_field (t
, "v8_int8",
2213 init_vector_type (bt
->builtin_int8
, 8));
2215 TYPE_VECTOR (t
) = 1;
2216 TYPE_NAME (t
) = "builtin_type_vec64i";
2217 tdep
->i386_mmx_type
= t
;
2220 return tdep
->i386_mmx_type
;
2224 i386_sse_type (struct gdbarch
*gdbarch
)
2226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2228 if (!tdep
->i386_sse_type
)
2230 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2232 /* The type we're building is this: */
2234 union __gdb_builtin_type_vec128i
2237 int64_t v2_int64
[2];
2238 int32_t v4_int32
[4];
2239 int16_t v8_int16
[8];
2240 int8_t v16_int8
[16];
2241 double v2_double
[2];
2248 t
= arch_composite_type (gdbarch
,
2249 "__gdb_builtin_type_vec128i", TYPE_CODE_UNION
);
2250 append_composite_type_field (t
, "v4_float",
2251 init_vector_type (bt
->builtin_float
, 4));
2252 append_composite_type_field (t
, "v2_double",
2253 init_vector_type (bt
->builtin_double
, 2));
2254 append_composite_type_field (t
, "v16_int8",
2255 init_vector_type (bt
->builtin_int8
, 16));
2256 append_composite_type_field (t
, "v8_int16",
2257 init_vector_type (bt
->builtin_int16
, 8));
2258 append_composite_type_field (t
, "v4_int32",
2259 init_vector_type (bt
->builtin_int32
, 4));
2260 append_composite_type_field (t
, "v2_int64",
2261 init_vector_type (bt
->builtin_int64
, 2));
2262 append_composite_type_field (t
, "uint128", bt
->builtin_int128
);
2264 TYPE_VECTOR (t
) = 1;
2265 TYPE_NAME (t
) = "builtin_type_vec128i";
2266 tdep
->i386_sse_type
= t
;
2269 return tdep
->i386_sse_type
;
2272 /* Return the GDB type object for the "standard" data type of data in
2273 register REGNUM. Perhaps %esi and %edi should go here, but
2274 potentially they could be used for things other than address. */
2276 static struct type
*
2277 i386_register_type (struct gdbarch
*gdbarch
, int regnum
)
2279 if (regnum
== I386_EIP_REGNUM
)
2280 return builtin_type (gdbarch
)->builtin_func_ptr
;
2282 if (regnum
== I386_EFLAGS_REGNUM
)
2283 return i386_eflags_type (gdbarch
);
2285 if (regnum
== I386_EBP_REGNUM
|| regnum
== I386_ESP_REGNUM
)
2286 return builtin_type (gdbarch
)->builtin_data_ptr
;
2288 if (i386_fp_regnum_p (gdbarch
, regnum
))
2289 return i387_ext_type (gdbarch
);
2291 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2292 return i386_mmx_type (gdbarch
);
2294 if (i386_sse_regnum_p (gdbarch
, regnum
))
2295 return i386_sse_type (gdbarch
);
2297 if (regnum
== I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch
)))
2298 return i386_mxcsr_type (gdbarch
);
2300 return builtin_type (gdbarch
)->builtin_int
;
2303 /* Map a cooked register onto a raw register or memory. For the i386,
2304 the MMX registers need to be mapped onto floating point registers. */
2307 i386_mmx_regnum_to_fp_regnum (struct regcache
*regcache
, int regnum
)
2309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
2314 mmxreg
= regnum
- tdep
->mm0_regnum
;
2315 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2316 tos
= (fstat
>> 11) & 0x7;
2317 fpreg
= (mmxreg
+ tos
) % 8;
2319 return (I387_ST0_REGNUM (tdep
) + fpreg
);
2323 i386_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2324 int regnum
, gdb_byte
*buf
)
2326 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2328 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2329 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2331 /* Extract (always little endian). */
2332 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2333 memcpy (buf
, mmx_buf
, register_size (gdbarch
, regnum
));
2336 regcache_raw_read (regcache
, regnum
, buf
);
2340 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2341 int regnum
, const gdb_byte
*buf
)
2343 if (i386_mmx_regnum_p (gdbarch
, regnum
))
2345 gdb_byte mmx_buf
[MAX_REGISTER_SIZE
];
2346 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
2349 regcache_raw_read (regcache
, fpnum
, mmx_buf
);
2350 /* ... Modify ... (always little endian). */
2351 memcpy (mmx_buf
, buf
, register_size (gdbarch
, regnum
));
2353 regcache_raw_write (regcache
, fpnum
, mmx_buf
);
2356 regcache_raw_write (regcache
, regnum
, buf
);
2360 /* Return the register number of the register allocated by GCC after
2361 REGNUM, or -1 if there is no such register. */
2364 i386_next_regnum (int regnum
)
2366 /* GCC allocates the registers in the order:
2368 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
2370 Since storing a variable in %esp doesn't make any sense we return
2371 -1 for %ebp and for %esp itself. */
2372 static int next_regnum
[] =
2374 I386_EDX_REGNUM
, /* Slot for %eax. */
2375 I386_EBX_REGNUM
, /* Slot for %ecx. */
2376 I386_ECX_REGNUM
, /* Slot for %edx. */
2377 I386_ESI_REGNUM
, /* Slot for %ebx. */
2378 -1, -1, /* Slots for %esp and %ebp. */
2379 I386_EDI_REGNUM
, /* Slot for %esi. */
2380 I386_EBP_REGNUM
/* Slot for %edi. */
2383 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
2384 return next_regnum
[regnum
];
2389 /* Return nonzero if a value of type TYPE stored in register REGNUM
2390 needs any special handling. */
2393 i386_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
2395 int len
= TYPE_LENGTH (type
);
2397 /* Values may be spread across multiple registers. Most debugging
2398 formats aren't expressive enough to specify the locations, so
2399 some heuristics is involved. Right now we only handle types that
2400 have a length that is a multiple of the word size, since GCC
2401 doesn't seem to put any other types into registers. */
2402 if (len
> 4 && len
% 4 == 0)
2404 int last_regnum
= regnum
;
2408 last_regnum
= i386_next_regnum (last_regnum
);
2412 if (last_regnum
!= -1)
2416 return i387_convert_register_p (gdbarch
, regnum
, type
);
2419 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
2420 return its contents in TO. */
2423 i386_register_to_value (struct frame_info
*frame
, int regnum
,
2424 struct type
*type
, gdb_byte
*to
)
2426 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2427 int len
= TYPE_LENGTH (type
);
2429 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
2430 available in FRAME (i.e. if it wasn't saved)? */
2432 if (i386_fp_regnum_p (gdbarch
, regnum
))
2434 i387_register_to_value (frame
, regnum
, type
, to
);
2438 /* Read a value spread across multiple registers. */
2440 gdb_assert (len
> 4 && len
% 4 == 0);
2444 gdb_assert (regnum
!= -1);
2445 gdb_assert (register_size (gdbarch
, regnum
) == 4);
2447 get_frame_register (frame
, regnum
, to
);
2448 regnum
= i386_next_regnum (regnum
);
2454 /* Write the contents FROM of a value of type TYPE into register
2455 REGNUM in frame FRAME. */
2458 i386_value_to_register (struct frame_info
*frame
, int regnum
,
2459 struct type
*type
, const gdb_byte
*from
)
2461 int len
= TYPE_LENGTH (type
);
2463 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
2465 i387_value_to_register (frame
, regnum
, type
, from
);
2469 /* Write a value spread across multiple registers. */
2471 gdb_assert (len
> 4 && len
% 4 == 0);
2475 gdb_assert (regnum
!= -1);
2476 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
2478 put_frame_register (frame
, regnum
, from
);
2479 regnum
= i386_next_regnum (regnum
);
2485 /* Supply register REGNUM from the buffer specified by GREGS and LEN
2486 in the general-purpose register set REGSET to register cache
2487 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2490 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
2491 int regnum
, const void *gregs
, size_t len
)
2493 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2494 const gdb_byte
*regs
= gregs
;
2497 gdb_assert (len
== tdep
->sizeof_gregset
);
2499 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2501 if ((regnum
== i
|| regnum
== -1)
2502 && tdep
->gregset_reg_offset
[i
] != -1)
2503 regcache_raw_supply (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2507 /* Collect register REGNUM from the register cache REGCACHE and store
2508 it in the buffer specified by GREGS and LEN as described by the
2509 general-purpose register set REGSET. If REGNUM is -1, do this for
2510 all registers in REGSET. */
2513 i386_collect_gregset (const struct regset
*regset
,
2514 const struct regcache
*regcache
,
2515 int regnum
, void *gregs
, size_t len
)
2517 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2518 gdb_byte
*regs
= gregs
;
2521 gdb_assert (len
== tdep
->sizeof_gregset
);
2523 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
2525 if ((regnum
== i
|| regnum
== -1)
2526 && tdep
->gregset_reg_offset
[i
] != -1)
2527 regcache_raw_collect (regcache
, i
, regs
+ tdep
->gregset_reg_offset
[i
]);
2531 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2532 in the floating-point register set REGSET to register cache
2533 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2536 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2537 int regnum
, const void *fpregs
, size_t len
)
2539 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2541 if (len
== I387_SIZEOF_FXSAVE
)
2543 i387_supply_fxsave (regcache
, regnum
, fpregs
);
2547 gdb_assert (len
== tdep
->sizeof_fpregset
);
2548 i387_supply_fsave (regcache
, regnum
, fpregs
);
2551 /* Collect register REGNUM from the register cache REGCACHE and store
2552 it in the buffer specified by FPREGS and LEN as described by the
2553 floating-point register set REGSET. If REGNUM is -1, do this for
2554 all registers in REGSET. */
2557 i386_collect_fpregset (const struct regset
*regset
,
2558 const struct regcache
*regcache
,
2559 int regnum
, void *fpregs
, size_t len
)
2561 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2563 if (len
== I387_SIZEOF_FXSAVE
)
2565 i387_collect_fxsave (regcache
, regnum
, fpregs
);
2569 gdb_assert (len
== tdep
->sizeof_fpregset
);
2570 i387_collect_fsave (regcache
, regnum
, fpregs
);
2573 /* Return the appropriate register set for the core section identified
2574 by SECT_NAME and SECT_SIZE. */
2576 const struct regset
*
2577 i386_regset_from_core_section (struct gdbarch
*gdbarch
,
2578 const char *sect_name
, size_t sect_size
)
2580 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2582 if (strcmp (sect_name
, ".reg") == 0 && sect_size
== tdep
->sizeof_gregset
)
2584 if (tdep
->gregset
== NULL
)
2585 tdep
->gregset
= regset_alloc (gdbarch
, i386_supply_gregset
,
2586 i386_collect_gregset
);
2587 return tdep
->gregset
;
2590 if ((strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2591 || (strcmp (sect_name
, ".reg-xfp") == 0
2592 && sect_size
== I387_SIZEOF_FXSAVE
))
2594 if (tdep
->fpregset
== NULL
)
2595 tdep
->fpregset
= regset_alloc (gdbarch
, i386_supply_fpregset
,
2596 i386_collect_fpregset
);
2597 return tdep
->fpregset
;
2604 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
2607 i386_pe_skip_trampoline_code (struct frame_info
*frame
,
2608 CORE_ADDR pc
, char *name
)
2610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2611 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2614 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
2616 unsigned long indirect
=
2617 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
2618 struct minimal_symbol
*indsym
=
2619 indirect
? lookup_minimal_symbol_by_pc (indirect
) : 0;
2620 char *symname
= indsym
? SYMBOL_LINKAGE_NAME (indsym
) : 0;
2624 if (strncmp (symname
, "__imp_", 6) == 0
2625 || strncmp (symname
, "_imp_", 5) == 0)
2627 read_memory_unsigned_integer (indirect
, 4, byte_order
);
2630 return 0; /* Not a trampoline. */
2634 /* Return whether the THIS_FRAME corresponds to a sigtramp
2638 i386_sigtramp_p (struct frame_info
*this_frame
)
2640 CORE_ADDR pc
= get_frame_pc (this_frame
);
2643 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2644 return (name
&& strcmp ("_sigtramp", name
) == 0);
2648 /* We have two flavours of disassembly. The machinery on this page
2649 deals with switching between those. */
2652 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
2654 gdb_assert (disassembly_flavor
== att_flavor
2655 || disassembly_flavor
== intel_flavor
);
2657 /* FIXME: kettenis/20020915: Until disassembler_options is properly
2658 constified, cast to prevent a compiler warning. */
2659 info
->disassembler_options
= (char *) disassembly_flavor
;
2661 return print_insn_i386 (pc
, info
);
2665 /* There are a few i386 architecture variants that differ only
2666 slightly from the generic i386 target. For now, we don't give them
2667 their own source file, but include them here. As a consequence,
2668 they'll always be included. */
2670 /* System V Release 4 (SVR4). */
2672 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
2676 i386_svr4_sigtramp_p (struct frame_info
*this_frame
)
2678 CORE_ADDR pc
= get_frame_pc (this_frame
);
2681 /* UnixWare uses _sigacthandler. The origin of the other symbols is
2682 currently unknown. */
2683 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2684 return (name
&& (strcmp ("_sigreturn", name
) == 0
2685 || strcmp ("_sigacthandler", name
) == 0
2686 || strcmp ("sigvechandler", name
) == 0));
2689 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
2690 address of the associated sigcontext (ucontext) structure. */
2693 i386_svr4_sigcontext_addr (struct frame_info
*this_frame
)
2695 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2696 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2700 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2701 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2703 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
2710 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2712 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
2713 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2716 /* System V Release 4 (SVR4). */
2719 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2723 /* System V Release 4 uses ELF. */
2724 i386_elf_init_abi (info
, gdbarch
);
2726 /* System V Release 4 has shared libraries. */
2727 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
2729 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
2730 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
2731 tdep
->sc_pc_offset
= 36 + 14 * 4;
2732 tdep
->sc_sp_offset
= 36 + 17 * 4;
2734 tdep
->jb_pc_offset
= 20;
2740 i386_go32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2744 /* DJGPP doesn't have any special frames for signal handlers. */
2745 tdep
->sigtramp_p
= NULL
;
2747 tdep
->jb_pc_offset
= 36;
2749 /* DJGPP does not support the SSE registers. */
2750 tdep
->num_xmm_regs
= 0;
2751 set_gdbarch_num_regs (gdbarch
, I386_NUM_GREGS
+ I386_NUM_FREGS
);
2753 /* Native compiler is GCC, which uses the SVR4 register numbering
2754 even in COFF and STABS. See the comment in i386_gdbarch_init,
2755 before the calls to set_gdbarch_stab_reg_to_regnum and
2756 set_gdbarch_sdb_reg_to_regnum. */
2757 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2758 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
2762 /* i386 register groups. In addition to the normal groups, add "mmx"
2765 static struct reggroup
*i386_sse_reggroup
;
2766 static struct reggroup
*i386_mmx_reggroup
;
2769 i386_init_reggroups (void)
2771 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
2772 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
2776 i386_add_reggroups (struct gdbarch
*gdbarch
)
2778 reggroup_add (gdbarch
, i386_sse_reggroup
);
2779 reggroup_add (gdbarch
, i386_mmx_reggroup
);
2780 reggroup_add (gdbarch
, general_reggroup
);
2781 reggroup_add (gdbarch
, float_reggroup
);
2782 reggroup_add (gdbarch
, all_reggroup
);
2783 reggroup_add (gdbarch
, save_reggroup
);
2784 reggroup_add (gdbarch
, restore_reggroup
);
2785 reggroup_add (gdbarch
, vector_reggroup
);
2786 reggroup_add (gdbarch
, system_reggroup
);
2790 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2791 struct reggroup
*group
)
2793 int sse_regnum_p
= (i386_sse_regnum_p (gdbarch
, regnum
)
2794 || i386_mxcsr_regnum_p (gdbarch
, regnum
));
2795 int fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
2796 || i386_fpc_regnum_p (gdbarch
, regnum
));
2797 int mmx_regnum_p
= (i386_mmx_regnum_p (gdbarch
, regnum
));
2799 if (group
== i386_mmx_reggroup
)
2800 return mmx_regnum_p
;
2801 if (group
== i386_sse_reggroup
)
2802 return sse_regnum_p
;
2803 if (group
== vector_reggroup
)
2804 return (mmx_regnum_p
|| sse_regnum_p
);
2805 if (group
== float_reggroup
)
2807 if (group
== general_reggroup
)
2808 return (!fp_regnum_p
&& !mmx_regnum_p
&& !sse_regnum_p
);
2810 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2814 /* Get the ARGIth function argument for the current function. */
2817 i386_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
2820 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2821 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2822 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
2823 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
2827 i386_skip_permanent_breakpoint (struct regcache
*regcache
)
2829 CORE_ADDR current_pc
= regcache_read_pc (regcache
);
2831 /* On i386, breakpoint is exactly 1 byte long, so we just
2832 adjust the PC in the regcache. */
2834 regcache_write_pc (regcache
, current_pc
);
2838 #define PREFIX_REPZ 0x01
2839 #define PREFIX_REPNZ 0x02
2840 #define PREFIX_LOCK 0x04
2841 #define PREFIX_DATA 0x08
2842 #define PREFIX_ADDR 0x10
2853 /* i386 arith/logic operations */
2866 struct i386_record_s
2868 struct gdbarch
*gdbarch
;
2869 struct regcache
*regcache
;
2875 uint8_t mod
, reg
, rm
;
2884 /* Parse "modrm" part in current memory address that irp->addr point to
2885 Return -1 if something wrong. */
2888 i386_record_modrm (struct i386_record_s
*irp
)
2890 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2892 if (target_read_memory (irp
->addr
, &irp
->modrm
, 1))
2895 printf_unfiltered (_("Process record: error reading memory at "
2896 "addr %s len = 1.\n"),
2897 paddress (gdbarch
, irp
->addr
));
2901 irp
->mod
= (irp
->modrm
>> 6) & 3;
2902 irp
->reg
= (irp
->modrm
>> 3) & 7;
2903 irp
->rm
= irp
->modrm
& 7;
2908 /* Get the memory address that current instruction write to and set it to
2909 the argument "addr".
2910 Return -1 if something wrong. */
2913 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
2915 struct gdbarch
*gdbarch
= irp
->gdbarch
;
2919 ULONGEST tmpulongest
;
2928 uint8_t base
= irp
->rm
;
2933 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2936 printf_unfiltered (_("Process record: error reading memory "
2937 "at addr %s len = 1.\n"),
2938 paddress (gdbarch
, irp
->addr
));
2942 scale
= (tmpu8
>> 6) & 3;
2943 index
= ((tmpu8
>> 3) & 7) | irp
->rex_x
;
2951 if ((base
& 7) == 5)
2954 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
2957 printf_unfiltered (_("Process record: error reading "
2958 "memory at addr %s len = 4.\n"),
2959 paddress (gdbarch
, irp
->addr
));
2964 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
2965 *addr
+= irp
->addr
+ irp
->rip_offset
;
2973 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
2976 printf_unfiltered (_("Process record: error reading memory "
2977 "at addr %s len = 1.\n"),
2978 paddress (gdbarch
, irp
->addr
));
2982 *addr
= (int8_t) tmpu8
;
2985 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi32
, 4))
2988 printf_unfiltered (_("Process record: error reading memory "
2989 "at addr %s len = 4.\n"),
2990 paddress (gdbarch
, irp
->addr
));
3001 if (base
== 4 && irp
->popl_esp_hack
)
3002 *addr
+= irp
->popl_esp_hack
;
3003 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
3006 if (irp
->aflag
== 2)
3008 *addr
+= tmpulongest
;
3011 *addr
= (uint32_t) (tmpulongest
+ *addr
);
3013 if (havesib
&& (index
!= 4 || scale
!= 0))
3015 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
3017 if (irp
->aflag
== 2)
3018 *addr
+= tmpulongest
<< scale
;
3020 *addr
= (uint32_t) (*addr
+ (tmpulongest
<< scale
));
3031 if (target_read_memory
3032 (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3035 printf_unfiltered (_("Process record: error reading "
3036 "memory at addr %s len = 2.\n"),
3037 paddress (gdbarch
, irp
->addr
));
3051 if (target_read_memory (irp
->addr
, &tmpu8
, 1))
3054 printf_unfiltered (_("Process record: error reading memory "
3055 "at addr %s len = 1.\n"),
3056 paddress (gdbarch
, irp
->addr
));
3060 *addr
= (int8_t) tmpu8
;
3063 if (target_read_memory (irp
->addr
, (gdb_byte
*) &tmpi16
, 2))
3066 printf_unfiltered (_("Process record: error reading memory "
3067 "at addr %s len = 2.\n"),
3068 paddress (gdbarch
, irp
->addr
));
3079 regcache_raw_read_unsigned (irp
->regcache
,
3080 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3082 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3083 regcache_raw_read_unsigned (irp
->regcache
,
3084 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3086 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3089 regcache_raw_read_unsigned (irp
->regcache
,
3090 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3092 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3093 regcache_raw_read_unsigned (irp
->regcache
,
3094 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3096 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3099 regcache_raw_read_unsigned (irp
->regcache
,
3100 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3102 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3103 regcache_raw_read_unsigned (irp
->regcache
,
3104 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3106 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3109 regcache_raw_read_unsigned (irp
->regcache
,
3110 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3112 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3113 regcache_raw_read_unsigned (irp
->regcache
,
3114 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3116 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3119 regcache_raw_read_unsigned (irp
->regcache
,
3120 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
3122 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3125 regcache_raw_read_unsigned (irp
->regcache
,
3126 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
3128 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3131 regcache_raw_read_unsigned (irp
->regcache
,
3132 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
3134 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3137 regcache_raw_read_unsigned (irp
->regcache
,
3138 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
3140 *addr
= (uint32_t) (*addr
+ tmpulongest
);
3150 /* Record the value of the memory that willbe changed in current instruction
3151 to "record_arch_list".
3152 Return -1 if something wrong. */
3155 i386_record_lea_modrm (struct i386_record_s
*irp
)
3157 struct gdbarch
*gdbarch
= irp
->gdbarch
;
3160 if (irp
->override
>= 0)
3163 printf_unfiltered (_("Process record ignores the memory change "
3164 "of instruction at address %s because it "
3165 "can't get the value of the segment register.\n"),
3166 paddress (gdbarch
, irp
->addr
));
3170 if (i386_record_lea_modrm_addr (irp
, &addr
))
3173 if (record_arch_list_add_mem (addr
, 1 << irp
->ot
))
3179 /* Record the push operation to "record_arch_list".
3180 Return -1 if something wrong. */
3183 i386_record_push (struct i386_record_s
*irp
, int size
)
3185 ULONGEST tmpulongest
;
3187 if (record_arch_list_add_reg (irp
->regcache
,
3188 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
3190 regcache_raw_read_unsigned (irp
->regcache
,
3191 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
3193 if (record_arch_list_add_mem ((CORE_ADDR
) tmpulongest
- size
, size
))
3199 /* Parse the current instruction and record the values of the registers and
3200 memory that will be changed in current instruction to "record_arch_list".
3201 Return -1 if something wrong. */
3203 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \
3204 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
3207 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3214 ULONGEST tmpulongest
;
3216 struct i386_record_s ir
;
3221 memset (&ir
, 0, sizeof (struct i386_record_s
));
3222 ir
.regcache
= regcache
;
3227 ir
.popl_esp_hack
= 0;
3228 ir
.regmap
= gdbarch_tdep (gdbarch
)->record_regmap
;
3229 ir
.gdbarch
= gdbarch
;
3231 if (record_debug
> 1)
3232 fprintf_unfiltered (gdb_stdlog
, "Process record: i386_process_record "
3234 paddress (gdbarch
, ir
.addr
));
3239 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3242 printf_unfiltered (_("Process record: error reading memory at "
3243 "addr %s len = 1.\n"),
3244 paddress (gdbarch
, ir
.addr
));
3251 prefixes
|= PREFIX_REPZ
;
3254 prefixes
|= PREFIX_REPNZ
;
3257 prefixes
|= PREFIX_LOCK
;
3260 ir
.override
= X86_RECORD_CS_REGNUM
;
3263 ir
.override
= X86_RECORD_SS_REGNUM
;
3266 ir
.override
= X86_RECORD_DS_REGNUM
;
3269 ir
.override
= X86_RECORD_ES_REGNUM
;
3272 ir
.override
= X86_RECORD_FS_REGNUM
;
3275 ir
.override
= X86_RECORD_GS_REGNUM
;
3278 prefixes
|= PREFIX_DATA
;
3281 prefixes
|= PREFIX_ADDR
;
3299 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3303 rex_w
= (tmpu8
>> 3) & 1;
3304 rex_r
= (tmpu8
& 0x4) << 1;
3305 ir
.rex_x
= (tmpu8
& 0x2) << 2;
3306 ir
.rex_b
= (tmpu8
& 0x1) << 3;
3315 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
3321 if (prefixes
& PREFIX_DATA
)
3324 if (prefixes
& PREFIX_ADDR
)
3326 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3329 /* now check op code */
3330 opcode
= (uint32_t) tmpu8
;
3335 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
3338 printf_unfiltered (_("Process record: error reading memory at "
3339 "addr %s len = 1.\n"),
3340 paddress (gdbarch
, ir
.addr
));
3344 opcode
= (uint16_t) tmpu8
| 0x0f00;
3397 if (((opcode
>> 3) & 7) != OP_CMPL
)
3399 if ((opcode
& 1) == 0)
3402 ir
.ot
= ir
.dflag
+ OT_WORD
;
3404 switch ((opcode
>> 1) & 3)
3408 if (i386_record_modrm (&ir
))
3412 if (i386_record_lea_modrm (&ir
))
3418 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3420 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3425 if (i386_record_modrm (&ir
))
3428 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3430 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3434 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3438 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3446 if (i386_record_modrm (&ir
))
3449 if (ir
.reg
!= OP_CMPL
)
3451 if ((opcode
& 1) == 0)
3454 ir
.ot
= ir
.dflag
+ OT_WORD
;
3461 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3462 if (i386_record_lea_modrm (&ir
))
3466 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3468 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3489 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 7);
3490 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3496 if ((opcode
& 1) == 0)
3499 ir
.ot
= ir
.dflag
+ OT_WORD
;
3500 if (i386_record_modrm (&ir
))
3503 if (ir
.mod
!= 3 && ir
.reg
== 0)
3504 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3510 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3518 if (i386_record_lea_modrm (&ir
))
3524 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3526 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3530 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3540 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3541 if (ir
.ot
!= OT_BYTE
)
3542 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3543 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3547 opcode
= opcode
<< 8 | ir
.modrm
;
3557 if (i386_record_modrm (&ir
))
3559 if (ir
.reg
>= 2 && opcode
== 0xfe)
3562 opcode
= opcode
<< 8 | ir
.modrm
;
3571 if ((opcode
& 1) == 0)
3574 ir
.ot
= ir
.dflag
+ OT_WORD
;
3577 if (i386_record_lea_modrm (&ir
))
3583 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3585 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3587 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3591 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3593 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3595 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
3600 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3602 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3608 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3612 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3614 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3619 opcode
= opcode
<< 8 | ir
.modrm
;
3630 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3635 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3640 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3641 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3648 ir
.ot
= ir
.dflag
+ OT_WORD
;
3649 if (i386_record_modrm (&ir
))
3652 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3653 else if (opcode
== 0x6b)
3656 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3658 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3665 if ((opcode
& 1) == 0)
3668 ir
.ot
= ir
.dflag
+ OT_WORD
;
3669 if (i386_record_modrm (&ir
))
3674 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3676 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3677 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3679 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3683 if (i386_record_lea_modrm (&ir
))
3685 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3687 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3689 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3695 if ((opcode
& 1) == 0)
3698 ir
.ot
= ir
.dflag
+ OT_WORD
;
3699 if (i386_record_modrm (&ir
))
3704 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3705 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3707 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3711 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3712 if (i386_record_lea_modrm (&ir
))
3715 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3720 if (i386_record_modrm (&ir
))
3725 opcode
= opcode
<< 8 | ir
.modrm
;
3728 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
3729 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
3730 if (i386_record_lea_modrm (&ir
))
3732 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3746 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3748 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3760 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3765 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3773 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3778 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3784 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3789 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
3802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3803 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
3808 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3813 for (tmpu8
= X86_RECORD_REAX_REGNUM
; tmpu8
<= X86_RECORD_REDI_REGNUM
;
3815 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
3820 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3821 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
3823 ir
.ot
= ir
.dflag
+ OT_WORD
;
3824 if (i386_record_modrm (&ir
))
3827 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
3830 ir
.popl_esp_hack
= 1 << ir
.ot
;
3831 if (i386_record_lea_modrm (&ir
))
3834 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3839 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3840 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
3842 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
3848 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3849 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
3854 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3859 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3860 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
3861 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3866 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3871 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3872 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
3873 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3878 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
3883 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3884 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
3885 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3891 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
3892 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
3898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
3899 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
3907 if ((opcode
& 1) == 0)
3910 ir
.ot
= ir
.dflag
+ OT_WORD
;
3912 if (i386_record_modrm (&ir
))
3917 if (opcode
== 0xc6 || opcode
== 0xc7)
3918 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
3919 if (i386_record_lea_modrm (&ir
))
3924 if (opcode
== 0xc6 || opcode
== 0xc7)
3926 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3928 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3935 if ((opcode
& 1) == 0)
3938 ir
.ot
= ir
.dflag
+ OT_WORD
;
3939 if (i386_record_modrm (&ir
))
3942 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
3944 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
3949 if (i386_record_modrm (&ir
))
3954 opcode
= opcode
<< 8 | ir
.modrm
;
3959 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
3963 if (i386_record_lea_modrm (&ir
))
3970 if (i386_record_modrm (&ir
))
3975 tmpu8
= X86_RECORD_ES_REGNUM
;
3978 tmpu8
= X86_RECORD_SS_REGNUM
;
3981 tmpu8
= X86_RECORD_DS_REGNUM
;
3984 tmpu8
= X86_RECORD_FS_REGNUM
;
3987 tmpu8
= X86_RECORD_GS_REGNUM
;
3991 opcode
= opcode
<< 8 | ir
.modrm
;
3995 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
3996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4007 if (i386_record_modrm (&ir
))
4009 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4014 if (i386_record_modrm (&ir
))
4019 opcode
= opcode
<< 8 | ir
.modrm
;
4024 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4026 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4034 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4040 if (ir
.override
>= 0)
4043 printf_unfiltered (_("Process record ignores the memory change "
4044 "of instruction at address 0x%s because "
4045 "it can't get the value of the segment "
4047 paddress (gdbarch
, ir
.addr
));
4051 if ((opcode
& 1) == 0)
4054 ir
.ot
= ir
.dflag
+ OT_WORD
;
4057 if (target_read_memory (ir
.addr
, (gdb_byte
*) &addr
, 8))
4060 printf_unfiltered (_("Process record: error reading "
4061 "memory at addr 0x%s len = 8.\n"),
4062 paddress (gdbarch
, ir
.addr
));
4069 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu32
, 4))
4072 printf_unfiltered (_("Process record: error reading "
4073 "memory at addr 0x%s len = 4.\n"),
4074 paddress (gdbarch
, ir
.addr
));
4082 if (target_read_memory (ir
.addr
, (gdb_byte
*) &tmpu16
, 2))
4085 printf_unfiltered (_("Process record: error reading "
4086 "memory at addr 0x%s len = 2.\n"),
4087 paddress (gdbarch
, ir
.addr
));
4093 if (record_arch_list_add_mem (addr
, 1 << ir
.ot
))
4107 I386_RECORD_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
4108 ? ((opcode
& 0x7) | ir
.rex_b
)
4109 : ((opcode
& 0x7) & 0x3));
4121 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
4132 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4133 I386_RECORD_ARCH_LIST_ADD_REG (opcode
& 0x7);
4139 if ((opcode
& 1) == 0)
4142 ir
.ot
= ir
.dflag
+ OT_WORD
;
4143 if (i386_record_modrm (&ir
))
4148 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4150 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4154 if (i386_record_lea_modrm (&ir
))
4158 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4160 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4167 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4178 if (i386_record_modrm (&ir
))
4186 opcode
= opcode
<< 8 | ir
.modrm
;
4193 tmpu8
= X86_RECORD_ES_REGNUM
;
4197 tmpu8
= X86_RECORD_DS_REGNUM
;
4201 tmpu8
= X86_RECORD_SS_REGNUM
;
4205 tmpu8
= X86_RECORD_FS_REGNUM
;
4209 tmpu8
= X86_RECORD_GS_REGNUM
;
4212 I386_RECORD_ARCH_LIST_ADD_REG (tmpu8
);
4213 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4214 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4224 if ((opcode
& 1) == 0)
4227 ir
.ot
= ir
.dflag
+ OT_WORD
;
4228 if (i386_record_modrm (&ir
))
4230 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
4232 if (i386_record_lea_modrm (&ir
))
4238 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
4240 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
);
4242 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4249 if (i386_record_modrm (&ir
))
4253 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
))
4258 if (i386_record_lea_modrm (&ir
))
4264 /* It just record the memory change of instrcution. */
4273 if (i386_record_modrm (&ir
))
4275 ir
.reg
|= ((opcode
& 7) << 3);
4281 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
4338 switch (ir
.reg
>> 4)
4341 if (record_arch_list_add_mem (tmpu64
, 4))
4345 if (record_arch_list_add_mem (tmpu64
, 8))
4350 if (record_arch_list_add_mem (tmpu64
, 2))
4356 switch (ir
.reg
>> 4)
4360 if (record_arch_list_add_mem (tmpu64
, 4))
4364 if (record_arch_list_add_mem (tmpu64
, 8))
4369 if (record_arch_list_add_mem (tmpu64
, 2))
4386 if (record_arch_list_add_mem (tmpu64
, 28))
4391 if (record_arch_list_add_mem (tmpu64
, 14))
4397 if (record_arch_list_add_mem (tmpu64
, 2))
4402 if (record_arch_list_add_mem (tmpu64
, 10))
4408 if (record_arch_list_add_mem (tmpu64
, 28))
4414 if (record_arch_list_add_mem (tmpu64
, 14))
4418 if (record_arch_list_add_mem (tmpu64
, 80))
4422 if (record_arch_list_add_mem (tmpu64
, 8))
4427 opcode
= opcode
<< 8 | ir
.modrm
;
4444 if ((opcode
& 1) == 0)
4447 ir
.ot
= ir
.dflag
+ OT_WORD
;
4448 regcache_raw_read_unsigned (ir
.regcache
,
4449 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4453 tmpulongest
&= 0xffff;
4454 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
4456 printf_unfiltered (_("Process record ignores the memory change "
4457 "of instruction at address 0x%s because "
4458 "it can't get the value of the segment "
4460 paddress (gdbarch
, ir
.addr
));
4462 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4464 ULONGEST count
, eflags
;
4465 regcache_raw_read_unsigned (ir
.regcache
,
4466 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
4470 regcache_raw_read_unsigned (ir
.regcache
,
4471 ir
.regmap
[X86_RECORD_EFLAGS_REGNUM
],
4473 if ((eflags
>> 10) & 0x1)
4474 tmpulongest
-= (count
- 1) * (1 << ir
.ot
);
4475 if (record_arch_list_add_mem (tmpulongest
, count
* (1 << ir
.ot
)))
4477 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4481 if (record_arch_list_add_mem (tmpulongest
, 1 << ir
.ot
))
4484 if (opcode
== 0xa4 || opcode
== 0xa5)
4485 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4486 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4487 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4493 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4494 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4495 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4496 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4503 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4504 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4505 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4506 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4513 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
4514 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4522 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
4523 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
4524 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4525 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4533 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4534 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4548 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4549 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4558 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4559 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4560 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4565 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4567 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4573 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
4579 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4642 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4644 if (i386_record_modrm (&ir
))
4647 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
4651 if (i386_record_lea_modrm (&ir
))
4673 if (i386_record_modrm (&ir
))
4676 if (ir
.dflag
== OT_BYTE
)
4678 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
);
4684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4685 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
4687 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
4693 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
4694 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4699 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4714 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4719 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4724 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4725 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4728 /* bit operations */
4729 /* bt/bts/btr/btc Gv, im */
4731 ir
.ot
= ir
.dflag
+ OT_WORD
;
4732 if (i386_record_modrm (&ir
))
4737 opcode
= opcode
<< 8 | ir
.modrm
;
4743 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4746 if (i386_record_lea_modrm (&ir
))
4750 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4764 ir
.ot
= ir
.dflag
+ OT_WORD
;
4765 if (i386_record_modrm (&ir
))
4768 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
4772 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
4774 regcache_raw_read_unsigned (ir
.regcache
,
4775 ir
.regmap
[ir
.reg
| rex_r
],
4780 tmpu64
+= ((int16_t) tmpulongest
>> 4) << 4;
4783 tmpu64
+= ((int32_t) tmpulongest
>> 5) << 5;
4786 tmpu64
+= ((int64_t) tmpulongest
>> 6) << 6;
4789 if (record_arch_list_add_mem (tmpu64
, 1 << ir
.ot
))
4791 if (i386_record_lea_modrm (&ir
))
4794 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4801 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
4802 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4818 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4823 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4824 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4830 if (prefixes
& PREFIX_LOCK
)
4840 printf_unfiltered (_("Process record doesn't support instruction "
4849 printf_unfiltered (_("Process record doesn't support instruction "
4860 if (target_read_memory (ir
.addr
, &tmpu8
, 1))
4863 printf_unfiltered (_("Process record: error reading memory "
4864 "at addr %s len = 1.\n"),
4865 paddress (gdbarch
, ir
.addr
));
4870 || gdbarch_tdep (gdbarch
)->i386_intx80_record
== NULL
)
4872 printf_unfiltered (_("Process record doesn't support "
4873 "instruction int 0x%02x.\n"),
4878 ret
= gdbarch_tdep (gdbarch
)->i386_intx80_record (ir
.regcache
);
4887 printf_unfiltered (_("Process record doesn't support "
4888 "instruction into.\n"));
4901 printf_unfiltered (_("Process record doesn't support "
4902 "instruction bound.\n"));
4916 I386_RECORD_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
4921 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4926 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
4927 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4938 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
4939 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
4944 printf_unfiltered (_("Process record doesn't support "
4945 "instruction wrmsr.\n"));
4952 printf_unfiltered (_("Process record doesn't support "
4953 "instruction rdmsr.\n"));
4960 printf_unfiltered (_("Process record doesn't support "
4961 "instruction rdtsc.\n"));
4970 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
4975 if (gdbarch_tdep (gdbarch
)->i386_sysenter_record
== NULL
)
4977 printf_unfiltered (_("Process record doesn't support "
4978 "instruction sysenter.\n"));
4982 ret
= gdbarch_tdep (gdbarch
)->i386_sysenter_record (ir
.regcache
);
4990 printf_unfiltered (_("Process record doesn't support "
4991 "instruction sysexit.\n"));
5000 if (gdbarch_tdep (gdbarch
)->i386_syscall_record
== NULL
)
5002 printf_unfiltered (_("Process record doesn't support "
5003 "instruction syscall.\n"));
5007 ret
= gdbarch_tdep (gdbarch
)->i386_syscall_record (ir
.regcache
);
5015 printf_unfiltered (_("Process record doesn't support "
5016 "instruction sysret.\n"));
5023 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5024 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
5025 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5026 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
5031 printf_unfiltered (_("Process record doesn't support "
5032 "instruction hlt.\n"));
5038 if (i386_record_modrm (&ir
))
5047 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5051 if (i386_record_lea_modrm (&ir
))
5064 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5068 opcode
= opcode
<< 8 | ir
.modrm
;
5075 if (i386_record_modrm (&ir
))
5087 opcode
= opcode
<< 8 | ir
.modrm
;
5090 if (ir
.override
>= 0)
5093 printf_unfiltered (_("Process record ignores the memory "
5094 "change of instruction at "
5095 "address %s because it can't get "
5096 "the value of the segment "
5098 paddress (gdbarch
, ir
.addr
));
5102 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5104 if (record_arch_list_add_mem (tmpu64
, 2))
5107 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5109 if (record_arch_list_add_mem (tmpu64
, 8))
5114 if (record_arch_list_add_mem (tmpu64
, 4))
5130 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5134 opcode
= opcode
<< 8 | ir
.modrm
;
5142 if (ir
.override
>= 0)
5145 printf_unfiltered (_("Process record ignores the memory "
5146 "change of instruction at "
5147 "address %s because it can't get "
5148 "the value of the segment "
5150 paddress (gdbarch
, ir
.addr
));
5156 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
5158 if (record_arch_list_add_mem (tmpu64
, 2))
5161 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5163 if (record_arch_list_add_mem (tmpu64
, 8))
5168 if (record_arch_list_add_mem (tmpu64
, 4))
5181 opcode
= opcode
<< 8 | ir
.modrm
;
5189 if (record_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
5195 if (i386_record_lea_modrm (&ir
))
5198 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5202 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5208 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
5209 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5213 opcode
= opcode
<< 8 | ir
.modrm
;
5218 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5222 opcode
= opcode
<< 8 | ir
.modrm
;
5236 if (i386_record_modrm (&ir
))
5238 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
5240 I386_RECORD_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
5241 ? (ir
.reg
| rex_r
) : ir
.rm
);
5245 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
5246 if (i386_record_lea_modrm (&ir
))
5249 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
5250 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5257 if (i386_record_modrm (&ir
))
5259 I386_RECORD_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5260 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5264 if (i386_record_modrm (&ir
))
5266 if (ir
.mod
== 3 && ir
.reg
== 3)
5269 opcode
= opcode
<< 8 | ir
.modrm
;
5274 /* nop (multi byte) */
5288 if (i386_record_modrm (&ir
))
5290 if ((ir
.modrm
& 0xc0) != 0xc0)
5293 opcode
= opcode
<< 8 | ir
.modrm
;
5304 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5306 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5310 opcode
= opcode
<< 8 | ir
.modrm
;
5320 if (i386_record_modrm (&ir
))
5322 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
5323 || ir
.reg
== 5 || ir
.reg
>= 8)
5326 opcode
= opcode
<< 8 | ir
.modrm
;
5330 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5332 I386_RECORD_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5340 /* MMX/SSE/SSE2/PNI support */
5352 /* In the future, maybe still need to deal with need_dasm. */
5353 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
5354 if (record_arch_list_add_end ())
5360 printf_unfiltered (_("Process record doesn't support instruction 0x%02x "
5361 "at address %s.\n"),
5362 (unsigned int) (opcode
), paddress (gdbarch
, ir
.addr
));
5366 static const int i386_record_regmap
[] =
5368 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
5369 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
5370 0, 0, 0, 0, 0, 0, 0, 0,
5371 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
5372 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
5376 static struct gdbarch
*
5377 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5379 struct gdbarch_tdep
*tdep
;
5380 struct gdbarch
*gdbarch
;
5382 /* If there is already a candidate, use it. */
5383 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5385 return arches
->gdbarch
;
5387 /* Allocate space for the new architecture. */
5388 tdep
= XCALLOC (1, struct gdbarch_tdep
);
5389 gdbarch
= gdbarch_alloc (&info
, tdep
);
5391 /* General-purpose registers. */
5392 tdep
->gregset
= NULL
;
5393 tdep
->gregset_reg_offset
= NULL
;
5394 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
5395 tdep
->sizeof_gregset
= 0;
5397 /* Floating-point registers. */
5398 tdep
->fpregset
= NULL
;
5399 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
5401 /* The default settings include the FPU registers, the MMX registers
5402 and the SSE registers. This can be overridden for a specific ABI
5403 by adjusting the members `st0_regnum', `mm0_regnum' and
5404 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
5405 will show up in the output of "info all-registers". Ideally we
5406 should try to autodetect whether they are available, such that we
5407 can prevent "info all-registers" from displaying registers that
5410 NOTE: kevinb/2003-07-13: ... if it's a choice between printing
5411 [the SSE registers] always (even when they don't exist) or never
5412 showing them to the user (even when they do exist), I prefer the
5413 former over the latter. */
5415 tdep
->st0_regnum
= I386_ST0_REGNUM
;
5417 /* The MMX registers are implemented as pseudo-registers. Put off
5418 calculating the register number for %mm0 until we know the number
5419 of raw registers. */
5420 tdep
->mm0_regnum
= 0;
5422 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
5423 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
5425 tdep
->jb_pc_offset
= -1;
5426 tdep
->struct_return
= pcc_struct_return
;
5427 tdep
->sigtramp_start
= 0;
5428 tdep
->sigtramp_end
= 0;
5429 tdep
->sigtramp_p
= i386_sigtramp_p
;
5430 tdep
->sigcontext_addr
= NULL
;
5431 tdep
->sc_reg_offset
= NULL
;
5432 tdep
->sc_pc_offset
= -1;
5433 tdep
->sc_sp_offset
= -1;
5435 tdep
->record_regmap
= i386_record_regmap
;
5437 /* The format used for `long double' on almost all i386 targets is
5438 the i387 extended floating-point format. In fact, of all targets
5439 in the GCC 2.95 tree, only OSF/1 does it different, and insists
5440 on having a `long double' that's not `long' at all. */
5441 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
5443 /* Although the i387 extended floating-point has only 80 significant
5444 bits, a `long double' actually takes up 96, probably to enforce
5446 set_gdbarch_long_double_bit (gdbarch
, 96);
5448 /* The default ABI includes general-purpose registers,
5449 floating-point registers, and the SSE registers. */
5450 set_gdbarch_num_regs (gdbarch
, I386_SSE_NUM_REGS
);
5451 set_gdbarch_register_name (gdbarch
, i386_register_name
);
5452 set_gdbarch_register_type (gdbarch
, i386_register_type
);
5454 /* Register numbers of various important registers. */
5455 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
5456 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
5457 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
5458 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
5460 /* NOTE: kettenis/20040418: GCC does have two possible register
5461 numbering schemes on the i386: dbx and SVR4. These schemes
5462 differ in how they number %ebp, %esp, %eflags, and the
5463 floating-point registers, and are implemented by the arrays
5464 dbx_register_map[] and svr4_dbx_register_map in
5465 gcc/config/i386.c. GCC also defines a third numbering scheme in
5466 gcc/config/i386.c, which it designates as the "default" register
5467 map used in 64bit mode. This last register numbering scheme is
5468 implemented in dbx64_register_map, and is used for AMD64; see
5471 Currently, each GCC i386 target always uses the same register
5472 numbering scheme across all its supported debugging formats
5473 i.e. SDB (COFF), stabs and DWARF 2. This is because
5474 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
5475 DBX_REGISTER_NUMBER macro which is defined by each target's
5476 respective config header in a manner independent of the requested
5477 output debugging format.
5479 This does not match the arrangement below, which presumes that
5480 the SDB and stabs numbering schemes differ from the DWARF and
5481 DWARF 2 ones. The reason for this arrangement is that it is
5482 likely to get the numbering scheme for the target's
5483 default/native debug format right. For targets where GCC is the
5484 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
5485 targets where the native toolchain uses a different numbering
5486 scheme for a particular debug format (stabs-in-ELF on Solaris)
5487 the defaults below will have to be overridden, like
5488 i386_elf_init_abi() does. */
5490 /* Use the dbx register numbering scheme for stabs and COFF. */
5491 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5492 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
5494 /* Use the SVR4 register numbering scheme for DWARF 2. */
5495 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
5497 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
5498 be in use on any of the supported i386 targets. */
5500 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
5502 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
5504 /* Call dummy code. */
5505 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
5507 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
5508 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
5509 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
5511 set_gdbarch_return_value (gdbarch
, i386_return_value
);
5513 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
5515 /* Stack grows downward. */
5516 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5518 set_gdbarch_breakpoint_from_pc (gdbarch
, i386_breakpoint_from_pc
);
5519 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
5520 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
5522 set_gdbarch_frame_args_skip (gdbarch
, 8);
5524 /* Wire in the MMX registers. */
5525 set_gdbarch_num_pseudo_regs (gdbarch
, i386_num_mmx_regs
);
5526 set_gdbarch_pseudo_register_read (gdbarch
, i386_pseudo_register_read
);
5527 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
5529 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
5531 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
5533 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
5535 /* Add the i386 register groups. */
5536 i386_add_reggroups (gdbarch
);
5537 set_gdbarch_register_reggroup_p (gdbarch
, i386_register_reggroup_p
);
5539 /* Helper for function argument information. */
5540 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
5542 /* Hook the function epilogue frame unwinder. This unwinder is
5543 appended to the list first, so that it supercedes the Dwarf
5544 unwinder in function epilogues (where the Dwarf unwinder
5545 currently fails). */
5546 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
5548 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
5549 to the list before the prologue-based unwinders, so that Dwarf
5550 CFI info will be used if it is available. */
5551 dwarf2_append_unwinders (gdbarch
);
5553 frame_base_set_default (gdbarch
, &i386_frame_base
);
5555 /* Hook in ABI-specific overrides, if they have been registered. */
5556 gdbarch_init_osabi (info
, gdbarch
);
5558 /* Hook in the legacy prologue-based unwinders last (fallback). */
5559 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
5560 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
5562 /* If we have a register mapping, enable the generic core file
5563 support, unless it has already been enabled. */
5564 if (tdep
->gregset_reg_offset
5565 && !gdbarch_regset_from_core_section_p (gdbarch
))
5566 set_gdbarch_regset_from_core_section (gdbarch
,
5567 i386_regset_from_core_section
);
5569 /* Unless support for MMX has been disabled, make %mm0 the first
5571 if (tdep
->mm0_regnum
== 0)
5572 tdep
->mm0_regnum
= gdbarch_num_regs (gdbarch
);
5574 set_gdbarch_skip_permanent_breakpoint (gdbarch
,
5575 i386_skip_permanent_breakpoint
);
5580 static enum gdb_osabi
5581 i386_coff_osabi_sniffer (bfd
*abfd
)
5583 if (strcmp (bfd_get_target (abfd
), "coff-go32-exe") == 0
5584 || strcmp (bfd_get_target (abfd
), "coff-go32") == 0)
5585 return GDB_OSABI_GO32
;
5587 return GDB_OSABI_UNKNOWN
;
5591 /* Provide a prototype to silence -Wmissing-prototypes. */
5592 void _initialize_i386_tdep (void);
5595 _initialize_i386_tdep (void)
5597 register_gdbarch_init (bfd_arch_i386
, i386_gdbarch_init
);
5599 /* Add the variable that controls the disassembly flavor. */
5600 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
5601 &disassembly_flavor
, _("\
5602 Set the disassembly flavor."), _("\
5603 Show the disassembly flavor."), _("\
5604 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
5606 NULL
, /* FIXME: i18n: */
5607 &setlist
, &showlist
);
5609 /* Add the variable that controls the convention for returning
5611 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
5612 &struct_convention
, _("\
5613 Set the convention for returning small structs."), _("\
5614 Show the convention for returning small structs."), _("\
5615 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
5618 NULL
, /* FIXME: i18n: */
5619 &setlist
, &showlist
);
5621 gdbarch_register_osabi_sniffer (bfd_arch_i386
, bfd_target_coff_flavour
,
5622 i386_coff_osabi_sniffer
);
5624 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
5625 i386_svr4_init_abi
);
5626 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_GO32
,
5627 i386_go32_init_abi
);
5629 /* Initialize the i386-specific register groups. */
5630 i386_init_reggroups ();