1 /* Intel 387 floating point stuff.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "target-float.h"
29 #include "i386-tdep.h"
30 #include "i387-tdep.h"
31 #include "gdbsupport/x86-xstate.h"
33 /* Print the floating point number specified by RAW. */
36 print_i387_value (struct gdbarch
*gdbarch
,
37 const gdb_byte
*raw
, struct ui_file
*file
)
39 /* We try to print 19 digits. The last digit may or may not contain
40 garbage, but we'd better print one too many. We need enough room
41 to print the value, 1 position for the sign, 1 for the decimal
42 point, 19 for the digits and 6 for the exponent adds up to 27. */
43 const struct type
*type
= i387_ext_type (gdbarch
);
44 std::string str
= target_float_to_string (raw
, type
, " %-+27.19g");
45 fprintf_filtered (file
, "%s", str
.c_str ());
48 /* Print the classification for the register contents RAW. */
51 print_i387_ext (struct gdbarch
*gdbarch
,
52 const gdb_byte
*raw
, struct ui_file
*file
)
56 unsigned int exponent
;
57 unsigned long fraction
[2];
60 integer
= raw
[7] & 0x80;
61 exponent
= (((raw
[9] & 0x7f) << 8) | raw
[8]);
62 fraction
[0] = ((raw
[3] << 24) | (raw
[2] << 16) | (raw
[1] << 8) | raw
[0]);
63 fraction
[1] = (((raw
[7] & 0x7f) << 24) | (raw
[6] << 16)
64 | (raw
[5] << 8) | raw
[4]);
66 if (exponent
== 0x7fff && integer
)
68 if (fraction
[0] == 0x00000000 && fraction
[1] == 0x00000000)
70 fprintf_filtered (file
, " %cInf", (sign
? '-' : '+'));
71 else if (sign
&& fraction
[0] == 0x00000000 && fraction
[1] == 0x40000000)
72 /* Real Indefinite (QNaN). */
73 fputs_unfiltered (" Real Indefinite (QNaN)", file
);
74 else if (fraction
[1] & 0x40000000)
76 fputs_filtered (" QNaN", file
);
79 fputs_filtered (" SNaN", file
);
81 else if (exponent
< 0x7fff && exponent
> 0x0000 && integer
)
83 print_i387_value (gdbarch
, raw
, file
);
84 else if (exponent
== 0x0000)
86 /* Denormal or zero. */
87 print_i387_value (gdbarch
, raw
, file
);
90 /* Pseudo-denormal. */
91 fputs_filtered (" Pseudo-denormal", file
);
92 else if (fraction
[0] || fraction
[1])
94 fputs_filtered (" Denormal", file
);
98 fputs_filtered (" Unsupported", file
);
101 /* Print the status word STATUS. If STATUS_P is false, then STATUS
105 print_i387_status_word (int status_p
,
106 unsigned int status
, struct ui_file
*file
)
108 fprintf_filtered (file
, "Status Word: ");
111 fprintf_filtered (file
, "%s\n", _("<unavailable>"));
115 fprintf_filtered (file
, "%s", hex_string_custom (status
, 4));
116 fputs_filtered (" ", file
);
117 fprintf_filtered (file
, " %s", (status
& 0x0001) ? "IE" : " ");
118 fprintf_filtered (file
, " %s", (status
& 0x0002) ? "DE" : " ");
119 fprintf_filtered (file
, " %s", (status
& 0x0004) ? "ZE" : " ");
120 fprintf_filtered (file
, " %s", (status
& 0x0008) ? "OE" : " ");
121 fprintf_filtered (file
, " %s", (status
& 0x0010) ? "UE" : " ");
122 fprintf_filtered (file
, " %s", (status
& 0x0020) ? "PE" : " ");
123 fputs_filtered (" ", file
);
124 fprintf_filtered (file
, " %s", (status
& 0x0080) ? "ES" : " ");
125 fputs_filtered (" ", file
);
126 fprintf_filtered (file
, " %s", (status
& 0x0040) ? "SF" : " ");
127 fputs_filtered (" ", file
);
128 fprintf_filtered (file
, " %s", (status
& 0x0100) ? "C0" : " ");
129 fprintf_filtered (file
, " %s", (status
& 0x0200) ? "C1" : " ");
130 fprintf_filtered (file
, " %s", (status
& 0x0400) ? "C2" : " ");
131 fprintf_filtered (file
, " %s", (status
& 0x4000) ? "C3" : " ");
133 fputs_filtered ("\n", file
);
135 fprintf_filtered (file
,
136 " TOP: %d\n", ((status
>> 11) & 7));
139 /* Print the control word CONTROL. If CONTROL_P is false, then
140 CONTROL was unavailable. */
143 print_i387_control_word (int control_p
,
144 unsigned int control
, struct ui_file
*file
)
146 fprintf_filtered (file
, "Control Word: ");
149 fprintf_filtered (file
, "%s\n", _("<unavailable>"));
153 fprintf_filtered (file
, "%s", hex_string_custom (control
, 4));
154 fputs_filtered (" ", file
);
155 fprintf_filtered (file
, " %s", (control
& 0x0001) ? "IM" : " ");
156 fprintf_filtered (file
, " %s", (control
& 0x0002) ? "DM" : " ");
157 fprintf_filtered (file
, " %s", (control
& 0x0004) ? "ZM" : " ");
158 fprintf_filtered (file
, " %s", (control
& 0x0008) ? "OM" : " ");
159 fprintf_filtered (file
, " %s", (control
& 0x0010) ? "UM" : " ");
160 fprintf_filtered (file
, " %s", (control
& 0x0020) ? "PM" : " ");
162 fputs_filtered ("\n", file
);
164 fputs_filtered (" PC: ", file
);
165 switch ((control
>> 8) & 3)
168 fputs_filtered ("Single Precision (24-bits)\n", file
);
171 fputs_filtered ("Reserved\n", file
);
174 fputs_filtered ("Double Precision (53-bits)\n", file
);
177 fputs_filtered ("Extended Precision (64-bits)\n", file
);
181 fputs_filtered (" RC: ", file
);
182 switch ((control
>> 10) & 3)
185 fputs_filtered ("Round to nearest\n", file
);
188 fputs_filtered ("Round down\n", file
);
191 fputs_filtered ("Round up\n", file
);
194 fputs_filtered ("Round toward zero\n", file
);
199 /* Print out the i387 floating point state. Note that we ignore FRAME
200 in the code below. That's OK since floating-point registers are
201 never saved on the stack. */
204 i387_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
205 struct frame_info
*frame
, const char *args
)
207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
227 gdb_assert (gdbarch
== get_frame_arch (frame
));
229 fctrl_p
= read_frame_register_unsigned (frame
,
230 I387_FCTRL_REGNUM (tdep
), &fctrl
);
231 fstat_p
= read_frame_register_unsigned (frame
,
232 I387_FSTAT_REGNUM (tdep
), &fstat
);
233 ftag_p
= read_frame_register_unsigned (frame
,
234 I387_FTAG_REGNUM (tdep
), &ftag
);
235 fiseg_p
= read_frame_register_unsigned (frame
,
236 I387_FISEG_REGNUM (tdep
), &fiseg
);
237 fioff_p
= read_frame_register_unsigned (frame
,
238 I387_FIOFF_REGNUM (tdep
), &fioff
);
239 foseg_p
= read_frame_register_unsigned (frame
,
240 I387_FOSEG_REGNUM (tdep
), &foseg
);
241 fooff_p
= read_frame_register_unsigned (frame
,
242 I387_FOOFF_REGNUM (tdep
), &fooff
);
243 fop_p
= read_frame_register_unsigned (frame
,
244 I387_FOP_REGNUM (tdep
), &fop
);
248 top
= ((fstat
>> 11) & 7);
250 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
252 struct value
*regval
;
257 fprintf_filtered (file
, "%sR%d: ", fpreg
== top
? "=>" : " ", fpreg
);
261 tag
= (ftag
>> (fpreg
* 2)) & 3;
266 fputs_filtered ("Valid ", file
);
269 fputs_filtered ("Zero ", file
);
272 fputs_filtered ("Special ", file
);
275 fputs_filtered ("Empty ", file
);
280 fputs_filtered ("Unknown ", file
);
282 regnum
= (fpreg
+ 8 - top
) % 8 + I387_ST0_REGNUM (tdep
);
283 regval
= get_frame_register_value (frame
, regnum
);
285 if (value_entirely_available (regval
))
287 const gdb_byte
*raw
= value_contents (regval
).data ();
289 fputs_filtered ("0x", file
);
290 for (i
= 9; i
>= 0; i
--)
291 fprintf_filtered (file
, "%02x", raw
[i
]);
293 if (tag
!= -1 && tag
!= 3)
294 print_i387_ext (gdbarch
, raw
, file
);
297 fprintf_filtered (file
, "%s", _("<unavailable>"));
299 fputs_filtered ("\n", file
);
303 fputs_filtered ("\n", file
);
304 print_i387_status_word (fstat_p
, fstat
, file
);
305 print_i387_control_word (fctrl_p
, fctrl
, file
);
306 fprintf_filtered (file
, "Tag Word: %s\n",
307 ftag_p
? hex_string_custom (ftag
, 4) : _("<unavailable>"));
308 fprintf_filtered (file
, "Instruction Pointer: %s:",
309 fiseg_p
? hex_string_custom (fiseg
, 2) : _("<unavailable>"));
310 fprintf_filtered (file
, "%s\n",
311 fioff_p
? hex_string_custom (fioff
, 8) : _("<unavailable>"));
312 fprintf_filtered (file
, "Operand Pointer: %s:",
313 foseg_p
? hex_string_custom (foseg
, 2) : _("<unavailable>"));
314 fprintf_filtered (file
, "%s\n",
315 fooff_p
? hex_string_custom (fooff
, 8) : _("<unavailable>"));
316 fprintf_filtered (file
, "Opcode: %s\n",
318 ? (hex_string_custom (fop
? (fop
| 0xd800) : 0, 4))
319 : _("<unavailable>"));
323 /* Return nonzero if a value of type TYPE stored in register REGNUM
324 needs any special handling. */
327 i387_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
330 if (i386_fp_regnum_p (gdbarch
, regnum
))
332 /* Floating point registers must be converted unless we are
333 accessing them in their hardware type or TYPE is not float. */
334 if (type
== i387_ext_type (gdbarch
)
335 || type
->code () != TYPE_CODE_FLT
)
344 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
345 return its contents in TO. */
348 i387_register_to_value (struct frame_info
*frame
, int regnum
,
349 struct type
*type
, gdb_byte
*to
,
350 int *optimizedp
, int *unavailablep
)
352 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
353 gdb_byte from
[I386_MAX_REGISTER_SIZE
];
355 gdb_assert (i386_fp_regnum_p (gdbarch
, regnum
));
357 /* We only support floating-point values. */
358 if (type
->code () != TYPE_CODE_FLT
)
360 warning (_("Cannot convert floating-point register value "
361 "to non-floating-point type."));
362 *optimizedp
= *unavailablep
= 0;
366 /* Convert to TYPE. */
367 if (!get_frame_register_bytes (frame
, regnum
, 0,
368 gdb::make_array_view (from
,
369 register_size (gdbarch
,
371 optimizedp
, unavailablep
))
374 target_float_convert (from
, i387_ext_type (gdbarch
), to
, type
);
375 *optimizedp
= *unavailablep
= 0;
379 /* Write the contents FROM of a value of type TYPE into register
380 REGNUM in frame FRAME. */
383 i387_value_to_register (struct frame_info
*frame
, int regnum
,
384 struct type
*type
, const gdb_byte
*from
)
386 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
387 gdb_byte to
[I386_MAX_REGISTER_SIZE
];
389 gdb_assert (i386_fp_regnum_p (gdbarch
, regnum
));
391 /* We only support floating-point values. */
392 if (type
->code () != TYPE_CODE_FLT
)
394 warning (_("Cannot convert non-floating-point type "
395 "to floating-point register value."));
399 /* Convert from TYPE. */
400 target_float_convert (from
, type
, to
, i387_ext_type (gdbarch
));
401 put_frame_register (frame
, regnum
, to
);
405 /* Handle FSAVE and FXSAVE formats. */
407 /* At fsave_offset[REGNUM] you'll find the offset to the location in
408 the data structure used by the "fsave" instruction where GDB
409 register REGNUM is stored. */
411 static int fsave_offset
[] =
413 28 + 0 * 10, /* %st(0) ... */
420 28 + 7 * 10, /* ... %st(7). */
421 0, /* `fctrl' (16 bits). */
422 4, /* `fstat' (16 bits). */
423 8, /* `ftag' (16 bits). */
424 16, /* `fiseg' (16 bits). */
426 24, /* `foseg' (16 bits). */
428 18 /* `fop' (bottom 11 bits). */
431 #define FSAVE_ADDR(tdep, fsave, regnum) \
432 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
435 /* Fill register REGNUM in REGCACHE with the appropriate value from
436 *FSAVE. This function masks off any of the reserved bits in
440 i387_supply_fsave (struct regcache
*regcache
, int regnum
, const void *fsave
)
442 struct gdbarch
*gdbarch
= regcache
->arch ();
443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
444 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
445 const gdb_byte
*regs
= (const gdb_byte
*) fsave
;
448 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
450 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
451 if (regnum
== -1 || regnum
== i
)
455 regcache
->raw_supply (i
, NULL
);
459 /* Most of the FPU control registers occupy only 16 bits in the
460 fsave area. Give those a special treatment. */
461 if (i
>= I387_FCTRL_REGNUM (tdep
)
462 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
466 memcpy (val
, FSAVE_ADDR (tdep
, regs
, i
), 2);
468 if (i
== I387_FOP_REGNUM (tdep
))
469 val
[1] &= ((1 << 3) - 1);
470 regcache
->raw_supply (i
, val
);
473 regcache
->raw_supply (i
, FSAVE_ADDR (tdep
, regs
, i
));
476 /* Provide dummy values for the SSE registers. */
477 for (i
= I387_XMM0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
478 if (regnum
== -1 || regnum
== i
)
479 regcache
->raw_supply (i
, NULL
);
480 if (regnum
== -1 || regnum
== I387_MXCSR_REGNUM (tdep
))
484 store_unsigned_integer (buf
, 4, byte_order
, I387_MXCSR_INIT_VAL
);
485 regcache
->raw_supply (I387_MXCSR_REGNUM (tdep
), buf
);
489 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
490 with the value from REGCACHE. If REGNUM is -1, do this for all
491 registers. This function doesn't touch any of the reserved bits in
495 i387_collect_fsave (const struct regcache
*regcache
, int regnum
, void *fsave
)
497 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
498 gdb_byte
*regs
= (gdb_byte
*) fsave
;
501 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
503 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
504 if (regnum
== -1 || regnum
== i
)
506 /* Most of the FPU control registers occupy only 16 bits in
507 the fsave area. Give those a special treatment. */
508 if (i
>= I387_FCTRL_REGNUM (tdep
)
509 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
513 regcache
->raw_collect (i
, buf
);
515 if (i
== I387_FOP_REGNUM (tdep
))
517 /* The opcode occupies only 11 bits. Make sure we
518 don't touch the other bits. */
519 buf
[1] &= ((1 << 3) - 1);
520 buf
[1] |= ((FSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
522 memcpy (FSAVE_ADDR (tdep
, regs
, i
), buf
, 2);
525 regcache
->raw_collect (i
, FSAVE_ADDR (tdep
, regs
, i
));
530 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
531 the data structure used by the "fxsave" instruction where GDB
532 register REGNUM is stored. */
534 static int fxsave_offset
[] =
536 32, /* %st(0) through ... */
543 144, /* ... %st(7) (80 bits each). */
544 0, /* `fctrl' (16 bits). */
545 2, /* `fstat' (16 bits). */
546 4, /* `ftag' (16 bits). */
547 12, /* `fiseg' (16 bits). */
549 20, /* `foseg' (16 bits). */
551 6, /* `fop' (bottom 11 bits). */
552 160 + 0 * 16, /* %xmm0 through ... */
567 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
570 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
571 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
573 /* We made an unfortunate choice in putting %mxcsr after the SSE
574 registers %xmm0-%xmm7 instead of before, since it makes supporting
575 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
576 don't include the offset for %mxcsr here above. */
578 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
580 static int i387_tag (const gdb_byte
*raw
);
583 /* Fill register REGNUM in REGCACHE with the appropriate
584 floating-point or SSE register value from *FXSAVE. This function
585 masks off any of the reserved bits in *FXSAVE. */
588 i387_supply_fxsave (struct regcache
*regcache
, int regnum
, const void *fxsave
)
590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
591 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
594 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
595 gdb_assert (tdep
->num_xmm_regs
> 0);
597 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
598 if (regnum
== -1 || regnum
== i
)
602 regcache
->raw_supply (i
, NULL
);
606 /* Most of the FPU control registers occupy only 16 bits in
607 the fxsave area. Give those a special treatment. */
608 if (i
>= I387_FCTRL_REGNUM (tdep
) && i
< I387_XMM0_REGNUM (tdep
)
609 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
613 memcpy (val
, FXSAVE_ADDR (tdep
, regs
, i
), 2);
615 if (i
== I387_FOP_REGNUM (tdep
))
616 val
[1] &= ((1 << 3) - 1);
617 else if (i
== I387_FTAG_REGNUM (tdep
))
619 /* The fxsave area contains a simplified version of
620 the tag word. We have to look at the actual 80-bit
621 FP data to recreate the traditional i387 tag word. */
623 unsigned long ftag
= 0;
627 top
= ((FXSAVE_ADDR (tdep
, regs
,
628 I387_FSTAT_REGNUM (tdep
)))[1] >> 3);
631 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
635 if (val
[0] & (1 << fpreg
))
637 int thisreg
= (fpreg
+ 8 - top
) % 8
638 + I387_ST0_REGNUM (tdep
);
639 tag
= i387_tag (FXSAVE_ADDR (tdep
, regs
, thisreg
));
644 ftag
|= tag
<< (2 * fpreg
);
646 val
[0] = ftag
& 0xff;
647 val
[1] = (ftag
>> 8) & 0xff;
649 regcache
->raw_supply (i
, val
);
652 regcache
->raw_supply (i
, FXSAVE_ADDR (tdep
, regs
, i
));
655 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
658 regcache
->raw_supply (I387_MXCSR_REGNUM (tdep
), NULL
);
660 regcache
->raw_supply (I387_MXCSR_REGNUM (tdep
),
661 FXSAVE_MXCSR_ADDR (regs
));
665 /* Fill register REGNUM (if it is a floating-point or SSE register) in
666 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
667 all registers. This function doesn't touch any of the reserved
671 i387_collect_fxsave (const struct regcache
*regcache
, int regnum
, void *fxsave
)
673 struct gdbarch_tdep
*tdep
= gdbarch_tdep (regcache
->arch ());
674 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
677 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
678 gdb_assert (tdep
->num_xmm_regs
> 0);
680 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
681 if (regnum
== -1 || regnum
== i
)
683 /* Most of the FPU control registers occupy only 16 bits in
684 the fxsave area. Give those a special treatment. */
685 if (i
>= I387_FCTRL_REGNUM (tdep
) && i
< I387_XMM0_REGNUM (tdep
)
686 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
690 regcache
->raw_collect (i
, buf
);
692 if (i
== I387_FOP_REGNUM (tdep
))
694 /* The opcode occupies only 11 bits. Make sure we
695 don't touch the other bits. */
696 buf
[1] &= ((1 << 3) - 1);
697 buf
[1] |= ((FXSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
699 else if (i
== I387_FTAG_REGNUM (tdep
))
701 /* Converting back is much easier. */
706 ftag
= (buf
[1] << 8) | buf
[0];
710 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
712 int tag
= (ftag
>> (fpreg
* 2)) & 3;
715 buf
[0] |= (1 << fpreg
);
718 memcpy (FXSAVE_ADDR (tdep
, regs
, i
), buf
, 2);
721 regcache
->raw_collect (i
, FXSAVE_ADDR (tdep
, regs
, i
));
724 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
725 regcache
->raw_collect (I387_MXCSR_REGNUM (tdep
),
726 FXSAVE_MXCSR_ADDR (regs
));
729 /* `xstate_bv' is at byte offset 512. */
730 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
732 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
733 the upper 128bit of AVX register data structure used by the "xsave"
734 instruction where GDB register REGNUM is stored. */
736 static int xsave_avxh_offset
[] =
738 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
753 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
756 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
757 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
759 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
760 the upper 128bit of ZMM register data structure used by the "xsave"
761 instruction where GDB register REGNUM is stored. */
763 static int xsave_ymm_avx512_offset
[] =
765 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
766 1664 + 16 + 0 * 64, /* %ymm16 through... */
781 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
784 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
785 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
787 static int xsave_xmm_avx512_offset
[] =
789 1664 + 0 * 64, /* %ymm16 through... */
804 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
807 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
808 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
810 static int xsave_mpx_offset
[] = {
811 960 + 0 * 16, /* bnd0r...bnd3r registers. */
815 1024 + 0 * 8, /* bndcfg ... bndstatus. */
819 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
820 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
822 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
823 of the AVX512 opmask register data structure used by the "xsave"
824 instruction where GDB register REGNUM is stored. */
826 static int xsave_avx512_k_offset
[] =
828 1088 + 0 * 8, /* %k0 through... */
835 1088 + 7 * 8 /* %k7 (64 bits each). */
838 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
839 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
841 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
842 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
843 instruction where GDB register REGNUM is stored. */
845 static int xsave_avx512_zmm_h_offset
[] =
848 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
862 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
863 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
878 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
881 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
882 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
884 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location
885 of the PKRU register data structure used by the "xsave"
886 instruction where GDB register REGNUM is stored. */
888 static int xsave_pkeys_offset
[] =
890 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by
891 instructions and applications). */
894 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \
895 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)])
898 /* Extract from XSAVE a bitset of the features that are available on the
899 target, but which have not yet been enabled. */
902 i387_xsave_get_clear_bv (struct gdbarch
*gdbarch
, const void *xsave
)
904 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
905 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
908 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
909 ULONGEST xstate_bv
= extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
912 /* Clear part in vector registers if its bit in xstat_bv is zero. */
913 ULONGEST clear_bv
= (~(xstate_bv
)) & tdep
->xcr0
;
918 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
921 i387_supply_xsave (struct regcache
*regcache
, int regnum
,
924 struct gdbarch
*gdbarch
= regcache
->arch ();
925 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
927 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
929 /* In 64-bit mode the split between "low" and "high" ZMM registers is at
930 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all.
931 Precalculate the number to be used for the split point, with the all
932 registers in the "low" portion outside of 64-bit mode. */
933 unsigned int zmm_endlo_regnum
= I387_ZMM0H_REGNUM (tdep
)
934 + std::min (tdep
->num_zmm_regs
, 16);
936 static const gdb_byte zero
[I386_MAX_REGISTER_SIZE
] = { 0 };
946 avx512_ymmh_avx512
= 0x40,
947 avx512_xmm_avx512
= 0x80,
949 all
= x87
| sse
| avxh
| mpx
| avx512_k
| avx512_zmm_h
950 | avx512_ymmh_avx512
| avx512_xmm_avx512
| pkeys
953 gdb_assert (regs
!= NULL
);
954 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
955 gdb_assert (tdep
->num_xmm_regs
> 0);
959 else if (regnum
>= I387_PKRU_REGNUM (tdep
)
960 && regnum
< I387_PKEYSEND_REGNUM (tdep
))
962 else if (regnum
>= I387_ZMM0H_REGNUM (tdep
)
963 && regnum
< I387_ZMMENDH_REGNUM (tdep
))
964 regclass
= avx512_zmm_h
;
965 else if (regnum
>= I387_K0_REGNUM (tdep
)
966 && regnum
< I387_KEND_REGNUM (tdep
))
968 else if (regnum
>= I387_YMM16H_REGNUM (tdep
)
969 && regnum
< I387_YMMH_AVX512_END_REGNUM (tdep
))
970 regclass
= avx512_ymmh_avx512
;
971 else if (regnum
>= I387_XMM16_REGNUM (tdep
)
972 && regnum
< I387_XMM_AVX512_END_REGNUM (tdep
))
973 regclass
= avx512_xmm_avx512
;
974 else if (regnum
>= I387_YMM0H_REGNUM (tdep
)
975 && regnum
< I387_YMMENDH_REGNUM (tdep
))
977 else if (regnum
>= I387_BND0R_REGNUM (tdep
)
978 && regnum
< I387_MPXEND_REGNUM (tdep
))
980 else if (regnum
>= I387_XMM0_REGNUM (tdep
)
981 && regnum
< I387_MXCSR_REGNUM (tdep
))
983 else if (regnum
>= I387_ST0_REGNUM (tdep
)
984 && regnum
< I387_FCTRL_REGNUM (tdep
))
989 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
991 /* With the delayed xsave mechanism, in between the program
992 starting, and the program accessing the vector registers for the
993 first time, the register's values are invalid. The kernel
994 initializes register states to zero when they are set the first
995 time in a program. This means that from the user-space programs'
996 perspective, it's the same as if the registers have always been
997 zero from the start of the program. Therefore, the debugger
998 should provide the same illusion to the user. */
1006 if ((clear_bv
& X86_XSTATE_PKRU
))
1007 regcache
->raw_supply (regnum
, zero
);
1009 regcache
->raw_supply (regnum
, XSAVE_PKEYS_ADDR (tdep
, regs
, regnum
));
1013 if ((clear_bv
& (regnum
< zmm_endlo_regnum
? X86_XSTATE_ZMM_H
1015 regcache
->raw_supply (regnum
, zero
);
1017 regcache
->raw_supply (regnum
,
1018 XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, regnum
));
1022 if ((clear_bv
& X86_XSTATE_K
))
1023 regcache
->raw_supply (regnum
, zero
);
1025 regcache
->raw_supply (regnum
, XSAVE_AVX512_K_ADDR (tdep
, regs
, regnum
));
1028 case avx512_ymmh_avx512
:
1029 if ((clear_bv
& X86_XSTATE_ZMM
))
1030 regcache
->raw_supply (regnum
, zero
);
1032 regcache
->raw_supply (regnum
,
1033 XSAVE_YMM_AVX512_ADDR (tdep
, regs
, regnum
));
1036 case avx512_xmm_avx512
:
1037 if ((clear_bv
& X86_XSTATE_ZMM
))
1038 regcache
->raw_supply (regnum
, zero
);
1040 regcache
->raw_supply (regnum
,
1041 XSAVE_XMM_AVX512_ADDR (tdep
, regs
, regnum
));
1045 if ((clear_bv
& X86_XSTATE_AVX
))
1046 regcache
->raw_supply (regnum
, zero
);
1048 regcache
->raw_supply (regnum
, XSAVE_AVXH_ADDR (tdep
, regs
, regnum
));
1052 if ((clear_bv
& X86_XSTATE_BNDREGS
))
1053 regcache
->raw_supply (regnum
, zero
);
1055 regcache
->raw_supply (regnum
, XSAVE_MPX_ADDR (tdep
, regs
, regnum
));
1059 if ((clear_bv
& X86_XSTATE_SSE
))
1060 regcache
->raw_supply (regnum
, zero
);
1062 regcache
->raw_supply (regnum
, FXSAVE_ADDR (tdep
, regs
, regnum
));
1066 if ((clear_bv
& X86_XSTATE_X87
))
1067 regcache
->raw_supply (regnum
, zero
);
1069 regcache
->raw_supply (regnum
, FXSAVE_ADDR (tdep
, regs
, regnum
));
1073 /* Handle PKEYS registers. */
1074 if ((tdep
->xcr0
& X86_XSTATE_PKRU
))
1076 if ((clear_bv
& X86_XSTATE_PKRU
))
1078 for (i
= I387_PKRU_REGNUM (tdep
);
1079 i
< I387_PKEYSEND_REGNUM (tdep
);
1081 regcache
->raw_supply (i
, zero
);
1085 for (i
= I387_PKRU_REGNUM (tdep
);
1086 i
< I387_PKEYSEND_REGNUM (tdep
);
1088 regcache
->raw_supply (i
, XSAVE_PKEYS_ADDR (tdep
, regs
, i
));
1092 /* Handle the upper halves of the low 8/16 ZMM registers. */
1093 if ((tdep
->xcr0
& X86_XSTATE_ZMM_H
))
1095 if ((clear_bv
& X86_XSTATE_ZMM_H
))
1097 for (i
= I387_ZMM0H_REGNUM (tdep
); i
< zmm_endlo_regnum
; i
++)
1098 regcache
->raw_supply (i
, zero
);
1102 for (i
= I387_ZMM0H_REGNUM (tdep
); i
< zmm_endlo_regnum
; i
++)
1103 regcache
->raw_supply (i
,
1104 XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
));
1108 /* Handle AVX512 OpMask registers. */
1109 if ((tdep
->xcr0
& X86_XSTATE_K
))
1111 if ((clear_bv
& X86_XSTATE_K
))
1113 for (i
= I387_K0_REGNUM (tdep
);
1114 i
< I387_KEND_REGNUM (tdep
);
1116 regcache
->raw_supply (i
, zero
);
1120 for (i
= I387_K0_REGNUM (tdep
);
1121 i
< I387_KEND_REGNUM (tdep
);
1123 regcache
->raw_supply (i
, XSAVE_AVX512_K_ADDR (tdep
, regs
, i
));
1127 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */
1128 if ((tdep
->xcr0
& X86_XSTATE_ZMM
))
1130 if ((clear_bv
& X86_XSTATE_ZMM
))
1132 for (i
= zmm_endlo_regnum
; i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1133 regcache
->raw_supply (i
, zero
);
1134 for (i
= I387_YMM16H_REGNUM (tdep
);
1135 i
< I387_YMMH_AVX512_END_REGNUM (tdep
);
1137 regcache
->raw_supply (i
, zero
);
1138 for (i
= I387_XMM16_REGNUM (tdep
);
1139 i
< I387_XMM_AVX512_END_REGNUM (tdep
);
1141 regcache
->raw_supply (i
, zero
);
1145 for (i
= zmm_endlo_regnum
; i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1146 regcache
->raw_supply (i
,
1147 XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
));
1148 for (i
= I387_YMM16H_REGNUM (tdep
);
1149 i
< I387_YMMH_AVX512_END_REGNUM (tdep
);
1151 regcache
->raw_supply (i
, XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
));
1152 for (i
= I387_XMM16_REGNUM (tdep
);
1153 i
< I387_XMM_AVX512_END_REGNUM (tdep
);
1155 regcache
->raw_supply (i
, XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
));
1158 /* Handle the upper YMM registers. */
1159 if ((tdep
->xcr0
& X86_XSTATE_AVX
))
1161 if ((clear_bv
& X86_XSTATE_AVX
))
1163 for (i
= I387_YMM0H_REGNUM (tdep
);
1164 i
< I387_YMMENDH_REGNUM (tdep
);
1166 regcache
->raw_supply (i
, zero
);
1170 for (i
= I387_YMM0H_REGNUM (tdep
);
1171 i
< I387_YMMENDH_REGNUM (tdep
);
1173 regcache
->raw_supply (i
, XSAVE_AVXH_ADDR (tdep
, regs
, i
));
1177 /* Handle the MPX registers. */
1178 if ((tdep
->xcr0
& X86_XSTATE_BNDREGS
))
1180 if (clear_bv
& X86_XSTATE_BNDREGS
)
1182 for (i
= I387_BND0R_REGNUM (tdep
);
1183 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1184 regcache
->raw_supply (i
, zero
);
1188 for (i
= I387_BND0R_REGNUM (tdep
);
1189 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1190 regcache
->raw_supply (i
, XSAVE_MPX_ADDR (tdep
, regs
, i
));
1194 /* Handle the MPX registers. */
1195 if ((tdep
->xcr0
& X86_XSTATE_BNDCFG
))
1197 if (clear_bv
& X86_XSTATE_BNDCFG
)
1199 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1200 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1201 regcache
->raw_supply (i
, zero
);
1205 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1206 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1207 regcache
->raw_supply (i
, XSAVE_MPX_ADDR (tdep
, regs
, i
));
1211 /* Handle the XMM registers. */
1212 if ((tdep
->xcr0
& X86_XSTATE_SSE
))
1214 if ((clear_bv
& X86_XSTATE_SSE
))
1216 for (i
= I387_XMM0_REGNUM (tdep
);
1217 i
< I387_MXCSR_REGNUM (tdep
);
1219 regcache
->raw_supply (i
, zero
);
1223 for (i
= I387_XMM0_REGNUM (tdep
);
1224 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1225 regcache
->raw_supply (i
, FXSAVE_ADDR (tdep
, regs
, i
));
1229 /* Handle the x87 registers. */
1230 if ((tdep
->xcr0
& X86_XSTATE_X87
))
1232 if ((clear_bv
& X86_XSTATE_X87
))
1234 for (i
= I387_ST0_REGNUM (tdep
);
1235 i
< I387_FCTRL_REGNUM (tdep
);
1237 regcache
->raw_supply (i
, zero
);
1241 for (i
= I387_ST0_REGNUM (tdep
);
1242 i
< I387_FCTRL_REGNUM (tdep
);
1244 regcache
->raw_supply (i
, FXSAVE_ADDR (tdep
, regs
, i
));
1250 /* Only handle x87 control registers. */
1251 for (i
= I387_FCTRL_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
1252 if (regnum
== -1 || regnum
== i
)
1254 if (clear_bv
& X86_XSTATE_X87
)
1256 if (i
== I387_FCTRL_REGNUM (tdep
))
1260 store_unsigned_integer (buf
, 4, byte_order
,
1261 I387_FCTRL_INIT_VAL
);
1262 regcache
->raw_supply (i
, buf
);
1264 else if (i
== I387_FTAG_REGNUM (tdep
))
1268 store_unsigned_integer (buf
, 4, byte_order
, 0xffff);
1269 regcache
->raw_supply (i
, buf
);
1272 regcache
->raw_supply (i
, zero
);
1274 /* Most of the FPU control registers occupy only 16 bits in
1275 the xsave extended state. Give those a special treatment. */
1276 else if (i
!= I387_FIOFF_REGNUM (tdep
)
1277 && i
!= I387_FOOFF_REGNUM (tdep
))
1281 memcpy (val
, FXSAVE_ADDR (tdep
, regs
, i
), 2);
1282 val
[2] = val
[3] = 0;
1283 if (i
== I387_FOP_REGNUM (tdep
))
1284 val
[1] &= ((1 << 3) - 1);
1285 else if (i
== I387_FTAG_REGNUM (tdep
))
1287 /* The fxsave area contains a simplified version of
1288 the tag word. We have to look at the actual 80-bit
1289 FP data to recreate the traditional i387 tag word. */
1291 unsigned long ftag
= 0;
1295 top
= ((FXSAVE_ADDR (tdep
, regs
,
1296 I387_FSTAT_REGNUM (tdep
)))[1] >> 3);
1299 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
1303 if (val
[0] & (1 << fpreg
))
1305 int thisreg
= (fpreg
+ 8 - top
) % 8
1306 + I387_ST0_REGNUM (tdep
);
1307 tag
= i387_tag (FXSAVE_ADDR (tdep
, regs
, thisreg
));
1310 tag
= 3; /* Empty */
1312 ftag
|= tag
<< (2 * fpreg
);
1314 val
[0] = ftag
& 0xff;
1315 val
[1] = (ftag
>> 8) & 0xff;
1317 regcache
->raw_supply (i
, val
);
1320 regcache
->raw_supply (i
, FXSAVE_ADDR (tdep
, regs
, i
));
1323 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
1325 /* The MXCSR register is placed into the xsave buffer if either the
1326 AVX or SSE features are enabled. */
1327 if ((clear_bv
& (X86_XSTATE_AVX
| X86_XSTATE_SSE
))
1328 == (X86_XSTATE_AVX
| X86_XSTATE_SSE
))
1332 store_unsigned_integer (buf
, 4, byte_order
, I387_MXCSR_INIT_VAL
);
1333 regcache
->raw_supply (I387_MXCSR_REGNUM (tdep
), buf
);
1336 regcache
->raw_supply (I387_MXCSR_REGNUM (tdep
),
1337 FXSAVE_MXCSR_ADDR (regs
));
1341 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1344 i387_collect_xsave (const struct regcache
*regcache
, int regnum
,
1345 void *xsave
, int gcore
)
1347 struct gdbarch
*gdbarch
= regcache
->arch ();
1348 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1350 gdb_byte
*p
, *regs
= (gdb_byte
*) xsave
;
1351 gdb_byte raw
[I386_MAX_REGISTER_SIZE
];
1352 ULONGEST initial_xstate_bv
, clear_bv
, xstate_bv
= 0;
1354 /* See the comment in i387_supply_xsave(). */
1355 unsigned int zmm_endlo_regnum
= I387_ZMM0H_REGNUM (tdep
)
1356 + std::min (tdep
->num_zmm_regs
, 16);
1359 x87_ctrl_or_mxcsr
= 0x1,
1365 avx512_zmm_h
= 0x40,
1366 avx512_ymmh_avx512
= 0x80,
1367 avx512_xmm_avx512
= 0x100,
1369 all
= x87
| sse
| avxh
| mpx
| avx512_k
| avx512_zmm_h
1370 | avx512_ymmh_avx512
| avx512_xmm_avx512
| pkeys
1373 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
1374 gdb_assert (tdep
->num_xmm_regs
> 0);
1378 else if (regnum
>= I387_PKRU_REGNUM (tdep
)
1379 && regnum
< I387_PKEYSEND_REGNUM (tdep
))
1381 else if (regnum
>= I387_ZMM0H_REGNUM (tdep
)
1382 && regnum
< I387_ZMMENDH_REGNUM (tdep
))
1383 regclass
= avx512_zmm_h
;
1384 else if (regnum
>= I387_K0_REGNUM (tdep
)
1385 && regnum
< I387_KEND_REGNUM (tdep
))
1386 regclass
= avx512_k
;
1387 else if (regnum
>= I387_YMM16H_REGNUM (tdep
)
1388 && regnum
< I387_YMMH_AVX512_END_REGNUM (tdep
))
1389 regclass
= avx512_ymmh_avx512
;
1390 else if (regnum
>= I387_XMM16_REGNUM (tdep
)
1391 && regnum
< I387_XMM_AVX512_END_REGNUM (tdep
))
1392 regclass
= avx512_xmm_avx512
;
1393 else if (regnum
>= I387_YMM0H_REGNUM (tdep
)
1394 && regnum
< I387_YMMENDH_REGNUM (tdep
))
1396 else if (regnum
>= I387_BND0R_REGNUM (tdep
)
1397 && regnum
< I387_MPXEND_REGNUM (tdep
))
1399 else if (regnum
>= I387_XMM0_REGNUM (tdep
)
1400 && regnum
< I387_MXCSR_REGNUM (tdep
))
1402 else if (regnum
>= I387_ST0_REGNUM (tdep
)
1403 && regnum
< I387_FCTRL_REGNUM (tdep
))
1405 else if ((regnum
>= I387_FCTRL_REGNUM (tdep
)
1406 && regnum
< I387_XMM0_REGNUM (tdep
))
1407 || regnum
== I387_MXCSR_REGNUM (tdep
))
1408 regclass
= x87_ctrl_or_mxcsr
;
1410 internal_error (__FILE__
, __LINE__
, _("invalid i387 regnum %d"), regnum
);
1414 /* Clear XSAVE extended state. */
1415 memset (regs
, 0, X86_XSTATE_SIZE (tdep
->xcr0
));
1417 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1418 if (tdep
->xsave_xcr0_offset
!= -1)
1419 memcpy (regs
+ tdep
->xsave_xcr0_offset
, &tdep
->xcr0
, 8);
1420 memcpy (XSAVE_XSTATE_BV_ADDR (regs
), &tdep
->xcr0
, 8);
1423 /* The supported bits in `xstat_bv' are 8 bytes. */
1424 initial_xstate_bv
= extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
1426 clear_bv
= (~(initial_xstate_bv
)) & tdep
->xcr0
;
1428 /* The XSAVE buffer was filled lazily by the kernel. Only those
1429 features that are enabled were written into the buffer, disabled
1430 features left the buffer uninitialised. In order to identify if any
1431 registers have changed we will be comparing the register cache
1432 version to the version in the XSAVE buffer, it is important then that
1433 at this point we initialise to the default values any features in
1434 XSAVE that are not yet initialised.
1436 This could be made more efficient, we know which features (from
1437 REGNUM) we will be potentially updating, and could limit ourselves to
1438 only clearing that feature. However, the extra complexity does not
1439 seem justified at this point. */
1442 if ((clear_bv
& X86_XSTATE_PKRU
))
1443 for (i
= I387_PKRU_REGNUM (tdep
);
1444 i
< I387_PKEYSEND_REGNUM (tdep
); i
++)
1445 memset (XSAVE_PKEYS_ADDR (tdep
, regs
, i
), 0, 4);
1447 if ((clear_bv
& X86_XSTATE_BNDREGS
))
1448 for (i
= I387_BND0R_REGNUM (tdep
);
1449 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1450 memset (XSAVE_MPX_ADDR (tdep
, regs
, i
), 0, 16);
1452 if ((clear_bv
& X86_XSTATE_BNDCFG
))
1453 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1454 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1455 memset (XSAVE_MPX_ADDR (tdep
, regs
, i
), 0, 8);
1457 if ((clear_bv
& X86_XSTATE_ZMM_H
))
1458 for (i
= I387_ZMM0H_REGNUM (tdep
); i
< zmm_endlo_regnum
; i
++)
1459 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
), 0, 32);
1461 if ((clear_bv
& X86_XSTATE_K
))
1462 for (i
= I387_K0_REGNUM (tdep
);
1463 i
< I387_KEND_REGNUM (tdep
); i
++)
1464 memset (XSAVE_AVX512_K_ADDR (tdep
, regs
, i
), 0, 8);
1466 if ((clear_bv
& X86_XSTATE_ZMM
))
1468 for (i
= zmm_endlo_regnum
; i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1469 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
), 0, 32);
1470 for (i
= I387_YMM16H_REGNUM (tdep
);
1471 i
< I387_YMMH_AVX512_END_REGNUM (tdep
); i
++)
1472 memset (XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
), 0, 16);
1473 for (i
= I387_XMM16_REGNUM (tdep
);
1474 i
< I387_XMM_AVX512_END_REGNUM (tdep
); i
++)
1475 memset (XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
), 0, 16);
1478 if ((clear_bv
& X86_XSTATE_AVX
))
1479 for (i
= I387_YMM0H_REGNUM (tdep
);
1480 i
< I387_YMMENDH_REGNUM (tdep
); i
++)
1481 memset (XSAVE_AVXH_ADDR (tdep
, regs
, i
), 0, 16);
1483 if ((clear_bv
& X86_XSTATE_SSE
))
1484 for (i
= I387_XMM0_REGNUM (tdep
);
1485 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1486 memset (FXSAVE_ADDR (tdep
, regs
, i
), 0, 16);
1488 /* The mxcsr register is written into the xsave buffer if either AVX
1489 or SSE is enabled, so only clear it if both of those features
1490 require clearing. */
1491 if ((clear_bv
& (X86_XSTATE_AVX
| X86_XSTATE_SSE
))
1492 == (X86_XSTATE_AVX
| X86_XSTATE_SSE
))
1493 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs
), 2, byte_order
,
1494 I387_MXCSR_INIT_VAL
);
1496 if ((clear_bv
& X86_XSTATE_X87
))
1498 for (i
= I387_ST0_REGNUM (tdep
);
1499 i
< I387_FCTRL_REGNUM (tdep
); i
++)
1500 memset (FXSAVE_ADDR (tdep
, regs
, i
), 0, 10);
1502 for (i
= I387_FCTRL_REGNUM (tdep
);
1503 i
< I387_XMM0_REGNUM (tdep
); i
++)
1505 if (i
== I387_FCTRL_REGNUM (tdep
))
1506 store_unsigned_integer (FXSAVE_ADDR (tdep
, regs
, i
), 2,
1507 byte_order
, I387_FCTRL_INIT_VAL
);
1509 memset (FXSAVE_ADDR (tdep
, regs
, i
), 0,
1510 regcache_register_size (regcache
, i
));
1515 if (regclass
== all
)
1517 /* Check if any PKEYS registers are changed. */
1518 if ((tdep
->xcr0
& X86_XSTATE_PKRU
))
1519 for (i
= I387_PKRU_REGNUM (tdep
);
1520 i
< I387_PKEYSEND_REGNUM (tdep
); i
++)
1522 regcache
->raw_collect (i
, raw
);
1523 p
= XSAVE_PKEYS_ADDR (tdep
, regs
, i
);
1524 if (memcmp (raw
, p
, 4) != 0)
1526 xstate_bv
|= X86_XSTATE_PKRU
;
1531 /* Check if any ZMMH registers are changed. */
1532 if ((tdep
->xcr0
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
1533 for (i
= I387_ZMM0H_REGNUM (tdep
);
1534 i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1536 regcache
->raw_collect (i
, raw
);
1537 p
= XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
);
1538 if (memcmp (raw
, p
, 32) != 0)
1540 xstate_bv
|= (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
);
1541 memcpy (p
, raw
, 32);
1545 /* Check if any K registers are changed. */
1546 if ((tdep
->xcr0
& X86_XSTATE_K
))
1547 for (i
= I387_K0_REGNUM (tdep
);
1548 i
< I387_KEND_REGNUM (tdep
); i
++)
1550 regcache
->raw_collect (i
, raw
);
1551 p
= XSAVE_AVX512_K_ADDR (tdep
, regs
, i
);
1552 if (memcmp (raw
, p
, 8) != 0)
1554 xstate_bv
|= X86_XSTATE_K
;
1559 /* Check if any XMM or upper YMM registers are changed. */
1560 if ((tdep
->xcr0
& X86_XSTATE_ZMM
))
1562 for (i
= I387_YMM16H_REGNUM (tdep
);
1563 i
< I387_YMMH_AVX512_END_REGNUM (tdep
); i
++)
1565 regcache
->raw_collect (i
, raw
);
1566 p
= XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
);
1567 if (memcmp (raw
, p
, 16) != 0)
1569 xstate_bv
|= X86_XSTATE_ZMM
;
1570 memcpy (p
, raw
, 16);
1573 for (i
= I387_XMM16_REGNUM (tdep
);
1574 i
< I387_XMM_AVX512_END_REGNUM (tdep
); i
++)
1576 regcache
->raw_collect (i
, raw
);
1577 p
= XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
);
1578 if (memcmp (raw
, p
, 16) != 0)
1580 xstate_bv
|= X86_XSTATE_ZMM
;
1581 memcpy (p
, raw
, 16);
1586 /* Check if any upper MPX registers are changed. */
1587 if ((tdep
->xcr0
& X86_XSTATE_BNDREGS
))
1588 for (i
= I387_BND0R_REGNUM (tdep
);
1589 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1591 regcache
->raw_collect (i
, raw
);
1592 p
= XSAVE_MPX_ADDR (tdep
, regs
, i
);
1593 if (memcmp (raw
, p
, 16))
1595 xstate_bv
|= X86_XSTATE_BNDREGS
;
1596 memcpy (p
, raw
, 16);
1600 /* Check if any upper MPX registers are changed. */
1601 if ((tdep
->xcr0
& X86_XSTATE_BNDCFG
))
1602 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1603 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1605 regcache
->raw_collect (i
, raw
);
1606 p
= XSAVE_MPX_ADDR (tdep
, regs
, i
);
1607 if (memcmp (raw
, p
, 8))
1609 xstate_bv
|= X86_XSTATE_BNDCFG
;
1614 /* Check if any upper YMM registers are changed. */
1615 if ((tdep
->xcr0
& X86_XSTATE_AVX
))
1616 for (i
= I387_YMM0H_REGNUM (tdep
);
1617 i
< I387_YMMENDH_REGNUM (tdep
); i
++)
1619 regcache
->raw_collect (i
, raw
);
1620 p
= XSAVE_AVXH_ADDR (tdep
, regs
, i
);
1621 if (memcmp (raw
, p
, 16))
1623 xstate_bv
|= X86_XSTATE_AVX
;
1624 memcpy (p
, raw
, 16);
1628 /* Check if any SSE registers are changed. */
1629 if ((tdep
->xcr0
& X86_XSTATE_SSE
))
1630 for (i
= I387_XMM0_REGNUM (tdep
);
1631 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1633 regcache
->raw_collect (i
, raw
);
1634 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1635 if (memcmp (raw
, p
, 16))
1637 xstate_bv
|= X86_XSTATE_SSE
;
1638 memcpy (p
, raw
, 16);
1642 if ((tdep
->xcr0
& X86_XSTATE_AVX
) || (tdep
->xcr0
& X86_XSTATE_SSE
))
1644 i
= I387_MXCSR_REGNUM (tdep
);
1645 regcache
->raw_collect (i
, raw
);
1646 p
= FXSAVE_MXCSR_ADDR (regs
);
1647 if (memcmp (raw
, p
, 4))
1649 /* Now, we need to mark one of either SSE of AVX as enabled.
1650 We could pick either. What we do is check to see if one
1651 of the features is already enabled, if it is then we leave
1652 it at that, otherwise we pick SSE. */
1653 if ((xstate_bv
& (X86_XSTATE_SSE
| X86_XSTATE_AVX
)) == 0)
1654 xstate_bv
|= X86_XSTATE_SSE
;
1659 /* Check if any X87 registers are changed. Only the non-control
1660 registers are handled here, the control registers are all handled
1661 later on in this function. */
1662 if ((tdep
->xcr0
& X86_XSTATE_X87
))
1663 for (i
= I387_ST0_REGNUM (tdep
);
1664 i
< I387_FCTRL_REGNUM (tdep
); i
++)
1666 regcache
->raw_collect (i
, raw
);
1667 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1668 if (memcmp (raw
, p
, 10))
1670 xstate_bv
|= X86_XSTATE_X87
;
1671 memcpy (p
, raw
, 10);
1677 /* Check if REGNUM is changed. */
1678 regcache
->raw_collect (regnum
, raw
);
1683 internal_error (__FILE__
, __LINE__
,
1684 _("invalid i387 regclass"));
1687 /* This is a PKEYS register. */
1688 p
= XSAVE_PKEYS_ADDR (tdep
, regs
, regnum
);
1689 if (memcmp (raw
, p
, 4) != 0)
1691 xstate_bv
|= X86_XSTATE_PKRU
;
1697 /* This is a ZMM register. */
1698 p
= XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, regnum
);
1699 if (memcmp (raw
, p
, 32) != 0)
1701 xstate_bv
|= (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
);
1702 memcpy (p
, raw
, 32);
1706 /* This is a AVX512 mask register. */
1707 p
= XSAVE_AVX512_K_ADDR (tdep
, regs
, regnum
);
1708 if (memcmp (raw
, p
, 8) != 0)
1710 xstate_bv
|= X86_XSTATE_K
;
1715 case avx512_ymmh_avx512
:
1716 /* This is an upper YMM16-31 register. */
1717 p
= XSAVE_YMM_AVX512_ADDR (tdep
, regs
, regnum
);
1718 if (memcmp (raw
, p
, 16) != 0)
1720 xstate_bv
|= X86_XSTATE_ZMM
;
1721 memcpy (p
, raw
, 16);
1725 case avx512_xmm_avx512
:
1726 /* This is an upper XMM16-31 register. */
1727 p
= XSAVE_XMM_AVX512_ADDR (tdep
, regs
, regnum
);
1728 if (memcmp (raw
, p
, 16) != 0)
1730 xstate_bv
|= X86_XSTATE_ZMM
;
1731 memcpy (p
, raw
, 16);
1736 /* This is an upper YMM register. */
1737 p
= XSAVE_AVXH_ADDR (tdep
, regs
, regnum
);
1738 if (memcmp (raw
, p
, 16))
1740 xstate_bv
|= X86_XSTATE_AVX
;
1741 memcpy (p
, raw
, 16);
1746 if (regnum
< I387_BNDCFGU_REGNUM (tdep
))
1748 regcache
->raw_collect (regnum
, raw
);
1749 p
= XSAVE_MPX_ADDR (tdep
, regs
, regnum
);
1750 if (memcmp (raw
, p
, 16))
1752 xstate_bv
|= X86_XSTATE_BNDREGS
;
1753 memcpy (p
, raw
, 16);
1758 p
= XSAVE_MPX_ADDR (tdep
, regs
, regnum
);
1759 xstate_bv
|= X86_XSTATE_BNDCFG
;
1765 /* This is an SSE register. */
1766 p
= FXSAVE_ADDR (tdep
, regs
, regnum
);
1767 if (memcmp (raw
, p
, 16))
1769 xstate_bv
|= X86_XSTATE_SSE
;
1770 memcpy (p
, raw
, 16);
1775 /* This is an x87 register. */
1776 p
= FXSAVE_ADDR (tdep
, regs
, regnum
);
1777 if (memcmp (raw
, p
, 10))
1779 xstate_bv
|= X86_XSTATE_X87
;
1780 memcpy (p
, raw
, 10);
1784 case x87_ctrl_or_mxcsr
:
1785 /* We only handle MXCSR here. All other x87 control registers
1786 are handled separately below. */
1787 if (regnum
== I387_MXCSR_REGNUM (tdep
))
1789 p
= FXSAVE_MXCSR_ADDR (regs
);
1790 if (memcmp (raw
, p
, 2))
1792 /* We're only setting MXCSR, so check the initial state
1793 to see if either of AVX or SSE are already enabled.
1794 If they are then we'll attribute this changed MXCSR to
1795 that feature. If neither feature is enabled, then
1796 we'll attribute this change to the SSE feature. */
1797 xstate_bv
|= (initial_xstate_bv
1798 & (X86_XSTATE_AVX
| X86_XSTATE_SSE
));
1799 if ((xstate_bv
& (X86_XSTATE_AVX
| X86_XSTATE_SSE
)) == 0)
1800 xstate_bv
|= X86_XSTATE_SSE
;
1807 /* Only handle x87 control registers. */
1808 for (i
= I387_FCTRL_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
1809 if (regnum
== -1 || regnum
== i
)
1811 /* Most of the FPU control registers occupy only 16 bits in
1812 the xsave extended state. Give those a special treatment. */
1813 if (i
!= I387_FIOFF_REGNUM (tdep
)
1814 && i
!= I387_FOOFF_REGNUM (tdep
))
1818 regcache
->raw_collect (i
, buf
);
1820 if (i
== I387_FOP_REGNUM (tdep
))
1822 /* The opcode occupies only 11 bits. Make sure we
1823 don't touch the other bits. */
1824 buf
[1] &= ((1 << 3) - 1);
1825 buf
[1] |= ((FXSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
1827 else if (i
== I387_FTAG_REGNUM (tdep
))
1829 /* Converting back is much easier. */
1831 unsigned short ftag
;
1834 ftag
= (buf
[1] << 8) | buf
[0];
1838 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
1840 int tag
= (ftag
>> (fpreg
* 2)) & 3;
1843 buf
[0] |= (1 << fpreg
);
1846 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1847 if (memcmp (p
, buf
, 2))
1849 xstate_bv
|= X86_XSTATE_X87
;
1857 regcache
->raw_collect (i
, raw
);
1858 regsize
= regcache_register_size (regcache
, i
);
1859 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1860 if (memcmp (raw
, p
, regsize
))
1862 xstate_bv
|= X86_XSTATE_X87
;
1863 memcpy (p
, raw
, regsize
);
1868 /* Update the corresponding bits in `xstate_bv' if any
1869 registers are changed. */
1872 /* The supported bits in `xstat_bv' are 8 bytes. */
1873 initial_xstate_bv
|= xstate_bv
;
1874 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
1880 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1884 i387_tag (const gdb_byte
*raw
)
1887 unsigned int exponent
;
1888 unsigned long fraction
[2];
1890 integer
= raw
[7] & 0x80;
1891 exponent
= (((raw
[9] & 0x7f) << 8) | raw
[8]);
1892 fraction
[0] = ((raw
[3] << 24) | (raw
[2] << 16) | (raw
[1] << 8) | raw
[0]);
1893 fraction
[1] = (((raw
[7] & 0x7f) << 24) | (raw
[6] << 16)
1894 | (raw
[5] << 8) | raw
[4]);
1896 if (exponent
== 0x7fff)
1901 else if (exponent
== 0x0000)
1903 if (fraction
[0] == 0x0000 && fraction
[1] == 0x0000 && !integer
)
1929 /* Prepare the FPU stack in REGCACHE for a function return. */
1932 i387_return_value (struct gdbarch
*gdbarch
, struct regcache
*regcache
)
1934 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1937 /* Set the top of the floating-point register stack to 7. The
1938 actual value doesn't really matter, but 7 is what a normal
1939 function return would end up with if the program started out with
1940 a freshly initialized FPU. */
1941 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1943 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1945 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1946 floating-point register stack to 7, the appropriate value for the
1947 tag word is 0x3fff. */
1948 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
1952 /* See i387-tdep.h. */
1955 i387_reset_bnd_regs (struct gdbarch
*gdbarch
, struct regcache
*regcache
)
1957 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1959 if (I387_BND0R_REGNUM (tdep
) > 0)
1961 gdb_byte bnd_buf
[16];
1963 memset (bnd_buf
, 0, 16);
1964 for (int i
= 0; i
< I387_NUM_BND_REGS
; i
++)
1965 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + i
, bnd_buf
);