1 /* Intel 387 floating point stuff.
3 Copyright (C) 1988-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "floatformat.h"
30 #include "i386-tdep.h"
31 #include "i387-tdep.h"
32 #include "x86-xstate.h"
34 /* Print the floating point number specified by RAW. */
37 print_i387_value (struct gdbarch
*gdbarch
,
38 const gdb_byte
*raw
, struct ui_file
*file
)
42 /* Using extract_typed_floating here might affect the representation
43 of certain numbers such as NaNs, even if GDB is running natively.
44 This is fine since our caller already detects such special
45 numbers and we print the hexadecimal representation anyway. */
46 value
= extract_typed_floating (raw
, i387_ext_type (gdbarch
));
48 /* We try to print 19 digits. The last digit may or may not contain
49 garbage, but we'd better print one too many. We need enough room
50 to print the value, 1 position for the sign, 1 for the decimal
51 point, 19 for the digits and 6 for the exponent adds up to 27. */
52 #ifdef PRINTF_HAS_LONG_DOUBLE
53 fprintf_filtered (file
, " %-+27.19Lg", (long double) value
);
55 fprintf_filtered (file
, " %-+27.19g", (double) value
);
59 /* Print the classification for the register contents RAW. */
62 print_i387_ext (struct gdbarch
*gdbarch
,
63 const gdb_byte
*raw
, struct ui_file
*file
)
67 unsigned int exponent
;
68 unsigned long fraction
[2];
71 integer
= raw
[7] & 0x80;
72 exponent
= (((raw
[9] & 0x7f) << 8) | raw
[8]);
73 fraction
[0] = ((raw
[3] << 24) | (raw
[2] << 16) | (raw
[1] << 8) | raw
[0]);
74 fraction
[1] = (((raw
[7] & 0x7f) << 24) | (raw
[6] << 16)
75 | (raw
[5] << 8) | raw
[4]);
77 if (exponent
== 0x7fff && integer
)
79 if (fraction
[0] == 0x00000000 && fraction
[1] == 0x00000000)
81 fprintf_filtered (file
, " %cInf", (sign
? '-' : '+'));
82 else if (sign
&& fraction
[0] == 0x00000000 && fraction
[1] == 0x40000000)
83 /* Real Indefinite (QNaN). */
84 fputs_unfiltered (" Real Indefinite (QNaN)", file
);
85 else if (fraction
[1] & 0x40000000)
87 fputs_filtered (" QNaN", file
);
90 fputs_filtered (" SNaN", file
);
92 else if (exponent
< 0x7fff && exponent
> 0x0000 && integer
)
94 print_i387_value (gdbarch
, raw
, file
);
95 else if (exponent
== 0x0000)
97 /* Denormal or zero. */
98 print_i387_value (gdbarch
, raw
, file
);
101 /* Pseudo-denormal. */
102 fputs_filtered (" Pseudo-denormal", file
);
103 else if (fraction
[0] || fraction
[1])
105 fputs_filtered (" Denormal", file
);
109 fputs_filtered (" Unsupported", file
);
112 /* Print the status word STATUS. If STATUS_P is false, then STATUS
116 print_i387_status_word (int status_p
,
117 unsigned int status
, struct ui_file
*file
)
119 fprintf_filtered (file
, "Status Word: ");
122 fprintf_filtered (file
, "%s\n", _("<unavailable>"));
126 fprintf_filtered (file
, "%s", hex_string_custom (status
, 4));
127 fputs_filtered (" ", file
);
128 fprintf_filtered (file
, " %s", (status
& 0x0001) ? "IE" : " ");
129 fprintf_filtered (file
, " %s", (status
& 0x0002) ? "DE" : " ");
130 fprintf_filtered (file
, " %s", (status
& 0x0004) ? "ZE" : " ");
131 fprintf_filtered (file
, " %s", (status
& 0x0008) ? "OE" : " ");
132 fprintf_filtered (file
, " %s", (status
& 0x0010) ? "UE" : " ");
133 fprintf_filtered (file
, " %s", (status
& 0x0020) ? "PE" : " ");
134 fputs_filtered (" ", file
);
135 fprintf_filtered (file
, " %s", (status
& 0x0080) ? "ES" : " ");
136 fputs_filtered (" ", file
);
137 fprintf_filtered (file
, " %s", (status
& 0x0040) ? "SF" : " ");
138 fputs_filtered (" ", file
);
139 fprintf_filtered (file
, " %s", (status
& 0x0100) ? "C0" : " ");
140 fprintf_filtered (file
, " %s", (status
& 0x0200) ? "C1" : " ");
141 fprintf_filtered (file
, " %s", (status
& 0x0400) ? "C2" : " ");
142 fprintf_filtered (file
, " %s", (status
& 0x4000) ? "C3" : " ");
144 fputs_filtered ("\n", file
);
146 fprintf_filtered (file
,
147 " TOP: %d\n", ((status
>> 11) & 7));
150 /* Print the control word CONTROL. If CONTROL_P is false, then
151 CONTROL was unavailable. */
154 print_i387_control_word (int control_p
,
155 unsigned int control
, struct ui_file
*file
)
157 fprintf_filtered (file
, "Control Word: ");
160 fprintf_filtered (file
, "%s\n", _("<unavailable>"));
164 fprintf_filtered (file
, "%s", hex_string_custom (control
, 4));
165 fputs_filtered (" ", file
);
166 fprintf_filtered (file
, " %s", (control
& 0x0001) ? "IM" : " ");
167 fprintf_filtered (file
, " %s", (control
& 0x0002) ? "DM" : " ");
168 fprintf_filtered (file
, " %s", (control
& 0x0004) ? "ZM" : " ");
169 fprintf_filtered (file
, " %s", (control
& 0x0008) ? "OM" : " ");
170 fprintf_filtered (file
, " %s", (control
& 0x0010) ? "UM" : " ");
171 fprintf_filtered (file
, " %s", (control
& 0x0020) ? "PM" : " ");
173 fputs_filtered ("\n", file
);
175 fputs_filtered (" PC: ", file
);
176 switch ((control
>> 8) & 3)
179 fputs_filtered ("Single Precision (24-bits)\n", file
);
182 fputs_filtered ("Reserved\n", file
);
185 fputs_filtered ("Double Precision (53-bits)\n", file
);
188 fputs_filtered ("Extended Precision (64-bits)\n", file
);
192 fputs_filtered (" RC: ", file
);
193 switch ((control
>> 10) & 3)
196 fputs_filtered ("Round to nearest\n", file
);
199 fputs_filtered ("Round down\n", file
);
202 fputs_filtered ("Round up\n", file
);
205 fputs_filtered ("Round toward zero\n", file
);
210 /* Print out the i387 floating point state. Note that we ignore FRAME
211 in the code below. That's OK since floating-point registers are
212 never saved on the stack. */
215 i387_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
216 struct frame_info
*frame
, const char *args
)
218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
238 gdb_assert (gdbarch
== get_frame_arch (frame
));
240 fctrl_p
= read_frame_register_unsigned (frame
,
241 I387_FCTRL_REGNUM (tdep
), &fctrl
);
242 fstat_p
= read_frame_register_unsigned (frame
,
243 I387_FSTAT_REGNUM (tdep
), &fstat
);
244 ftag_p
= read_frame_register_unsigned (frame
,
245 I387_FTAG_REGNUM (tdep
), &ftag
);
246 fiseg_p
= read_frame_register_unsigned (frame
,
247 I387_FISEG_REGNUM (tdep
), &fiseg
);
248 fioff_p
= read_frame_register_unsigned (frame
,
249 I387_FIOFF_REGNUM (tdep
), &fioff
);
250 foseg_p
= read_frame_register_unsigned (frame
,
251 I387_FOSEG_REGNUM (tdep
), &foseg
);
252 fooff_p
= read_frame_register_unsigned (frame
,
253 I387_FOOFF_REGNUM (tdep
), &fooff
);
254 fop_p
= read_frame_register_unsigned (frame
,
255 I387_FOP_REGNUM (tdep
), &fop
);
259 top
= ((fstat
>> 11) & 7);
261 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
263 struct value
*regval
;
268 fprintf_filtered (file
, "%sR%d: ", fpreg
== top
? "=>" : " ", fpreg
);
272 tag
= (ftag
>> (fpreg
* 2)) & 3;
277 fputs_filtered ("Valid ", file
);
280 fputs_filtered ("Zero ", file
);
283 fputs_filtered ("Special ", file
);
286 fputs_filtered ("Empty ", file
);
291 fputs_filtered ("Unknown ", file
);
293 regnum
= (fpreg
+ 8 - top
) % 8 + I387_ST0_REGNUM (tdep
);
294 regval
= get_frame_register_value (frame
, regnum
);
296 if (value_entirely_available (regval
))
298 const gdb_byte
*raw
= value_contents (regval
);
300 fputs_filtered ("0x", file
);
301 for (i
= 9; i
>= 0; i
--)
302 fprintf_filtered (file
, "%02x", raw
[i
]);
304 if (tag
!= -1 && tag
!= 3)
305 print_i387_ext (gdbarch
, raw
, file
);
308 fprintf_filtered (file
, "%s", _("<unavailable>"));
310 fputs_filtered ("\n", file
);
314 fputs_filtered ("\n", file
);
315 print_i387_status_word (fstat_p
, fstat
, file
);
316 print_i387_control_word (fctrl_p
, fctrl
, file
);
317 fprintf_filtered (file
, "Tag Word: %s\n",
318 ftag_p
? hex_string_custom (ftag
, 4) : _("<unavailable>"));
319 fprintf_filtered (file
, "Instruction Pointer: %s:",
320 fiseg_p
? hex_string_custom (fiseg
, 2) : _("<unavailable>"));
321 fprintf_filtered (file
, "%s\n",
322 fioff_p
? hex_string_custom (fioff
, 8) : _("<unavailable>"));
323 fprintf_filtered (file
, "Operand Pointer: %s:",
324 foseg_p
? hex_string_custom (foseg
, 2) : _("<unavailable>"));
325 fprintf_filtered (file
, "%s\n",
326 fooff_p
? hex_string_custom (fooff
, 8) : _("<unavailable>"));
327 fprintf_filtered (file
, "Opcode: %s\n",
329 ? (hex_string_custom (fop
? (fop
| 0xd800) : 0, 4))
330 : _("<unavailable>"));
334 /* Return nonzero if a value of type TYPE stored in register REGNUM
335 needs any special handling. */
338 i387_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
341 if (i386_fp_regnum_p (gdbarch
, regnum
))
343 /* Floating point registers must be converted unless we are
344 accessing them in their hardware type. */
345 if (type
== i387_ext_type (gdbarch
))
354 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
355 return its contents in TO. */
358 i387_register_to_value (struct frame_info
*frame
, int regnum
,
359 struct type
*type
, gdb_byte
*to
,
360 int *optimizedp
, int *unavailablep
)
362 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
363 gdb_byte from
[I386_MAX_REGISTER_SIZE
];
365 gdb_assert (i386_fp_regnum_p (gdbarch
, regnum
));
367 /* We only support floating-point values. */
368 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
370 warning (_("Cannot convert floating-point register value "
371 "to non-floating-point type."));
372 *optimizedp
= *unavailablep
= 0;
376 /* Convert to TYPE. */
377 if (!get_frame_register_bytes (frame
, regnum
, 0, TYPE_LENGTH (type
),
378 from
, optimizedp
, unavailablep
))
381 convert_typed_floating (from
, i387_ext_type (gdbarch
), to
, type
);
382 *optimizedp
= *unavailablep
= 0;
386 /* Write the contents FROM of a value of type TYPE into register
387 REGNUM in frame FRAME. */
390 i387_value_to_register (struct frame_info
*frame
, int regnum
,
391 struct type
*type
, const gdb_byte
*from
)
393 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
394 gdb_byte to
[I386_MAX_REGISTER_SIZE
];
396 gdb_assert (i386_fp_regnum_p (gdbarch
, regnum
));
398 /* We only support floating-point values. */
399 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
401 warning (_("Cannot convert non-floating-point type "
402 "to floating-point register value."));
406 /* Convert from TYPE. */
407 convert_typed_floating (from
, type
, to
, i387_ext_type (gdbarch
));
408 put_frame_register (frame
, regnum
, to
);
412 /* Handle FSAVE and FXSAVE formats. */
414 /* At fsave_offset[REGNUM] you'll find the offset to the location in
415 the data structure used by the "fsave" instruction where GDB
416 register REGNUM is stored. */
418 static int fsave_offset
[] =
420 28 + 0 * 10, /* %st(0) ... */
427 28 + 7 * 10, /* ... %st(7). */
428 0, /* `fctrl' (16 bits). */
429 4, /* `fstat' (16 bits). */
430 8, /* `ftag' (16 bits). */
431 16, /* `fiseg' (16 bits). */
433 24, /* `foseg' (16 bits). */
435 18 /* `fop' (bottom 11 bits). */
438 #define FSAVE_ADDR(tdep, fsave, regnum) \
439 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
442 /* Fill register REGNUM in REGCACHE with the appropriate value from
443 *FSAVE. This function masks off any of the reserved bits in
447 i387_supply_fsave (struct regcache
*regcache
, int regnum
, const void *fsave
)
449 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
450 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
451 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
452 const gdb_byte
*regs
= (const gdb_byte
*) fsave
;
455 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
457 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
458 if (regnum
== -1 || regnum
== i
)
462 regcache_raw_supply (regcache
, i
, NULL
);
466 /* Most of the FPU control registers occupy only 16 bits in the
467 fsave area. Give those a special treatment. */
468 if (i
>= I387_FCTRL_REGNUM (tdep
)
469 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
473 memcpy (val
, FSAVE_ADDR (tdep
, regs
, i
), 2);
475 if (i
== I387_FOP_REGNUM (tdep
))
476 val
[1] &= ((1 << 3) - 1);
477 regcache_raw_supply (regcache
, i
, val
);
480 regcache_raw_supply (regcache
, i
, FSAVE_ADDR (tdep
, regs
, i
));
483 /* Provide dummy values for the SSE registers. */
484 for (i
= I387_XMM0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
485 if (regnum
== -1 || regnum
== i
)
486 regcache_raw_supply (regcache
, i
, NULL
);
487 if (regnum
== -1 || regnum
== I387_MXCSR_REGNUM (tdep
))
491 store_unsigned_integer (buf
, 4, byte_order
, 0x1f80);
492 regcache_raw_supply (regcache
, I387_MXCSR_REGNUM (tdep
), buf
);
496 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE
497 with the value from REGCACHE. If REGNUM is -1, do this for all
498 registers. This function doesn't touch any of the reserved bits in
502 i387_collect_fsave (const struct regcache
*regcache
, int regnum
, void *fsave
)
504 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
505 gdb_byte
*regs
= (gdb_byte
*) fsave
;
508 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
510 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
511 if (regnum
== -1 || regnum
== i
)
513 /* Most of the FPU control registers occupy only 16 bits in
514 the fsave area. Give those a special treatment. */
515 if (i
>= I387_FCTRL_REGNUM (tdep
)
516 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
520 regcache_raw_collect (regcache
, i
, buf
);
522 if (i
== I387_FOP_REGNUM (tdep
))
524 /* The opcode occupies only 11 bits. Make sure we
525 don't touch the other bits. */
526 buf
[1] &= ((1 << 3) - 1);
527 buf
[1] |= ((FSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
529 memcpy (FSAVE_ADDR (tdep
, regs
, i
), buf
, 2);
532 regcache_raw_collect (regcache
, i
, FSAVE_ADDR (tdep
, regs
, i
));
537 /* At fxsave_offset[REGNUM] you'll find the offset to the location in
538 the data structure used by the "fxsave" instruction where GDB
539 register REGNUM is stored. */
541 static int fxsave_offset
[] =
543 32, /* %st(0) through ... */
550 144, /* ... %st(7) (80 bits each). */
551 0, /* `fctrl' (16 bits). */
552 2, /* `fstat' (16 bits). */
553 4, /* `ftag' (16 bits). */
554 12, /* `fiseg' (16 bits). */
556 20, /* `foseg' (16 bits). */
558 6, /* `fop' (bottom 11 bits). */
559 160 + 0 * 16, /* %xmm0 through ... */
574 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
577 #define FXSAVE_ADDR(tdep, fxsave, regnum) \
578 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
580 /* We made an unfortunate choice in putting %mxcsr after the SSE
581 registers %xmm0-%xmm7 instead of before, since it makes supporting
582 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
583 don't include the offset for %mxcsr here above. */
585 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
587 static int i387_tag (const gdb_byte
*raw
);
590 /* Fill register REGNUM in REGCACHE with the appropriate
591 floating-point or SSE register value from *FXSAVE. This function
592 masks off any of the reserved bits in *FXSAVE. */
595 i387_supply_fxsave (struct regcache
*regcache
, int regnum
, const void *fxsave
)
597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
598 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
601 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
602 gdb_assert (tdep
->num_xmm_regs
> 0);
604 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
605 if (regnum
== -1 || regnum
== i
)
609 regcache_raw_supply (regcache
, i
, NULL
);
613 /* Most of the FPU control registers occupy only 16 bits in
614 the fxsave area. Give those a special treatment. */
615 if (i
>= I387_FCTRL_REGNUM (tdep
) && i
< I387_XMM0_REGNUM (tdep
)
616 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
620 memcpy (val
, FXSAVE_ADDR (tdep
, regs
, i
), 2);
622 if (i
== I387_FOP_REGNUM (tdep
))
623 val
[1] &= ((1 << 3) - 1);
624 else if (i
== I387_FTAG_REGNUM (tdep
))
626 /* The fxsave area contains a simplified version of
627 the tag word. We have to look at the actual 80-bit
628 FP data to recreate the traditional i387 tag word. */
630 unsigned long ftag
= 0;
634 top
= ((FXSAVE_ADDR (tdep
, regs
,
635 I387_FSTAT_REGNUM (tdep
)))[1] >> 3);
638 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
642 if (val
[0] & (1 << fpreg
))
644 int thisreg
= (fpreg
+ 8 - top
) % 8
645 + I387_ST0_REGNUM (tdep
);
646 tag
= i387_tag (FXSAVE_ADDR (tdep
, regs
, thisreg
));
651 ftag
|= tag
<< (2 * fpreg
);
653 val
[0] = ftag
& 0xff;
654 val
[1] = (ftag
>> 8) & 0xff;
656 regcache_raw_supply (regcache
, i
, val
);
659 regcache_raw_supply (regcache
, i
, FXSAVE_ADDR (tdep
, regs
, i
));
662 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
665 regcache_raw_supply (regcache
, I387_MXCSR_REGNUM (tdep
), NULL
);
667 regcache_raw_supply (regcache
, I387_MXCSR_REGNUM (tdep
),
668 FXSAVE_MXCSR_ADDR (regs
));
672 /* Fill register REGNUM (if it is a floating-point or SSE register) in
673 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
674 all registers. This function doesn't touch any of the reserved
678 i387_collect_fxsave (const struct regcache
*regcache
, int regnum
, void *fxsave
)
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
681 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
684 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
685 gdb_assert (tdep
->num_xmm_regs
> 0);
687 for (i
= I387_ST0_REGNUM (tdep
); i
< I387_MXCSR_REGNUM (tdep
); i
++)
688 if (regnum
== -1 || regnum
== i
)
690 /* Most of the FPU control registers occupy only 16 bits in
691 the fxsave area. Give those a special treatment. */
692 if (i
>= I387_FCTRL_REGNUM (tdep
) && i
< I387_XMM0_REGNUM (tdep
)
693 && i
!= I387_FIOFF_REGNUM (tdep
) && i
!= I387_FOOFF_REGNUM (tdep
))
697 regcache_raw_collect (regcache
, i
, buf
);
699 if (i
== I387_FOP_REGNUM (tdep
))
701 /* The opcode occupies only 11 bits. Make sure we
702 don't touch the other bits. */
703 buf
[1] &= ((1 << 3) - 1);
704 buf
[1] |= ((FXSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
706 else if (i
== I387_FTAG_REGNUM (tdep
))
708 /* Converting back is much easier. */
713 ftag
= (buf
[1] << 8) | buf
[0];
717 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
719 int tag
= (ftag
>> (fpreg
* 2)) & 3;
722 buf
[0] |= (1 << fpreg
);
725 memcpy (FXSAVE_ADDR (tdep
, regs
, i
), buf
, 2);
728 regcache_raw_collect (regcache
, i
, FXSAVE_ADDR (tdep
, regs
, i
));
731 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
732 regcache_raw_collect (regcache
, I387_MXCSR_REGNUM (tdep
),
733 FXSAVE_MXCSR_ADDR (regs
));
736 /* `xstate_bv' is at byte offset 512. */
737 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
739 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
740 the upper 128bit of AVX register data structure used by the "xsave"
741 instruction where GDB register REGNUM is stored. */
743 static int xsave_avxh_offset
[] =
745 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
760 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
763 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
764 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
766 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in
767 the upper 128bit of ZMM register data structure used by the "xsave"
768 instruction where GDB register REGNUM is stored. */
770 static int xsave_ymm_avx512_offset
[] =
772 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */
773 1664 + 16 + 0 * 64, /* %ymm16 through... */
788 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */
791 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \
792 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)])
794 static int xsave_xmm_avx512_offset
[] =
796 1664 + 0 * 64, /* %ymm16 through... */
811 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */
814 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \
815 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)])
817 static int xsave_mpx_offset
[] = {
818 960 + 0 * 16, /* bnd0r...bnd3r registers. */
822 1024 + 0 * 8, /* bndcfg ... bndstatus. */
826 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \
827 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)])
829 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location
830 of the AVX512 opmask register data structure used by the "xsave"
831 instruction where GDB register REGNUM is stored. */
833 static int xsave_avx512_k_offset
[] =
835 1088 + 0 * 8, /* %k0 through... */
842 1088 + 7 * 8 /* %k7 (64 bits each). */
845 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \
846 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)])
848 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in
849 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave"
850 instruction where GDB register REGNUM is stored. */
852 static int xsave_avx512_zmm_h_offset
[] =
855 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */
869 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */
870 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */
885 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */
888 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \
889 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)])
891 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */
894 i387_supply_xsave (struct regcache
*regcache
, int regnum
,
897 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
898 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
899 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
902 static const gdb_byte zero
[MAX_REGISTER_SIZE
] = { 0 };
912 avx512_ymmh_avx512
= 0x40,
913 avx512_xmm_avx512
= 0x80,
914 all
= x87
| sse
| avxh
| mpx
| avx512_k
| avx512_zmm_h
915 | avx512_ymmh_avx512
| avx512_xmm_avx512
918 gdb_assert (regs
!= NULL
);
919 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
920 gdb_assert (tdep
->num_xmm_regs
> 0);
924 else if (regnum
>= I387_ZMM0H_REGNUM (tdep
)
925 && regnum
< I387_ZMMENDH_REGNUM (tdep
))
926 regclass
= avx512_zmm_h
;
927 else if (regnum
>= I387_K0_REGNUM (tdep
)
928 && regnum
< I387_KEND_REGNUM (tdep
))
930 else if (regnum
>= I387_YMM16H_REGNUM (tdep
)
931 && regnum
< I387_YMMH_AVX512_END_REGNUM (tdep
))
932 regclass
= avx512_ymmh_avx512
;
933 else if (regnum
>= I387_XMM16_REGNUM (tdep
)
934 && regnum
< I387_XMM_AVX512_END_REGNUM (tdep
))
935 regclass
= avx512_xmm_avx512
;
936 else if (regnum
>= I387_YMM0H_REGNUM (tdep
)
937 && regnum
< I387_YMMENDH_REGNUM (tdep
))
939 else if (regnum
>= I387_BND0R_REGNUM (tdep
)
940 && regnum
< I387_MPXEND_REGNUM (tdep
))
942 else if (regnum
>= I387_XMM0_REGNUM (tdep
)
943 && regnum
< I387_MXCSR_REGNUM (tdep
))
945 else if (regnum
>= I387_ST0_REGNUM (tdep
)
946 && regnum
< I387_FCTRL_REGNUM (tdep
))
951 if (regclass
!= none
)
953 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */
954 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
955 ULONGEST xstate_bv
= 0;
957 xstate_bv
= extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
960 /* Clear part in vector registers if its bit in xstat_bv is zero. */
961 clear_bv
= (~(xstate_bv
)) & tdep
->xcr0
;
964 clear_bv
= X86_XSTATE_ALL_MASK
;
966 /* With the delayed xsave mechanism, in between the program
967 starting, and the program accessing the vector registers for the
968 first time, the register's values are invalid. The kernel
969 initializes register states to zero when they are set the first
970 time in a program. This means that from the user-space programs'
971 perspective, it's the same as if the registers have always been
972 zero from the start of the program. Therefore, the debugger
973 should provide the same illusion to the user. */
981 if ((clear_bv
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
982 regcache_raw_supply (regcache
, regnum
, zero
);
984 regcache_raw_supply (regcache
, regnum
,
985 XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, regnum
));
989 if ((clear_bv
& X86_XSTATE_K
))
990 regcache_raw_supply (regcache
, regnum
, zero
);
992 regcache_raw_supply (regcache
, regnum
,
993 XSAVE_AVX512_K_ADDR (tdep
, regs
, regnum
));
996 case avx512_ymmh_avx512
:
997 if ((clear_bv
& X86_XSTATE_ZMM
))
998 regcache_raw_supply (regcache
, regnum
, zero
);
1000 regcache_raw_supply (regcache
, regnum
,
1001 XSAVE_YMM_AVX512_ADDR (tdep
, regs
, regnum
));
1004 case avx512_xmm_avx512
:
1005 if ((clear_bv
& X86_XSTATE_ZMM
))
1006 regcache_raw_supply (regcache
, regnum
, zero
);
1008 regcache_raw_supply (regcache
, regnum
,
1009 XSAVE_XMM_AVX512_ADDR (tdep
, regs
, regnum
));
1013 if ((clear_bv
& X86_XSTATE_AVX
))
1014 regcache_raw_supply (regcache
, regnum
, zero
);
1016 regcache_raw_supply (regcache
, regnum
,
1017 XSAVE_AVXH_ADDR (tdep
, regs
, regnum
));
1021 if ((clear_bv
& X86_XSTATE_BNDREGS
))
1022 regcache_raw_supply (regcache
, regnum
, zero
);
1024 regcache_raw_supply (regcache
, regnum
,
1025 XSAVE_MPX_ADDR (tdep
, regs
, regnum
));
1029 if ((clear_bv
& X86_XSTATE_SSE
))
1030 regcache_raw_supply (regcache
, regnum
, zero
);
1032 regcache_raw_supply (regcache
, regnum
,
1033 FXSAVE_ADDR (tdep
, regs
, regnum
));
1037 if ((clear_bv
& X86_XSTATE_X87
))
1038 regcache_raw_supply (regcache
, regnum
, zero
);
1040 regcache_raw_supply (regcache
, regnum
,
1041 FXSAVE_ADDR (tdep
, regs
, regnum
));
1045 /* Handle the upper ZMM registers. */
1046 if ((tdep
->xcr0
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
1048 if ((clear_bv
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
1050 for (i
= I387_ZMM0H_REGNUM (tdep
);
1051 i
< I387_ZMMENDH_REGNUM (tdep
);
1053 regcache_raw_supply (regcache
, i
, zero
);
1057 for (i
= I387_ZMM0H_REGNUM (tdep
);
1058 i
< I387_ZMMENDH_REGNUM (tdep
);
1060 regcache_raw_supply (regcache
, i
,
1061 XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
));
1065 /* Handle AVX512 OpMask registers. */
1066 if ((tdep
->xcr0
& X86_XSTATE_K
))
1068 if ((clear_bv
& X86_XSTATE_K
))
1070 for (i
= I387_K0_REGNUM (tdep
);
1071 i
< I387_KEND_REGNUM (tdep
);
1073 regcache_raw_supply (regcache
, i
, zero
);
1077 for (i
= I387_K0_REGNUM (tdep
);
1078 i
< I387_KEND_REGNUM (tdep
);
1080 regcache_raw_supply (regcache
, i
,
1081 XSAVE_AVX512_K_ADDR (tdep
, regs
, i
));
1085 /* Handle the YMM_AVX512 registers. */
1086 if ((tdep
->xcr0
& X86_XSTATE_ZMM
))
1088 if ((clear_bv
& X86_XSTATE_ZMM
))
1090 for (i
= I387_YMM16H_REGNUM (tdep
);
1091 i
< I387_YMMH_AVX512_END_REGNUM (tdep
);
1093 regcache_raw_supply (regcache
, i
, zero
);
1094 for (i
= I387_XMM16_REGNUM (tdep
);
1095 i
< I387_XMM_AVX512_END_REGNUM (tdep
);
1097 regcache_raw_supply (regcache
, i
, zero
);
1101 for (i
= I387_YMM16H_REGNUM (tdep
);
1102 i
< I387_YMMH_AVX512_END_REGNUM (tdep
);
1104 regcache_raw_supply (regcache
, i
,
1105 XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
));
1106 for (i
= I387_XMM16_REGNUM (tdep
);
1107 i
< I387_XMM_AVX512_END_REGNUM (tdep
);
1109 regcache_raw_supply (regcache
, i
,
1110 XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
));
1113 /* Handle the upper YMM registers. */
1114 if ((tdep
->xcr0
& X86_XSTATE_AVX
))
1116 if ((clear_bv
& X86_XSTATE_AVX
))
1118 for (i
= I387_YMM0H_REGNUM (tdep
);
1119 i
< I387_YMMENDH_REGNUM (tdep
);
1121 regcache_raw_supply (regcache
, i
, zero
);
1125 for (i
= I387_YMM0H_REGNUM (tdep
);
1126 i
< I387_YMMENDH_REGNUM (tdep
);
1128 regcache_raw_supply (regcache
, i
,
1129 XSAVE_AVXH_ADDR (tdep
, regs
, i
));
1133 /* Handle the MPX registers. */
1134 if ((tdep
->xcr0
& X86_XSTATE_BNDREGS
))
1136 if (clear_bv
& X86_XSTATE_BNDREGS
)
1138 for (i
= I387_BND0R_REGNUM (tdep
);
1139 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1140 regcache_raw_supply (regcache
, i
, zero
);
1144 for (i
= I387_BND0R_REGNUM (tdep
);
1145 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1146 regcache_raw_supply (regcache
, i
,
1147 XSAVE_MPX_ADDR (tdep
, regs
, i
));
1151 /* Handle the MPX registers. */
1152 if ((tdep
->xcr0
& X86_XSTATE_BNDCFG
))
1154 if (clear_bv
& X86_XSTATE_BNDCFG
)
1156 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1157 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1158 regcache_raw_supply (regcache
, i
, zero
);
1162 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1163 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1164 regcache_raw_supply (regcache
, i
,
1165 XSAVE_MPX_ADDR (tdep
, regs
, i
));
1169 /* Handle the XMM registers. */
1170 if ((tdep
->xcr0
& X86_XSTATE_SSE
))
1172 if ((clear_bv
& X86_XSTATE_SSE
))
1174 for (i
= I387_XMM0_REGNUM (tdep
);
1175 i
< I387_MXCSR_REGNUM (tdep
);
1177 regcache_raw_supply (regcache
, i
, zero
);
1181 for (i
= I387_XMM0_REGNUM (tdep
);
1182 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1183 regcache_raw_supply (regcache
, i
,
1184 FXSAVE_ADDR (tdep
, regs
, i
));
1188 /* Handle the x87 registers. */
1189 if ((tdep
->xcr0
& X86_XSTATE_X87
))
1191 if ((clear_bv
& X86_XSTATE_X87
))
1193 for (i
= I387_ST0_REGNUM (tdep
);
1194 i
< I387_FCTRL_REGNUM (tdep
);
1196 regcache_raw_supply (regcache
, i
, zero
);
1200 for (i
= I387_ST0_REGNUM (tdep
);
1201 i
< I387_FCTRL_REGNUM (tdep
);
1203 regcache_raw_supply (regcache
, i
, FXSAVE_ADDR (tdep
, regs
, i
));
1209 /* Only handle x87 control registers. */
1210 for (i
= I387_FCTRL_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
1211 if (regnum
== -1 || regnum
== i
)
1213 /* Most of the FPU control registers occupy only 16 bits in
1214 the xsave extended state. Give those a special treatment. */
1215 if (i
!= I387_FIOFF_REGNUM (tdep
)
1216 && i
!= I387_FOOFF_REGNUM (tdep
))
1220 memcpy (val
, FXSAVE_ADDR (tdep
, regs
, i
), 2);
1221 val
[2] = val
[3] = 0;
1222 if (i
== I387_FOP_REGNUM (tdep
))
1223 val
[1] &= ((1 << 3) - 1);
1224 else if (i
== I387_FTAG_REGNUM (tdep
))
1226 /* The fxsave area contains a simplified version of
1227 the tag word. We have to look at the actual 80-bit
1228 FP data to recreate the traditional i387 tag word. */
1230 unsigned long ftag
= 0;
1234 top
= ((FXSAVE_ADDR (tdep
, regs
,
1235 I387_FSTAT_REGNUM (tdep
)))[1] >> 3);
1238 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
1242 if (val
[0] & (1 << fpreg
))
1244 int thisreg
= (fpreg
+ 8 - top
) % 8
1245 + I387_ST0_REGNUM (tdep
);
1246 tag
= i387_tag (FXSAVE_ADDR (tdep
, regs
, thisreg
));
1249 tag
= 3; /* Empty */
1251 ftag
|= tag
<< (2 * fpreg
);
1253 val
[0] = ftag
& 0xff;
1254 val
[1] = (ftag
>> 8) & 0xff;
1256 regcache_raw_supply (regcache
, i
, val
);
1259 regcache_raw_supply (regcache
, i
, FXSAVE_ADDR (tdep
, regs
, i
));
1262 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
1263 regcache_raw_supply (regcache
, I387_MXCSR_REGNUM (tdep
),
1264 FXSAVE_MXCSR_ADDR (regs
));
1267 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */
1270 i387_collect_xsave (const struct regcache
*regcache
, int regnum
,
1271 void *xsave
, int gcore
)
1273 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1275 gdb_byte
*regs
= (gdb_byte
*) xsave
;
1285 avx512_k
= 0x20 | check
,
1286 avx512_zmm_h
= 0x40 | check
,
1287 avx512_ymmh_avx512
= 0x80 | check
,
1288 avx512_xmm_avx512
= 0x100 | check
,
1289 all
= x87
| sse
| avxh
| mpx
| avx512_k
| avx512_zmm_h
1290 | avx512_ymmh_avx512
| avx512_xmm_avx512
1293 gdb_assert (tdep
->st0_regnum
>= I386_ST0_REGNUM
);
1294 gdb_assert (tdep
->num_xmm_regs
> 0);
1298 else if (regnum
>= I387_ZMM0H_REGNUM (tdep
)
1299 && regnum
< I387_ZMMENDH_REGNUM (tdep
))
1300 regclass
= avx512_zmm_h
;
1301 else if (regnum
>= I387_K0_REGNUM (tdep
)
1302 && regnum
< I387_KEND_REGNUM (tdep
))
1303 regclass
= avx512_k
;
1304 else if (regnum
>= I387_YMM16H_REGNUM (tdep
)
1305 && regnum
< I387_YMMH_AVX512_END_REGNUM (tdep
))
1306 regclass
= avx512_ymmh_avx512
;
1307 else if (regnum
>= I387_XMM16_REGNUM (tdep
)
1308 && regnum
< I387_XMM_AVX512_END_REGNUM (tdep
))
1309 regclass
= avx512_xmm_avx512
;
1310 else if (regnum
>= I387_YMM0H_REGNUM (tdep
)
1311 && regnum
< I387_YMMENDH_REGNUM (tdep
))
1313 else if (regnum
>= I387_BND0R_REGNUM (tdep
)
1314 && regnum
< I387_MPXEND_REGNUM (tdep
))
1316 else if (regnum
>= I387_XMM0_REGNUM (tdep
)
1317 && regnum
< I387_MXCSR_REGNUM (tdep
))
1319 else if (regnum
>= I387_ST0_REGNUM (tdep
)
1320 && regnum
< I387_FCTRL_REGNUM (tdep
))
1327 /* Clear XSAVE extended state. */
1328 memset (regs
, 0, X86_XSTATE_SIZE (tdep
->xcr0
));
1330 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1331 if (tdep
->xsave_xcr0_offset
!= -1)
1332 memcpy (regs
+ tdep
->xsave_xcr0_offset
, &tdep
->xcr0
, 8);
1333 memcpy (XSAVE_XSTATE_BV_ADDR (regs
), &tdep
->xcr0
, 8);
1336 if ((regclass
& check
))
1338 gdb_byte raw
[I386_MAX_REGISTER_SIZE
];
1339 ULONGEST initial_xstate_bv
, clear_bv
, xstate_bv
= 0;
1341 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1343 /* The supported bits in `xstat_bv' are 8 bytes. */
1344 initial_xstate_bv
= extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
1346 clear_bv
= (~(initial_xstate_bv
)) & tdep
->xcr0
;
1348 /* Clear register set if its bit in xstat_bv is zero. */
1351 if ((clear_bv
& X86_XSTATE_BNDREGS
))
1352 for (i
= I387_BND0R_REGNUM (tdep
);
1353 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1354 memset (XSAVE_MPX_ADDR (tdep
, regs
, i
), 0, 16);
1356 if ((clear_bv
& X86_XSTATE_BNDCFG
))
1357 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1358 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1359 memset (XSAVE_MPX_ADDR (tdep
, regs
, i
), 0, 8);
1361 if ((clear_bv
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
1362 for (i
= I387_ZMM0H_REGNUM (tdep
);
1363 i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1364 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
), 0, 32);
1366 if ((clear_bv
& X86_XSTATE_K
))
1367 for (i
= I387_K0_REGNUM (tdep
);
1368 i
< I387_KEND_REGNUM (tdep
); i
++)
1369 memset (XSAVE_AVX512_K_ADDR (tdep
, regs
, i
), 0, 8);
1371 if ((clear_bv
& X86_XSTATE_ZMM
))
1373 for (i
= I387_YMM16H_REGNUM (tdep
);
1374 i
< I387_YMMH_AVX512_END_REGNUM (tdep
); i
++)
1375 memset (XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
), 0, 16);
1376 for (i
= I387_XMM16_REGNUM (tdep
);
1377 i
< I387_XMM_AVX512_END_REGNUM (tdep
); i
++)
1378 memset (XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
), 0, 16);
1381 if ((clear_bv
& X86_XSTATE_AVX
))
1382 for (i
= I387_YMM0H_REGNUM (tdep
);
1383 i
< I387_YMMENDH_REGNUM (tdep
); i
++)
1384 memset (XSAVE_AVXH_ADDR (tdep
, regs
, i
), 0, 16);
1386 if ((clear_bv
& X86_XSTATE_SSE
))
1387 for (i
= I387_XMM0_REGNUM (tdep
);
1388 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1389 memset (FXSAVE_ADDR (tdep
, regs
, i
), 0, 16);
1391 if ((clear_bv
& X86_XSTATE_X87
))
1392 for (i
= I387_ST0_REGNUM (tdep
);
1393 i
< I387_FCTRL_REGNUM (tdep
); i
++)
1394 memset (FXSAVE_ADDR (tdep
, regs
, i
), 0, 10);
1397 if (regclass
== all
)
1399 /* Check if any ZMMH registers are changed. */
1400 if ((tdep
->xcr0
& (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
)))
1401 for (i
= I387_ZMM0H_REGNUM (tdep
);
1402 i
< I387_ZMMENDH_REGNUM (tdep
); i
++)
1404 regcache_raw_collect (regcache
, i
, raw
);
1405 p
= XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, i
);
1406 if (memcmp (raw
, p
, 32) != 0)
1408 xstate_bv
|= (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
);
1409 memcpy (p
, raw
, 32);
1413 /* Check if any K registers are changed. */
1414 if ((tdep
->xcr0
& X86_XSTATE_K
))
1415 for (i
= I387_K0_REGNUM (tdep
);
1416 i
< I387_KEND_REGNUM (tdep
); i
++)
1418 regcache_raw_collect (regcache
, i
, raw
);
1419 p
= XSAVE_AVX512_K_ADDR (tdep
, regs
, i
);
1420 if (memcmp (raw
, p
, 8) != 0)
1422 xstate_bv
|= X86_XSTATE_K
;
1427 /* Check if any XMM or upper YMM registers are changed. */
1428 if ((tdep
->xcr0
& X86_XSTATE_ZMM
))
1430 for (i
= I387_YMM16H_REGNUM (tdep
);
1431 i
< I387_YMMH_AVX512_END_REGNUM (tdep
); i
++)
1433 regcache_raw_collect (regcache
, i
, raw
);
1434 p
= XSAVE_YMM_AVX512_ADDR (tdep
, regs
, i
);
1435 if (memcmp (raw
, p
, 16) != 0)
1437 xstate_bv
|= X86_XSTATE_ZMM
;
1438 memcpy (p
, raw
, 16);
1441 for (i
= I387_XMM16_REGNUM (tdep
);
1442 i
< I387_XMM_AVX512_END_REGNUM (tdep
); i
++)
1444 regcache_raw_collect (regcache
, i
, raw
);
1445 p
= XSAVE_XMM_AVX512_ADDR (tdep
, regs
, i
);
1446 if (memcmp (raw
, p
, 16) != 0)
1448 xstate_bv
|= X86_XSTATE_ZMM
;
1449 memcpy (p
, raw
, 16);
1454 /* Check if any upper YMM registers are changed. */
1455 if ((tdep
->xcr0
& X86_XSTATE_AVX
))
1456 for (i
= I387_YMM0H_REGNUM (tdep
);
1457 i
< I387_YMMENDH_REGNUM (tdep
); i
++)
1459 regcache_raw_collect (regcache
, i
, raw
);
1460 p
= XSAVE_AVXH_ADDR (tdep
, regs
, i
);
1461 if (memcmp (raw
, p
, 16))
1463 xstate_bv
|= X86_XSTATE_AVX
;
1464 memcpy (p
, raw
, 16);
1467 /* Check if any upper MPX registers are changed. */
1468 if ((tdep
->xcr0
& X86_XSTATE_BNDREGS
))
1469 for (i
= I387_BND0R_REGNUM (tdep
);
1470 i
< I387_BNDCFGU_REGNUM (tdep
); i
++)
1472 regcache_raw_collect (regcache
, i
, raw
);
1473 p
= XSAVE_MPX_ADDR (tdep
, regs
, i
);
1474 if (memcmp (raw
, p
, 16))
1476 xstate_bv
|= X86_XSTATE_BNDREGS
;
1477 memcpy (p
, raw
, 16);
1481 /* Check if any upper MPX registers are changed. */
1482 if ((tdep
->xcr0
& X86_XSTATE_BNDCFG
))
1483 for (i
= I387_BNDCFGU_REGNUM (tdep
);
1484 i
< I387_MPXEND_REGNUM (tdep
); i
++)
1486 regcache_raw_collect (regcache
, i
, raw
);
1487 p
= XSAVE_MPX_ADDR (tdep
, regs
, i
);
1488 if (memcmp (raw
, p
, 8))
1490 xstate_bv
|= X86_XSTATE_BNDCFG
;
1495 /* Check if any SSE registers are changed. */
1496 if ((tdep
->xcr0
& X86_XSTATE_SSE
))
1497 for (i
= I387_XMM0_REGNUM (tdep
);
1498 i
< I387_MXCSR_REGNUM (tdep
); i
++)
1500 regcache_raw_collect (regcache
, i
, raw
);
1501 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1502 if (memcmp (raw
, p
, 16))
1504 xstate_bv
|= X86_XSTATE_SSE
;
1505 memcpy (p
, raw
, 16);
1509 /* Check if any X87 registers are changed. */
1510 if ((tdep
->xcr0
& X86_XSTATE_X87
))
1511 for (i
= I387_ST0_REGNUM (tdep
);
1512 i
< I387_FCTRL_REGNUM (tdep
); i
++)
1514 regcache_raw_collect (regcache
, i
, raw
);
1515 p
= FXSAVE_ADDR (tdep
, regs
, i
);
1516 if (memcmp (raw
, p
, 10))
1518 xstate_bv
|= X86_XSTATE_X87
;
1519 memcpy (p
, raw
, 10);
1525 /* Check if REGNUM is changed. */
1526 regcache_raw_collect (regcache
, regnum
, raw
);
1531 internal_error (__FILE__
, __LINE__
,
1532 _("invalid i387 regclass"));
1535 /* This is a ZMM register. */
1536 p
= XSAVE_AVX512_ZMM_H_ADDR (tdep
, regs
, regnum
);
1537 if (memcmp (raw
, p
, 32) != 0)
1539 xstate_bv
|= (X86_XSTATE_ZMM_H
| X86_XSTATE_ZMM
);
1540 memcpy (p
, raw
, 32);
1544 /* This is a AVX512 mask register. */
1545 p
= XSAVE_AVX512_K_ADDR (tdep
, regs
, regnum
);
1546 if (memcmp (raw
, p
, 8) != 0)
1548 xstate_bv
|= X86_XSTATE_K
;
1553 case avx512_ymmh_avx512
:
1554 /* This is an upper YMM16-31 register. */
1555 p
= XSAVE_YMM_AVX512_ADDR (tdep
, regs
, regnum
);
1556 if (memcmp (raw
, p
, 16) != 0)
1558 xstate_bv
|= X86_XSTATE_ZMM
;
1559 memcpy (p
, raw
, 16);
1563 case avx512_xmm_avx512
:
1564 /* This is an upper XMM16-31 register. */
1565 p
= XSAVE_XMM_AVX512_ADDR (tdep
, regs
, regnum
);
1566 if (memcmp (raw
, p
, 16) != 0)
1568 xstate_bv
|= X86_XSTATE_ZMM
;
1569 memcpy (p
, raw
, 16);
1574 /* This is an upper YMM register. */
1575 p
= XSAVE_AVXH_ADDR (tdep
, regs
, regnum
);
1576 if (memcmp (raw
, p
, 16))
1578 xstate_bv
|= X86_XSTATE_AVX
;
1579 memcpy (p
, raw
, 16);
1584 if (regnum
< I387_BNDCFGU_REGNUM (tdep
))
1586 regcache_raw_collect (regcache
, regnum
, raw
);
1587 p
= XSAVE_MPX_ADDR (tdep
, regs
, regnum
);
1588 if (memcmp (raw
, p
, 16))
1590 xstate_bv
|= X86_XSTATE_BNDREGS
;
1591 memcpy (p
, raw
, 16);
1596 p
= XSAVE_MPX_ADDR (tdep
, regs
, regnum
);
1597 xstate_bv
|= X86_XSTATE_BNDCFG
;
1603 /* This is an SSE register. */
1604 p
= FXSAVE_ADDR (tdep
, regs
, regnum
);
1605 if (memcmp (raw
, p
, 16))
1607 xstate_bv
|= X86_XSTATE_SSE
;
1608 memcpy (p
, raw
, 16);
1613 /* This is an x87 register. */
1614 p
= FXSAVE_ADDR (tdep
, regs
, regnum
);
1615 if (memcmp (raw
, p
, 10))
1617 xstate_bv
|= X86_XSTATE_X87
;
1618 memcpy (p
, raw
, 10);
1624 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1625 registers are changed. */
1628 /* The supported bits in `xstat_bv' are 8 bytes. */
1629 initial_xstate_bv
|= xstate_bv
;
1630 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs
),
1637 internal_error (__FILE__
, __LINE__
,
1638 _("invalid i387 regclass"));
1649 case avx512_ymmh_avx512
:
1650 case avx512_xmm_avx512
:
1651 /* Register REGNUM has been updated. Return. */
1657 /* Return if REGNUM isn't changed. */
1658 if (regclass
!= all
)
1663 /* Only handle x87 control registers. */
1664 for (i
= I387_FCTRL_REGNUM (tdep
); i
< I387_XMM0_REGNUM (tdep
); i
++)
1665 if (regnum
== -1 || regnum
== i
)
1667 /* Most of the FPU control registers occupy only 16 bits in
1668 the xsave extended state. Give those a special treatment. */
1669 if (i
!= I387_FIOFF_REGNUM (tdep
)
1670 && i
!= I387_FOOFF_REGNUM (tdep
))
1674 regcache_raw_collect (regcache
, i
, buf
);
1676 if (i
== I387_FOP_REGNUM (tdep
))
1678 /* The opcode occupies only 11 bits. Make sure we
1679 don't touch the other bits. */
1680 buf
[1] &= ((1 << 3) - 1);
1681 buf
[1] |= ((FXSAVE_ADDR (tdep
, regs
, i
))[1] & ~((1 << 3) - 1));
1683 else if (i
== I387_FTAG_REGNUM (tdep
))
1685 /* Converting back is much easier. */
1687 unsigned short ftag
;
1690 ftag
= (buf
[1] << 8) | buf
[0];
1694 for (fpreg
= 7; fpreg
>= 0; fpreg
--)
1696 int tag
= (ftag
>> (fpreg
* 2)) & 3;
1699 buf
[0] |= (1 << fpreg
);
1702 memcpy (FXSAVE_ADDR (tdep
, regs
, i
), buf
, 2);
1705 regcache_raw_collect (regcache
, i
, FXSAVE_ADDR (tdep
, regs
, i
));
1708 if (regnum
== I387_MXCSR_REGNUM (tdep
) || regnum
== -1)
1709 regcache_raw_collect (regcache
, I387_MXCSR_REGNUM (tdep
),
1710 FXSAVE_MXCSR_ADDR (regs
));
1713 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1717 i387_tag (const gdb_byte
*raw
)
1720 unsigned int exponent
;
1721 unsigned long fraction
[2];
1723 integer
= raw
[7] & 0x80;
1724 exponent
= (((raw
[9] & 0x7f) << 8) | raw
[8]);
1725 fraction
[0] = ((raw
[3] << 24) | (raw
[2] << 16) | (raw
[1] << 8) | raw
[0]);
1726 fraction
[1] = (((raw
[7] & 0x7f) << 24) | (raw
[6] << 16)
1727 | (raw
[5] << 8) | raw
[4]);
1729 if (exponent
== 0x7fff)
1734 else if (exponent
== 0x0000)
1736 if (fraction
[0] == 0x0000 && fraction
[1] == 0x0000 && !integer
)
1762 /* Prepare the FPU stack in REGCACHE for a function return. */
1765 i387_return_value (struct gdbarch
*gdbarch
, struct regcache
*regcache
)
1767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1770 /* Set the top of the floating-point register stack to 7. The
1771 actual value doesn't really matter, but 7 is what a normal
1772 function return would end up with if the program started out with
1773 a freshly initialized FPU. */
1774 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
1776 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
1778 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1779 floating-point register stack to 7, the appropriate value for the
1780 tag word is 0x3fff. */
1781 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);