1 /* Disassemble i80960 instructions.
10 extern char *reg_names
[];
12 static FILE *stream
; /* Output goes here */
13 static void print_addr();
21 static void invalid();
23 static void put_abs();
26 /* Print the i960 instruction at address 'memaddr' in debugged memory,
27 on stream 's'. Returns length of the instruction, in bytes. */
29 print_insn( memaddr
, s
)
33 unsigned int word1
, word2
;
36 word1
= read_memory_integer( memaddr
, 4 );
37 word2
= read_memory_integer( memaddr
+4, 4 );
38 return pinsn( memaddr
, word1
, word2
);
42 /* Read the i960 instruction at 'memaddr' and return the address of
43 the next instruction after that, or 0 if 'memaddr' is not the
44 address of a valid instruction. The first word of the instruction
45 is stored at 'pword1', and the second word, if any, is stored at
49 next_insn (memaddr
, pword1
, pword2
)
50 unsigned long *pword1
, *pword2
;
56 /* Read the two (potential) words of the instruction at once,
57 to eliminate the overhead of two calls to read_memory ().
58 TODO: read more instructions at once and cache them. */
60 read_memory (memaddr
, buf
, sizeof (buf
));
62 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
64 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
66 /* Divide instruction set into classes based on high 4 bits of opcode*/
68 switch ((*pword1
>> 28) & 0xf)
87 len
= mem (memaddr
, *pword1
, *pword2
, 1);
90 default: /* invalid instruction */
103 /*****************************************************************************
104 * All code below this point should be identical with that of
105 * the disassembler in gdmp960.
106 *****************************************************************************/
114 pinsn( memaddr
, word1
, word2
)
115 unsigned long memaddr
;
116 unsigned long word1
, word2
;
121 put_abs( word1
, word2
);
123 /* Divide instruction set into classes based on high 4 bits of opcode*/
125 switch ( (word1
>> 28) & 0xf ){
128 ctrl( memaddr
, word1
, word2
);
132 cobr( memaddr
, word1
, word2
);
144 instr_len
= mem( memaddr
, word1
, word2
, 0 );
147 /* invalid instruction, print as data word */
154 /****************************************/
156 /****************************************/
158 ctrl( memaddr
, word1
, word2
)
159 unsigned long memaddr
;
160 unsigned long word1
, word2
;
163 static struct tabent ctrl_tab
[] = {
173 "call", 1, /* 0x09 */
188 "faultno", 0, /* 0x18 */
189 "faultg", 0, /* 0x19 */
190 "faulte", 0, /* 0x1a */
191 "faultge", 0, /* 0x1b */
192 "faultl", 0, /* 0x1c */
193 "faultne", 0, /* 0x1d */
194 "faultle", 0, /* 0x1e */
195 "faulto", 0, /* 0x1f */
198 i
= (word1
>> 24) & 0xff;
199 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
204 fputs( ctrl_tab
[i
].name
, stream
);
205 if ( word1
& 2 ){ /* Predicts branch not taken */
206 fputs( ".f", stream
);
209 if ( ctrl_tab
[i
].numops
== 1 ){
210 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
212 if ( word1
& 0x00800000 ){ /* Sign bit is set */
213 word1
|= (-1 & ~0xffffff); /* Sign extend */
215 putc( '\t', stream
);
216 print_addr( word1
+ memaddr
);
220 /****************************************/
222 /****************************************/
224 cobr( memaddr
, word1
, word2
)
225 unsigned long memaddr
;
226 unsigned long word1
, word2
;
232 static struct tabent cobr_tab
[] = {
233 "testno", 1, /* 0x20 */
234 "testg", 1, /* 0x21 */
235 "teste", 1, /* 0x22 */
236 "testge", 1, /* 0x23 */
237 "testl", 1, /* 0x24 */
238 "testne", 1, /* 0x25 */
239 "testle", 1, /* 0x26 */
240 "testo", 1, /* 0x27 */
250 "cmpobg", 3, /* 0x31 */
251 "cmpobe", 3, /* 0x32 */
252 "cmpobge", 3, /* 0x33 */
253 "cmpobl", 3, /* 0x34 */
254 "cmpobne", 3, /* 0x35 */
255 "cmpoble", 3, /* 0x36 */
257 "cmpibno", 3, /* 0x38 */
258 "cmpibg", 3, /* 0x39 */
259 "cmpibe", 3, /* 0x3a */
260 "cmpibge", 3, /* 0x3b */
261 "cmpibl", 3, /* 0x3c */
262 "cmpibne", 3, /* 0x3d */
263 "cmpible", 3, /* 0x3e */
264 "cmpibo", 3, /* 0x3f */
267 i
= ((word1
>> 24) & 0xff) - 0x20;
268 if ( cobr_tab
[i
].name
== NULL
){
273 fputs( cobr_tab
[i
].name
, stream
);
274 if ( word1
& 2 ){ /* Predicts branch not taken */
275 fputs( ".f", stream
);
277 putc( '\t', stream
);
279 src1
= (word1
>> 19) & 0x1f;
280 src2
= (word1
>> 14) & 0x1f;
282 if ( word1
& 0x02000 ){ /* M1 is 1 */
283 fprintf( stream
, "%d", src1
);
284 } else { /* M1 is 0 */
285 fputs( reg_names
[src1
], stream
);
288 if ( cobr_tab
[i
].numops
> 1 ){
289 if ( word1
& 1 ){ /* S2 is 1 */
290 fprintf( stream
, ",sf%d,", src2
);
291 } else { /* S1 is 0 */
292 fprintf( stream
, ",%s,", reg_names
[src2
] );
295 /* Extract displacement and convert to address
298 if ( word1
& 0x00001000 ){ /* Negative displacement */
299 word1
|= (-1 & ~0x1fff); /* Sign extend */
301 print_addr( memaddr
+ word1
);
305 /****************************************/
307 /****************************************/
308 static int /* returns instruction length: 4 or 8 */
309 mem( memaddr
, word1
, word2
, noprint
)
310 unsigned long memaddr
;
311 unsigned long word1
, word2
;
312 int noprint
; /* If TRUE, return instruction length, but
313 don't output any text. */
319 char *reg1
, *reg2
, *reg3
;
321 /* This lookup table is too sparse to make it worth typing in, but not
322 * so large as to make a sparse array necessary. We allocate the
323 * table at runtime, initialize all entries to empty, and copy the
324 * real ones in from an initialization table.
326 * NOTE: In this table, the meaning of 'numops' is:
328 * 2: 2 operands, load instruction
329 * -2: 2 operands, store instruction
331 static struct tabent
*mem_tab
= NULL
;
332 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
355 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
359 if ( mem_tab
== NULL
){
360 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
361 bzero( mem_tab
, MEM_SIZ
);
362 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
363 j
= mem_init
[i
].opcode
- MEM_MIN
;
364 mem_tab
[j
].name
= mem_init
[i
].name
;
365 mem_tab
[j
].numops
= mem_init
[i
].numops
;
369 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
370 mode
= (word1
>> 10) & 0xf;
372 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
373 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
383 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
388 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
390 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
391 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
392 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
393 offset
= word1
& 0xfff; /* MEMA only */
395 switch ( mem_tab
[i
].numops
){
397 case 2: /* LOAD INSTRUCTION */
398 if ( mode
& 4 ){ /* MEMB FORMAT */
399 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
400 fprintf( stream
, ",%s", reg1
);
401 } else { /* MEMA FORMAT */
402 fprintf( stream
, "0x%x", offset
);
404 fprintf( stream
, "(%s)", reg2
);
406 fprintf( stream
, ",%s", reg1
);
410 case -2: /* STORE INSTRUCTION */
411 if ( mode
& 4 ){ /* MEMB FORMAT */
412 fprintf( stream
, "%s,", reg1
);
413 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
414 } else { /* MEMA FORMAT */
415 fprintf( stream
, "%s,0x%x", reg1
, offset
);
417 fprintf( stream
, "(%s)", reg2
);
422 case 1: /* BX/CALLX INSTRUCTION */
423 if ( mode
& 4 ){ /* MEMB FORMAT */
424 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
425 } else { /* MEMA FORMAT */
426 fprintf( stream
, "0x%x", offset
);
428 fprintf( stream
, "(%s)", reg2
);
437 /****************************************/
439 /****************************************/
452 /* This lookup table is too sparse to make it worth typing in, but not
453 * so large as to make a sparse array necessary. We allocate the
454 * table at runtime, initialize all entries to empty, and copy the
455 * real ones in from an initialization table.
457 * NOTE: In this table, the meaning of 'numops' is:
458 * 1: single operand, which is NOT a destination.
459 * -1: single operand, which IS a destination.
460 * 2: 2 operands, the 2nd of which is NOT a destination.
461 * -2: 2 operands, the 2nd of which IS a destination.
464 * If an opcode mnemonic begins with "F", it is a floating-point
465 * opcode (the "F" is not printed).
468 static struct tabent
*reg_tab
= NULL
;
469 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
470 #define REG_MIN 0x580
485 0x58f, "alterbit", 3,
504 0x5ac, "scanbyte", 2,
521 0x613, "inspacc", -2,
527 0x640, "spanbit", -2,
528 0x641, "scanbit", -2,
533 0x646, "condrec", -2,
538 0x656, "receive", -2,
542 0x663, "sendserv", 1,
543 0x664, "resumprcs", 1,
544 0x665, "schedprcs", 1,
545 0x666, "saveprcs", 0,
546 0x668, "condwait", 1,
551 0x66d, "flushreg", 0,
557 0x675, "Fcvtilr", -2,
558 0x676, "Fscalerl", 3,
568 0x68a, "Flogbnr", -2,
569 0x68b, "Froundr", -2,
575 0x691, "Flogeprl", 3,
580 0x698, "Fsqrtrl", -2,
582 0x69a, "Flogbnrl", -2,
583 0x69b, "Froundrl", -2,
587 0x69f, "Fclassrl", 1,
589 0x6c1, "Fcvtril", -2,
590 0x6c2, "Fcvtzri", -2,
591 0x6c3, "Fcvtzril", -2,
596 0x6e3, "Fcpyrsre", 3,
612 #define REG_MAX 0x79f
613 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
617 if ( reg_tab
== NULL
){
618 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
619 bzero( reg_tab
, REG_SIZ
);
620 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
621 j
= reg_init
[i
].opcode
- REG_MIN
;
622 reg_tab
[j
].name
= reg_init
[i
].name
;
623 reg_tab
[j
].numops
= reg_init
[i
].numops
;
627 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
628 i
= opcode
- REG_MIN
;
630 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
635 mnemp
= reg_tab
[i
].name
;
636 if ( *mnemp
== 'F' ){
643 fputs( mnemp
, stream
);
645 s1
= (word1
>> 5) & 1;
646 s2
= (word1
>> 6) & 1;
647 m1
= (word1
>> 11) & 1;
648 m2
= (word1
>> 12) & 1;
649 m3
= (word1
>> 13) & 1;
651 src2
= (word1
>> 14) & 0x1f;
652 dst
= (word1
>> 19) & 0x1f;
654 if ( reg_tab
[i
].numops
!= 0 ){
655 putc( '\t', stream
);
657 switch ( reg_tab
[i
].numops
){
659 regop( m1
, s1
, src
, fp
);
662 dstop( m3
, dst
, fp
);
665 regop( m1
, s1
, src
, fp
);
667 regop( m2
, s2
, src2
, fp
);
670 regop( m1
, s1
, src
, fp
);
672 dstop( m3
, dst
, fp
);
675 regop( m1
, s1
, src
, fp
);
677 regop( m2
, s2
, src2
, fp
);
679 dstop( m3
, dst
, fp
);
687 * Print out effective address for memb instructions.
690 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
691 unsigned long memaddr
;
697 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
699 scale
= (word1
>> 7) & 0x07;
700 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
704 scale
= scale_tab
[scale
];
708 fprintf( stream
, "(%s)", reg2
);
710 case 5: /* displ+8(ip) */
711 print_addr( word2
+8+memaddr
);
713 case 7: /* (reg)[index*scale] */
715 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
717 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
720 case 12: /* displacement */
723 case 13: /* displ(reg) */
725 fprintf( stream
, "(%s)", reg2
);
727 case 14: /* displ[index*scale] */
730 fprintf( stream
, "[%s]", reg3
);
732 fprintf( stream
, "[%s*%d]", reg3
, scale
);
735 case 15: /* displ(reg)[index*scale] */
738 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
740 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
750 /************************************************/
751 /* Register Instruction Operand */
752 /************************************************/
754 regop( mode
, spec
, reg
, fp
)
755 int mode
, spec
, reg
, fp
;
757 if ( fp
){ /* FLOATING POINT INSTRUCTION */
758 if ( mode
== 1 ){ /* FP operand */
760 case 0: fputs( "fp0", stream
); break;
761 case 1: fputs( "fp1", stream
); break;
762 case 2: fputs( "fp2", stream
); break;
763 case 3: fputs( "fp3", stream
); break;
764 case 16: fputs( "0f0.0", stream
); break;
765 case 22: fputs( "0f1.0", stream
); break;
766 default: putc( '?', stream
); break;
768 } else { /* Non-FP register */
769 fputs( reg_names
[reg
], stream
);
771 } else { /* NOT FLOATING POINT */
772 if ( mode
== 1 ){ /* Literal */
773 fprintf( stream
, "%d", reg
);
774 } else { /* Register */
776 fputs( reg_names
[reg
], stream
);
778 fprintf( stream
, "sf%d", reg
);
784 /************************************************/
785 /* Register Instruction Destination Operand */
786 /************************************************/
788 dstop( mode
, reg
, fp
)
791 /* 'dst' operand can't be a literal. On non-FP instructions, register
792 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
793 * sf registers are not allowed so m3 acts normally.
796 regop( mode
, 0, reg
, fp
);
798 regop( 0, mode
, reg
, fp
);
807 fprintf( stream
, ".word\t0x%08x", word1
);
813 fprintf( stream
, "0x%x", a
);
817 put_abs( word1
, word2
)
818 unsigned long word1
, word2
;
825 switch ( (word1
>> 28) & 0xf ){
831 /* MEM format instruction */
832 len
= mem( 0, word1
, word2
, 1 );
840 fprintf( stream
, "%08x %08x\t", word1
, word2
);
842 fprintf( stream
, "%08x \t", word1
);