1 /* i80960 instruction disassembler for GDB.
2 Copyright (C) 1990-1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
25 extern char *reg_names
[];
27 static FILE *stream
; /* Output goes here */
28 static void print_addr();
36 static void invalid();
38 static void put_abs();
41 /* Print the i960 instruction at address 'memaddr' in debugged memory,
42 on stream 's'. Returns length of the instruction, in bytes. */
44 print_insn( memaddr
, s
)
48 unsigned int word1
, word2
;
51 word1
= read_memory_integer( memaddr
, 4 );
52 word2
= read_memory_integer( memaddr
+4, 4 );
53 return pinsn( memaddr
, word1
, word2
);
57 /* Read the i960 instruction at 'memaddr' and return the address of
58 the next instruction after that, or 0 if 'memaddr' is not the
59 address of a valid instruction. The first word of the instruction
60 is stored at 'pword1', and the second word, if any, is stored at
64 next_insn (memaddr
, pword1
, pword2
)
65 unsigned long *pword1
, *pword2
;
71 /* Read the two (potential) words of the instruction at once,
72 to eliminate the overhead of two calls to read_memory ().
73 TODO: read more instructions at once and cache them. */
75 read_memory (memaddr
, buf
, sizeof (buf
));
77 SWAP_TARGET_AND_HOST (pword1
, sizeof (long));
79 SWAP_TARGET_AND_HOST (pword2
, sizeof (long));
81 /* Divide instruction set into classes based on high 4 bits of opcode*/
83 switch ((*pword1
>> 28) & 0xf)
102 len
= mem (memaddr
, *pword1
, *pword2
, 1);
105 default: /* invalid instruction */
111 return memaddr
+ len
;
118 /*****************************************************************************
119 * All code below this point should be identical with that of
120 * the disassembler in gdmp960.
121 *****************************************************************************/
129 pinsn( memaddr
, word1
, word2
)
130 unsigned long memaddr
;
131 unsigned long word1
, word2
;
136 put_abs( word1
, word2
);
138 /* Divide instruction set into classes based on high 4 bits of opcode*/
140 switch ( (word1
>> 28) & 0xf ){
143 ctrl( memaddr
, word1
, word2
);
147 cobr( memaddr
, word1
, word2
);
159 instr_len
= mem( memaddr
, word1
, word2
, 0 );
162 /* invalid instruction, print as data word */
169 /****************************************/
171 /****************************************/
173 ctrl( memaddr
, word1
, word2
)
174 unsigned long memaddr
;
175 unsigned long word1
, word2
;
178 static struct tabent ctrl_tab
[] = {
188 "call", 1, /* 0x09 */
203 "faultno", 0, /* 0x18 */
204 "faultg", 0, /* 0x19 */
205 "faulte", 0, /* 0x1a */
206 "faultge", 0, /* 0x1b */
207 "faultl", 0, /* 0x1c */
208 "faultne", 0, /* 0x1d */
209 "faultle", 0, /* 0x1e */
210 "faulto", 0, /* 0x1f */
213 i
= (word1
>> 24) & 0xff;
214 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
219 fputs( ctrl_tab
[i
].name
, stream
);
220 if ( word1
& 2 ){ /* Predicts branch not taken */
221 fputs( ".f", stream
);
224 if ( ctrl_tab
[i
].numops
== 1 ){
225 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
227 if ( word1
& 0x00800000 ){ /* Sign bit is set */
228 word1
|= (-1 & ~0xffffff); /* Sign extend */
230 putc( '\t', stream
);
231 print_addr( word1
+ memaddr
);
235 /****************************************/
237 /****************************************/
239 cobr( memaddr
, word1
, word2
)
240 unsigned long memaddr
;
241 unsigned long word1
, word2
;
247 static struct tabent cobr_tab
[] = {
248 "testno", 1, /* 0x20 */
249 "testg", 1, /* 0x21 */
250 "teste", 1, /* 0x22 */
251 "testge", 1, /* 0x23 */
252 "testl", 1, /* 0x24 */
253 "testne", 1, /* 0x25 */
254 "testle", 1, /* 0x26 */
255 "testo", 1, /* 0x27 */
265 "cmpobg", 3, /* 0x31 */
266 "cmpobe", 3, /* 0x32 */
267 "cmpobge", 3, /* 0x33 */
268 "cmpobl", 3, /* 0x34 */
269 "cmpobne", 3, /* 0x35 */
270 "cmpoble", 3, /* 0x36 */
272 "cmpibno", 3, /* 0x38 */
273 "cmpibg", 3, /* 0x39 */
274 "cmpibe", 3, /* 0x3a */
275 "cmpibge", 3, /* 0x3b */
276 "cmpibl", 3, /* 0x3c */
277 "cmpibne", 3, /* 0x3d */
278 "cmpible", 3, /* 0x3e */
279 "cmpibo", 3, /* 0x3f */
282 i
= ((word1
>> 24) & 0xff) - 0x20;
283 if ( cobr_tab
[i
].name
== NULL
){
288 fputs( cobr_tab
[i
].name
, stream
);
289 if ( word1
& 2 ){ /* Predicts branch not taken */
290 fputs( ".f", stream
);
292 putc( '\t', stream
);
294 src1
= (word1
>> 19) & 0x1f;
295 src2
= (word1
>> 14) & 0x1f;
297 if ( word1
& 0x02000 ){ /* M1 is 1 */
298 fprintf( stream
, "%d", src1
);
299 } else { /* M1 is 0 */
300 fputs( reg_names
[src1
], stream
);
303 if ( cobr_tab
[i
].numops
> 1 ){
304 if ( word1
& 1 ){ /* S2 is 1 */
305 fprintf( stream
, ",sf%d,", src2
);
306 } else { /* S1 is 0 */
307 fprintf( stream
, ",%s,", reg_names
[src2
] );
310 /* Extract displacement and convert to address
313 if ( word1
& 0x00001000 ){ /* Negative displacement */
314 word1
|= (-1 & ~0x1fff); /* Sign extend */
316 print_addr( memaddr
+ word1
);
320 /****************************************/
322 /****************************************/
323 static int /* returns instruction length: 4 or 8 */
324 mem( memaddr
, word1
, word2
, noprint
)
325 unsigned long memaddr
;
326 unsigned long word1
, word2
;
327 int noprint
; /* If TRUE, return instruction length, but
328 don't output any text. */
334 char *reg1
, *reg2
, *reg3
;
336 /* This lookup table is too sparse to make it worth typing in, but not
337 * so large as to make a sparse array necessary. We allocate the
338 * table at runtime, initialize all entries to empty, and copy the
339 * real ones in from an initialization table.
341 * NOTE: In this table, the meaning of 'numops' is:
343 * 2: 2 operands, load instruction
344 * -2: 2 operands, store instruction
346 static struct tabent
*mem_tab
= NULL
;
347 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
370 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
374 if ( mem_tab
== NULL
){
375 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
376 bzero( mem_tab
, MEM_SIZ
);
377 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
378 j
= mem_init
[i
].opcode
- MEM_MIN
;
379 mem_tab
[j
].name
= mem_init
[i
].name
;
380 mem_tab
[j
].numops
= mem_init
[i
].numops
;
384 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
385 mode
= (word1
>> 10) & 0xf;
387 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
388 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
398 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
403 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
405 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
406 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
407 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
408 offset
= word1
& 0xfff; /* MEMA only */
410 switch ( mem_tab
[i
].numops
){
412 case 2: /* LOAD INSTRUCTION */
413 if ( mode
& 4 ){ /* MEMB FORMAT */
414 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
415 fprintf( stream
, ",%s", reg1
);
416 } else { /* MEMA FORMAT */
417 fprintf( stream
, "0x%x", offset
);
419 fprintf( stream
, "(%s)", reg2
);
421 fprintf( stream
, ",%s", reg1
);
425 case -2: /* STORE INSTRUCTION */
426 if ( mode
& 4 ){ /* MEMB FORMAT */
427 fprintf( stream
, "%s,", reg1
);
428 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
429 } else { /* MEMA FORMAT */
430 fprintf( stream
, "%s,0x%x", reg1
, offset
);
432 fprintf( stream
, "(%s)", reg2
);
437 case 1: /* BX/CALLX INSTRUCTION */
438 if ( mode
& 4 ){ /* MEMB FORMAT */
439 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
440 } else { /* MEMA FORMAT */
441 fprintf( stream
, "0x%x", offset
);
443 fprintf( stream
, "(%s)", reg2
);
452 /****************************************/
454 /****************************************/
467 /* This lookup table is too sparse to make it worth typing in, but not
468 * so large as to make a sparse array necessary. We allocate the
469 * table at runtime, initialize all entries to empty, and copy the
470 * real ones in from an initialization table.
472 * NOTE: In this table, the meaning of 'numops' is:
473 * 1: single operand, which is NOT a destination.
474 * -1: single operand, which IS a destination.
475 * 2: 2 operands, the 2nd of which is NOT a destination.
476 * -2: 2 operands, the 2nd of which IS a destination.
479 * If an opcode mnemonic begins with "F", it is a floating-point
480 * opcode (the "F" is not printed).
483 static struct tabent
*reg_tab
= NULL
;
484 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
485 #define REG_MIN 0x580
500 0x58f, "alterbit", 3,
519 0x5ac, "scanbyte", 2,
536 0x613, "inspacc", -2,
542 0x640, "spanbit", -2,
543 0x641, "scanbit", -2,
548 0x646, "condrec", -2,
553 0x656, "receive", -2,
557 0x663, "sendserv", 1,
558 0x664, "resumprcs", 1,
559 0x665, "schedprcs", 1,
560 0x666, "saveprcs", 0,
561 0x668, "condwait", 1,
566 0x66d, "flushreg", 0,
572 0x675, "Fcvtilr", -2,
573 0x676, "Fscalerl", 3,
583 0x68a, "Flogbnr", -2,
584 0x68b, "Froundr", -2,
590 0x691, "Flogeprl", 3,
595 0x698, "Fsqrtrl", -2,
597 0x69a, "Flogbnrl", -2,
598 0x69b, "Froundrl", -2,
602 0x69f, "Fclassrl", 1,
604 0x6c1, "Fcvtril", -2,
605 0x6c2, "Fcvtzri", -2,
606 0x6c3, "Fcvtzril", -2,
611 0x6e3, "Fcpyrsre", 3,
627 #define REG_MAX 0x79f
628 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
632 if ( reg_tab
== NULL
){
633 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
634 bzero( reg_tab
, REG_SIZ
);
635 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
636 j
= reg_init
[i
].opcode
- REG_MIN
;
637 reg_tab
[j
].name
= reg_init
[i
].name
;
638 reg_tab
[j
].numops
= reg_init
[i
].numops
;
642 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
643 i
= opcode
- REG_MIN
;
645 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
650 mnemp
= reg_tab
[i
].name
;
651 if ( *mnemp
== 'F' ){
658 fputs( mnemp
, stream
);
660 s1
= (word1
>> 5) & 1;
661 s2
= (word1
>> 6) & 1;
662 m1
= (word1
>> 11) & 1;
663 m2
= (word1
>> 12) & 1;
664 m3
= (word1
>> 13) & 1;
666 src2
= (word1
>> 14) & 0x1f;
667 dst
= (word1
>> 19) & 0x1f;
669 if ( reg_tab
[i
].numops
!= 0 ){
670 putc( '\t', stream
);
672 switch ( reg_tab
[i
].numops
){
674 regop( m1
, s1
, src
, fp
);
677 dstop( m3
, dst
, fp
);
680 regop( m1
, s1
, src
, fp
);
682 regop( m2
, s2
, src2
, fp
);
685 regop( m1
, s1
, src
, fp
);
687 dstop( m3
, dst
, fp
);
690 regop( m1
, s1
, src
, fp
);
692 regop( m2
, s2
, src2
, fp
);
694 dstop( m3
, dst
, fp
);
702 * Print out effective address for memb instructions.
705 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
706 unsigned long memaddr
;
712 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
714 scale
= (word1
>> 7) & 0x07;
715 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
719 scale
= scale_tab
[scale
];
723 fprintf( stream
, "(%s)", reg2
);
725 case 5: /* displ+8(ip) */
726 print_addr( word2
+8+memaddr
);
728 case 7: /* (reg)[index*scale] */
730 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
732 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
735 case 12: /* displacement */
738 case 13: /* displ(reg) */
740 fprintf( stream
, "(%s)", reg2
);
742 case 14: /* displ[index*scale] */
745 fprintf( stream
, "[%s]", reg3
);
747 fprintf( stream
, "[%s*%d]", reg3
, scale
);
750 case 15: /* displ(reg)[index*scale] */
753 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
755 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
765 /************************************************/
766 /* Register Instruction Operand */
767 /************************************************/
769 regop( mode
, spec
, reg
, fp
)
770 int mode
, spec
, reg
, fp
;
772 if ( fp
){ /* FLOATING POINT INSTRUCTION */
773 if ( mode
== 1 ){ /* FP operand */
775 case 0: fputs( "fp0", stream
); break;
776 case 1: fputs( "fp1", stream
); break;
777 case 2: fputs( "fp2", stream
); break;
778 case 3: fputs( "fp3", stream
); break;
779 case 16: fputs( "0f0.0", stream
); break;
780 case 22: fputs( "0f1.0", stream
); break;
781 default: putc( '?', stream
); break;
783 } else { /* Non-FP register */
784 fputs( reg_names
[reg
], stream
);
786 } else { /* NOT FLOATING POINT */
787 if ( mode
== 1 ){ /* Literal */
788 fprintf( stream
, "%d", reg
);
789 } else { /* Register */
791 fputs( reg_names
[reg
], stream
);
793 fprintf( stream
, "sf%d", reg
);
799 /************************************************/
800 /* Register Instruction Destination Operand */
801 /************************************************/
803 dstop( mode
, reg
, fp
)
806 /* 'dst' operand can't be a literal. On non-FP instructions, register
807 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
808 * sf registers are not allowed so m3 acts normally.
811 regop( mode
, 0, reg
, fp
);
813 regop( 0, mode
, reg
, fp
);
822 fprintf( stream
, ".word\t0x%08x", word1
);
828 fprintf( stream
, "0x%x", a
);
832 put_abs( word1
, word2
)
833 unsigned long word1
, word2
;
840 switch ( (word1
>> 28) & 0xf ){
846 /* MEM format instruction */
847 len
= mem( 0, word1
, word2
, 1 );
855 fprintf( stream
, "%08x %08x\t", word1
, word2
);
857 fprintf( stream
, "%08x \t", word1
);