1 /* Target-machine dependent code for the Intel 960
2 Copyright (C) 1991 Free Software Foundation, Inc.
3 Contributed by Intel Corporation.
4 examine_prologue and other parts contributed by Wind River Systems.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "floatformat.h"
29 /* gdb960 is always running on a non-960 host. Check its characteristics.
30 This routine must be called as part of gdb initialization. */
37 static struct typestruct
{
38 int hostsize
; /* Size of type on host */
39 int i960size
; /* Size of type on i960 */
40 char *typename
; /* Name of type, for error msg */
42 { sizeof(short), 2, "short" },
43 { sizeof(int), 4, "int" },
44 { sizeof(long), 4, "long" },
45 { sizeof(float), 4, "float" },
46 { sizeof(double), 8, "double" },
47 { sizeof(char *), 4, "pointer" },
49 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
51 /* Make sure that host type sizes are same as i960
53 for ( i
= 0; i
< TYPELEN
; i
++ ){
54 if ( types
[i
].hostsize
!= types
[i
].i960size
){
55 printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
56 types
[i
].typename
, types
[i
].i960size
);
62 /* Examine an i960 function prologue, recording the addresses at which
63 registers are saved explicitly by the prologue code, and returning
64 the address of the first instruction after the prologue (but not
65 after the instruction at address LIMIT, as explained below).
67 LIMIT places an upper bound on addresses of the instructions to be
68 examined. If the prologue code scan reaches LIMIT, the scan is
69 aborted and LIMIT is returned. This is used, when examining the
70 prologue for the current frame, to keep examine_prologue () from
71 claiming that a given register has been saved when in fact the
72 instruction that saves it has not yet been executed. LIMIT is used
73 at other times to stop the scan when we hit code after the true
74 function prologue (e.g. for the first source line) which might
75 otherwise be mistaken for function prologue.
77 The format of the function prologue matched by this routine is
78 derived from examination of the source to gcc960 1.21, particularly
79 the routine i960_function_prologue (). A "regular expression" for
80 the function prologue is given below:
84 (mov 0, g14) | (lda 0, g14))?
86 (mov[qtl]? g[0-15], r[4-15])*
87 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
88 (st[qtl]? g[0-15], n(fp))*
101 /* Macros for extracting fields from i960 instructions. */
103 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
104 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
106 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
107 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
108 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
109 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
110 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
112 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
113 is not the address of a valid instruction, the address of the next
114 instruction beyond ADDR otherwise. *PWORD1 receives the first word
115 of the instruction, and (for two-word instructions), *PWORD2 receives
118 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
119 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
122 examine_prologue (ip
, limit
, frame_addr
, fsr
)
123 register CORE_ADDR ip
;
124 register CORE_ADDR limit
;
125 CORE_ADDR frame_addr
;
126 struct frame_saved_regs
*fsr
;
128 register CORE_ADDR next_ip
;
129 register int src
, dst
;
130 register unsigned int *pcode
;
131 unsigned int insn1
, insn2
;
133 int within_leaf_prologue
;
135 static unsigned int varargs_prologue_code
[] =
137 0x3507a00c, /* cmpobne 0x0, g14, LFn */
138 0x5cf01601, /* mov sp, g14 */
139 0x8c086030, /* lda 0x30(sp), sp */
140 0xb2879000, /* LFn: stq g0, (g14) */
141 0xb2a7a010, /* stq g4, 0x10(g14) */
142 0xb2c7a020 /* stq g8, 0x20(g14) */
145 /* Accept a leaf procedure prologue code fragment if present.
146 Note that ip might point to either the leaf or non-leaf
147 entry point; we look for the non-leaf entry point first: */
149 within_leaf_prologue
= 0;
150 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
151 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
152 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
154 within_leaf_prologue
= 1;
155 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
158 /* Now look for the prologue code at a leaf entry point: */
161 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
162 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
164 within_leaf_prologue
= 1;
165 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
166 && (insn1
== 0x8cf00000 /* lda 0, g14 */
167 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
170 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
171 within_leaf_prologue
= 0;
175 /* If something that looks like the beginning of a leaf prologue
176 has been seen, but the remainder of the prologue is missing, bail.
177 We don't know what we've got. */
179 if (within_leaf_prologue
)
182 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
183 This may cause us to mistake the moving of a register
184 parameter to a local register for the saving of a callee-saved
185 register, but that can't be helped, since with the
186 "-fcall-saved" flag, any register can be made callee-saved. */
189 && (insn1
& 0xfc802fb0) == 0x5c000610
190 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
192 src
= REG_SRC1 (insn1
);
193 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
194 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
197 fsr
->regs
[src
++] = save_addr
;
201 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
204 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
207 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
208 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
209 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
212 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
215 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
216 This may cause us to mistake the copying of a register
217 parameter to the frame for the saving of a callee-saved
218 register, but that can't be helped, since with the
219 "-fcall-saved" flag, any register can be made callee-saved.
220 We can, however, refuse to accept a save of register g14,
221 since that is matched explicitly below. */
224 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
225 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
226 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
227 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
228 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
230 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
231 ? insn2
: MEMA_OFFSET (insn1
));
232 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
233 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
236 fsr
->regs
[src
++] = save_addr
;
240 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
243 /* Accept the varargs prologue code if present. */
245 size
= sizeof (varargs_prologue_code
) / sizeof (int);
246 pcode
= varargs_prologue_code
;
247 while (size
-- && next_ip
&& *pcode
++ == insn1
)
250 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
253 /* Accept an optional "st g14, n(fp)". */
256 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
257 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
259 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
260 ? insn2
: MEMA_OFFSET (insn1
));
262 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
265 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
266 This is saving the address where a struct should be returned. */
269 && (insn1
& 0xff802fbf) == 0x5c00061d
270 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
272 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
273 fsr
->regs
[G0_REGNUM
+13] = save_addr
;
275 #if 0 /* We'll need this once there is a subsequent instruction examined. */
276 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
283 /* Given an ip value corresponding to the start of a function,
284 return the ip of the first instruction after the function
291 struct frame_saved_regs saved_regs_dummy
;
292 struct symtab_and_line sal
;
295 sal
= find_pc_line (ip
, 0);
296 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
298 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
301 /* Put here the code to store, into a struct frame_saved_regs,
302 the addresses of the saved registers of frame described by FRAME_INFO.
303 This includes special registers such as pc and fp saved in special
304 ways in the stack frame. sp is even more special:
305 the address we return for it IS the sp for the next frame.
307 We cache the result of doing this in the frame_cache_obstack, since
308 it is fairly expensive. */
311 frame_find_saved_regs (fi
, fsr
)
312 struct frame_info
*fi
;
313 struct frame_saved_regs
*fsr
;
315 register CORE_ADDR next_addr
;
316 register CORE_ADDR
*saved_regs
;
318 register struct frame_saved_regs
*cache_fsr
;
319 extern struct obstack frame_cache_obstack
;
321 struct symtab_and_line sal
;
326 cache_fsr
= (struct frame_saved_regs
*)
327 obstack_alloc (&frame_cache_obstack
,
328 sizeof (struct frame_saved_regs
));
329 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
332 /* Find the start and end of the function prologue. If the PC
333 is in the function prologue, we only consider the part that
334 has executed already. */
336 ip
= get_pc_function_start (fi
->pc
);
337 sal
= find_pc_line (ip
, 0);
338 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
340 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
342 /* Record the addresses at which the local registers are saved.
343 Strictly speaking, we should only do this for non-leaf procedures,
344 but no one will ever look at these values if it is a leaf procedure,
345 since local registers are always caller-saved. */
347 next_addr
= (CORE_ADDR
) fi
->frame
;
348 saved_regs
= cache_fsr
->regs
;
349 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
351 *saved_regs
++ = next_addr
;
355 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
360 /* Fetch the value of the sp from memory every time, since it
361 is conceivable that it has changed since the cache was flushed.
362 This unfortunately undoes much of the savings from caching the
363 saved register values. I suggest adding an argument to
364 get_frame_saved_regs () specifying the register number we're
365 interested in (or -1 for all registers). This would be passed
366 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
367 computation of saved register addresses (e.g., on the i960,
368 we don't have to examine the prologue to find local registers).
370 FIXME, we don't need to refetch this, since the cache is cleared
371 every time the child process is restarted. If GDB itself
372 modifies SP, it has to clear the cache by hand (does it?). -gnu */
374 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
377 /* Return the address of the argument block for the frame
378 described by FI. Returns 0 if the address is unknown. */
381 frame_args_address (fi
, must_be_correct
)
382 struct frame_info
*fi
;
384 struct frame_saved_regs fsr
;
387 /* If g14 was saved in the frame by the function prologue code, return
388 the saved value. If the frame is current and we are being sloppy,
389 return the value of g14. Otherwise, return zero. */
391 get_frame_saved_regs (fi
, &fsr
);
392 if (fsr
.regs
[G14_REGNUM
])
393 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
],4);
397 return 0; /* Don't cache this result */
398 if (get_next_frame (fi
))
401 ap
= read_register (G14_REGNUM
);
405 fi
->arg_pointer
= ap
; /* Cache it for next time */
409 /* Return the address of the return struct for the frame
410 described by FI. Returns 0 if the address is unknown. */
413 frame_struct_result_address (fi
)
414 struct frame_info
*fi
;
416 struct frame_saved_regs fsr
;
419 /* If the frame is non-current, check to see if g14 was saved in the
420 frame by the function prologue code; return the saved value if so,
421 zero otherwise. If the frame is current, return the value of g14.
423 FIXME, shouldn't this use the saved value as long as we are past
424 the function prologue, and only use the current value if we have
425 no saved value and are at TOS? -- gnu@cygnus.com */
427 if (get_next_frame (fi
))
429 get_frame_saved_regs (fi
, &fsr
);
430 if (fsr
.regs
[G13_REGNUM
])
431 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
],4);
436 ap
= read_register (G13_REGNUM
);
441 /* Return address to which the currently executing leafproc will return,
442 or 0 if ip is not in a leafproc (or if we can't tell if it is).
444 Do this by finding the starting address of the routine in which ip lies.
445 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
446 is a leafproc and the return address is in register gx. Well, this is
447 true unless the return address points at a RET instruction in the current
448 procedure, which indicates that we have a 'dual entry' routine that
449 has been entered through the CALL entry point. */
453 CORE_ADDR ip
; /* ip from currently executing function */
455 register struct minimal_symbol
*msymbol
;
458 unsigned int insn1
, insn2
;
459 CORE_ADDR return_addr
;
461 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
463 if ((p
= strchr(SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
465 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
466 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
467 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
469 /* Get the return address. If the "mov g14, gx"
470 instruction hasn't been executed yet, read
471 the return address from g14; otherwise, read it
472 from the register into which g14 was moved. */
475 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
478 /* We know we are in a leaf procedure, but we don't know
479 whether the caller actually did a "bal" to the ".lf"
480 entry point, or a normal "call" to the non-leaf entry
481 point one instruction before. In the latter case, the
482 return address will be the address of a "ret"
483 instruction within the procedure itself. We test for
486 if (!next_insn (return_addr
, &insn1
, &insn2
)
487 || (insn1
& 0xff000000) != 0xa000000 /* ret */
488 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
489 return (return_addr
);
497 /* Immediately after a function call, return the saved pc.
498 Can't go through the frames for this because on some machines
499 the new frame is not set up until the new function executes
501 On the i960, the frame *is* set up immediately after the call,
502 unless the function is a leaf procedure. */
505 saved_pc_after_call (frame
)
506 struct frame_info
*frame
;
510 saved_pc
= leafproc_return (get_frame_pc (frame
));
512 saved_pc
= FRAME_SAVED_PC (frame
);
517 /* Discard from the stack the innermost frame,
518 restoring all saved registers. */
522 register struct frame_info
*current_fi
, *prev_fi
;
525 CORE_ADDR leaf_return_addr
;
526 struct frame_saved_regs fsr
;
527 char local_regs_buf
[16 * 4];
529 current_fi
= get_current_frame ();
531 /* First, undo what the hardware does when we return.
532 If this is a non-leaf procedure, restore local registers from
533 the save area in the calling frame. Otherwise, load the return
534 address obtained from leafproc_return () into the rip. */
536 leaf_return_addr
= leafproc_return (current_fi
->pc
);
537 if (!leaf_return_addr
)
539 /* Non-leaf procedure. Restore local registers, incl IP. */
540 prev_fi
= get_prev_frame (current_fi
);
541 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
542 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
543 sizeof (local_regs_buf
));
545 /* Restore frame pointer. */
546 write_register (FP_REGNUM
, prev_fi
->frame
);
550 /* Leaf procedure. Just restore the return address into the IP. */
551 write_register (RIP_REGNUM
, leaf_return_addr
);
554 /* Now restore any global regs that the current function had saved. */
555 get_frame_saved_regs (current_fi
, &fsr
);
556 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
558 if (save_addr
= fsr
.regs
[i
])
559 write_register (i
, read_memory_integer (save_addr
, 4));
562 /* Flush the frame cache, create a frame for the new innermost frame,
563 and make it the current frame. */
565 flush_cached_frames ();
568 /* Given a 960 stop code (fault or trace), return the signal which
572 i960_fault_to_signal (fault
)
577 case 0: return TARGET_SIGNAL_BUS
; /* parallel fault */
578 case 1: return TARGET_SIGNAL_UNKNOWN
;
579 case 2: return TARGET_SIGNAL_ILL
; /* operation fault */
580 case 3: return TARGET_SIGNAL_FPE
; /* arithmetic fault */
581 case 4: return TARGET_SIGNAL_FPE
; /* floating point fault */
583 /* constraint fault. This appears not to distinguish between
584 a range constraint fault (which should be SIGFPE) and a privileged
585 fault (which should be SIGILL). */
586 case 5: return TARGET_SIGNAL_ILL
;
588 case 6: return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
590 /* protection fault. This is for an out-of-range argument to
591 "calls". I guess it also could be SIGILL. */
592 case 7: return TARGET_SIGNAL_SEGV
;
594 case 8: return TARGET_SIGNAL_BUS
; /* machine fault */
595 case 9: return TARGET_SIGNAL_BUS
; /* structural fault */
596 case 0xa: return TARGET_SIGNAL_ILL
; /* type fault */
597 case 0xb: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
598 case 0xc: return TARGET_SIGNAL_BUS
; /* process fault */
599 case 0xd: return TARGET_SIGNAL_SEGV
; /* descriptor fault */
600 case 0xe: return TARGET_SIGNAL_BUS
; /* event fault */
601 case 0xf: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
602 case 0x10: return TARGET_SIGNAL_TRAP
; /* single-step trace */
603 case 0x11: return TARGET_SIGNAL_TRAP
; /* branch trace */
604 case 0x12: return TARGET_SIGNAL_TRAP
; /* call trace */
605 case 0x13: return TARGET_SIGNAL_TRAP
; /* return trace */
606 case 0x14: return TARGET_SIGNAL_TRAP
; /* pre-return trace */
607 case 0x15: return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
608 case 0x16: return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
609 default: return TARGET_SIGNAL_UNKNOWN
;
613 /* Initialization stub */
616 _initialize_i960_tdep ()