1 /* Target-machine dependent code for the Intel 960
3 Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Intel Corporation.
7 examine_prologue and other parts contributed by Wind River Systems.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
30 #include "floatformat.h"
36 static CORE_ADDR
next_insn (CORE_ADDR memaddr
,
37 unsigned int *pword1
, unsigned int *pword2
);
40 i960_register_type (int regnum
)
42 if (regnum
< FP0_REGNUM
)
43 return builtin_type_int32
;
45 return builtin_type_i960_ext
;
49 /* Does the specified function use the "struct returning" convention
50 or the "value returning" convention? The "value returning" convention
51 almost invariably returns the entire value in registers. The
52 "struct returning" convention often returns the entire value in
53 memory, and passes a pointer (out of or into the function) saying
54 where the value (is or should go).
56 Since this sometimes depends on whether it was compiled with GCC,
57 this is also an argument. This is used in call_function to build a
58 stack, and in value_being_returned to print return values.
60 On i960, a structure is returned in registers g0-g3, if it will fit.
61 If it's more than 16 bytes long, g13 pointed to it on entry. */
64 i960_use_struct_convention (int gcc_p
, struct type
*type
)
66 return (TYPE_LENGTH (type
) > 16);
69 /* gdb960 is always running on a non-960 host. Check its characteristics.
70 This routine must be called as part of gdb initialization. */
77 static struct typestruct
79 int hostsize
; /* Size of type on host */
80 int i960size
; /* Size of type on i960 */
81 char *typename
; /* Name of type, for error msg */
86 sizeof (short), 2, "short"
90 sizeof (int), 4, "int"
94 sizeof (long), 4, "long"
98 sizeof (float), 4, "float"
102 sizeof (double), 8, "double"
106 sizeof (char *), 4, "pointer"
110 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
112 /* Make sure that host type sizes are same as i960
114 for (i
= 0; i
< TYPELEN
; i
++)
116 if (types
[i
].hostsize
!= types
[i
].i960size
)
118 printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
119 types
[i
].typename
, types
[i
].i960size
);
125 /* i960_find_saved_register ()
127 Return the address in which frame FRAME's value of register REGNUM
128 has been saved in memory. Or return zero if it has not been saved.
129 If REGNUM specifies the SP, the value we return is actually the SP
130 value, not an address where it was saved. */
133 i960_find_saved_register (struct frame_info
*frame
, int regnum
)
135 register struct frame_info
*frame1
= NULL
;
136 register CORE_ADDR addr
= 0;
138 if (frame
== NULL
) /* No regs saved if want current frame */
141 /* We assume that a register in a register window will only be saved
142 in one place (since the name changes and/or disappears as you go
143 towards inner frames), so we only call get_frame_saved_regs on
144 the current frame. This is directly in contradiction to the
145 usage below, which assumes that registers used in a frame must be
146 saved in a lower (more interior) frame. This change is a result
147 of working on a register window machine; get_frame_saved_regs
148 always returns the registers saved within a frame, within the
149 context (register namespace) of that frame. */
151 /* However, note that we don't want this to return anything if
152 nothing is saved (if there's a frame inside of this one). Also,
153 callers to this routine asking for the stack pointer want the
154 stack pointer saved for *this* frame; this is returned from the
157 if (REGISTER_IN_WINDOW_P (regnum
))
159 frame1
= get_next_frame (frame
);
161 return 0; /* Registers of this frame are active. */
163 /* Get the SP from the next frame in; it will be this
165 if (regnum
!= SP_REGNUM
)
168 FRAME_INIT_SAVED_REGS (frame1
);
169 return frame1
->saved_regs
[regnum
]; /* ... which might be zero */
172 /* Note that this next routine assumes that registers used in
173 frame x will be saved only in the frame that x calls and
174 frames interior to it. This is not true on the sparc, but the
175 above macro takes care of it, so we should be all right. */
179 frame1
= get_next_frame (frame
);
183 FRAME_INIT_SAVED_REGS (frame1
);
184 if (frame1
->saved_regs
[regnum
])
185 addr
= frame1
->saved_regs
[regnum
];
191 /* i960_get_saved_register ()
193 Find register number REGNUM relative to FRAME and put its (raw,
194 target format) contents in *RAW_BUFFER. Set *OPTIMIZED if the
195 variable was optimized out (and thus can't be fetched). Set *LVAL
196 to lval_memory, lval_register, or not_lval, depending on whether
197 the value was fetched from memory, from a register, or in a strange
198 and non-modifiable way (e.g. a frame pointer which was calculated
199 rather than fetched). Set *ADDRP to the address, either in memory
200 on as a REGISTER_BYTE offset into the registers array.
202 Note that this implementation never sets *LVAL to not_lval. But it
203 can be replaced by defining GET_SAVED_REGISTER and supplying your
206 The argument RAW_BUFFER must point to aligned memory. */
209 i960_get_saved_register (char *raw_buffer
,
212 struct frame_info
*frame
,
214 enum lval_type
*lval
)
218 if (!target_has_registers
)
219 error ("No registers.");
221 /* Normal systems don't optimize out things with register numbers. */
222 if (optimized
!= NULL
)
224 addr
= i960_find_saved_register (frame
, regnum
);
229 if (regnum
== SP_REGNUM
)
231 if (raw_buffer
!= NULL
)
233 /* Put it back in target format. */
234 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
241 if (raw_buffer
!= NULL
)
242 target_read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
247 *lval
= lval_register
;
248 addr
= REGISTER_BYTE (regnum
);
249 if (raw_buffer
!= NULL
)
250 read_register_gen (regnum
, raw_buffer
);
256 /* Examine an i960 function prologue, recording the addresses at which
257 registers are saved explicitly by the prologue code, and returning
258 the address of the first instruction after the prologue (but not
259 after the instruction at address LIMIT, as explained below).
261 LIMIT places an upper bound on addresses of the instructions to be
262 examined. If the prologue code scan reaches LIMIT, the scan is
263 aborted and LIMIT is returned. This is used, when examining the
264 prologue for the current frame, to keep examine_prologue () from
265 claiming that a given register has been saved when in fact the
266 instruction that saves it has not yet been executed. LIMIT is used
267 at other times to stop the scan when we hit code after the true
268 function prologue (e.g. for the first source line) which might
269 otherwise be mistaken for function prologue.
271 The format of the function prologue matched by this routine is
272 derived from examination of the source to gcc960 1.21, particularly
273 the routine i960_function_prologue (). A "regular expression" for
274 the function prologue is given below:
278 (mov 0, g14) | (lda 0, g14))?
280 (mov[qtl]? g[0-15], r[4-15])*
281 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
282 (st[qtl]? g[0-15], n(fp))*
295 /* Macros for extracting fields from i960 instructions. */
297 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
298 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
300 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
301 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
302 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
303 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
304 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
306 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
307 is not the address of a valid instruction, the address of the next
308 instruction beyond ADDR otherwise. *PWORD1 receives the first word
309 of the instruction, and (for two-word instructions), *PWORD2 receives
312 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
313 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
316 examine_prologue (register CORE_ADDR ip
, register CORE_ADDR limit
,
317 CORE_ADDR frame_addr
, struct frame_saved_regs
*fsr
)
319 register CORE_ADDR next_ip
;
320 register int src
, dst
;
321 register unsigned int *pcode
;
322 unsigned int insn1
, insn2
;
324 int within_leaf_prologue
;
326 static unsigned int varargs_prologue_code
[] =
328 0x3507a00c, /* cmpobne 0x0, g14, LFn */
329 0x5cf01601, /* mov sp, g14 */
330 0x8c086030, /* lda 0x30(sp), sp */
331 0xb2879000, /* LFn: stq g0, (g14) */
332 0xb2a7a010, /* stq g4, 0x10(g14) */
333 0xb2c7a020 /* stq g8, 0x20(g14) */
336 /* Accept a leaf procedure prologue code fragment if present.
337 Note that ip might point to either the leaf or non-leaf
338 entry point; we look for the non-leaf entry point first: */
340 within_leaf_prologue
= 0;
341 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
342 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
343 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
345 within_leaf_prologue
= 1;
346 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
349 /* Now look for the prologue code at a leaf entry point: */
352 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
353 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
355 within_leaf_prologue
= 1;
356 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
357 && (insn1
== 0x8cf00000 /* lda 0, g14 */
358 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
361 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
362 within_leaf_prologue
= 0;
366 /* If something that looks like the beginning of a leaf prologue
367 has been seen, but the remainder of the prologue is missing, bail.
368 We don't know what we've got. */
370 if (within_leaf_prologue
)
373 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
374 This may cause us to mistake the moving of a register
375 parameter to a local register for the saving of a callee-saved
376 register, but that can't be helped, since with the
377 "-fcall-saved" flag, any register can be made callee-saved. */
380 && (insn1
& 0xfc802fb0) == 0x5c000610
381 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
383 src
= REG_SRC1 (insn1
);
384 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
385 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
388 fsr
->regs
[src
++] = save_addr
;
392 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
395 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
398 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
399 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
400 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
403 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
406 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
407 This may cause us to mistake the copying of a register
408 parameter to the frame for the saving of a callee-saved
409 register, but that can't be helped, since with the
410 "-fcall-saved" flag, any register can be made callee-saved.
411 We can, however, refuse to accept a save of register g14,
412 since that is matched explicitly below. */
415 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
416 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
417 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
418 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
419 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
421 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
422 ? insn2
: MEMA_OFFSET (insn1
));
423 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
424 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
427 fsr
->regs
[src
++] = save_addr
;
431 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
434 /* Accept the varargs prologue code if present. */
436 size
= sizeof (varargs_prologue_code
) / sizeof (int);
437 pcode
= varargs_prologue_code
;
438 while (size
-- && next_ip
&& *pcode
++ == insn1
)
441 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
444 /* Accept an optional "st g14, n(fp)". */
447 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
448 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
450 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
451 ? insn2
: MEMA_OFFSET (insn1
));
453 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
456 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
457 This is saving the address where a struct should be returned. */
460 && (insn1
& 0xff802fbf) == 0x5c00061d
461 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
463 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
464 fsr
->regs
[G0_REGNUM
+ 13] = save_addr
;
466 #if 0 /* We'll need this once there is a subsequent instruction examined. */
467 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
474 /* Given an ip value corresponding to the start of a function,
475 return the ip of the first instruction after the function
479 i960_skip_prologue (CORE_ADDR ip
)
481 struct frame_saved_regs saved_regs_dummy
;
482 struct symtab_and_line sal
;
485 sal
= find_pc_line (ip
, 0);
486 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
488 return (examine_prologue (ip
, limit
, (CORE_ADDR
) 0, &saved_regs_dummy
));
491 /* Put here the code to store, into a struct frame_saved_regs,
492 the addresses of the saved registers of frame described by FRAME_INFO.
493 This includes special registers such as pc and fp saved in special
494 ways in the stack frame. sp is even more special:
495 the address we return for it IS the sp for the next frame.
497 We cache the result of doing this in the frame_obstack, since it is
501 frame_find_saved_regs (struct frame_info
*fi
, struct frame_saved_regs
*fsr
)
503 register CORE_ADDR next_addr
;
504 register CORE_ADDR
*saved_regs
;
506 register struct frame_saved_regs
*cache_fsr
;
508 struct symtab_and_line sal
;
513 cache_fsr
= (struct frame_saved_regs
*)
514 frame_obstack_alloc (sizeof (struct frame_saved_regs
));
515 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
518 /* Find the start and end of the function prologue. If the PC
519 is in the function prologue, we only consider the part that
520 has executed already. */
522 ip
= get_pc_function_start (fi
->pc
);
523 sal
= find_pc_line (ip
, 0);
524 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
526 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
528 /* Record the addresses at which the local registers are saved.
529 Strictly speaking, we should only do this for non-leaf procedures,
530 but no one will ever look at these values if it is a leaf procedure,
531 since local registers are always caller-saved. */
533 next_addr
= (CORE_ADDR
) fi
->frame
;
534 saved_regs
= cache_fsr
->regs
;
535 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
537 *saved_regs
++ = next_addr
;
541 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
546 /* Fetch the value of the sp from memory every time, since it
547 is conceivable that it has changed since the cache was flushed.
548 This unfortunately undoes much of the savings from caching the
549 saved register values. I suggest adding an argument to
550 get_frame_saved_regs () specifying the register number we're
551 interested in (or -1 for all registers). This would be passed
552 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
553 computation of saved register addresses (e.g., on the i960,
554 we don't have to examine the prologue to find local registers).
556 FIXME, we don't need to refetch this, since the cache is cleared
557 every time the child process is restarted. If GDB itself
558 modifies SP, it has to clear the cache by hand (does it?). -gnu */
560 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
563 /* Return the address of the argument block for the frame
564 described by FI. Returns 0 if the address is unknown. */
567 frame_args_address (struct frame_info
*fi
, int must_be_correct
)
569 struct frame_saved_regs fsr
;
572 /* If g14 was saved in the frame by the function prologue code, return
573 the saved value. If the frame is current and we are being sloppy,
574 return the value of g14. Otherwise, return zero. */
576 get_frame_saved_regs (fi
, &fsr
);
577 if (fsr
.regs
[G14_REGNUM
])
578 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
], 4);
582 return 0; /* Don't cache this result */
583 if (get_next_frame (fi
))
586 ap
= read_register (G14_REGNUM
);
590 fi
->arg_pointer
= ap
; /* Cache it for next time */
594 /* Return the address of the return struct for the frame
595 described by FI. Returns 0 if the address is unknown. */
598 frame_struct_result_address (struct frame_info
*fi
)
600 struct frame_saved_regs fsr
;
603 /* If the frame is non-current, check to see if g14 was saved in the
604 frame by the function prologue code; return the saved value if so,
605 zero otherwise. If the frame is current, return the value of g14.
607 FIXME, shouldn't this use the saved value as long as we are past
608 the function prologue, and only use the current value if we have
609 no saved value and are at TOS? -- gnu@cygnus.com */
611 if (get_next_frame (fi
))
613 get_frame_saved_regs (fi
, &fsr
);
614 if (fsr
.regs
[G13_REGNUM
])
615 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
], 4);
620 ap
= read_register (G13_REGNUM
);
625 /* Return address to which the currently executing leafproc will return,
626 or 0 if IP, the value of the instruction pointer from the currently
627 executing function, is not in a leafproc (or if we can't tell if it
630 Do this by finding the starting address of the routine in which IP lies.
631 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
632 is a leafproc and the return address is in register gx. Well, this is
633 true unless the return address points at a RET instruction in the current
634 procedure, which indicates that we have a 'dual entry' routine that
635 has been entered through the CALL entry point. */
638 leafproc_return (CORE_ADDR ip
)
640 register struct minimal_symbol
*msymbol
;
643 unsigned int insn1
, insn2
;
644 CORE_ADDR return_addr
;
646 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
648 if ((p
= strchr (SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
650 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
651 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
652 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
654 /* Get the return address. If the "mov g14, gx"
655 instruction hasn't been executed yet, read
656 the return address from g14; otherwise, read it
657 from the register into which g14 was moved. */
660 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
663 /* We know we are in a leaf procedure, but we don't know
664 whether the caller actually did a "bal" to the ".lf"
665 entry point, or a normal "call" to the non-leaf entry
666 point one instruction before. In the latter case, the
667 return address will be the address of a "ret"
668 instruction within the procedure itself. We test for
671 if (!next_insn (return_addr
, &insn1
, &insn2
)
672 || (insn1
& 0xff000000) != 0xa000000 /* ret */
673 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
674 return (return_addr
);
682 /* Immediately after a function call, return the saved pc.
683 Can't go through the frames for this because on some machines
684 the new frame is not set up until the new function executes
686 On the i960, the frame *is* set up immediately after the call,
687 unless the function is a leaf procedure. */
690 saved_pc_after_call (struct frame_info
*frame
)
694 saved_pc
= leafproc_return (get_frame_pc (frame
));
696 saved_pc
= FRAME_SAVED_PC (frame
);
701 /* Discard from the stack the innermost frame,
702 restoring all saved registers. */
705 i960_pop_frame (void)
707 register struct frame_info
*current_fi
, *prev_fi
;
710 CORE_ADDR leaf_return_addr
;
711 struct frame_saved_regs fsr
;
712 char local_regs_buf
[16 * 4];
714 current_fi
= get_current_frame ();
716 /* First, undo what the hardware does when we return.
717 If this is a non-leaf procedure, restore local registers from
718 the save area in the calling frame. Otherwise, load the return
719 address obtained from leafproc_return () into the rip. */
721 leaf_return_addr
= leafproc_return (current_fi
->pc
);
722 if (!leaf_return_addr
)
724 /* Non-leaf procedure. Restore local registers, incl IP. */
725 prev_fi
= get_prev_frame (current_fi
);
726 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
727 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
728 sizeof (local_regs_buf
));
730 /* Restore frame pointer. */
731 write_register (FP_REGNUM
, prev_fi
->frame
);
735 /* Leaf procedure. Just restore the return address into the IP. */
736 write_register (RIP_REGNUM
, leaf_return_addr
);
739 /* Now restore any global regs that the current function had saved. */
740 get_frame_saved_regs (current_fi
, &fsr
);
741 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
743 save_addr
= fsr
.regs
[i
];
745 write_register (i
, read_memory_integer (save_addr
, 4));
748 /* Flush the frame cache, create a frame for the new innermost frame,
749 and make it the current frame. */
751 flush_cached_frames ();
754 /* Given a 960 stop code (fault or trace), return the signal which
758 i960_fault_to_signal (int fault
)
763 return TARGET_SIGNAL_BUS
; /* parallel fault */
765 return TARGET_SIGNAL_UNKNOWN
;
767 return TARGET_SIGNAL_ILL
; /* operation fault */
769 return TARGET_SIGNAL_FPE
; /* arithmetic fault */
771 return TARGET_SIGNAL_FPE
; /* floating point fault */
773 /* constraint fault. This appears not to distinguish between
774 a range constraint fault (which should be SIGFPE) and a privileged
775 fault (which should be SIGILL). */
777 return TARGET_SIGNAL_ILL
;
780 return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
782 /* protection fault. This is for an out-of-range argument to
783 "calls". I guess it also could be SIGILL. */
785 return TARGET_SIGNAL_SEGV
;
788 return TARGET_SIGNAL_BUS
; /* machine fault */
790 return TARGET_SIGNAL_BUS
; /* structural fault */
792 return TARGET_SIGNAL_ILL
; /* type fault */
794 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
796 return TARGET_SIGNAL_BUS
; /* process fault */
798 return TARGET_SIGNAL_SEGV
; /* descriptor fault */
800 return TARGET_SIGNAL_BUS
; /* event fault */
802 return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
804 return TARGET_SIGNAL_TRAP
; /* single-step trace */
806 return TARGET_SIGNAL_TRAP
; /* branch trace */
808 return TARGET_SIGNAL_TRAP
; /* call trace */
810 return TARGET_SIGNAL_TRAP
; /* return trace */
812 return TARGET_SIGNAL_TRAP
; /* pre-return trace */
814 return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
816 return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
818 return TARGET_SIGNAL_UNKNOWN
;
822 /****************************************/
824 /****************************************/
832 /* Return instruction length, either 4 or 8. When NOPRINT is non-zero
833 (TRUE), don't output any text. (Actually, as implemented, if NOPRINT
834 is 0, abort() is called.) */
837 mem (unsigned long memaddr
, unsigned long word1
, unsigned long word2
,
844 const char *reg1
, *reg2
, *reg3
;
846 /* This lookup table is too sparse to make it worth typing in, but not
847 * so large as to make a sparse array necessary. We allocate the
848 * table at runtime, initialize all entries to empty, and copy the
849 * real ones in from an initialization table.
851 * NOTE: In this table, the meaning of 'numops' is:
853 * 2: 2 operands, load instruction
854 * -2: 2 operands, store instruction
856 static struct tabent
*mem_tab
= NULL
;
857 /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */
860 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
895 mem_tab
= (struct tabent
*) xmalloc (MEM_SIZ
);
896 memset (mem_tab
, '\0', MEM_SIZ
);
897 for (i
= 0; mem_init
[i
].opcode
!= 0; i
++)
899 j
= mem_init
[i
].opcode
- MEM_MIN
;
900 mem_tab
[j
].name
= mem_init
[i
].name
;
901 mem_tab
[j
].numops
= mem_init
[i
].numops
;
905 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
906 mode
= (word1
>> 10) & 0xf;
908 if ((mem_tab
[i
].name
!= NULL
) /* Valid instruction */
909 && ((mode
== 5) || (mode
>= 12)))
910 { /* With 32-bit displacement */
922 internal_error (__FILE__
, __LINE__
, "failed internal consistency check");
925 /* Read the i960 instruction at 'memaddr' and return the address of
926 the next instruction after that, or 0 if 'memaddr' is not the
927 address of a valid instruction. The first word of the instruction
928 is stored at 'pword1', and the second word, if any, is stored at
932 next_insn (CORE_ADDR memaddr
, unsigned int *pword1
, unsigned int *pword2
)
937 /* Read the two (potential) words of the instruction at once,
938 to eliminate the overhead of two calls to read_memory ().
939 FIXME: Loses if the first one is readable but the second is not
940 (e.g. last word of the segment). */
942 read_memory (memaddr
, buf
, 8);
943 *pword1
= extract_unsigned_integer (buf
, 4);
944 *pword2
= extract_unsigned_integer (buf
+ 4, 4);
946 /* Divide instruction set into classes based on high 4 bits of opcode */
948 switch ((*pword1
>> 28) & 0xf)
967 len
= mem (memaddr
, *pword1
, *pword2
, 1);
970 default: /* invalid instruction */
976 return memaddr
+ len
;
981 /* 'start_frame' is a variable in the MON960 runtime startup routine
982 that contains the frame pointer of the 'start' routine (the routine
983 that calls 'main'). By reading its contents out of remote memory,
984 we can tell where the frame chain ends: backtraces should halt before
985 they display this frame. */
988 mon960_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*curframe
)
991 struct minimal_symbol
*msymbol
;
993 /* crtmon960.o is an assembler module that is assumed to be linked
994 * first in an i80960 executable. It contains the true entry point;
995 * it performs startup up initialization and then calls 'main'.
997 * 'sf' is the name of a variable in crtmon960.o that is set
998 * during startup to the address of the first frame.
1000 * 'a' is the address of that variable in 80960 memory.
1002 static char sf
[] = "start_frame";
1006 chain
&= ~0x3f; /* Zero low 6 bits because previous frame pointers
1007 contain return status info in them. */
1013 sym
= lookup_symbol (sf
, 0, VAR_NAMESPACE
, (int *) NULL
,
1014 (struct symtab
**) NULL
);
1017 a
= SYMBOL_VALUE (sym
);
1021 msymbol
= lookup_minimal_symbol (sf
, NULL
, NULL
);
1022 if (msymbol
== NULL
)
1024 a
= SYMBOL_VALUE_ADDRESS (msymbol
);
1027 return (chain
!= read_memory_integer (a
, 4));
1032 _initialize_i960_tdep (void)
1036 tm_print_insn
= print_insn_i960
;