1 /* Target-machine dependent code for the Intel 960
2 Copyright (C) 1991 Free Software Foundation, Inc.
3 Contributed by Intel Corporation.
4 examine_prologue and other parts contributed by Wind River Systems.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Miscellaneous i80960-dependent routines.
23 Most are called from macros defined in "tm-i960.h". */
29 #include "floatformat.h"
32 /* gdb960 is always running on a non-960 host. Check its characteristics.
33 This routine must be called as part of gdb initialization. */
40 static struct typestruct
{
41 int hostsize
; /* Size of type on host */
42 int i960size
; /* Size of type on i960 */
43 char *typename
; /* Name of type, for error msg */
45 { sizeof(short), 2, "short" },
46 { sizeof(int), 4, "int" },
47 { sizeof(long), 4, "long" },
48 { sizeof(float), 4, "float" },
49 { sizeof(double), 8, "double" },
50 { sizeof(char *), 4, "pointer" },
52 #define TYPELEN (sizeof(types) / sizeof(struct typestruct))
54 /* Make sure that host type sizes are same as i960
56 for ( i
= 0; i
< TYPELEN
; i
++ ){
57 if ( types
[i
].hostsize
!= types
[i
].i960size
){
58 printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n",
59 types
[i
].typename
, types
[i
].i960size
);
65 /* Examine an i960 function prologue, recording the addresses at which
66 registers are saved explicitly by the prologue code, and returning
67 the address of the first instruction after the prologue (but not
68 after the instruction at address LIMIT, as explained below).
70 LIMIT places an upper bound on addresses of the instructions to be
71 examined. If the prologue code scan reaches LIMIT, the scan is
72 aborted and LIMIT is returned. This is used, when examining the
73 prologue for the current frame, to keep examine_prologue () from
74 claiming that a given register has been saved when in fact the
75 instruction that saves it has not yet been executed. LIMIT is used
76 at other times to stop the scan when we hit code after the true
77 function prologue (e.g. for the first source line) which might
78 otherwise be mistaken for function prologue.
80 The format of the function prologue matched by this routine is
81 derived from examination of the source to gcc960 1.21, particularly
82 the routine i960_function_prologue (). A "regular expression" for
83 the function prologue is given below:
87 (mov 0, g14) | (lda 0, g14))?
89 (mov[qtl]? g[0-15], r[4-15])*
90 ((addo [1-31], sp, sp) | (lda n(sp), sp))?
91 (st[qtl]? g[0-15], n(fp))*
104 /* Macros for extracting fields from i960 instructions. */
106 #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos))
107 #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width))
109 #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5)
110 #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5)
111 #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
112 #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5)
113 #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12)
115 /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or
116 is not the address of a valid instruction, the address of the next
117 instruction beyond ADDR otherwise. *PWORD1 receives the first word
118 of the instruction, and (for two-word instructions), *PWORD2 receives
121 #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \
122 (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0)
125 examine_prologue (ip
, limit
, frame_addr
, fsr
)
126 register CORE_ADDR ip
;
127 register CORE_ADDR limit
;
128 FRAME_ADDR frame_addr
;
129 struct frame_saved_regs
*fsr
;
131 register CORE_ADDR next_ip
;
132 register int src
, dst
;
133 register unsigned int *pcode
;
134 unsigned int insn1
, insn2
;
136 int within_leaf_prologue
;
138 static unsigned int varargs_prologue_code
[] =
140 0x3507a00c, /* cmpobne 0x0, g14, LFn */
141 0x5cf01601, /* mov sp, g14 */
142 0x8c086030, /* lda 0x30(sp), sp */
143 0xb2879000, /* LFn: stq g0, (g14) */
144 0xb2a7a010, /* stq g4, 0x10(g14) */
145 0xb2c7a020 /* stq g8, 0x20(g14) */
148 /* Accept a leaf procedure prologue code fragment if present.
149 Note that ip might point to either the leaf or non-leaf
150 entry point; we look for the non-leaf entry point first: */
152 within_leaf_prologue
= 0;
153 if ((next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
))
154 && ((insn1
& 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */
155 || (insn1
& 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */
157 within_leaf_prologue
= 1;
158 next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
);
161 /* Now look for the prologue code at a leaf entry point: */
164 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
165 && REG_SRCDST (insn1
) <= G0_REGNUM
+ 7)
167 within_leaf_prologue
= 1;
168 if ((next_ip
= NEXT_PROLOGUE_INSN (next_ip
, limit
, &insn1
, &insn2
))
169 && (insn1
== 0x8cf00000 /* lda 0, g14 */
170 || insn1
== 0x5cf01e00)) /* mov 0, g14 */
173 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
174 within_leaf_prologue
= 0;
178 /* If something that looks like the beginning of a leaf prologue
179 has been seen, but the remainder of the prologue is missing, bail.
180 We don't know what we've got. */
182 if (within_leaf_prologue
)
185 /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4.
186 This may cause us to mistake the moving of a register
187 parameter to a local register for the saving of a callee-saved
188 register, but that can't be helped, since with the
189 "-fcall-saved" flag, any register can be made callee-saved. */
192 && (insn1
& 0xfc802fb0) == 0x5c000610
193 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
195 src
= REG_SRC1 (insn1
);
196 size
= EXTRACT_FIELD (insn1
, 24, 2) + 1;
197 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
200 fsr
->regs
[src
++] = save_addr
;
204 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
207 /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */
210 ((insn1
& 0xffffffe0) == 0x59084800 /* addo n, sp, sp */
211 || (insn1
& 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */
212 || (insn1
& 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */
215 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
218 /* Accept zero or more instances of "st[qtl]? gx, n(fp)".
219 This may cause us to mistake the copying of a register
220 parameter to the frame for the saving of a callee-saved
221 register, but that can't be helped, since with the
222 "-fcall-saved" flag, any register can be made callee-saved.
223 We can, however, refuse to accept a save of register g14,
224 since that is matched explicitly below. */
227 ((insn1
& 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */
228 || (insn1
& 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */
229 || (insn1
& 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */
230 || (insn1
& 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */
231 && ((src
= MEM_SRCDST (insn1
)) != G14_REGNUM
))
233 save_addr
= frame_addr
+ ((insn1
& BITMASK (12, 1))
234 ? insn2
: MEMA_OFFSET (insn1
));
235 size
= (insn1
& BITMASK (29, 1)) ? ((insn1
& BITMASK (28, 1)) ? 4 : 3)
236 : ((insn1
& BITMASK (27, 1)) ? 2 : 1);
239 fsr
->regs
[src
++] = save_addr
;
243 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
246 /* Accept the varargs prologue code if present. */
248 size
= sizeof (varargs_prologue_code
) / sizeof (int);
249 pcode
= varargs_prologue_code
;
250 while (size
-- && next_ip
&& *pcode
++ == insn1
)
253 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
256 /* Accept an optional "st g14, n(fp)". */
259 ((insn1
& 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */
260 || (insn1
& 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */
262 fsr
->regs
[G14_REGNUM
] = frame_addr
+ ((insn1
& BITMASK (12, 1))
263 ? insn2
: MEMA_OFFSET (insn1
));
265 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
268 /* Accept zero or one instance of "mov g13, ry", where y >= 4.
269 This is saving the address where a struct should be returned. */
272 && (insn1
& 0xff802fbf) == 0x5c00061d
273 && (dst
= REG_SRCDST (insn1
)) >= (R0_REGNUM
+ 4))
275 save_addr
= frame_addr
+ ((dst
- R0_REGNUM
) * 4);
276 fsr
->regs
[G0_REGNUM
+13] = save_addr
;
278 #if 0 /* We'll need this once there is a subsequent instruction examined. */
279 next_ip
= NEXT_PROLOGUE_INSN (ip
, limit
, &insn1
, &insn2
);
286 /* Given an ip value corresponding to the start of a function,
287 return the ip of the first instruction after the function
294 struct frame_saved_regs saved_regs_dummy
;
295 struct symtab_and_line sal
;
298 sal
= find_pc_line (ip
, 0);
299 limit
= (sal
.end
) ? sal
.end
: 0xffffffff;
301 return (examine_prologue (ip
, limit
, (FRAME_ADDR
) 0, &saved_regs_dummy
));
304 /* Put here the code to store, into a struct frame_saved_regs,
305 the addresses of the saved registers of frame described by FRAME_INFO.
306 This includes special registers such as pc and fp saved in special
307 ways in the stack frame. sp is even more special:
308 the address we return for it IS the sp for the next frame.
310 We cache the result of doing this in the frame_cache_obstack, since
311 it is fairly expensive. */
314 frame_find_saved_regs (fi
, fsr
)
315 struct frame_info
*fi
;
316 struct frame_saved_regs
*fsr
;
318 register CORE_ADDR next_addr
;
319 register CORE_ADDR
*saved_regs
;
321 register struct frame_saved_regs
*cache_fsr
;
322 extern struct obstack frame_cache_obstack
;
324 struct symtab_and_line sal
;
329 cache_fsr
= (struct frame_saved_regs
*)
330 obstack_alloc (&frame_cache_obstack
,
331 sizeof (struct frame_saved_regs
));
332 memset (cache_fsr
, '\0', sizeof (struct frame_saved_regs
));
335 /* Find the start and end of the function prologue. If the PC
336 is in the function prologue, we only consider the part that
337 has executed already. */
339 ip
= get_pc_function_start (fi
->pc
);
340 sal
= find_pc_line (ip
, 0);
341 limit
= (sal
.end
&& sal
.end
< fi
->pc
) ? sal
.end
: fi
->pc
;
343 examine_prologue (ip
, limit
, fi
->frame
, cache_fsr
);
345 /* Record the addresses at which the local registers are saved.
346 Strictly speaking, we should only do this for non-leaf procedures,
347 but no one will ever look at these values if it is a leaf procedure,
348 since local registers are always caller-saved. */
350 next_addr
= (CORE_ADDR
) fi
->frame
;
351 saved_regs
= cache_fsr
->regs
;
352 for (regnum
= R0_REGNUM
; regnum
<= R15_REGNUM
; regnum
++)
354 *saved_regs
++ = next_addr
;
358 cache_fsr
->regs
[FP_REGNUM
] = cache_fsr
->regs
[PFP_REGNUM
];
363 /* Fetch the value of the sp from memory every time, since it
364 is conceivable that it has changed since the cache was flushed.
365 This unfortunately undoes much of the savings from caching the
366 saved register values. I suggest adding an argument to
367 get_frame_saved_regs () specifying the register number we're
368 interested in (or -1 for all registers). This would be passed
369 through to FRAME_FIND_SAVED_REGS (), permitting more efficient
370 computation of saved register addresses (e.g., on the i960,
371 we don't have to examine the prologue to find local registers).
373 FIXME, we don't need to refetch this, since the cache is cleared
374 every time the child process is restarted. If GDB itself
375 modifies SP, it has to clear the cache by hand (does it?). -gnu */
377 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[SP_REGNUM
], 4);
380 /* Return the address of the argument block for the frame
381 described by FI. Returns 0 if the address is unknown. */
384 frame_args_address (fi
, must_be_correct
)
385 struct frame_info
*fi
;
387 register FRAME frame
;
388 struct frame_saved_regs fsr
;
391 /* If g14 was saved in the frame by the function prologue code, return
392 the saved value. If the frame is current and we are being sloppy,
393 return the value of g14. Otherwise, return zero. */
395 frame
= FRAME_INFO_ID (fi
);
396 get_frame_saved_regs (fi
, &fsr
);
397 if (fsr
.regs
[G14_REGNUM
])
398 ap
= read_memory_integer (fsr
.regs
[G14_REGNUM
],4);
401 return 0; /* Don't cache this result */
402 if (get_next_frame (frame
))
405 ap
= read_register (G14_REGNUM
);
409 fi
->arg_pointer
= ap
; /* Cache it for next time */
413 /* Return the address of the return struct for the frame
414 described by FI. Returns 0 if the address is unknown. */
417 frame_struct_result_address (fi
)
418 struct frame_info
*fi
;
420 register FRAME frame
;
421 struct frame_saved_regs fsr
;
424 /* If the frame is non-current, check to see if g14 was saved in the
425 frame by the function prologue code; return the saved value if so,
426 zero otherwise. If the frame is current, return the value of g14.
428 FIXME, shouldn't this use the saved value as long as we are past
429 the function prologue, and only use the current value if we have
430 no saved value and are at TOS? -- gnu@cygnus.com */
432 frame
= FRAME_INFO_ID (fi
);
433 if (get_next_frame (frame
)) {
434 get_frame_saved_regs (fi
, &fsr
);
435 if (fsr
.regs
[G13_REGNUM
])
436 ap
= read_memory_integer (fsr
.regs
[G13_REGNUM
],4);
440 ap
= read_register (G13_REGNUM
);
445 /* Return address to which the currently executing leafproc will return,
446 or 0 if ip is not in a leafproc (or if we can't tell if it is).
448 Do this by finding the starting address of the routine in which ip lies.
449 If the instruction there is "mov g14, gx" (where x is in [0,7]), this
450 is a leafproc and the return address is in register gx. Well, this is
451 true unless the return address points at a RET instruction in the current
452 procedure, which indicates that we have a 'dual entry' routine that
453 has been entered through the CALL entry point. */
457 CORE_ADDR ip
; /* ip from currently executing function */
459 register struct minimal_symbol
*msymbol
;
462 unsigned int insn1
, insn2
;
463 CORE_ADDR return_addr
;
465 if ((msymbol
= lookup_minimal_symbol_by_pc (ip
)) != NULL
)
467 if ((p
= strchr(SYMBOL_NAME (msymbol
), '.')) && STREQ (p
, ".lf"))
469 if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol
), &insn1
, &insn2
)
470 && (insn1
& 0xff87ffff) == 0x5c80161e /* mov g14, gx */
471 && (dst
= REG_SRCDST (insn1
)) <= G0_REGNUM
+ 7)
473 /* Get the return address. If the "mov g14, gx"
474 instruction hasn't been executed yet, read
475 the return address from g14; otherwise, read it
476 from the register into which g14 was moved. */
479 read_register ((ip
== SYMBOL_VALUE_ADDRESS (msymbol
))
482 /* We know we are in a leaf procedure, but we don't know
483 whether the caller actually did a "bal" to the ".lf"
484 entry point, or a normal "call" to the non-leaf entry
485 point one instruction before. In the latter case, the
486 return address will be the address of a "ret"
487 instruction within the procedure itself. We test for
490 if (!next_insn (return_addr
, &insn1
, &insn2
)
491 || (insn1
& 0xff000000) != 0xa000000 /* ret */
492 || lookup_minimal_symbol_by_pc (return_addr
) != msymbol
)
493 return (return_addr
);
501 /* Immediately after a function call, return the saved pc.
502 Can't go through the frames for this because on some machines
503 the new frame is not set up until the new function executes
505 On the i960, the frame *is* set up immediately after the call,
506 unless the function is a leaf procedure. */
509 saved_pc_after_call (frame
)
513 CORE_ADDR
get_frame_pc ();
515 saved_pc
= leafproc_return (get_frame_pc (frame
));
517 saved_pc
= FRAME_SAVED_PC (frame
);
522 /* Discard from the stack the innermost frame,
523 restoring all saved registers. */
527 register struct frame_info
*current_fi
, *prev_fi
;
530 CORE_ADDR leaf_return_addr
;
531 struct frame_saved_regs fsr
;
532 char local_regs_buf
[16 * 4];
534 current_fi
= get_frame_info (get_current_frame ());
536 /* First, undo what the hardware does when we return.
537 If this is a non-leaf procedure, restore local registers from
538 the save area in the calling frame. Otherwise, load the return
539 address obtained from leafproc_return () into the rip. */
541 leaf_return_addr
= leafproc_return (current_fi
->pc
);
542 if (!leaf_return_addr
)
544 /* Non-leaf procedure. Restore local registers, incl IP. */
545 prev_fi
= get_frame_info (get_prev_frame (FRAME_INFO_ID (current_fi
)));
546 read_memory (prev_fi
->frame
, local_regs_buf
, sizeof (local_regs_buf
));
547 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), local_regs_buf
,
548 sizeof (local_regs_buf
));
550 /* Restore frame pointer. */
551 write_register (FP_REGNUM
, prev_fi
->frame
);
555 /* Leaf procedure. Just restore the return address into the IP. */
556 write_register (RIP_REGNUM
, leaf_return_addr
);
559 /* Now restore any global regs that the current function had saved. */
560 get_frame_saved_regs (current_fi
, &fsr
);
561 for (i
= G0_REGNUM
; i
< G14_REGNUM
; i
++)
563 if (save_addr
= fsr
.regs
[i
])
564 write_register (i
, read_memory_integer (save_addr
, 4));
567 /* Flush the frame cache, create a frame for the new innermost frame,
568 and make it the current frame. */
570 flush_cached_frames ();
571 set_current_frame (create_new_frame (read_register (FP_REGNUM
), read_pc ()));
574 /* Given a 960 stop code (fault or trace), return the signal which
578 i960_fault_to_signal (fault
)
583 case 0: return TARGET_SIGNAL_BUS
; /* parallel fault */
584 case 1: return TARGET_SIGNAL_UNKNOWN
;
585 case 2: return TARGET_SIGNAL_ILL
; /* operation fault */
586 case 3: return TARGET_SIGNAL_FPE
; /* arithmetic fault */
587 case 4: return TARGET_SIGNAL_FPE
; /* floating point fault */
589 /* constraint fault. This appears not to distinguish between
590 a range constraint fault (which should be SIGFPE) and a privileged
591 fault (which should be SIGILL). */
592 case 5: return TARGET_SIGNAL_ILL
;
594 case 6: return TARGET_SIGNAL_SEGV
; /* virtual memory fault */
596 /* protection fault. This is for an out-of-range argument to
597 "calls". I guess it also could be SIGILL. */
598 case 7: return TARGET_SIGNAL_SEGV
;
600 case 8: return TARGET_SIGNAL_BUS
; /* machine fault */
601 case 9: return TARGET_SIGNAL_BUS
; /* structural fault */
602 case 0xa: return TARGET_SIGNAL_ILL
; /* type fault */
603 case 0xb: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
604 case 0xc: return TARGET_SIGNAL_BUS
; /* process fault */
605 case 0xd: return TARGET_SIGNAL_SEGV
; /* descriptor fault */
606 case 0xe: return TARGET_SIGNAL_BUS
; /* event fault */
607 case 0xf: return TARGET_SIGNAL_UNKNOWN
; /* reserved fault */
608 case 0x10: return TARGET_SIGNAL_TRAP
; /* single-step trace */
609 case 0x11: return TARGET_SIGNAL_TRAP
; /* branch trace */
610 case 0x12: return TARGET_SIGNAL_TRAP
; /* call trace */
611 case 0x13: return TARGET_SIGNAL_TRAP
; /* return trace */
612 case 0x14: return TARGET_SIGNAL_TRAP
; /* pre-return trace */
613 case 0x15: return TARGET_SIGNAL_TRAP
; /* supervisor call trace */
614 case 0x16: return TARGET_SIGNAL_TRAP
; /* breakpoint trace */
615 default: return TARGET_SIGNAL_UNKNOWN
;
619 /* Initialization stub */
622 _initialize_i960_tdep ()