1 /* Functions specific to running gdb native on IA-64 running Linux.
2 Copyright 1999, 2000 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include <sys/ptrace.h>
34 #include <asm/ptrace_offsets.h>
35 #include <sys/procfs.h>
37 /* These must match the order of the register names.
39 Some sort of lookup table is needed because the offsets associated
40 with the registers are all over the board. */
42 static int u_offsets
[] =
44 /* general registers */
45 -1, /* gr0 not available; i.e, it's always zero */
77 /* gr32 through gr127 not directly available via the ptrace interface */
78 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
79 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
80 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
82 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
83 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
84 /* Floating point registers */
85 -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
212 /* predicate registers - we don't fetch these individually */
213 -1, -1, -1, -1, -1, -1, -1, -1,
214 -1, -1, -1, -1, -1, -1, -1, -1,
215 -1, -1, -1, -1, -1, -1, -1, -1,
216 -1, -1, -1, -1, -1, -1, -1, -1,
217 -1, -1, -1, -1, -1, -1, -1, -1,
218 -1, -1, -1, -1, -1, -1, -1, -1,
219 -1, -1, -1, -1, -1, -1, -1, -1,
220 -1, -1, -1, -1, -1, -1, -1, -1,
221 /* branch registers */
230 /* virtual frame pointer and virtual return address pointer */
232 /* other registers */
235 PT_CR_IPSR
, /* psr */
237 /* kernel registers not visible via ptrace interface (?) */
238 -1, -1, -1, -1, -1, -1, -1, -1,
240 -1, -1, -1, -1, -1, -1, -1, -1,
246 -1, /* Not available: FCR, IA32 floating control register */
248 -1, /* Not available: EFLAG */
249 -1, /* Not available: CSD */
250 -1, /* Not available: SSD */
251 -1, /* Not available: CFLG */
252 -1, /* Not available: FSR */
253 -1, /* Not available: FIR */
254 -1, /* Not available: FDR */
262 -1, /* Not available: ITC */
263 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
264 -1, -1, -1, -1, -1, -1, -1, -1, -1,
267 -1, /* Not available: EC, the Epilog Count register */
268 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
269 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
270 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
271 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
272 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
273 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
275 /* nat bits - not fetched directly; instead we obtain these bits from
276 either rnat or unat or from memory. */
277 -1, -1, -1, -1, -1, -1, -1, -1,
278 -1, -1, -1, -1, -1, -1, -1, -1,
279 -1, -1, -1, -1, -1, -1, -1, -1,
280 -1, -1, -1, -1, -1, -1, -1, -1,
281 -1, -1, -1, -1, -1, -1, -1, -1,
282 -1, -1, -1, -1, -1, -1, -1, -1,
283 -1, -1, -1, -1, -1, -1, -1, -1,
284 -1, -1, -1, -1, -1, -1, -1, -1,
285 -1, -1, -1, -1, -1, -1, -1, -1,
286 -1, -1, -1, -1, -1, -1, -1, -1,
287 -1, -1, -1, -1, -1, -1, -1, -1,
288 -1, -1, -1, -1, -1, -1, -1, -1,
289 -1, -1, -1, -1, -1, -1, -1, -1,
290 -1, -1, -1, -1, -1, -1, -1, -1,
291 -1, -1, -1, -1, -1, -1, -1, -1,
292 -1, -1, -1, -1, -1, -1, -1, -1,
296 register_addr (regno
, blockend
)
302 if (regno
< 0 || regno
>= NUM_REGS
)
303 error ("Invalid register number %d.", regno
);
305 if (u_offsets
[regno
] == -1)
308 addr
= (CORE_ADDR
) u_offsets
[regno
];
313 int ia64_cannot_fetch_register (regno
)
316 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1;
319 int ia64_cannot_store_register (regno
)
322 /* Rationale behind not permitting stores to bspstore...
324 The IA-64 architecture provides bspstore and bsp which refer
325 memory locations in the RSE's backing store. bspstore is the
326 next location which will be written when the RSE needs to write
327 to memory. bsp is the address at which r32 in the current frame
328 would be found if it were written to the backing store.
330 The IA-64 architecture provides read-only access to bsp and
331 read/write access to bspstore (but only when the RSE is in
332 the enforced lazy mode). It should be noted that stores
333 to bspstore also affect the value of bsp. Changing bspstore
334 does not affect the number of dirty entries between bspstore
335 and bsp, so changing bspstore by N words will also cause bsp
336 to be changed by (roughly) N as well. (It could be N-1 or N+1
337 depending upon where the NaT collection bits fall.)
339 OTOH, the linux kernel provides read/write access to bsp (and
340 currently read/write access to bspstore as well). But it
341 is definitely the case that if you change one, the other
342 will change at the same time. It is more useful to gdb to
343 be able to change bsp. So in order to prevent strange and
344 undesirable things from happening when a dummy stack frame
345 is popped (after calling an inferior function), we allow
346 bspstore to be read, but not written. (Note that popping
347 a (generic) dummy stack frame causes all registers that
348 were previously read from the inferior process to be written
351 return regno
< 0 || regno
>= NUM_REGS
|| u_offsets
[regno
] == -1
352 || regno
== IA64_BSPSTORE_REGNUM
;
356 supply_gregset (gregsetp
)
360 greg_t
*regp
= (greg_t
*) gregsetp
;
362 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
364 supply_register (regi
, (char *) (regp
+ (regi
- IA64_GR0_REGNUM
)));
367 /* FIXME: NAT collection bits are at index 32; gotta deal with these
370 supply_register (IA64_PR_REGNUM
, (char *) (regp
+ 33));
372 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
374 supply_register (regi
, (char *) (regp
+ 34 + (regi
- IA64_BR0_REGNUM
)));
377 supply_register (IA64_IP_REGNUM
, (char *) (regp
+ 42));
378 supply_register (IA64_CFM_REGNUM
, (char *) (regp
+ 43));
379 supply_register (IA64_PSR_REGNUM
, (char *) (regp
+ 44));
380 supply_register (IA64_RSC_REGNUM
, (char *) (regp
+ 45));
381 supply_register (IA64_BSP_REGNUM
, (char *) (regp
+ 46));
382 supply_register (IA64_BSPSTORE_REGNUM
, (char *) (regp
+ 47));
383 supply_register (IA64_RNAT_REGNUM
, (char *) (regp
+ 48));
384 supply_register (IA64_CCV_REGNUM
, (char *) (regp
+ 49));
385 supply_register (IA64_UNAT_REGNUM
, (char *) (regp
+ 50));
386 supply_register (IA64_FPSR_REGNUM
, (char *) (regp
+ 51));
387 supply_register (IA64_PFS_REGNUM
, (char *) (regp
+ 52));
388 supply_register (IA64_LC_REGNUM
, (char *) (regp
+ 53));
389 supply_register (IA64_EC_REGNUM
, (char *) (regp
+ 54));
393 fill_gregset (gregsetp
, regno
)
398 greg_t
*regp
= (greg_t
*) gregsetp
;
400 #define COPY_REG(_idx_,_regi_) \
401 if ((regno == -1) || regno == _regi_) \
402 memcpy (regp + _idx_, ®isters[REGISTER_BYTE (_regi_)], \
403 REGISTER_RAW_SIZE (_regi_))
405 for (regi
= IA64_GR0_REGNUM
; regi
<= IA64_GR31_REGNUM
; regi
++)
407 COPY_REG (regi
- IA64_GR0_REGNUM
, regi
);
410 /* FIXME: NAT collection bits at index 32? */
412 COPY_REG (33, IA64_PR_REGNUM
);
414 for (regi
= IA64_BR0_REGNUM
; regi
<= IA64_BR7_REGNUM
; regi
++)
416 COPY_REG (34 + (regi
- IA64_BR0_REGNUM
), regi
);
419 COPY_REG (42, IA64_IP_REGNUM
);
420 COPY_REG (43, IA64_CFM_REGNUM
);
421 COPY_REG (44, IA64_PSR_REGNUM
);
422 COPY_REG (45, IA64_RSC_REGNUM
);
423 COPY_REG (46, IA64_BSP_REGNUM
);
424 COPY_REG (47, IA64_BSPSTORE_REGNUM
);
425 COPY_REG (48, IA64_RNAT_REGNUM
);
426 COPY_REG (49, IA64_CCV_REGNUM
);
427 COPY_REG (50, IA64_UNAT_REGNUM
);
428 COPY_REG (51, IA64_FPSR_REGNUM
);
429 COPY_REG (52, IA64_PFS_REGNUM
);
430 COPY_REG (53, IA64_LC_REGNUM
);
431 COPY_REG (54, IA64_EC_REGNUM
);
434 /* Given a pointer to a floating point register set in /proc format
435 (fpregset_t *), unpack the register contents and supply them as gdb's
436 idea of the current floating point register values. */
439 supply_fpregset (fpregsetp
)
440 fpregset_t
*fpregsetp
;
445 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
447 from
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
448 supply_register (regi
, from
);
452 /* Given a pointer to a floating point register set in /proc format
453 (fpregset_t *), update the register specified by REGNO from gdb's idea
454 of the current floating point register set. If REGNO is -1, update
458 fill_fpregset (fpregsetp
, regno
)
459 fpregset_t
*fpregsetp
;
466 for (regi
= IA64_FR0_REGNUM
; regi
<= IA64_FR127_REGNUM
; regi
++)
468 if ((regno
== -1) || (regno
== regi
))
470 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
471 to
= (char *) &((*fpregsetp
)[regi
- IA64_FR0_REGNUM
]);
472 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
477 #define IA64_PSR_DB (1UL << 24)
478 #define IA64_PSR_DD (1UL << 39)
481 enable_watchpoints_in_psr (int pid
)
485 psr
= read_register_pid (IA64_PSR_REGNUM
, pid
);
486 if (!(psr
& IA64_PSR_DB
))
488 psr
|= IA64_PSR_DB
; /* Set the db bit - this enables hardware
489 watchpoints and breakpoints. */
490 write_register_pid (IA64_PSR_REGNUM
, psr
, pid
);
495 fetch_debug_register (int pid
, int idx
)
504 val
= ptrace (PT_READ_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), 0);
510 store_debug_register (int pid
, int idx
, long val
)
518 (void) ptrace (PT_WRITE_U
, tid
, (PTRACE_ARG3_TYPE
) (PT_DBR
+ 8 * idx
), val
);
522 fetch_debug_register_pair (int pid
, int idx
, long *dbr_addr
, long *dbr_mask
)
525 *dbr_addr
= fetch_debug_register (pid
, 2 * idx
);
527 *dbr_mask
= fetch_debug_register (pid
, 2 * idx
+ 1);
531 store_debug_register_pair (int pid
, int idx
, long *dbr_addr
, long *dbr_mask
)
534 store_debug_register (pid
, 2 * idx
, *dbr_addr
);
536 store_debug_register (pid
, 2 * idx
+ 1, *dbr_mask
);
540 is_power_of_2 (int val
)
545 for (i
= 0; i
< 8 * sizeof (val
); i
++)
549 return onecount
<= 1;
553 ia64_linux_insert_watchpoint (int pid
, CORE_ADDR addr
, int len
, int rw
)
556 long dbr_addr
, dbr_mask
;
557 int max_watchpoints
= 4;
559 if (len
<= 0 || !is_power_of_2 (len
))
562 for (idx
= 0; idx
< max_watchpoints
; idx
++)
564 fetch_debug_register_pair (pid
, idx
, NULL
, &dbr_mask
);
565 if ((dbr_mask
& (0x3UL
<< 62)) == 0)
567 /* Exit loop if both r and w bits clear */
572 if (idx
== max_watchpoints
)
575 dbr_addr
= (long) addr
;
576 dbr_mask
= (~(len
- 1) & 0x00ffffffffffffffL
); /* construct mask to match */
577 dbr_mask
|= 0x0800000000000000L
; /* Only match privilege level 3 */
581 dbr_mask
|= (1L << 62); /* Set w bit */
584 dbr_mask
|= (1L << 63); /* Set r bit */
587 dbr_mask
|= (3L << 62); /* Set both r and w bits */
593 store_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
594 enable_watchpoints_in_psr (pid
);
600 ia64_linux_remove_watchpoint (int pid
, CORE_ADDR addr
, int len
)
603 long dbr_addr
, dbr_mask
;
604 int max_watchpoints
= 4;
606 if (len
<= 0 || !is_power_of_2 (len
))
609 for (idx
= 0; idx
< max_watchpoints
; idx
++)
611 fetch_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
612 if ((dbr_mask
& (0x3UL
<< 62)) && addr
== (CORE_ADDR
) dbr_addr
)
616 store_debug_register_pair (pid
, idx
, &dbr_addr
, &dbr_mask
);
624 ia64_linux_stopped_by_watchpoint (int pid
)
628 struct siginfo siginfo
;
635 ptrace (PTRACE_GETSIGINFO
, tid
, (PTRACE_ARG3_TYPE
) 0, &siginfo
);
637 if (errno
!= 0 || siginfo
.si_code
!= 4 /* TRAP_HWBKPT */)
640 psr
= read_register_pid (IA64_PSR_REGNUM
, pid
);
641 psr
|= IA64_PSR_DD
; /* Set the dd bit - this will disable the watchpoint
642 for the next instruction */
643 write_register_pid (IA64_PSR_REGNUM
, psr
, pid
);
645 return (CORE_ADDR
) siginfo
.si_addr
;