gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2022 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "arch-utils.h"
  32 #include "regcache.h"
  33 #include "trad-frame.h"
  34 #include "reggroups.h"
  35 #include "opcodes/lm32-desc.h"
  36 #include <algorithm>
  37 #include "gdbarch.h"
  38
  39 /* Macros to extract fields from an instruction.  */
  40 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  41 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  42 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  43 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  44 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  45
  46 struct lm32_gdbarch_tdep : gdbarch_tdep_base
  47 {
  48   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  49 };
  50
  51 struct lm32_frame_cache
  52 {
  53   /* The frame's base.  Used when constructing a frame ID.  */
  54   CORE_ADDR base;
  55   CORE_ADDR pc;
  56   /* Size of frame.  */
  57   int size;
  58   /* Table indicating the location of each and every register.  */
  59   trad_frame_saved_reg *saved_regs;
  60 };
  61
  62 /* Return whether a given register is in a given group.  */
  63
  64 static int
  65 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  66                           const struct reggroup *group)
  67 {
  68   if (group == general_reggroup)
  69     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  70       || (regnum == SIM_LM32_PC_REGNUM);
  71   else if (group == system_reggroup)
  72     return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
  73       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  74   return default_register_reggroup_p (gdbarch, regnum, group);
  75 }
  76
  77 /* Return a name that corresponds to the given register number.  */
  78
  79 static const char *
  80 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  81 {
  82   static const char *register_names[] = {
  83     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  84     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  85     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  86     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  87     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
  88   };
  89
  90   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
  91     return NULL;
  92   else
  93     return register_names[reg_nr];
  94 }
  95
  96 /* Return type of register.  */
  97
  98 static struct type *
  99 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 100 {
 101   return builtin_type (gdbarch)->builtin_int32;
 102 }
 103
 104 /* Return non-zero if a register can't be written.  */
 105
 106 static int
 107 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 108 {
 109   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 110 }
 111
 112 /* Analyze a function's prologue.  */
 113
 114 static CORE_ADDR
 115 lm32_analyze_prologue (struct gdbarch *gdbarch,
 116                        CORE_ADDR pc, CORE_ADDR limit,
 117                        struct lm32_frame_cache *info)
 118 {
 119   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 120   unsigned long instruction;
 121
 122   /* Keep reading though instructions, until we come across an instruction
 123      that isn't likely to be part of the prologue.  */
 124   info->size = 0;
 125   for (; pc < limit; pc += 4)
 126     {
 127
 128       /* Read an instruction.  */
 129       instruction = read_memory_integer (pc, 4, byte_order);
 130
 131       if ((LM32_OPCODE (instruction) == OP_SW)
 132           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 133         {
 134           /* Any stack displaced store is likely part of the prologue.
 135              Record that the register is being saved, and the offset
 136              into the stack.  */
 137           info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
 138         }
 139       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 140                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 141         {
 142           /* An add to the SP is likely to be part of the prologue.
 143              Adjust stack size by whatever the instruction adds to the sp.  */
 144           info->size -= LM32_IMM16 (instruction);
 145         }
 146       else if (                 /* add fp,fp,sp */
 147                 ((LM32_OPCODE (instruction) == OP_ADD)
 148                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 149                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 150                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 151                 /* mv fp,imm */
 152                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 153                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 154                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 155         {
 156           /* Likely to be in the prologue for functions that require
 157              a frame pointer.  */
 158         }
 159       else
 160         {
 161           /* Any other instruction is likely not to be part of the
 162              prologue.  */
 163           break;
 164         }
 165     }
 166
 167   return pc;
 168 }
 169
 170 /* Return PC of first non prologue instruction, for the function at the
 171    specified address.  */
 172
 173 static CORE_ADDR
 174 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 175 {
 176   CORE_ADDR func_addr, limit_pc;
 177   struct lm32_frame_cache frame_info;
 178   trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 179
 180   /* See if we can determine the end of the prologue via the symbol table.
 181      If so, then return either PC, or the PC after the prologue, whichever
 182      is greater.  */
 183   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 184     {
 185       CORE_ADDR post_prologue_pc
 186         = skip_prologue_using_sal (gdbarch, func_addr);
 187       if (post_prologue_pc != 0)
 188         return std::max (pc, post_prologue_pc);
 189     }
 190
 191   /* Can't determine prologue from the symbol table, need to examine
 192      instructions.  */
 193
 194   /* Find an upper limit on the function prologue using the debug
 195      information.  If the debug information could not be used to provide
 196      that bound, then use an arbitrary large number as the upper bound.  */
 197   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 198   if (limit_pc == 0)
 199     limit_pc = pc + 100;        /* Magic.  */
 200
 201   frame_info.saved_regs = saved_regs;
 202   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 203 }
 204
 205 /* Create a breakpoint instruction.  */
 206 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 207
 208 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 209
 210
 211 /* Setup registers and stack for faking a call to a function in the
 212    inferior.  */
 213
 214 static CORE_ADDR
 215 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 216                       struct regcache *regcache, CORE_ADDR bp_addr,
 217                       int nargs, struct value **args, CORE_ADDR sp,
 218                       function_call_return_method return_method,
 219                       CORE_ADDR struct_addr)
 220 {
 221   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 222   int first_arg_reg = SIM_LM32_R1_REGNUM;
 223   int num_arg_regs = 8;
 224   int i;
 225
 226   /* Set the return address.  */
 227   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 228
 229   /* If we're returning a large struct, a pointer to the address to
 230      store it at is passed as a first hidden parameter.  */
 231   if (return_method == return_method_struct)
 232     {
 233       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 234       first_arg_reg++;
 235       num_arg_regs--;
 236       sp -= 4;
 237     }
 238
 239   /* Setup parameters.  */
 240   for (i = 0; i < nargs; i++)
 241     {
 242       struct value *arg = args[i];
 243       struct type *arg_type = check_typedef (value_type (arg));
 244       gdb_byte *contents;
 245       ULONGEST val;
 246
 247       /* Promote small integer types to int.  */
 248       switch (arg_type->code ())
 249         {
 250         case TYPE_CODE_INT:
 251         case TYPE_CODE_BOOL:
 252         case TYPE_CODE_CHAR:
 253         case TYPE_CODE_RANGE:
 254         case TYPE_CODE_ENUM:
 255           if (TYPE_LENGTH (arg_type) < 4)
 256             {
 257               arg_type = builtin_type (gdbarch)->builtin_int32;
 258               arg = value_cast (arg_type, arg);
 259             }
 260           break;
 261         }
 262
 263       /* FIXME: Handle structures.  */
 264
 265       contents = (gdb_byte *) value_contents (arg).data ();
 266       val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
 267                                       byte_order);
 268
 269       /* First num_arg_regs parameters are passed by registers,
 270          and the rest are passed on the stack.  */
 271       if (i < num_arg_regs)
 272         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 273       else
 274         {
 275           write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
 276                                          val);
 277           sp -= 4;
 278         }
 279     }
 280
 281   /* Update stack pointer.  */
 282   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 283
 284   /* Return adjusted stack pointer.  */
 285   return sp;
 286 }
 287
 288 /* Extract return value after calling a function in the inferior.  */
 289
 290 static void
 291 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 292                            gdb_byte *valbuf)
 293 {
 294   struct gdbarch *gdbarch = regcache->arch ();
 295   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 296   ULONGEST l;
 297   CORE_ADDR return_buffer;
 298
 299   if (type->code () != TYPE_CODE_STRUCT
 300       && type->code () != TYPE_CODE_UNION
 301       && type->code () != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 302     {
 303       /* Return value is returned in a single register.  */
 304       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 305       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 306     }
 307   else if ((type->code () == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 308     {
 309       /* 64-bit values are returned in a register pair.  */
 310       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 311       memcpy (valbuf, &l, 4);
 312       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 313       memcpy (valbuf + 4, &l, 4);
 314     }
 315   else
 316     {
 317       /* Aggregate types greater than a single register are returned
 318          in memory.  FIXME: Unless they are only 2 regs?.  */
 319       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 320       return_buffer = l;
 321       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 322     }
 323 }
 324
 325 /* Write into appropriate registers a function return value of type
 326    TYPE, given in virtual format.  */
 327 static void
 328 lm32_store_return_value (struct type *type, struct regcache *regcache,
 329                          const gdb_byte *valbuf)
 330 {
 331   struct gdbarch *gdbarch = regcache->arch ();
 332   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 333   ULONGEST val;
 334   int len = TYPE_LENGTH (type);
 335
 336   if (len <= 4)
 337     {
 338       val = extract_unsigned_integer (valbuf, len, byte_order);
 339       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 340     }
 341   else if (len <= 8)
 342     {
 343       val = extract_unsigned_integer (valbuf, 4, byte_order);
 344       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 345       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 346       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 347     }
 348   else
 349     error (_("lm32_store_return_value: type length too large."));
 350 }
 351
 352 /* Determine whether a functions return value is in a register or memory.  */
 353 static enum return_value_convention
 354 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 355                    struct type *valtype, struct regcache *regcache,
 356                    gdb_byte *readbuf, const gdb_byte *writebuf)
 357 {
 358   enum type_code code = valtype->code ();
 359
 360   if (code == TYPE_CODE_STRUCT
 361       || code == TYPE_CODE_UNION
 362       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 363     return RETURN_VALUE_STRUCT_CONVENTION;
 364
 365   if (readbuf)
 366     lm32_extract_return_value (valtype, regcache, readbuf);
 367   if (writebuf)
 368     lm32_store_return_value (valtype, regcache, writebuf);
 369
 370   return RETURN_VALUE_REGISTER_CONVENTION;
 371 }
 372
 373 /* Put here the code to store, into fi->saved_regs, the addresses of
 374    the saved registers of frame described by FRAME_INFO.  This
 375    includes special registers such as pc and fp saved in special ways
 376    in the stack frame.  sp is even more special: the address we return
 377    for it IS the sp for the next frame.  */
 378
 379 static struct lm32_frame_cache *
 380 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 381 {
 382   CORE_ADDR current_pc;
 383   ULONGEST prev_sp;
 384   ULONGEST this_base;
 385   struct lm32_frame_cache *info;
 386   int i;
 387
 388   if ((*this_prologue_cache))
 389     return (struct lm32_frame_cache *) (*this_prologue_cache);
 390
 391   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 392   (*this_prologue_cache) = info;
 393   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 394
 395   info->pc = get_frame_func (this_frame);
 396   current_pc = get_frame_pc (this_frame);
 397   lm32_analyze_prologue (get_frame_arch (this_frame),
 398                          info->pc, current_pc, info);
 399
 400   /* Compute the frame's base, and the previous frame's SP.  */
 401   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 402   prev_sp = this_base + info->size;
 403   info->base = this_base;
 404
 405   /* Convert callee save offsets into addresses.  */
 406   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 407     {
 408       if (info->saved_regs[i].is_addr ())
 409         info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
 410     }
 411
 412   /* The call instruction moves the caller's PC in the callee's RA register.
 413      Since this is an unwind, do the reverse.  Copy the location of RA register
 414      into PC (the address / regnum) so that a request for PC will be
 415      converted into a request for the RA register.  */
 416   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 417
 418   /* The previous frame's SP needed to be computed.  Save the computed
 419      value.  */
 420   info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
 421
 422   return info;
 423 }
 424
 425 static void
 426 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 427                     struct frame_id *this_id)
 428 {
 429   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 430
 431   /* This marks the outermost frame.  */
 432   if (cache->base == 0)
 433     return;
 434
 435   (*this_id) = frame_id_build (cache->base, cache->pc);
 436 }
 437
 438 static struct value *
 439 lm32_frame_prev_register (struct frame_info *this_frame,
 440                           void **this_prologue_cache, int regnum)
 441 {
 442   struct lm32_frame_cache *info;
 443
 444   info = lm32_frame_cache (this_frame, this_prologue_cache);
 445   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 446 }
 447
 448 static const struct frame_unwind lm32_frame_unwind = {
 449   "lm32 prologue",
 450   NORMAL_FRAME,
 451   default_frame_unwind_stop_reason,
 452   lm32_frame_this_id,
 453   lm32_frame_prev_register,
 454   NULL,
 455   default_frame_sniffer
 456 };
 457
 458 static CORE_ADDR
 459 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 460 {
 461   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 462
 463   return info->base;
 464 }
 465
 466 static const struct frame_base lm32_frame_base = {
 467   &lm32_frame_unwind,
 468   lm32_frame_base_address,
 469   lm32_frame_base_address,
 470   lm32_frame_base_address
 471 };
 472
 473 static CORE_ADDR
 474 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 475 {
 476   /* Align to the size of an instruction (so that they can safely be
 477      pushed onto the stack.  */
 478   return sp & ~3;
 479 }
 480
 481 static struct gdbarch *
 482 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 483 {
 484   struct gdbarch *gdbarch;
 485
 486   /* If there is already a candidate, use it.  */
 487   arches = gdbarch_list_lookup_by_info (arches, &info);
 488   if (arches != NULL)
 489     return arches->gdbarch;
 490
 491   /* None found, create a new architecture from the information provided.  */
 492   lm32_gdbarch_tdep *tdep = new lm32_gdbarch_tdep;
 493   gdbarch = gdbarch_alloc (&info, tdep);
 494
 495   /* Type sizes.  */
 496   set_gdbarch_short_bit (gdbarch, 16);
 497   set_gdbarch_int_bit (gdbarch, 32);
 498   set_gdbarch_long_bit (gdbarch, 32);
 499   set_gdbarch_long_long_bit (gdbarch, 64);
 500   set_gdbarch_float_bit (gdbarch, 32);
 501   set_gdbarch_double_bit (gdbarch, 64);
 502   set_gdbarch_long_double_bit (gdbarch, 64);
 503   set_gdbarch_ptr_bit (gdbarch, 32);
 504
 505   /* Register info.  */
 506   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 507   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 508   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 509   set_gdbarch_register_name (gdbarch, lm32_register_name);
 510   set_gdbarch_register_type (gdbarch, lm32_register_type);
 511   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 512
 513   /* Frame info.  */
 514   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 515   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 516   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 517   set_gdbarch_frame_args_skip (gdbarch, 0);
 518
 519   /* Frame unwinding.  */
 520   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 521   frame_base_set_default (gdbarch, &lm32_frame_base);
 522   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 523
 524   /* Breakpoints.  */
 525   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 526   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 527   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 528
 529   /* Calling functions in the inferior.  */
 530   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 531   set_gdbarch_return_value (gdbarch, lm32_return_value);
 532
 533   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 534
 535   return gdbarch;
 536 }
 537
 538 void _initialize_lm32_tdep ();
 539 void
 540 _initialize_lm32_tdep ()
 541 {
 542   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 543 }