gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2022 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "gdb/sim-lm32.h"
  31 #include "arch-utils.h"
  32 #include "regcache.h"
  33 #include "trad-frame.h"
  34 #include "reggroups.h"
  35 #include "opcodes/lm32-desc.h"
  36 #include <algorithm>
  37 #include "gdbarch.h"
  38
  39 /* Macros to extract fields from an instruction.  */
  40 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  41 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  42 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  43 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  44 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  45
  46 struct lm32_gdbarch_tdep : gdbarch_tdep
  47 {
  48   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  49 };
  50
  51 struct lm32_frame_cache
  52 {
  53   /* The frame's base.  Used when constructing a frame ID.  */
  54   CORE_ADDR base;
  55   CORE_ADDR pc;
  56   /* Size of frame.  */
  57   int size;
  58   /* Table indicating the location of each and every register.  */
  59   trad_frame_saved_reg *saved_regs;
  60 };
  61
  62 /* Add the available register groups.  */
  63
  64 static void
  65 lm32_add_reggroups (struct gdbarch *gdbarch)
  66 {
  67   reggroup_add (gdbarch, general_reggroup);
  68   reggroup_add (gdbarch, all_reggroup);
  69   reggroup_add (gdbarch, system_reggroup);
  70 }
  71
  72 /* Return whether a given register is in a given group.  */
  73
  74 static int
  75 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  76                           struct reggroup *group)
  77 {
  78   if (group == general_reggroup)
  79     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  80       || (regnum == SIM_LM32_PC_REGNUM);
  81   else if (group == system_reggroup)
  82     return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
  83       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  84   return default_register_reggroup_p (gdbarch, regnum, group);
  85 }
  86
  87 /* Return a name that corresponds to the given register number.  */
  88
  89 static const char *
  90 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  91 {
  92   static const char *register_names[] = {
  93     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  94     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  95     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  96     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  97     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
  98   };
  99
 100   if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
 101     return NULL;
 102   else
 103     return register_names[reg_nr];
 104 }
 105
 106 /* Return type of register.  */
 107
 108 static struct type *
 109 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 110 {
 111   return builtin_type (gdbarch)->builtin_int32;
 112 }
 113
 114 /* Return non-zero if a register can't be written.  */
 115
 116 static int
 117 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 118 {
 119   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 120 }
 121
 122 /* Analyze a function's prologue.  */
 123
 124 static CORE_ADDR
 125 lm32_analyze_prologue (struct gdbarch *gdbarch,
 126                        CORE_ADDR pc, CORE_ADDR limit,
 127                        struct lm32_frame_cache *info)
 128 {
 129   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 130   unsigned long instruction;
 131
 132   /* Keep reading though instructions, until we come across an instruction
 133      that isn't likely to be part of the prologue.  */
 134   info->size = 0;
 135   for (; pc < limit; pc += 4)
 136     {
 137
 138       /* Read an instruction.  */
 139       instruction = read_memory_integer (pc, 4, byte_order);
 140
 141       if ((LM32_OPCODE (instruction) == OP_SW)
 142           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 143         {
 144           /* Any stack displaced store is likely part of the prologue.
 145              Record that the register is being saved, and the offset
 146              into the stack.  */
 147           info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
 148         }
 149       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 150                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 151         {
 152           /* An add to the SP is likely to be part of the prologue.
 153              Adjust stack size by whatever the instruction adds to the sp.  */
 154           info->size -= LM32_IMM16 (instruction);
 155         }
 156       else if (                 /* add fp,fp,sp */
 157                 ((LM32_OPCODE (instruction) == OP_ADD)
 158                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 159                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 160                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 161                 /* mv fp,imm */
 162                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 163                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 164                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 165         {
 166           /* Likely to be in the prologue for functions that require
 167              a frame pointer.  */
 168         }
 169       else
 170         {
 171           /* Any other instruction is likely not to be part of the
 172              prologue.  */
 173           break;
 174         }
 175     }
 176
 177   return pc;
 178 }
 179
 180 /* Return PC of first non prologue instruction, for the function at the
 181    specified address.  */
 182
 183 static CORE_ADDR
 184 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 185 {
 186   CORE_ADDR func_addr, limit_pc;
 187   struct lm32_frame_cache frame_info;
 188   trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 189
 190   /* See if we can determine the end of the prologue via the symbol table.
 191      If so, then return either PC, or the PC after the prologue, whichever
 192      is greater.  */
 193   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 194     {
 195       CORE_ADDR post_prologue_pc
 196         = skip_prologue_using_sal (gdbarch, func_addr);
 197       if (post_prologue_pc != 0)
 198         return std::max (pc, post_prologue_pc);
 199     }
 200
 201   /* Can't determine prologue from the symbol table, need to examine
 202      instructions.  */
 203
 204   /* Find an upper limit on the function prologue using the debug
 205      information.  If the debug information could not be used to provide
 206      that bound, then use an arbitrary large number as the upper bound.  */
 207   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 208   if (limit_pc == 0)
 209     limit_pc = pc + 100;        /* Magic.  */
 210
 211   frame_info.saved_regs = saved_regs;
 212   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 213 }
 214
 215 /* Create a breakpoint instruction.  */
 216 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 217
 218 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 219
 220
 221 /* Setup registers and stack for faking a call to a function in the
 222    inferior.  */
 223
 224 static CORE_ADDR
 225 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 226                       struct regcache *regcache, CORE_ADDR bp_addr,
 227                       int nargs, struct value **args, CORE_ADDR sp,
 228                       function_call_return_method return_method,
 229                       CORE_ADDR struct_addr)
 230 {
 231   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 232   int first_arg_reg = SIM_LM32_R1_REGNUM;
 233   int num_arg_regs = 8;
 234   int i;
 235
 236   /* Set the return address.  */
 237   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 238
 239   /* If we're returning a large struct, a pointer to the address to
 240      store it at is passed as a first hidden parameter.  */
 241   if (return_method == return_method_struct)
 242     {
 243       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 244       first_arg_reg++;
 245       num_arg_regs--;
 246       sp -= 4;
 247     }
 248
 249   /* Setup parameters.  */
 250   for (i = 0; i < nargs; i++)
 251     {
 252       struct value *arg = args[i];
 253       struct type *arg_type = check_typedef (value_type (arg));
 254       gdb_byte *contents;
 255       ULONGEST val;
 256
 257       /* Promote small integer types to int.  */
 258       switch (arg_type->code ())
 259         {
 260         case TYPE_CODE_INT:
 261         case TYPE_CODE_BOOL:
 262         case TYPE_CODE_CHAR:
 263         case TYPE_CODE_RANGE:
 264         case TYPE_CODE_ENUM:
 265           if (TYPE_LENGTH (arg_type) < 4)
 266             {
 267               arg_type = builtin_type (gdbarch)->builtin_int32;
 268               arg = value_cast (arg_type, arg);
 269             }
 270           break;
 271         }
 272
 273       /* FIXME: Handle structures.  */
 274
 275       contents = (gdb_byte *) value_contents (arg).data ();
 276       val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
 277                                       byte_order);
 278
 279       /* First num_arg_regs parameters are passed by registers,
 280          and the rest are passed on the stack.  */
 281       if (i < num_arg_regs)
 282         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 283       else
 284         {
 285           write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
 286                                          val);
 287           sp -= 4;
 288         }
 289     }
 290
 291   /* Update stack pointer.  */
 292   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 293
 294   /* Return adjusted stack pointer.  */
 295   return sp;
 296 }
 297
 298 /* Extract return value after calling a function in the inferior.  */
 299
 300 static void
 301 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 302                            gdb_byte *valbuf)
 303 {
 304   struct gdbarch *gdbarch = regcache->arch ();
 305   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 306   ULONGEST l;
 307   CORE_ADDR return_buffer;
 308
 309   if (type->code () != TYPE_CODE_STRUCT
 310       && type->code () != TYPE_CODE_UNION
 311       && type->code () != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
 312     {
 313       /* Return value is returned in a single register.  */
 314       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 315       store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
 316     }
 317   else if ((type->code () == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
 318     {
 319       /* 64-bit values are returned in a register pair.  */
 320       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 321       memcpy (valbuf, &l, 4);
 322       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 323       memcpy (valbuf + 4, &l, 4);
 324     }
 325   else
 326     {
 327       /* Aggregate types greater than a single register are returned
 328          in memory.  FIXME: Unless they are only 2 regs?.  */
 329       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 330       return_buffer = l;
 331       read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
 332     }
 333 }
 334
 335 /* Write into appropriate registers a function return value of type
 336    TYPE, given in virtual format.  */
 337 static void
 338 lm32_store_return_value (struct type *type, struct regcache *regcache,
 339                          const gdb_byte *valbuf)
 340 {
 341   struct gdbarch *gdbarch = regcache->arch ();
 342   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 343   ULONGEST val;
 344   int len = TYPE_LENGTH (type);
 345
 346   if (len <= 4)
 347     {
 348       val = extract_unsigned_integer (valbuf, len, byte_order);
 349       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 350     }
 351   else if (len <= 8)
 352     {
 353       val = extract_unsigned_integer (valbuf, 4, byte_order);
 354       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 355       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 356       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 357     }
 358   else
 359     error (_("lm32_store_return_value: type length too large."));
 360 }
 361
 362 /* Determine whether a functions return value is in a register or memory.  */
 363 static enum return_value_convention
 364 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 365                    struct type *valtype, struct regcache *regcache,
 366                    gdb_byte *readbuf, const gdb_byte *writebuf)
 367 {
 368   enum type_code code = valtype->code ();
 369
 370   if (code == TYPE_CODE_STRUCT
 371       || code == TYPE_CODE_UNION
 372       || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
 373     return RETURN_VALUE_STRUCT_CONVENTION;
 374
 375   if (readbuf)
 376     lm32_extract_return_value (valtype, regcache, readbuf);
 377   if (writebuf)
 378     lm32_store_return_value (valtype, regcache, writebuf);
 379
 380   return RETURN_VALUE_REGISTER_CONVENTION;
 381 }
 382
 383 /* Put here the code to store, into fi->saved_regs, the addresses of
 384    the saved registers of frame described by FRAME_INFO.  This
 385    includes special registers such as pc and fp saved in special ways
 386    in the stack frame.  sp is even more special: the address we return
 387    for it IS the sp for the next frame.  */
 388
 389 static struct lm32_frame_cache *
 390 lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
 391 {
 392   CORE_ADDR current_pc;
 393   ULONGEST prev_sp;
 394   ULONGEST this_base;
 395   struct lm32_frame_cache *info;
 396   int i;
 397
 398   if ((*this_prologue_cache))
 399     return (struct lm32_frame_cache *) (*this_prologue_cache);
 400
 401   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 402   (*this_prologue_cache) = info;
 403   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 404
 405   info->pc = get_frame_func (this_frame);
 406   current_pc = get_frame_pc (this_frame);
 407   lm32_analyze_prologue (get_frame_arch (this_frame),
 408                          info->pc, current_pc, info);
 409
 410   /* Compute the frame's base, and the previous frame's SP.  */
 411   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 412   prev_sp = this_base + info->size;
 413   info->base = this_base;
 414
 415   /* Convert callee save offsets into addresses.  */
 416   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 417     {
 418       if (info->saved_regs[i].is_addr ())
 419         info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
 420     }
 421
 422   /* The call instruction moves the caller's PC in the callee's RA register.
 423      Since this is an unwind, do the reverse.  Copy the location of RA register
 424      into PC (the address / regnum) so that a request for PC will be
 425      converted into a request for the RA register.  */
 426   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 427
 428   /* The previous frame's SP needed to be computed.  Save the computed
 429      value.  */
 430   info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
 431
 432   return info;
 433 }
 434
 435 static void
 436 lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
 437                     struct frame_id *this_id)
 438 {
 439   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 440
 441   /* This marks the outermost frame.  */
 442   if (cache->base == 0)
 443     return;
 444
 445   (*this_id) = frame_id_build (cache->base, cache->pc);
 446 }
 447
 448 static struct value *
 449 lm32_frame_prev_register (struct frame_info *this_frame,
 450                           void **this_prologue_cache, int regnum)
 451 {
 452   struct lm32_frame_cache *info;
 453
 454   info = lm32_frame_cache (this_frame, this_prologue_cache);
 455   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 456 }
 457
 458 static const struct frame_unwind lm32_frame_unwind = {
 459   "lm32 prologue",
 460   NORMAL_FRAME,
 461   default_frame_unwind_stop_reason,
 462   lm32_frame_this_id,
 463   lm32_frame_prev_register,
 464   NULL,
 465   default_frame_sniffer
 466 };
 467
 468 static CORE_ADDR
 469 lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
 470 {
 471   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 472
 473   return info->base;
 474 }
 475
 476 static const struct frame_base lm32_frame_base = {
 477   &lm32_frame_unwind,
 478   lm32_frame_base_address,
 479   lm32_frame_base_address,
 480   lm32_frame_base_address
 481 };
 482
 483 static CORE_ADDR
 484 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 485 {
 486   /* Align to the size of an instruction (so that they can safely be
 487      pushed onto the stack.  */
 488   return sp & ~3;
 489 }
 490
 491 static struct gdbarch *
 492 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 493 {
 494   struct gdbarch *gdbarch;
 495
 496   /* If there is already a candidate, use it.  */
 497   arches = gdbarch_list_lookup_by_info (arches, &info);
 498   if (arches != NULL)
 499     return arches->gdbarch;
 500
 501   /* None found, create a new architecture from the information provided.  */
 502   lm32_gdbarch_tdep *tdep = new lm32_gdbarch_tdep;
 503   gdbarch = gdbarch_alloc (&info, tdep);
 504
 505   /* Type sizes.  */
 506   set_gdbarch_short_bit (gdbarch, 16);
 507   set_gdbarch_int_bit (gdbarch, 32);
 508   set_gdbarch_long_bit (gdbarch, 32);
 509   set_gdbarch_long_long_bit (gdbarch, 64);
 510   set_gdbarch_float_bit (gdbarch, 32);
 511   set_gdbarch_double_bit (gdbarch, 64);
 512   set_gdbarch_long_double_bit (gdbarch, 64);
 513   set_gdbarch_ptr_bit (gdbarch, 32);
 514
 515   /* Register info.  */
 516   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 517   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 518   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 519   set_gdbarch_register_name (gdbarch, lm32_register_name);
 520   set_gdbarch_register_type (gdbarch, lm32_register_type);
 521   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 522
 523   /* Frame info.  */
 524   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 525   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 526   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 527   set_gdbarch_frame_args_skip (gdbarch, 0);
 528
 529   /* Frame unwinding.  */
 530   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 531   frame_base_set_default (gdbarch, &lm32_frame_base);
 532   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 533
 534   /* Breakpoints.  */
 535   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 536   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 537   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 538
 539   /* Calling functions in the inferior.  */
 540   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 541   set_gdbarch_return_value (gdbarch, lm32_return_value);
 542
 543   lm32_add_reggroups (gdbarch);
 544   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 545
 546   return gdbarch;
 547 }
 548
 549 void _initialize_lm32_tdep ();
 550 void
 551 _initialize_lm32_tdep ()
 552 {
 553   register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
 554 }