1 /* Target-dependent code for Xilinx MicroBlaze.
3 Copyright (C) 2009-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
24 #include "trad-frame.h"
28 #include "breakpoint.h"
32 #include "frame-base.h"
33 #include "frame-unwind.h"
34 #include "dwarf2-frame.h"
37 #include "target-descriptions.h"
38 #include "opcodes/microblaze-opcm.h"
39 #include "opcodes/microblaze-dis.h"
40 #include "microblaze-tdep.h"
43 #include "features/microblaze-with-stack-protect.c"
44 #include "features/microblaze.c"
46 /* Instruction macros used for analyzing the prologue. */
47 /* This set of instruction macros need to be changed whenever the
48 prologue generated by the compiler could have more instructions or
49 different type of instructions.
50 This set also needs to be verified if it is complete. */
51 #define IS_RETURN(op) (op == rtsd || op == rtid)
52 #define IS_UPDATE_SP(op, rd, ra) \
53 ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP)
54 #define IS_SPILL_SP(op, rd, ra) \
55 ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP)
56 #define IS_SPILL_REG(op, rd, ra) \
57 ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP)
58 #define IS_ALSO_SPILL_REG(op, rd, ra, rb) \
59 ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP)
60 #define IS_SETUP_FP(op, ra, rb) \
61 ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0)
62 #define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \
63 ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0)
64 #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
65 ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
67 /* The registers of the Xilinx microblaze processor. */
69 static const char *microblaze_register_names
[] =
71 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
72 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
73 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
74 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
75 "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr",
76 "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
77 "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
78 "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
82 #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
84 static unsigned int microblaze_debug_flag
= 0;
87 microblaze_debug (const char *fmt
, ...)
89 if (microblaze_debug_flag
)
94 printf_unfiltered ("MICROBLAZE: ");
95 vprintf_unfiltered (fmt
, args
);
100 /* Return the name of register REGNUM. */
103 microblaze_register_name (struct gdbarch
*gdbarch
, int regnum
)
105 if (regnum
>= 0 && regnum
< MICROBLAZE_NUM_REGS
)
106 return microblaze_register_names
[regnum
];
111 microblaze_register_type (struct gdbarch
*gdbarch
, int regnum
)
113 if (regnum
== MICROBLAZE_SP_REGNUM
)
114 return builtin_type (gdbarch
)->builtin_data_ptr
;
116 if (regnum
== MICROBLAZE_PC_REGNUM
)
117 return builtin_type (gdbarch
)->builtin_func_ptr
;
119 return builtin_type (gdbarch
)->builtin_int
;
123 /* Fetch the instruction at PC. */
126 microblaze_fetch_instruction (CORE_ADDR pc
)
128 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
131 /* If we can't read the instruction at PC, return zero. */
132 if (target_read_code (pc
, buf
, sizeof (buf
)))
135 return extract_unsigned_integer (buf
, 4, byte_order
);
140 microblaze_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
142 struct value
**args
, int nargs
,
143 struct type
*value_type
,
144 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
145 struct regcache
*regcache
)
147 error (_("push_dummy_code not implemented"));
153 microblaze_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
154 struct regcache
*regcache
, CORE_ADDR bp_addr
,
155 int nargs
, struct value
**args
, CORE_ADDR sp
,
156 int struct_return
, CORE_ADDR struct_addr
)
158 error (_("store_arguments not implemented"));
162 static const gdb_byte
*
163 microblaze_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
,
166 static gdb_byte break_insn
[] = MICROBLAZE_BREAKPOINT
;
168 *len
= sizeof (break_insn
);
172 /* Allocate and initialize a frame cache. */
174 static struct microblaze_frame_cache
*
175 microblaze_alloc_frame_cache (void)
177 struct microblaze_frame_cache
*cache
;
179 cache
= FRAME_OBSTACK_ZALLOC (struct microblaze_frame_cache
);
185 /* Frameless until proven otherwise. */
186 cache
->frameless_p
= 1;
191 /* The base of the current frame is actually in the stack pointer.
192 This happens when there is no frame pointer (microblaze ABI does not
193 require a frame pointer) or when we're stopped in the prologue or
194 epilogue itself. In these cases, microblaze_analyze_prologue will need
195 to update fi->frame before returning or analyzing the register
196 save instructions. */
197 #define MICROBLAZE_MY_FRAME_IN_SP 0x1
199 /* The base of the current frame is in a frame pointer register.
200 This register is noted in frame_extra_info->fp_regnum.
202 Note that the existance of an FP might also indicate that the
203 function has called alloca. */
204 #define MICROBLAZE_MY_FRAME_IN_FP 0x2
206 /* Function prologues on the Xilinx microblaze processors consist of:
208 - adjustments to the stack pointer (r1) (addi r1, r1, imm)
209 - making a copy of r1 into another register (a "frame" pointer)
211 - store word/multiples that use r1 or the frame pointer as the
212 base address (swi r?, r1, imm OR swi r?, fp, imm)
214 Note that microblaze really doesn't have a real frame pointer.
215 Instead, the compiler may copy the SP into a register (usually
216 r19) to act as an arg pointer. For our target-dependent purposes,
217 the frame info's "frame" member will be the beginning of the
218 frame. The SP could, in fact, point below this.
220 The prologue ends when an instruction fails to meet either of
223 /* Analyze the prologue to determine where registers are saved,
224 the end of the prologue, etc. Return the address of the first line
225 of "real" code (i.e., the end of the prologue). */
228 microblaze_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
229 CORE_ADDR current_pc
,
230 struct microblaze_frame_cache
*cache
)
233 CORE_ADDR func_addr
, func_end
, addr
, stop
, prologue_end_addr
= 0;
236 enum microblaze_instr op
;
238 int save_hidden_pointer_found
= 0;
239 int non_stack_instruction_found
= 0;
241 /* Find the start of this function. */
242 find_pc_partial_function (pc
, &name
, &func_addr
, &func_end
);
249 /* Initialize info about frame. */
250 cache
->framesize
= 0;
251 cache
->fp_regnum
= MICROBLAZE_SP_REGNUM
;
252 cache
->frameless_p
= 1;
254 /* Start decoding the prologue. We start by checking two special cases:
256 1. We're about to return
257 2. We're at the first insn of the prologue.
259 If we're about to return, our frame has already been deallocated.
260 If we are stopped at the first instruction of a prologue,
261 then our frame has not yet been set up. */
263 /* Get the first insn from memory. */
265 insn
= microblaze_fetch_instruction (pc
);
266 op
= microblaze_decode_insn (insn
, &rd
, &ra
, &rb
, &imm
);
271 /* Start at beginning of function and analyze until we get to the
272 current pc, or the end of the function, whichever is first. */
273 stop
= (current_pc
< func_end
? current_pc
: func_end
);
275 microblaze_debug ("Scanning prologue: name=%s, func_addr=%s, stop=%s\n",
276 name
, paddress (gdbarch
, func_addr
),
277 paddress (gdbarch
, stop
));
279 for (addr
= func_addr
; addr
< stop
; addr
+= INST_WORD_SIZE
)
281 insn
= microblaze_fetch_instruction (addr
);
282 op
= microblaze_decode_insn (insn
, &rd
, &ra
, &rb
, &imm
);
283 microblaze_debug ("%s %08lx\n", paddress (gdbarch
, pc
), insn
);
285 /* This code is very sensitive to what functions are present in the
286 prologue. It assumes that the (addi, addik, swi, sw) can be the
287 only instructions in the prologue. */
288 if (IS_UPDATE_SP(op
, rd
, ra
))
290 microblaze_debug ("got addi r1,r1,%d; contnuing\n", imm
);
291 if (cache
->framesize
)
292 break; /* break if framesize already computed. */
293 cache
->framesize
= -imm
; /* stack grows towards low memory. */
294 cache
->frameless_p
= 0; /* Frame found. */
295 save_hidden_pointer_found
= 0;
296 non_stack_instruction_found
= 0;
299 else if (IS_SPILL_SP(op
, rd
, ra
))
301 /* Spill stack pointer. */
302 cache
->register_offsets
[rd
] = imm
; /* SP spilled before updating. */
304 microblaze_debug ("swi r1 r1 %d, continuing\n", imm
);
305 save_hidden_pointer_found
= 0;
306 if (!cache
->framesize
)
307 non_stack_instruction_found
= 0;
310 else if (IS_SPILL_REG(op
, rd
, ra
))
312 /* Spill register. */
313 cache
->register_offsets
[rd
] = imm
- cache
->framesize
;
315 microblaze_debug ("swi %d r1 %d, continuing\n", rd
, imm
);
316 save_hidden_pointer_found
= 0;
317 if (!cache
->framesize
)
318 non_stack_instruction_found
= 0;
321 else if (IS_ALSO_SPILL_REG(op
, rd
, ra
, rb
))
323 /* Spill register. */
324 cache
->register_offsets
[rd
] = 0 - cache
->framesize
;
326 microblaze_debug ("sw %d r0 r1, continuing\n", rd
);
327 save_hidden_pointer_found
= 0;
328 if (!cache
->framesize
)
329 non_stack_instruction_found
= 0;
332 else if (IS_SETUP_FP(op
, ra
, rb
))
334 /* We have a frame pointer. Note the register which is
335 acting as the frame pointer. */
336 flags
|= MICROBLAZE_MY_FRAME_IN_FP
;
337 flags
&= ~MICROBLAZE_MY_FRAME_IN_SP
;
338 cache
->fp_regnum
= rd
;
339 microblaze_debug ("Found a frame pointer: r%d\n", cache
->fp_regnum
);
340 save_hidden_pointer_found
= 0;
341 if (!cache
->framesize
)
342 non_stack_instruction_found
= 0;
345 else if (IS_SPILL_REG_FP(op
, rd
, ra
, cache
->fp_regnum
))
347 /* reg spilled after updating. */
348 cache
->register_offsets
[rd
] = imm
- cache
->framesize
;
350 microblaze_debug ("swi %d %d %d, continuing\n", rd
, ra
, imm
);
351 save_hidden_pointer_found
= 0;
352 if (!cache
->framesize
)
353 non_stack_instruction_found
= 0;
356 else if (IS_SAVE_HIDDEN_PTR(op
, rd
, ra
, rb
))
358 /* If the first argument is a hidden pointer to the area where the
359 return structure is to be saved, then it is saved as part of the
362 microblaze_debug ("add %d %d %d, continuing\n", rd
, ra
, rb
);
363 save_hidden_pointer_found
= 1;
364 if (!cache
->framesize
)
365 non_stack_instruction_found
= 0;
369 /* As a result of the modification in the next step where we continue
370 to analyze the prologue till we reach a control flow instruction,
371 we need another variable to store when exactly a non-stack
372 instruction was encountered, which is the current definition
374 if (!non_stack_instruction_found
)
375 prologue_end_addr
= addr
;
376 non_stack_instruction_found
= 1;
378 /* When optimizations are enabled, it is not guaranteed that prologue
379 instructions are not mixed in with other instructions from the
380 program. Some programs show this behavior at -O2. This can be
381 avoided by adding -fno-schedule-insns2 switch as of now (edk 8.1)
382 In such cases, we scan the function until we see the first control
386 unsigned op
= (unsigned)insn
>> 26;
388 /* continue if not control flow (branch, return). */
389 if (op
!= 0x26 && op
!= 0x27 && op
!= 0x2d && op
!= 0x2e && op
!= 0x2f)
392 continue; /* continue if imm. */
395 /* This is not a prologue insn, so stop here. */
396 microblaze_debug ("insn is not a prologue insn -- ending scan\n");
400 microblaze_debug ("done analyzing prologue\n");
401 microblaze_debug ("prologue end = 0x%x\n", (int) addr
);
403 /* If the last instruction was an add rd, r5, r0 then don't count it as
404 part of the prologue. */
405 if (save_hidden_pointer_found
)
406 prologue_end_addr
-= INST_WORD_SIZE
;
408 return prologue_end_addr
;
412 microblaze_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
417 frame_unwind_register (next_frame
, MICROBLAZE_PC_REGNUM
, buf
);
418 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
419 /* For sentinel frame, return address is actual PC. For other frames,
420 return address is pc+8. This is a workaround because gcc does not
421 generate correct return address in CIE. */
422 if (frame_relative_level (next_frame
) >= 0)
427 /* Return PC of first real instruction of the function starting at
431 microblaze_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
433 struct symtab_and_line sal
;
434 CORE_ADDR func_start
, func_end
, ostart_pc
;
435 struct microblaze_frame_cache cache
;
437 /* This is the preferred method, find the end of the prologue by
438 using the debugging information. Debugging info does not always
439 give the right answer since parameters are stored on stack after this.
440 Always analyze the prologue. */
441 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
443 sal
= find_pc_line (func_start
, 0);
445 if (sal
.end
< func_end
446 && start_pc
<= sal
.end
)
450 ostart_pc
= microblaze_analyze_prologue (gdbarch
, func_start
, 0xffffffffUL
,
453 if (ostart_pc
> start_pc
)
460 static struct microblaze_frame_cache
*
461 microblaze_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
463 struct microblaze_frame_cache
*cache
;
464 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
471 cache
= microblaze_alloc_frame_cache ();
473 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
475 /* Clear offsets to saved regs in frame. */
476 for (rn
= 0; rn
< gdbarch_num_regs (gdbarch
); rn
++)
477 cache
->register_offsets
[rn
] = -1;
479 func
= get_frame_func (next_frame
);
481 cache
->pc
= get_frame_address_in_block (next_frame
);
487 microblaze_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
488 struct frame_id
*this_id
)
490 struct microblaze_frame_cache
*cache
=
491 microblaze_frame_cache (next_frame
, this_cache
);
493 /* This marks the outermost frame. */
494 if (cache
->base
== 0)
497 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
500 static struct value
*
501 microblaze_frame_prev_register (struct frame_info
*this_frame
,
502 void **this_cache
, int regnum
)
504 struct microblaze_frame_cache
*cache
=
505 microblaze_frame_cache (this_frame
, this_cache
);
507 if (cache
->frameless_p
)
509 if (regnum
== MICROBLAZE_PC_REGNUM
)
511 if (regnum
== MICROBLAZE_SP_REGNUM
)
513 return trad_frame_get_prev_register (this_frame
,
514 cache
->saved_regs
, regnum
);
517 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
522 static const struct frame_unwind microblaze_frame_unwind
=
525 default_frame_unwind_stop_reason
,
526 microblaze_frame_this_id
,
527 microblaze_frame_prev_register
,
529 default_frame_sniffer
533 microblaze_frame_base_address (struct frame_info
*next_frame
,
536 struct microblaze_frame_cache
*cache
=
537 microblaze_frame_cache (next_frame
, this_cache
);
542 static const struct frame_base microblaze_frame_base
=
544 µblaze_frame_unwind
,
545 microblaze_frame_base_address
,
546 microblaze_frame_base_address
,
547 microblaze_frame_base_address
550 /* Extract from an array REGBUF containing the (raw) register state, a
551 function return value of TYPE, and copy that into VALBUF. */
553 microblaze_extract_return_value (struct type
*type
, struct regcache
*regcache
,
558 /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */
559 switch (TYPE_LENGTH (type
))
561 case 1: /* return last byte in the register. */
562 regcache_cooked_read (regcache
, MICROBLAZE_RETVAL_REGNUM
, buf
);
563 memcpy(valbuf
, buf
+ MICROBLAZE_REGISTER_SIZE
- 1, 1);
565 case 2: /* return last 2 bytes in register. */
566 regcache_cooked_read (regcache
, MICROBLAZE_RETVAL_REGNUM
, buf
);
567 memcpy(valbuf
, buf
+ MICROBLAZE_REGISTER_SIZE
- 2, 2);
569 case 4: /* for sizes 4 or 8, copy the required length. */
571 regcache_cooked_read (regcache
, MICROBLAZE_RETVAL_REGNUM
, buf
);
572 regcache_cooked_read (regcache
, MICROBLAZE_RETVAL_REGNUM
+1, buf
+4);
573 memcpy (valbuf
, buf
, TYPE_LENGTH (type
));
576 internal_error (__FILE__
, __LINE__
,
577 _("Unsupported return value size requested"));
581 /* Store the return value in VALBUF (of type TYPE) where the caller
584 Integers up to four bytes are stored in r3.
586 Longs are stored in r3 (most significant word) and r4 (least
589 Small structures are always returned on stack. */
592 microblaze_store_return_value (struct type
*type
, struct regcache
*regcache
,
593 const gdb_byte
*valbuf
)
595 int len
= TYPE_LENGTH (type
);
598 memset (buf
, 0, sizeof(buf
));
600 /* Integral and pointer return values. */
604 gdb_assert (len
== 8);
605 memcpy (buf
, valbuf
, 8);
606 regcache_cooked_write (regcache
, MICROBLAZE_RETVAL_REGNUM
+1, buf
+ 4);
609 /* ??? Do we need to do any sign-extension here? */
610 memcpy (buf
+ 4 - len
, valbuf
, len
);
612 regcache_cooked_write (regcache
, MICROBLAZE_RETVAL_REGNUM
, buf
);
615 static enum return_value_convention
616 microblaze_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
617 struct type
*type
, struct regcache
*regcache
,
618 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
621 microblaze_extract_return_value (type
, regcache
, readbuf
);
623 microblaze_store_return_value (type
, regcache
, writebuf
);
625 return RETURN_VALUE_REGISTER_CONVENTION
;
629 microblaze_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
631 return (TYPE_LENGTH (type
) == 16);
635 microblaze_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
637 regcache_cooked_write_unsigned (regcache
, MICROBLAZE_PC_REGNUM
, pc
);
640 static int dwarf2_to_reg_map
[78] =
641 { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */
642 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */
643 8 /* r8 */, 9 /* r9 */, 10 /* r10 */, 11 /* r11 */, /* 8-11 */
644 12 /* r12 */, 13 /* r13 */, 14 /* r14 */, 15 /* r15 */, /* 12-15 */
645 16 /* r16 */, 17 /* r17 */, 18 /* r18 */, 19 /* r19 */, /* 16-19 */
646 20 /* r20 */, 21 /* r21 */, 22 /* r22 */, 23 /* r23 */, /* 20-23 */
647 24 /* r24 */, 25 /* r25 */, 26 /* r26 */, 27 /* r27 */, /* 24-25 */
648 28 /* r28 */, 29 /* r29 */, 30 /* r30 */, 31 /* r31 */, /* 28-31 */
649 -1 /* $f0 */, -1 /* $f1 */, -1 /* $f2 */, -1 /* $f3 */, /* 32-35 */
650 -1 /* $f4 */, -1 /* $f5 */, -1 /* $f6 */, -1 /* $f7 */, /* 36-39 */
651 -1 /* $f8 */, -1 /* $f9 */, -1 /* $f10 */, -1 /* $f11 */, /* 40-43 */
652 -1 /* $f12 */, -1 /* $f13 */, -1 /* $f14 */, -1 /* $f15 */, /* 44-47 */
653 -1 /* $f16 */, -1 /* $f17 */, -1 /* $f18 */, -1 /* $f19 */, /* 48-51 */
654 -1 /* $f20 */, -1 /* $f21 */, -1 /* $f22 */, -1 /* $f23 */, /* 52-55 */
655 -1 /* $f24 */, -1 /* $f25 */, -1 /* $f26 */, -1 /* $f27 */, /* 56-59 */
656 -1 /* $f28 */, -1 /* $f29 */, -1 /* $f30 */, -1 /* $f31 */, /* 60-63 */
657 -1 /* hi */, -1 /* lo */, -1 /* accum*/, 33 /* rmsr */, /* 64-67 */
658 -1 /* $fcc1*/, -1 /* $fcc2*/, -1 /* $fcc3*/, -1 /* $fcc4*/, /* 68-71 */
659 -1 /* $fcc5*/, -1 /* $fcc6*/, -1 /* $fcc7*/, -1 /* $ap */, /* 72-75 */
660 -1 /* $rap */, -1 /* $frp */ /* 76-77 */
664 microblaze_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
666 gdb_assert ((size_t) reg
< sizeof (dwarf2_to_reg_map
));
667 return dwarf2_to_reg_map
[reg
];
671 microblaze_register_g_packet_guesses (struct gdbarch
*gdbarch
)
673 register_remote_g_packet_guess (gdbarch
,
674 4 * MICROBLAZE_NUM_CORE_REGS
,
677 register_remote_g_packet_guess (gdbarch
,
678 4 * MICROBLAZE_NUM_REGS
,
679 tdesc_microblaze_with_stack_protect
);
682 static struct gdbarch
*
683 microblaze_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
685 struct gdbarch_tdep
*tdep
;
686 struct gdbarch
*gdbarch
;
687 struct tdesc_arch_data
*tdesc_data
= NULL
;
688 const struct target_desc
*tdesc
= info
.target_desc
;
690 /* If there is already a candidate, use it. */
691 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
693 return arches
->gdbarch
;
695 tdesc
= tdesc_microblaze
;
697 /* Check any target description for validity. */
698 if (tdesc_has_registers (tdesc
))
700 const struct tdesc_feature
*feature
;
704 feature
= tdesc_find_feature (tdesc
,
705 "org.gnu.gdb.microblaze.core");
708 tdesc_data
= tdesc_data_alloc ();
711 for (i
= 0; i
< MICROBLAZE_NUM_CORE_REGS
; i
++)
712 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
713 microblaze_register_names
[i
]);
714 feature
= tdesc_find_feature (tdesc
,
715 "org.gnu.gdb.microblaze.stack-protect");
719 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
720 MICROBLAZE_SLR_REGNUM
,
722 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
723 MICROBLAZE_SHR_REGNUM
,
728 /* Allocate space for the new architecture. */
729 tdep
= XNEW (struct gdbarch_tdep
);
730 gdbarch
= gdbarch_alloc (&info
, tdep
);
732 set_gdbarch_long_double_bit (gdbarch
, 128);
734 set_gdbarch_num_regs (gdbarch
, MICROBLAZE_NUM_REGS
);
735 set_gdbarch_register_name (gdbarch
, microblaze_register_name
);
736 set_gdbarch_register_type (gdbarch
, microblaze_register_type
);
738 /* Register numbers of various important registers. */
739 set_gdbarch_sp_regnum (gdbarch
, MICROBLAZE_SP_REGNUM
);
740 set_gdbarch_pc_regnum (gdbarch
, MICROBLAZE_PC_REGNUM
);
742 /* Map Dwarf2 registers to GDB registers. */
743 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, microblaze_dwarf2_reg_to_regnum
);
745 /* Call dummy code. */
746 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
747 set_gdbarch_push_dummy_code (gdbarch
, microblaze_push_dummy_code
);
748 set_gdbarch_push_dummy_call (gdbarch
, microblaze_push_dummy_call
);
750 set_gdbarch_return_value (gdbarch
, microblaze_return_value
);
751 set_gdbarch_stabs_argument_has_addr
752 (gdbarch
, microblaze_stabs_argument_has_addr
);
754 set_gdbarch_skip_prologue (gdbarch
, microblaze_skip_prologue
);
756 /* Stack grows downward. */
757 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
759 set_gdbarch_breakpoint_from_pc (gdbarch
, microblaze_breakpoint_from_pc
);
761 set_gdbarch_frame_args_skip (gdbarch
, 8);
763 set_gdbarch_print_insn (gdbarch
, print_insn_microblaze
);
765 set_gdbarch_write_pc (gdbarch
, microblaze_write_pc
);
767 set_gdbarch_unwind_pc (gdbarch
, microblaze_unwind_pc
);
769 microblaze_register_g_packet_guesses (gdbarch
);
771 frame_base_set_default (gdbarch
, µblaze_frame_base
);
773 /* Hook in ABI-specific overrides, if they have been registered. */
774 gdbarch_init_osabi (info
, gdbarch
);
776 /* Unwind the frame. */
777 dwarf2_append_unwinders (gdbarch
);
778 frame_unwind_append_unwinder (gdbarch
, µblaze_frame_unwind
);
779 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
780 if (tdesc_data
!= NULL
)
781 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
786 /* Provide a prototype to silence -Wmissing-prototypes. */
787 void _initialize_microblaze_tdep (void);
790 _initialize_microblaze_tdep (void)
792 register_gdbarch_init (bfd_arch_microblaze
, microblaze_gdbarch_init
);
794 initialize_tdesc_microblaze_with_stack_protect ();
795 initialize_tdesc_microblaze ();
796 /* Debug this files internals. */
797 add_setshow_zuinteger_cmd ("microblaze", class_maintenance
,
798 µblaze_debug_flag
, _("\
799 Set microblaze debugging."), _("\
800 Show microblaze debugging."), _("\
801 When non-zero, microblaze specific debugging is enabled."),
804 &setdebuglist
, &showdebuglist
);