1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
110 static int mips_debug
= 0;
112 /* MIPS specific per-architecture information */
115 /* from the elf header */
118 enum mips_abi mips_abi
;
119 const char *mips_abi_string
;
120 enum mips_fpu_type mips_fpu_type
;
121 int mips_last_arg_regnum
;
122 int mips_last_fp_arg_regnum
;
123 int mips_default_saved_regsize
;
124 int mips_fp_register_double
;
125 int mips_regs_have_home_p
;
126 int mips_default_stack_argsize
;
127 int gdb_target_is_mips64
;
128 int default_mask_address_p
;
133 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
134 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
138 #undef MIPS_LAST_FP_ARG_REGNUM
139 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
143 #undef MIPS_LAST_ARG_REGNUM
144 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
149 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
152 /* Return the currently configured (or set) saved register size. */
155 #undef MIPS_DEFAULT_SAVED_REGSIZE
156 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
157 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
158 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* Indicate that the ABI makes use of double-precision registers
177 provided by the FPU (rather than combining pairs of registers to
178 form double-precision values). Do not use "TARGET_IS_MIPS64" to
179 determine if the ABI is using double-precision registers. See also
182 #undef FP_REGISTER_DOUBLE
183 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
186 /* Does the caller allocate a ``home'' for each register used in the
187 function call? The N32 ABI and MIPS_EABI do not, the others do. */
190 #undef MIPS_REGS_HAVE_HOME_P
191 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
192 #elif !defined (MIPS_REGS_HAVE_HOME_P)
193 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
196 /* The amount of space reserved on the stack for registers. This is
197 different to MIPS_SAVED_REGSIZE as it determines the alignment of
198 data allocated after the registers have run out. */
201 #undef MIPS_DEFAULT_STACK_ARGSIZE
202 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
203 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
204 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
207 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
209 static const char *mips_stack_argsize_string
= size_auto
;
212 mips_stack_argsize (void)
214 if (mips_stack_argsize_string
== size_auto
)
215 return MIPS_DEFAULT_STACK_ARGSIZE
;
216 else if (mips_stack_argsize_string
== size_64
)
218 else /* if (mips_stack_argsize_string == size_32) */
223 #undef GDB_TARGET_IS_MIPS64
224 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
228 #undef MIPS_DEFAULT_MASK_ADDRESS_P
229 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
230 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
231 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
234 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
236 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
238 static void mips_print_register (int, int);
240 static mips_extra_func_info_t
241 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
243 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
245 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
247 int mips_set_processor_type (char *);
249 static void mips_show_processor_type_command (char *, int);
251 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
253 static mips_extra_func_info_t
254 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
256 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
257 mips_extra_func_info_t proc_desc
);
259 /* This value is the model of MIPS in use. It is derived from the value
260 of the PrID register. */
262 char *mips_processor_type
;
264 char *tmp_mips_processor_type
;
266 /* The list of available "set mips " and "show mips " commands */
268 static struct cmd_list_element
*setmipscmdlist
= NULL
;
269 static struct cmd_list_element
*showmipscmdlist
= NULL
;
271 /* A set of original names, to be used when restoring back to generic
272 registers from a specific set. */
274 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
275 char **mips_processor_reg_names
= mips_generic_reg_names
;
278 mips_register_name (int i
)
280 return mips_processor_reg_names
[i
];
283 /* Names of IDT R3041 registers. */
285 char *mips_r3041_reg_names
[] = {
286 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
287 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
288 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
289 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
290 "sr", "lo", "hi", "bad", "cause","pc",
291 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
292 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
293 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
294 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
295 "fsr", "fir", "fp", "",
296 "", "", "bus", "ccfg", "", "", "", "",
297 "", "", "port", "cmp", "", "", "epc", "prid",
300 /* Names of IDT R3051 registers. */
302 char *mips_r3051_reg_names
[] = {
303 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
304 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
305 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
306 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
307 "sr", "lo", "hi", "bad", "cause","pc",
308 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
309 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
310 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
311 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
312 "fsr", "fir", "fp", "",
313 "inx", "rand", "elo", "", "ctxt", "", "", "",
314 "", "", "ehi", "", "", "", "epc", "prid",
317 /* Names of IDT R3081 registers. */
319 char *mips_r3081_reg_names
[] = {
320 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
321 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
322 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
323 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
324 "sr", "lo", "hi", "bad", "cause","pc",
325 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
326 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
327 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
328 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
329 "fsr", "fir", "fp", "",
330 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
331 "", "", "ehi", "", "", "", "epc", "prid",
334 /* Names of LSI 33k registers. */
336 char *mips_lsi33k_reg_names
[] = {
337 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
338 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
339 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
340 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
341 "epc", "hi", "lo", "sr", "cause","badvaddr",
342 "dcic", "bpc", "bda", "", "", "", "", "",
343 "", "", "", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
345 "", "", "", "", "", "", "", "",
347 "", "", "", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
354 } mips_processor_type_table
[] = {
355 { "generic", mips_generic_reg_names
},
356 { "r3041", mips_r3041_reg_names
},
357 { "r3051", mips_r3051_reg_names
},
358 { "r3071", mips_r3081_reg_names
},
359 { "r3081", mips_r3081_reg_names
},
360 { "lsi33k", mips_lsi33k_reg_names
},
368 /* Table to translate MIPS16 register field to actual register number. */
369 static int mips16_to_32_reg
[8] =
370 {16, 17, 2, 3, 4, 5, 6, 7};
372 /* Heuristic_proc_start may hunt through the text section for a long
373 time across a 2400 baud serial line. Allows the user to limit this
376 static unsigned int heuristic_fence_post
= 0;
378 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
379 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
380 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
381 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
382 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
383 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
384 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
385 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
386 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
387 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
388 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
389 #define _PROC_MAGIC_ 0x0F0F0F0F
390 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
391 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
393 struct linked_proc_info
395 struct mips_extra_func_info info
;
396 struct linked_proc_info
*next
;
398 *linked_proc_desc_table
= NULL
;
401 mips_print_extra_frame_info (struct frame_info
*fi
)
405 && fi
->extra_info
->proc_desc
406 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
407 printf_filtered (" frame pointer is at %s+%s\n",
408 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
409 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
412 /* Convert between RAW and VIRTUAL registers. The RAW register size
413 defines the remote-gdb packet. */
415 static int mips64_transfers_32bit_regs_p
= 0;
418 mips_register_raw_size (int reg_nr
)
420 if (mips64_transfers_32bit_regs_p
)
421 return REGISTER_VIRTUAL_SIZE (reg_nr
);
427 mips_register_convertible (int reg_nr
)
429 if (mips64_transfers_32bit_regs_p
)
432 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
436 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
437 char *raw_buf
, char *virt_buf
)
439 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
441 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
442 TYPE_LENGTH (virtual_type
));
446 TYPE_LENGTH (virtual_type
));
450 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
451 char *virt_buf
, char *raw_buf
)
453 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
454 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
455 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
457 TYPE_LENGTH (virtual_type
));
461 TYPE_LENGTH (virtual_type
));
464 /* Should the upper word of 64-bit addresses be zeroed? */
465 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
468 mips_mask_address_p (void)
470 switch (mask_address_var
)
472 case CMD_AUTO_BOOLEAN_TRUE
:
474 case CMD_AUTO_BOOLEAN_FALSE
:
477 case CMD_AUTO_BOOLEAN_AUTO
:
478 return MIPS_DEFAULT_MASK_ADDRESS_P
;
480 internal_error (__FILE__
, __LINE__
,
481 "mips_mask_address_p: bad switch");
487 show_mask_address (char *cmd
, int from_tty
)
489 switch (mask_address_var
)
491 case CMD_AUTO_BOOLEAN_TRUE
:
492 printf_filtered ("The 32 bit mips address mask is enabled\n");
494 case CMD_AUTO_BOOLEAN_FALSE
:
495 printf_filtered ("The 32 bit mips address mask is disabled\n");
497 case CMD_AUTO_BOOLEAN_AUTO
:
498 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
499 mips_mask_address_p () ? "enabled" : "disabled");
502 internal_error (__FILE__
, __LINE__
,
503 "show_mask_address: bad switch");
508 /* Should call_function allocate stack space for a struct return? */
510 mips_use_struct_convention (int gcc_p
, struct type
*type
)
513 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
515 return 1; /* Structures are returned by ref in extra arg0 */
518 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
521 pc_is_mips16 (bfd_vma memaddr
)
523 struct minimal_symbol
*sym
;
525 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
526 if (IS_MIPS16_ADDR (memaddr
))
529 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
530 the high bit of the info field. Use this to decide if the function is
531 MIPS16 or normal MIPS. */
532 sym
= lookup_minimal_symbol_by_pc (memaddr
);
534 return MSYMBOL_IS_SPECIAL (sym
);
539 /* MIPS believes that the PC has a sign extended value. Perhaphs the
540 all registers should be sign extended for simplicity? */
543 mips_read_pc (int pid
)
545 return read_signed_register_pid (PC_REGNUM
, pid
);
548 /* This returns the PC of the first inst after the prologue. If we can't
549 find the prologue, then return 0. */
552 after_prologue (CORE_ADDR pc
,
553 mips_extra_func_info_t proc_desc
)
555 struct symtab_and_line sal
;
556 CORE_ADDR func_addr
, func_end
;
559 proc_desc
= find_proc_desc (pc
, NULL
);
563 /* If function is frameless, then we need to do it the hard way. I
564 strongly suspect that frameless always means prologueless... */
565 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
566 && PROC_FRAME_OFFSET (proc_desc
) == 0)
570 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
571 return 0; /* Unknown */
573 sal
= find_pc_line (func_addr
, 0);
575 if (sal
.end
< func_end
)
578 /* The line after the prologue is after the end of the function. In this
579 case, tell the caller to find the prologue the hard way. */
584 /* Decode a MIPS32 instruction that saves a register in the stack, and
585 set the appropriate bit in the general register mask or float register mask
586 to indicate which register is saved. This is a helper function
587 for mips_find_saved_regs. */
590 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
591 unsigned long *float_mask
)
595 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
596 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
597 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
599 /* It might be possible to use the instruction to
600 find the offset, rather than the code below which
601 is based on things being in a certain order in the
602 frame, but figuring out what the instruction's offset
603 is relative to might be a little tricky. */
604 reg
= (inst
& 0x001f0000) >> 16;
605 *gen_mask
|= (1 << reg
);
607 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
608 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
609 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
612 reg
= ((inst
& 0x001f0000) >> 16);
613 *float_mask
|= (1 << reg
);
617 /* Decode a MIPS16 instruction that saves a register in the stack, and
618 set the appropriate bit in the general register or float register mask
619 to indicate which register is saved. This is a helper function
620 for mips_find_saved_regs. */
623 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
625 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
627 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
628 *gen_mask
|= (1 << reg
);
630 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
632 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
633 *gen_mask
|= (1 << reg
);
635 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
636 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
637 *gen_mask
|= (1 << RA_REGNUM
);
641 /* Fetch and return instruction from the specified location. If the PC
642 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
645 mips_fetch_instruction (CORE_ADDR addr
)
647 char buf
[MIPS_INSTLEN
];
651 if (pc_is_mips16 (addr
))
653 instlen
= MIPS16_INSTLEN
;
654 addr
= UNMAKE_MIPS16_ADDR (addr
);
657 instlen
= MIPS_INSTLEN
;
658 status
= read_memory_nobpt (addr
, buf
, instlen
);
660 memory_error (status
, addr
);
661 return extract_unsigned_integer (buf
, instlen
);
665 /* These the fields of 32 bit mips instructions */
666 #define mips32_op(x) (x >> 25)
667 #define itype_op(x) (x >> 25)
668 #define itype_rs(x) ((x >> 21)& 0x1f)
669 #define itype_rt(x) ((x >> 16) & 0x1f)
670 #define itype_immediate(x) ( x & 0xffff)
672 #define jtype_op(x) (x >> 25)
673 #define jtype_target(x) ( x & 0x03fffff)
675 #define rtype_op(x) (x >>25)
676 #define rtype_rs(x) ((x>>21) & 0x1f)
677 #define rtype_rt(x) ((x>>16) & 0x1f)
678 #define rtype_rd(x) ((x>>11) & 0x1f)
679 #define rtype_shamt(x) ((x>>6) & 0x1f)
680 #define rtype_funct(x) (x & 0x3f )
683 mips32_relative_offset (unsigned long inst
)
686 x
= itype_immediate (inst
);
687 if (x
& 0x8000) /* sign bit set */
689 x
|= 0xffff0000; /* sign extension */
695 /* Determine whate to set a single step breakpoint while considering
698 mips32_next_pc (CORE_ADDR pc
)
702 inst
= mips_fetch_instruction (pc
);
703 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
705 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
707 op
= ((inst
>> 25) & 0x03);
711 goto equal_branch
; /* BEQL */
713 goto neq_branch
; /* BNEZ */
715 goto less_branch
; /* BLEZ */
717 goto greater_branch
; /* BGTZ */
723 pc
+= 4; /* Not a branch, next instruction is easy */
726 { /* This gets way messy */
728 /* Further subdivide into SPECIAL, REGIMM and other */
729 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
731 case 0: /* SPECIAL */
732 op
= rtype_funct (inst
);
737 /* Set PC to that address */
738 pc
= read_signed_register (rtype_rs (inst
));
744 break; /* end special */
747 op
= jtype_op (inst
); /* branch condition */
748 switch (jtype_op (inst
))
752 case 16: /* BLTZALL */
753 case 18: /* BLTZALL */
755 if (read_signed_register (itype_rs (inst
)) < 0)
756 pc
+= mips32_relative_offset (inst
) + 4;
758 pc
+= 8; /* after the delay slot */
762 case 17: /* BGEZAL */
763 case 19: /* BGEZALL */
764 greater_equal_branch
:
765 if (read_signed_register (itype_rs (inst
)) >= 0)
766 pc
+= mips32_relative_offset (inst
) + 4;
768 pc
+= 8; /* after the delay slot */
770 /* All of the other intructions in the REGIMM catagory */
775 break; /* end REGIMM */
780 reg
= jtype_target (inst
) << 2;
781 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
782 /* Whats this mysterious 0xf000000 adjustment ??? */
785 /* FIXME case JALX : */
788 reg
= jtype_target (inst
) << 2;
789 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
790 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
792 break; /* The new PC will be alternate mode */
793 case 4: /* BEQ , BEQL */
795 if (read_signed_register (itype_rs (inst
)) ==
796 read_signed_register (itype_rt (inst
)))
797 pc
+= mips32_relative_offset (inst
) + 4;
801 case 5: /* BNE , BNEL */
803 if (read_signed_register (itype_rs (inst
)) !=
804 read_signed_register (itype_rs (inst
)))
805 pc
+= mips32_relative_offset (inst
) + 4;
809 case 6: /* BLEZ , BLEZL */
811 if (read_signed_register (itype_rs (inst
) <= 0))
812 pc
+= mips32_relative_offset (inst
) + 4;
817 greater_branch
: /* BGTZ BGTZL */
818 if (read_signed_register (itype_rs (inst
) > 0))
819 pc
+= mips32_relative_offset (inst
) + 4;
828 } /* mips32_next_pc */
830 /* Decoding the next place to set a breakpoint is irregular for the
831 mips 16 variant, but fortunately, there fewer instructions. We have to cope
832 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
833 We dont want to set a single step instruction on the extend instruction
837 /* Lots of mips16 instruction formats */
838 /* Predicting jumps requires itype,ritype,i8type
839 and their extensions extItype,extritype,extI8type
841 enum mips16_inst_fmts
843 itype
, /* 0 immediate 5,10 */
844 ritype
, /* 1 5,3,8 */
845 rrtype
, /* 2 5,3,3,5 */
846 rritype
, /* 3 5,3,3,5 */
847 rrrtype
, /* 4 5,3,3,3,2 */
848 rriatype
, /* 5 5,3,3,1,4 */
849 shifttype
, /* 6 5,3,3,3,2 */
850 i8type
, /* 7 5,3,8 */
851 i8movtype
, /* 8 5,3,3,5 */
852 i8mov32rtype
, /* 9 5,3,5,3 */
853 i64type
, /* 10 5,3,8 */
854 ri64type
, /* 11 5,3,3,5 */
855 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
856 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
857 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
858 extRRItype
, /* 15 5,5,5,5,3,3,5 */
859 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
860 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
861 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
862 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
863 extRi64type
, /* 20 5,6,5,5,3,3,5 */
864 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
866 /* I am heaping all the fields of the formats into one structure and
867 then, only the fields which are involved in instruction extension */
871 unsigned int regx
; /* Function in i8 type */
876 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
877 for the bits which make up the immediatate extension. */
880 extended_offset (unsigned int extension
)
883 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
885 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
887 value
|= extension
& 0x01f; /* extract 4:0 */
891 /* Only call this function if you know that this is an extendable
892 instruction, It wont malfunction, but why make excess remote memory references?
893 If the immediate operands get sign extended or somthing, do it after
894 the extension is performed.
896 /* FIXME: Every one of these cases needs to worry about sign extension
897 when the offset is to be used in relative addressing */
901 fetch_mips_16 (CORE_ADDR pc
)
904 pc
&= 0xfffffffe; /* clear the low order bit */
905 target_read_memory (pc
, buf
, 2);
906 return extract_unsigned_integer (buf
, 2);
910 unpack_mips16 (CORE_ADDR pc
,
911 unsigned int extension
,
913 enum mips16_inst_fmts insn_format
,
914 struct upk_mips16
*upk
)
926 value
= extended_offset (extension
);
927 value
= value
<< 11; /* rom for the original value */
928 value
|= inst
& 0x7ff; /* eleven bits from instruction */
932 value
= inst
& 0x7ff;
933 /* FIXME : Consider sign extension */
942 { /* A register identifier and an offset */
943 /* Most of the fields are the same as I type but the
944 immediate value is of a different length */
948 value
= extended_offset (extension
);
949 value
= value
<< 8; /* from the original instruction */
950 value
|= inst
& 0xff; /* eleven bits from instruction */
951 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
952 if (value
& 0x4000) /* test the sign bit , bit 26 */
954 value
&= ~0x3fff; /* remove the sign bit */
960 value
= inst
& 0xff; /* 8 bits */
961 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
962 /* FIXME: Do sign extension , this format needs it */
963 if (value
& 0x80) /* THIS CONFUSES ME */
965 value
&= 0xef; /* remove the sign bit */
976 unsigned int nexthalf
;
977 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
979 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
987 internal_error (__FILE__
, __LINE__
,
990 upk
->offset
= offset
;
997 add_offset_16 (CORE_ADDR pc
, int offset
)
999 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1004 extended_mips16_next_pc (CORE_ADDR pc
,
1005 unsigned int extension
,
1008 int op
= (insn
>> 11);
1011 case 2: /* Branch */
1014 struct upk_mips16 upk
;
1015 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1016 offset
= upk
.offset
;
1022 pc
+= (offset
<< 1) + 2;
1025 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1027 struct upk_mips16 upk
;
1028 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1029 pc
= add_offset_16 (pc
, upk
.offset
);
1030 if ((insn
>> 10) & 0x01) /* Exchange mode */
1031 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1038 struct upk_mips16 upk
;
1040 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1041 reg
= read_signed_register (upk
.regx
);
1043 pc
+= (upk
.offset
<< 1) + 2;
1050 struct upk_mips16 upk
;
1052 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1053 reg
= read_signed_register (upk
.regx
);
1055 pc
+= (upk
.offset
<< 1) + 2;
1060 case 12: /* I8 Formats btez btnez */
1062 struct upk_mips16 upk
;
1064 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1065 /* upk.regx contains the opcode */
1066 reg
= read_signed_register (24); /* Test register is 24 */
1067 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1068 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1069 /* pc = add_offset_16(pc,upk.offset) ; */
1070 pc
+= (upk
.offset
<< 1) + 2;
1075 case 29: /* RR Formats JR, JALR, JALR-RA */
1077 struct upk_mips16 upk
;
1078 /* upk.fmt = rrtype; */
1083 upk
.regx
= (insn
>> 8) & 0x07;
1084 upk
.regy
= (insn
>> 5) & 0x07;
1092 break; /* Function return instruction */
1098 break; /* BOGUS Guess */
1100 pc
= read_signed_register (reg
);
1107 /* This is an instruction extension. Fetch the real instruction
1108 (which follows the extension) and decode things based on
1112 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1125 mips16_next_pc (CORE_ADDR pc
)
1127 unsigned int insn
= fetch_mips_16 (pc
);
1128 return extended_mips16_next_pc (pc
, 0, insn
);
1131 /* The mips_next_pc function supports single_step when the remote
1132 target monitor or stub is not developed enough to do a single_step.
1133 It works by decoding the current instruction and predicting where a
1134 branch will go. This isnt hard because all the data is available.
1135 The MIPS32 and MIPS16 variants are quite different */
1137 mips_next_pc (CORE_ADDR pc
)
1140 return mips16_next_pc (pc
);
1142 return mips32_next_pc (pc
);
1145 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1149 mips_find_saved_regs (struct frame_info
*fci
)
1152 CORE_ADDR reg_position
;
1153 /* r0 bit means kernel trap */
1155 /* What registers have been saved? Bitmasks. */
1156 unsigned long gen_mask
, float_mask
;
1157 mips_extra_func_info_t proc_desc
;
1160 frame_saved_regs_zalloc (fci
);
1162 /* If it is the frame for sigtramp, the saved registers are located
1163 in a sigcontext structure somewhere on the stack.
1164 If the stack layout for sigtramp changes we might have to change these
1165 constants and the companion fixup_sigtramp in mdebugread.c */
1166 #ifndef SIGFRAME_BASE
1167 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1168 above the sigtramp frame. */
1169 #define SIGFRAME_BASE MIPS_REGSIZE
1170 /* FIXME! Are these correct?? */
1171 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1172 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1173 #define SIGFRAME_FPREGSAVE_OFF \
1174 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1176 #ifndef SIGFRAME_REG_SIZE
1177 /* FIXME! Is this correct?? */
1178 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1180 if (fci
->signal_handler_caller
)
1182 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1184 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1185 + ireg
* SIGFRAME_REG_SIZE
;
1186 fci
->saved_regs
[ireg
] = reg_position
;
1188 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1190 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1191 + ireg
* SIGFRAME_REG_SIZE
;
1192 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1194 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1198 proc_desc
= fci
->extra_info
->proc_desc
;
1199 if (proc_desc
== NULL
)
1200 /* I'm not sure how/whether this can happen. Normally when we can't
1201 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1202 and set the saved_regs right away. */
1205 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1206 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1207 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1209 if ( /* In any frame other than the innermost or a frame interrupted by
1210 a signal, we assume that all registers have been saved.
1211 This assumes that all register saves in a function happen before
1212 the first function call. */
1213 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1215 /* In a dummy frame we know exactly where things are saved. */
1216 && !PROC_DESC_IS_DUMMY (proc_desc
)
1218 /* Don't bother unless we are inside a function prologue. Outside the
1219 prologue, we know where everything is. */
1221 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1223 /* Not sure exactly what kernel_trap means, but if it means
1224 the kernel saves the registers without a prologue doing it,
1225 we better not examine the prologue to see whether registers
1226 have been saved yet. */
1229 /* We need to figure out whether the registers that the proc_desc
1230 claims are saved have been saved yet. */
1234 /* Bitmasks; set if we have found a save for the register. */
1235 unsigned long gen_save_found
= 0;
1236 unsigned long float_save_found
= 0;
1239 /* If the address is odd, assume this is MIPS16 code. */
1240 addr
= PROC_LOW_ADDR (proc_desc
);
1241 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1243 /* Scan through this function's instructions preceding the current
1244 PC, and look for those that save registers. */
1245 while (addr
< fci
->pc
)
1247 inst
= mips_fetch_instruction (addr
);
1248 if (pc_is_mips16 (addr
))
1249 mips16_decode_reg_save (inst
, &gen_save_found
);
1251 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1254 gen_mask
= gen_save_found
;
1255 float_mask
= float_save_found
;
1258 /* Fill in the offsets for the registers which gen_mask says
1260 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1261 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1262 if (gen_mask
& 0x80000000)
1264 fci
->saved_regs
[ireg
] = reg_position
;
1265 reg_position
-= MIPS_SAVED_REGSIZE
;
1268 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1269 of that normally used by gcc. Therefore, we have to fetch the first
1270 instruction of the function, and if it's an entry instruction that
1271 saves $s0 or $s1, correct their saved addresses. */
1272 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1274 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1275 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1278 int sreg_count
= (inst
>> 6) & 3;
1280 /* Check if the ra register was pushed on the stack. */
1281 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1283 reg_position
-= MIPS_SAVED_REGSIZE
;
1285 /* Check if the s0 and s1 registers were pushed on the stack. */
1286 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1288 fci
->saved_regs
[reg
] = reg_position
;
1289 reg_position
-= MIPS_SAVED_REGSIZE
;
1294 /* Fill in the offsets for the registers which float_mask says
1296 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1298 /* The freg_offset points to where the first *double* register
1299 is saved. So skip to the high-order word. */
1300 if (!GDB_TARGET_IS_MIPS64
)
1301 reg_position
+= MIPS_SAVED_REGSIZE
;
1303 /* Fill in the offsets for the float registers which float_mask says
1305 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1306 if (float_mask
& 0x80000000)
1308 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1309 reg_position
-= MIPS_SAVED_REGSIZE
;
1312 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1316 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1318 for (; fi
; fi
= fi
->next
)
1320 /* We have to get the saved sp from the sigcontext
1321 if it is a signal handler frame. */
1322 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1326 if (fi
->saved_regs
== NULL
)
1327 mips_find_saved_regs (fi
);
1328 if (fi
->saved_regs
[regno
])
1329 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1332 return read_signed_register (regno
);
1335 /* mips_addr_bits_remove - remove useless address bits */
1338 mips_addr_bits_remove (CORE_ADDR addr
)
1340 if (GDB_TARGET_IS_MIPS64
)
1342 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1344 /* This hack is a work-around for existing boards using
1345 PMON, the simulator, and any other 64-bit targets that
1346 doesn't have true 64-bit addressing. On these targets,
1347 the upper 32 bits of addresses are ignored by the
1348 hardware. Thus, the PC or SP are likely to have been
1349 sign extended to all 1s by instruction sequences that
1350 load 32-bit addresses. For example, a typical piece of
1351 code that loads an address is this:
1352 lui $r2, <upper 16 bits>
1353 ori $r2, <lower 16 bits>
1354 But the lui sign-extends the value such that the upper 32
1355 bits may be all 1s. The workaround is simply to mask off
1356 these bits. In the future, gcc may be changed to support
1357 true 64-bit addressing, and this masking will have to be
1359 addr
&= (CORE_ADDR
) 0xffffffff;
1362 else if (mips_mask_address_p ())
1364 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1365 masking off bits, instead, the actual target should be asking
1366 for the address to be converted to a valid pointer. */
1367 /* Even when GDB is configured for some 32-bit targets
1368 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1369 so CORE_ADDR is 64 bits. So we still have to mask off
1370 useless bits from addresses. */
1371 addr
&= (CORE_ADDR
) 0xffffffff;
1377 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1381 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1382 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1383 tmp
= mips_skip_stub (pc
);
1384 prev
->pc
= tmp
? tmp
: pc
;
1389 mips_frame_saved_pc (struct frame_info
*frame
)
1392 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1393 /* We have to get the saved pc from the sigcontext
1394 if it is a signal handler frame. */
1395 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1396 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1398 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1399 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1401 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1403 return ADDR_BITS_REMOVE (saved_pc
);
1406 static struct mips_extra_func_info temp_proc_desc
;
1407 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1409 /* Set a register's saved stack address in temp_saved_regs. If an address
1410 has already been set for this register, do nothing; this way we will
1411 only recognize the first save of a given register in a function prologue.
1412 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1415 set_reg_offset (int regno
, CORE_ADDR offset
)
1417 if (temp_saved_regs
[regno
] == 0)
1418 temp_saved_regs
[regno
] = offset
;
1422 /* Test whether the PC points to the return instruction at the
1423 end of a function. */
1426 mips_about_to_return (CORE_ADDR pc
)
1428 if (pc_is_mips16 (pc
))
1429 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1430 generates a "jr $ra"; other times it generates code to load
1431 the return address from the stack to an accessible register (such
1432 as $a3), then a "jr" using that register. This second case
1433 is almost impossible to distinguish from an indirect jump
1434 used for switch statements, so we don't even try. */
1435 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1437 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1441 /* This fencepost looks highly suspicious to me. Removing it also
1442 seems suspicious as it could affect remote debugging across serial
1446 heuristic_proc_start (CORE_ADDR pc
)
1453 pc
= ADDR_BITS_REMOVE (pc
);
1455 fence
= start_pc
- heuristic_fence_post
;
1459 if (heuristic_fence_post
== UINT_MAX
1460 || fence
< VM_MIN_ADDRESS
)
1461 fence
= VM_MIN_ADDRESS
;
1463 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1465 /* search back for previous return */
1466 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1467 if (start_pc
< fence
)
1469 /* It's not clear to me why we reach this point when
1470 stop_soon_quietly, but with this test, at least we
1471 don't print out warnings for every child forked (eg, on
1472 decstation). 22apr93 rich@cygnus.com. */
1473 if (!stop_soon_quietly
)
1475 static int blurb_printed
= 0;
1477 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1482 /* This actually happens frequently in embedded
1483 development, when you first connect to a board
1484 and your stack pointer and pc are nowhere in
1485 particular. This message needs to give people
1486 in that situation enough information to
1487 determine that it's no big deal. */
1488 printf_filtered ("\n\
1489 GDB is unable to find the start of the function at 0x%s\n\
1490 and thus can't determine the size of that function's stack frame.\n\
1491 This means that GDB may be unable to access that stack frame, or\n\
1492 the frames below it.\n\
1493 This problem is most likely caused by an invalid program counter or\n\
1495 However, if you think GDB should simply search farther back\n\
1496 from 0x%s for code which looks like the beginning of a\n\
1497 function, you can increase the range of the search using the `set\n\
1498 heuristic-fence-post' command.\n",
1499 paddr_nz (pc
), paddr_nz (pc
));
1506 else if (pc_is_mips16 (start_pc
))
1508 unsigned short inst
;
1510 /* On MIPS16, any one of the following is likely to be the
1511 start of a function:
1515 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1516 inst
= mips_fetch_instruction (start_pc
);
1517 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1518 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1519 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1520 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1522 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1523 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1528 else if (mips_about_to_return (start_pc
))
1530 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1537 /* Fetch the immediate value from a MIPS16 instruction.
1538 If the previous instruction was an EXTEND, use it to extend
1539 the upper bits of the immediate value. This is a helper function
1540 for mips16_heuristic_proc_desc. */
1543 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1544 unsigned short inst
, /* current instruction */
1545 int nbits
, /* number of bits in imm field */
1546 int scale
, /* scale factor to be applied to imm */
1547 int is_signed
) /* is the imm field signed? */
1551 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1553 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1554 if (offset
& 0x8000) /* check for negative extend */
1555 offset
= 0 - (0x10000 - (offset
& 0xffff));
1556 return offset
| (inst
& 0x1f);
1560 int max_imm
= 1 << nbits
;
1561 int mask
= max_imm
- 1;
1562 int sign_bit
= max_imm
>> 1;
1564 offset
= inst
& mask
;
1565 if (is_signed
&& (offset
& sign_bit
))
1566 offset
= 0 - (max_imm
- offset
);
1567 return offset
* scale
;
1572 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1573 stream from start_pc to limit_pc. */
1576 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1577 struct frame_info
*next_frame
, CORE_ADDR sp
)
1580 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1581 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1582 unsigned inst
= 0; /* current instruction */
1583 unsigned entry_inst
= 0; /* the entry instruction */
1586 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1587 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1589 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1591 /* Save the previous instruction. If it's an EXTEND, we'll extract
1592 the immediate offset extension from it in mips16_get_imm. */
1595 /* Fetch and decode the instruction. */
1596 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1597 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1598 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1600 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1601 if (offset
< 0) /* negative stack adjustment? */
1602 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1604 /* Exit loop if a positive stack adjustment is found, which
1605 usually means that the stack cleanup code in the function
1606 epilogue is reached. */
1609 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1611 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1612 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1613 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1614 set_reg_offset (reg
, sp
+ offset
);
1616 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1618 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1619 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1620 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1621 set_reg_offset (reg
, sp
+ offset
);
1623 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1625 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1626 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1627 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1629 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1631 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1632 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1633 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1635 else if (inst
== 0x673d) /* move $s1, $sp */
1638 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1640 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1642 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1643 frame_addr
= sp
+ offset
;
1644 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1645 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1647 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1649 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1650 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1651 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1652 set_reg_offset (reg
, frame_addr
+ offset
);
1654 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1656 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1657 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1658 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1659 set_reg_offset (reg
, frame_addr
+ offset
);
1661 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1662 entry_inst
= inst
; /* save for later processing */
1663 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1664 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1667 /* The entry instruction is typically the first instruction in a function,
1668 and it stores registers at offsets relative to the value of the old SP
1669 (before the prologue). But the value of the sp parameter to this
1670 function is the new SP (after the prologue has been executed). So we
1671 can't calculate those offsets until we've seen the entire prologue,
1672 and can calculate what the old SP must have been. */
1673 if (entry_inst
!= 0)
1675 int areg_count
= (entry_inst
>> 8) & 7;
1676 int sreg_count
= (entry_inst
>> 6) & 3;
1678 /* The entry instruction always subtracts 32 from the SP. */
1679 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1681 /* Now we can calculate what the SP must have been at the
1682 start of the function prologue. */
1683 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1685 /* Check if a0-a3 were saved in the caller's argument save area. */
1686 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1688 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1689 set_reg_offset (reg
, sp
+ offset
);
1690 offset
+= MIPS_SAVED_REGSIZE
;
1693 /* Check if the ra register was pushed on the stack. */
1695 if (entry_inst
& 0x20)
1697 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1698 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1699 offset
-= MIPS_SAVED_REGSIZE
;
1702 /* Check if the s0 and s1 registers were pushed on the stack. */
1703 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1705 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1706 set_reg_offset (reg
, sp
+ offset
);
1707 offset
-= MIPS_SAVED_REGSIZE
;
1713 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1714 struct frame_info
*next_frame
, CORE_ADDR sp
)
1717 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1719 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1720 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1721 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1722 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1724 unsigned long inst
, high_word
, low_word
;
1727 /* Fetch the instruction. */
1728 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1730 /* Save some code by pre-extracting some useful fields. */
1731 high_word
= (inst
>> 16) & 0xffff;
1732 low_word
= inst
& 0xffff;
1733 reg
= high_word
& 0x1f;
1735 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1736 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1737 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1739 if (low_word
& 0x8000) /* negative stack adjustment? */
1740 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1742 /* Exit loop if a positive stack adjustment is found, which
1743 usually means that the stack cleanup code in the function
1744 epilogue is reached. */
1747 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1749 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1750 set_reg_offset (reg
, sp
+ low_word
);
1752 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1754 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1755 but the register size used is only 32 bits. Make the address
1756 for the saved register point to the lower 32 bits. */
1757 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1758 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1760 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1762 /* Old gcc frame, r30 is virtual frame pointer. */
1763 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1764 frame_addr
= sp
+ low_word
;
1765 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1767 unsigned alloca_adjust
;
1768 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1769 frame_addr
= read_next_frame_reg (next_frame
, 30);
1770 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1771 if (alloca_adjust
> 0)
1773 /* FP > SP + frame_size. This may be because
1774 * of an alloca or somethings similar.
1775 * Fix sp to "pre-alloca" value, and try again.
1777 sp
+= alloca_adjust
;
1782 /* move $30,$sp. With different versions of gas this will be either
1783 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1784 Accept any one of these. */
1785 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1787 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1788 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1790 unsigned alloca_adjust
;
1791 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1792 frame_addr
= read_next_frame_reg (next_frame
, 30);
1793 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1794 if (alloca_adjust
> 0)
1796 /* FP > SP + frame_size. This may be because
1797 * of an alloca or somethings similar.
1798 * Fix sp to "pre-alloca" value, and try again.
1800 sp
+= alloca_adjust
;
1805 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1807 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1808 set_reg_offset (reg
, frame_addr
+ low_word
);
1813 static mips_extra_func_info_t
1814 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1815 struct frame_info
*next_frame
)
1817 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1821 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1822 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1823 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1824 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1825 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1827 if (start_pc
+ 200 < limit_pc
)
1828 limit_pc
= start_pc
+ 200;
1829 if (pc_is_mips16 (start_pc
))
1830 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1832 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1833 return &temp_proc_desc
;
1836 static mips_extra_func_info_t
1837 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1839 CORE_ADDR startaddr
;
1840 mips_extra_func_info_t proc_desc
;
1841 struct block
*b
= block_for_pc (pc
);
1844 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1846 *addrptr
= startaddr
;
1847 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1851 if (startaddr
> BLOCK_START (b
))
1852 /* This is the "pathological" case referred to in a comment in
1853 print_frame_info. It might be better to move this check into
1857 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1860 /* If we never found a PDR for this function in symbol reading, then
1861 examine prologues to find the information. */
1864 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1865 if (PROC_FRAME_REG (proc_desc
) == -1)
1875 static mips_extra_func_info_t
1876 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
1878 mips_extra_func_info_t proc_desc
;
1879 CORE_ADDR startaddr
;
1881 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1885 /* IF this is the topmost frame AND
1886 * (this proc does not have debugging information OR
1887 * the PC is in the procedure prologue)
1888 * THEN create a "heuristic" proc_desc (by analyzing
1889 * the actual code) to replace the "official" proc_desc.
1891 if (next_frame
== NULL
)
1893 struct symtab_and_line val
;
1894 struct symbol
*proc_symbol
=
1895 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1899 val
= find_pc_line (BLOCK_START
1900 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1902 val
.pc
= val
.end
? val
.end
: pc
;
1904 if (!proc_symbol
|| pc
< val
.pc
)
1906 mips_extra_func_info_t found_heuristic
=
1907 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1909 if (found_heuristic
)
1910 proc_desc
= found_heuristic
;
1916 /* Is linked_proc_desc_table really necessary? It only seems to be used
1917 by procedure call dummys. However, the procedures being called ought
1918 to have their own proc_descs, and even if they don't,
1919 heuristic_proc_desc knows how to create them! */
1921 register struct linked_proc_info
*link
;
1923 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1924 if (PROC_LOW_ADDR (&link
->info
) <= pc
1925 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1929 startaddr
= heuristic_proc_start (pc
);
1932 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1938 get_frame_pointer (struct frame_info
*frame
,
1939 mips_extra_func_info_t proc_desc
)
1941 return ADDR_BITS_REMOVE (
1942 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1943 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1946 mips_extra_func_info_t cached_proc_desc
;
1949 mips_frame_chain (struct frame_info
*frame
)
1951 mips_extra_func_info_t proc_desc
;
1953 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1955 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1958 /* Check if the PC is inside a call stub. If it is, fetch the
1959 PC of the caller of that stub. */
1960 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1963 /* Look up the procedure descriptor for this PC. */
1964 proc_desc
= find_proc_desc (saved_pc
, frame
);
1968 cached_proc_desc
= proc_desc
;
1970 /* If no frame pointer and frame size is zero, we must be at end
1971 of stack (or otherwise hosed). If we don't check frame size,
1972 we loop forever if we see a zero size frame. */
1973 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1974 && PROC_FRAME_OFFSET (proc_desc
) == 0
1975 /* The previous frame from a sigtramp frame might be frameless
1976 and have frame size zero. */
1977 && !frame
->signal_handler_caller
)
1980 return get_frame_pointer (frame
, proc_desc
);
1984 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
1988 /* Use proc_desc calculated in frame_chain */
1989 mips_extra_func_info_t proc_desc
=
1990 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1992 fci
->extra_info
= (struct frame_extra_info
*)
1993 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1995 fci
->saved_regs
= NULL
;
1996 fci
->extra_info
->proc_desc
=
1997 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2000 /* Fixup frame-pointer - only needed for top frame */
2001 /* This may not be quite right, if proc has a real frame register.
2002 Get the value of the frame relative sp, procedure might have been
2003 interrupted by a signal at it's very start. */
2004 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2005 && !PROC_DESC_IS_DUMMY (proc_desc
))
2006 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2008 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2010 if (proc_desc
== &temp_proc_desc
)
2014 /* Do not set the saved registers for a sigtramp frame,
2015 mips_find_saved_registers will do that for us.
2016 We can't use fci->signal_handler_caller, it is not yet set. */
2017 find_pc_partial_function (fci
->pc
, &name
,
2018 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2019 if (!IN_SIGTRAMP (fci
->pc
, name
))
2021 frame_saved_regs_zalloc (fci
);
2022 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2023 fci
->saved_regs
[PC_REGNUM
]
2024 = fci
->saved_regs
[RA_REGNUM
];
2028 /* hack: if argument regs are saved, guess these contain args */
2029 /* assume we can't tell how many args for now */
2030 fci
->extra_info
->num_args
= -1;
2031 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2033 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2035 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2042 /* MIPS stack frames are almost impenetrable. When execution stops,
2043 we basically have to look at symbol information for the function
2044 that we stopped in, which tells us *which* register (if any) is
2045 the base of the frame pointer, and what offset from that register
2046 the frame itself is at.
2048 This presents a problem when trying to examine a stack in memory
2049 (that isn't executing at the moment), using the "frame" command. We
2050 don't have a PC, nor do we have any registers except SP.
2052 This routine takes two arguments, SP and PC, and tries to make the
2053 cached frames look as if these two arguments defined a frame on the
2054 cache. This allows the rest of info frame to extract the important
2055 arguments without difficulty. */
2058 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2061 error ("MIPS frame specifications require two arguments: sp and pc");
2063 return create_new_frame (argv
[0], argv
[1]);
2066 /* According to the current ABI, should the type be passed in a
2067 floating-point register (assuming that there is space)? When there
2068 is no FPU, FP are not even considered as possibile candidates for
2069 FP registers and, consequently this returns false - forces FP
2070 arguments into integer registers. */
2073 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2075 return ((typecode
== TYPE_CODE_FLT
2077 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2078 && TYPE_NFIELDS (arg_type
) == 1
2079 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2080 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2084 mips_push_arguments (int nargs
,
2088 CORE_ADDR struct_addr
)
2094 int stack_offset
= 0;
2096 /* Macros to round N up or down to the next A boundary; A must be
2098 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2099 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2101 /* First ensure that the stack and structure return address (if any)
2102 are properly aligned. The stack has to be at least 64-bit aligned
2103 even on 32-bit machines, because doubles must be 64-bit aligned.
2104 On at least one MIPS variant, stack frames need to be 128-bit
2105 aligned, so we round to this widest known alignment. */
2106 sp
= ROUND_DOWN (sp
, 16);
2107 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2109 /* Now make space on the stack for the args. We allocate more
2110 than necessary for EABI, because the first few arguments are
2111 passed in registers, but that's OK. */
2112 for (argnum
= 0; argnum
< nargs
; argnum
++)
2113 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2114 sp
-= ROUND_UP (len
, 16);
2117 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2118 (long) sp
, ROUND_UP (len
, 16));
2120 /* Initialize the integer and float register pointers. */
2122 float_argreg
= FPA0_REGNUM
;
2124 /* the struct_return pointer occupies the first parameter-passing reg */
2128 fprintf_unfiltered (gdb_stdlog
,
2129 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2130 argreg
, (long) struct_addr
);
2131 write_register (argreg
++, struct_addr
);
2132 if (MIPS_REGS_HAVE_HOME_P
)
2133 stack_offset
+= MIPS_STACK_ARGSIZE
;
2136 /* Now load as many as possible of the first arguments into
2137 registers, and push the rest onto the stack. Loop thru args
2138 from first to last. */
2139 for (argnum
= 0; argnum
< nargs
; argnum
++)
2142 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2143 value_ptr arg
= args
[argnum
];
2144 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2145 int len
= TYPE_LENGTH (arg_type
);
2146 enum type_code typecode
= TYPE_CODE (arg_type
);
2149 fprintf_unfiltered (gdb_stdlog
,
2150 "mips_push_arguments: %d len=%d type=%d",
2151 argnum
+ 1, len
, (int) typecode
);
2153 /* The EABI passes structures that do not fit in a register by
2154 reference. In all other cases, pass the structure by value. */
2156 && len
> MIPS_SAVED_REGSIZE
2157 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2159 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2160 typecode
= TYPE_CODE_PTR
;
2161 len
= MIPS_SAVED_REGSIZE
;
2164 fprintf_unfiltered (gdb_stdlog
, " push");
2167 val
= (char *) VALUE_CONTENTS (arg
);
2169 /* 32-bit ABIs always start floating point arguments in an
2170 even-numbered floating point register. Round the FP register
2171 up before the check to see if there are any FP registers
2172 left. Non MIPS_EABI targets also pass the FP in the integer
2173 registers so also round up normal registers. */
2174 if (!FP_REGISTER_DOUBLE
2175 && fp_register_arg_p (typecode
, arg_type
))
2177 if ((float_argreg
& 1))
2181 /* Floating point arguments passed in registers have to be
2182 treated specially. On 32-bit architectures, doubles
2183 are passed in register pairs; the even register gets
2184 the low word, and the odd register gets the high word.
2185 On non-EABI processors, the first two floating point arguments are
2186 also copied to general registers, because MIPS16 functions
2187 don't use float registers for arguments. This duplication of
2188 arguments in general registers can't hurt non-MIPS16 functions
2189 because those registers are normally skipped. */
2190 /* MIPS_EABI squeeses a struct that contains a single floating
2191 point value into an FP register instead of pusing it onto the
2193 if (fp_register_arg_p (typecode
, arg_type
)
2194 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2196 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2198 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2199 unsigned long regval
;
2201 /* Write the low word of the double to the even register(s). */
2202 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2204 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2205 float_argreg
, phex (regval
, 4));
2206 write_register (float_argreg
++, regval
);
2210 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2211 argreg
, phex (regval
, 4));
2212 write_register (argreg
++, regval
);
2215 /* Write the high word of the double to the odd register(s). */
2216 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2218 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2219 float_argreg
, phex (regval
, 4));
2220 write_register (float_argreg
++, regval
);
2224 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2225 argreg
, phex (regval
, 4));
2226 write_register (argreg
++, regval
);
2232 /* This is a floating point value that fits entirely
2233 in a single register. */
2234 /* On 32 bit ABI's the float_argreg is further adjusted
2235 above to ensure that it is even register aligned. */
2236 LONGEST regval
= extract_unsigned_integer (val
, len
);
2238 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2239 float_argreg
, phex (regval
, len
));
2240 write_register (float_argreg
++, regval
);
2243 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2244 registers for each argument. The below is (my
2245 guess) to ensure that the corresponding integer
2246 register has reserved the same space. */
2248 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2249 argreg
, phex (regval
, len
));
2250 write_register (argreg
, regval
);
2251 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2254 /* Reserve space for the FP register. */
2255 if (MIPS_REGS_HAVE_HOME_P
)
2256 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2260 /* Copy the argument to general registers or the stack in
2261 register-sized pieces. Large arguments are split between
2262 registers and stack. */
2263 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2264 are treated specially: Irix cc passes them in registers
2265 where gcc sometimes puts them on the stack. For maximum
2266 compatibility, we will put them in both places. */
2267 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2268 (len
% MIPS_SAVED_REGSIZE
!= 0));
2269 /* Note: Floating-point values that didn't fit into an FP
2270 register are only written to memory. */
2273 /* Rememer if the argument was written to the stack. */
2274 int stack_used_p
= 0;
2275 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2278 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2281 /* Write this portion of the argument to the stack. */
2282 if (argreg
> MIPS_LAST_ARG_REGNUM
2284 || fp_register_arg_p (typecode
, arg_type
))
2286 /* Should shorter than int integer values be
2287 promoted to int before being stored? */
2288 int longword_offset
= 0;
2291 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2293 if (MIPS_STACK_ARGSIZE
== 8 &&
2294 (typecode
== TYPE_CODE_INT
||
2295 typecode
== TYPE_CODE_PTR
||
2296 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2297 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2298 else if ((typecode
== TYPE_CODE_STRUCT
||
2299 typecode
== TYPE_CODE_UNION
) &&
2300 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2301 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2306 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2307 (long) stack_offset
);
2308 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2309 (long) longword_offset
);
2312 addr
= sp
+ stack_offset
+ longword_offset
;
2317 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2318 for (i
= 0; i
< partial_len
; i
++)
2320 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2323 write_memory (addr
, val
, partial_len
);
2326 /* Note!!! This is NOT an else clause. Odd sized
2327 structs may go thru BOTH paths. Floating point
2328 arguments will not. */
2329 /* Write this portion of the argument to a general
2330 purpose register. */
2331 if (argreg
<= MIPS_LAST_ARG_REGNUM
2332 && !fp_register_arg_p (typecode
, arg_type
))
2334 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2336 /* A non-floating-point argument being passed in a
2337 general register. If a struct or union, and if
2338 the remaining length is smaller than the register
2339 size, we have to adjust the register value on
2342 It does not seem to be necessary to do the
2343 same for integral types.
2345 Also don't do this adjustment on EABI and O64
2349 && MIPS_SAVED_REGSIZE
< 8
2350 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2351 && partial_len
< MIPS_SAVED_REGSIZE
2352 && (typecode
== TYPE_CODE_STRUCT
||
2353 typecode
== TYPE_CODE_UNION
))
2354 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2358 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2360 phex (regval
, MIPS_SAVED_REGSIZE
));
2361 write_register (argreg
, regval
);
2364 /* If this is the old ABI, prevent subsequent floating
2365 point arguments from being passed in floating point
2368 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2374 /* Compute the the offset into the stack at which we
2375 will copy the next parameter.
2377 In older ABIs, the caller reserved space for
2378 registers that contained arguments. This was loosely
2379 refered to as their "home". Consequently, space is
2382 In the new EABI (and the NABI32), the stack_offset
2383 only needs to be adjusted when it has been used.. */
2385 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2386 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2390 fprintf_unfiltered (gdb_stdlog
, "\n");
2393 /* Return adjusted stack pointer. */
2398 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2400 /* Set the return address register to point to the entry
2401 point of the program, where a breakpoint lies in wait. */
2402 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2407 mips_push_register (CORE_ADDR
* sp
, int regno
)
2409 char buffer
[MAX_REGISTER_RAW_SIZE
];
2412 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2414 regsize
= MIPS_SAVED_REGSIZE
;
2415 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2416 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2421 regsize
= REGISTER_RAW_SIZE (regno
);
2425 read_register_gen (regno
, buffer
);
2426 write_memory (*sp
, buffer
+ offset
, regsize
);
2429 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2430 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2433 mips_push_dummy_frame (void)
2436 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2437 xmalloc (sizeof (struct linked_proc_info
));
2438 mips_extra_func_info_t proc_desc
= &link
->info
;
2439 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2440 CORE_ADDR old_sp
= sp
;
2441 link
->next
= linked_proc_desc_table
;
2442 linked_proc_desc_table
= link
;
2444 /* FIXME! are these correct ? */
2445 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2446 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2447 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2448 #define FLOAT_SINGLE_REG_SAVE_MASK \
2449 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2451 * The registers we must save are all those not preserved across
2452 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2453 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2454 * and FP Control/Status registers.
2457 * Dummy frame layout:
2460 * Saved MMHI, MMLO, FPC_CSR
2465 * Saved D18 (i.e. F19, F18)
2467 * Saved D0 (i.e. F1, F0)
2468 * Argument build area and stack arguments written via mips_push_arguments
2472 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2473 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2474 PROC_FRAME_OFFSET (proc_desc
) = 0;
2475 PROC_FRAME_ADJUST (proc_desc
) = 0;
2476 mips_push_register (&sp
, PC_REGNUM
);
2477 mips_push_register (&sp
, HI_REGNUM
);
2478 mips_push_register (&sp
, LO_REGNUM
);
2479 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2481 /* Save general CPU registers */
2482 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2483 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2484 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2485 for (ireg
= 32; --ireg
>= 0;)
2486 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2487 mips_push_register (&sp
, ireg
);
2489 /* Save floating point registers starting with high order word */
2490 PROC_FREG_MASK (proc_desc
) =
2491 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2492 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2493 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2495 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2496 for (ireg
= 32; --ireg
>= 0;)
2497 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2498 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2500 /* Update the frame pointer for the call dummy and the stack pointer.
2501 Set the procedure's starting and ending addresses to point to the
2502 call dummy address at the entry point. */
2503 write_register (PUSH_FP_REGNUM
, old_sp
);
2504 write_register (SP_REGNUM
, sp
);
2505 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2506 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2507 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2508 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2512 mips_pop_frame (void)
2514 register int regnum
;
2515 struct frame_info
*frame
= get_current_frame ();
2516 CORE_ADDR new_sp
= FRAME_FP (frame
);
2518 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2520 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2521 if (frame
->saved_regs
== NULL
)
2522 mips_find_saved_regs (frame
);
2523 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2525 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2526 && frame
->saved_regs
[regnum
])
2527 write_register (regnum
,
2528 read_memory_integer (frame
->saved_regs
[regnum
],
2529 MIPS_SAVED_REGSIZE
));
2531 write_register (SP_REGNUM
, new_sp
);
2532 flush_cached_frames ();
2534 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2536 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2538 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2540 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2542 if (&pi_ptr
->info
== proc_desc
)
2547 error ("Can't locate dummy extra frame info\n");
2549 if (prev_ptr
!= NULL
)
2550 prev_ptr
->next
= pi_ptr
->next
;
2552 linked_proc_desc_table
= pi_ptr
->next
;
2556 write_register (HI_REGNUM
,
2557 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2558 MIPS_SAVED_REGSIZE
));
2559 write_register (LO_REGNUM
,
2560 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2561 MIPS_SAVED_REGSIZE
));
2562 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2563 write_register (FCRCS_REGNUM
,
2564 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2565 MIPS_SAVED_REGSIZE
));
2570 mips_print_register (int regnum
, int all
)
2572 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2574 /* Get the data in raw format. */
2575 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2577 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2581 /* If an even floating point register, also print as double. */
2582 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2583 && !((regnum
- FP0_REGNUM
) & 1))
2584 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2586 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2588 read_relative_register_raw_bytes (regnum
, dbuffer
);
2589 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2590 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2592 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2593 val_print (builtin_type_double
, dbuffer
, 0, 0,
2594 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2595 printf_filtered ("); ");
2597 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2599 /* The problem with printing numeric register names (r26, etc.) is that
2600 the user can't use them on input. Probably the best solution is to
2601 fix it so that either the numeric or the funky (a2, etc.) names
2602 are accepted on input. */
2603 if (regnum
< MIPS_NUMREGS
)
2604 printf_filtered ("(r%d): ", regnum
);
2606 printf_filtered (": ");
2608 /* If virtual format is floating, print it that way. */
2609 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2610 if (FP_REGISTER_DOUBLE
)
2611 { /* show 8-byte floats as float AND double: */
2612 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2614 printf_filtered (" (float) ");
2615 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2616 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2617 printf_filtered (", (double) ");
2618 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2619 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2622 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2623 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2624 /* Else print as integer in hex. */
2629 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2630 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2634 print_scalar_formatted (raw_buffer
+ offset
,
2635 REGISTER_VIRTUAL_TYPE (regnum
),
2636 'x', 0, gdb_stdout
);
2640 /* Replacement for generic do_registers_info.
2641 Print regs in pretty columns. */
2644 do_fp_register_row (int regnum
)
2645 { /* do values for FP (float) regs */
2646 char *raw_buffer
[2];
2648 /* use HI and LO to control the order of combining two flt regs */
2649 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2650 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2651 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2652 int inv1
, inv2
, inv3
;
2654 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2655 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2656 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2658 /* Get the data in raw format. */
2659 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2660 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2661 if (REGISTER_RAW_SIZE (regnum
) == 4)
2663 /* 4-byte registers: we can fit two registers per row. */
2664 /* Also print every pair of 4-byte regs as an 8-byte double. */
2665 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2666 error ("can't read register %d (%s)",
2667 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2669 /* copy the two floats into one double, and unpack both */
2670 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2671 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2672 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2673 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2675 printf_filtered (inv1
? " %-5s: <invalid float>" :
2676 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2677 printf_filtered (inv2
? " %-5s: <invalid float>" :
2678 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2679 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2680 " dbl: %-24.17g\n", doub
);
2681 /* may want to do hex display here (future enhancement) */
2685 { /* eight byte registers: print each one as float AND as double. */
2686 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2688 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2689 flt1
= unpack_double (builtin_type_float
,
2690 &raw_buffer
[HI
][offset
], &inv1
);
2691 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2693 printf_filtered (inv1
? " %-5s: <invalid float>" :
2694 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2695 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2696 " dbl: %-24.17g\n", doub
);
2697 /* may want to do hex display here (future enhancement) */
2703 /* Print a row's worth of GP (int) registers, with name labels above */
2706 do_gp_register_row (int regnum
)
2708 /* do values for GP (int) regs */
2709 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2710 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2712 int start_regnum
= regnum
;
2713 int numregs
= NUM_REGS
;
2716 /* For GP registers, we print a separate row of names above the vals */
2717 printf_filtered (" ");
2718 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2720 if (*REGISTER_NAME (regnum
) == '\0')
2721 continue; /* unused register */
2722 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2723 break; /* end the row: reached FP register */
2724 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2725 REGISTER_NAME (regnum
));
2728 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2729 start_regnum
); /* print the R0 to R31 names */
2731 regnum
= start_regnum
; /* go back to start of row */
2732 /* now print the values in hex, 4 or 8 to the row */
2733 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2735 if (*REGISTER_NAME (regnum
) == '\0')
2736 continue; /* unused register */
2737 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2738 break; /* end row: reached FP register */
2739 /* OK: get the data in raw format. */
2740 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2741 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2742 /* pad small registers */
2743 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2744 printf_filtered (" ");
2745 /* Now print the register value in hex, endian order. */
2746 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2747 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2748 byte
< REGISTER_RAW_SIZE (regnum
);
2750 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2752 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2755 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2756 printf_filtered (" ");
2759 if (col
> 0) /* ie. if we actually printed anything... */
2760 printf_filtered ("\n");
2765 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2768 mips_do_registers_info (int regnum
, int fpregs
)
2770 if (regnum
!= -1) /* do one specified register */
2772 if (*(REGISTER_NAME (regnum
)) == '\0')
2773 error ("Not a valid register for the current processor type");
2775 mips_print_register (regnum
, 0);
2776 printf_filtered ("\n");
2779 /* do all (or most) registers */
2782 while (regnum
< NUM_REGS
)
2784 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2785 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2786 regnum
= do_fp_register_row (regnum
); /* FP regs */
2788 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2790 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2795 /* Return number of args passed to a frame. described by FIP.
2796 Can return -1, meaning no way to tell. */
2799 mips_frame_num_args (struct frame_info
*frame
)
2804 /* Is this a branch with a delay slot? */
2806 static int is_delayed (unsigned long);
2809 is_delayed (unsigned long insn
)
2812 for (i
= 0; i
< NUMOPCODES
; ++i
)
2813 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2814 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2816 return (i
< NUMOPCODES
2817 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2818 | INSN_COND_BRANCH_DELAY
2819 | INSN_COND_BRANCH_LIKELY
)));
2823 mips_step_skips_delay (CORE_ADDR pc
)
2825 char buf
[MIPS_INSTLEN
];
2827 /* There is no branch delay slot on MIPS16. */
2828 if (pc_is_mips16 (pc
))
2831 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2832 /* If error reading memory, guess that it is not a delayed branch. */
2834 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2838 /* Skip the PC past function prologue instructions (32-bit version).
2839 This is a helper function for mips_skip_prologue. */
2842 mips32_skip_prologue (CORE_ADDR pc
)
2846 int seen_sp_adjust
= 0;
2847 int load_immediate_bytes
= 0;
2849 /* Skip the typical prologue instructions. These are the stack adjustment
2850 instruction and the instructions that save registers on the stack
2851 or in the gcc frame. */
2852 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2854 unsigned long high_word
;
2856 inst
= mips_fetch_instruction (pc
);
2857 high_word
= (inst
>> 16) & 0xffff;
2859 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2860 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2862 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2863 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2865 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2866 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2867 && (inst
& 0x001F0000)) /* reg != $zero */
2870 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2872 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2874 continue; /* reg != $zero */
2876 /* move $s8,$sp. With different versions of gas this will be either
2877 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2878 Accept any one of these. */
2879 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2882 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2884 else if (high_word
== 0x3c1c) /* lui $gp,n */
2886 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2888 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2889 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2891 /* The following instructions load $at or $t0 with an immediate
2892 value in preparation for a stack adjustment via
2893 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2894 a local variable, so we accept them only before a stack adjustment
2895 instruction was seen. */
2896 else if (!seen_sp_adjust
)
2898 if (high_word
== 0x3c01 || /* lui $at,n */
2899 high_word
== 0x3c08) /* lui $t0,n */
2901 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2904 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2905 high_word
== 0x3508 || /* ori $t0,$t0,n */
2906 high_word
== 0x3401 || /* ori $at,$zero,n */
2907 high_word
== 0x3408) /* ori $t0,$zero,n */
2909 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2919 /* In a frameless function, we might have incorrectly
2920 skipped some load immediate instructions. Undo the skipping
2921 if the load immediate was not followed by a stack adjustment. */
2922 if (load_immediate_bytes
&& !seen_sp_adjust
)
2923 pc
-= load_immediate_bytes
;
2927 /* Skip the PC past function prologue instructions (16-bit version).
2928 This is a helper function for mips_skip_prologue. */
2931 mips16_skip_prologue (CORE_ADDR pc
)
2934 int extend_bytes
= 0;
2935 int prev_extend_bytes
;
2937 /* Table of instructions likely to be found in a function prologue. */
2940 unsigned short inst
;
2941 unsigned short mask
;
2948 , /* addiu $sp,offset */
2952 , /* daddiu $sp,offset */
2956 , /* sw reg,n($sp) */
2960 , /* sd reg,n($sp) */
2964 , /* sw $ra,n($sp) */
2968 , /* sd $ra,n($sp) */
2976 , /* sw $a0-$a3,n($s1) */
2980 , /* move reg,$a0-$a3 */
2984 , /* entry pseudo-op */
2988 , /* addiu $s1,$sp,n */
2991 } /* end of table marker */
2994 /* Skip the typical prologue instructions. These are the stack adjustment
2995 instruction and the instructions that save registers on the stack
2996 or in the gcc frame. */
2997 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2999 unsigned short inst
;
3002 inst
= mips_fetch_instruction (pc
);
3004 /* Normally we ignore an extend instruction. However, if it is
3005 not followed by a valid prologue instruction, we must adjust
3006 the pc back over the extend so that it won't be considered
3007 part of the prologue. */
3008 if ((inst
& 0xf800) == 0xf000) /* extend */
3010 extend_bytes
= MIPS16_INSTLEN
;
3013 prev_extend_bytes
= extend_bytes
;
3016 /* Check for other valid prologue instructions besides extend. */
3017 for (i
= 0; table
[i
].mask
!= 0; i
++)
3018 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3020 if (table
[i
].mask
!= 0) /* it was in table? */
3021 continue; /* ignore it */
3025 /* Return the current pc, adjusted backwards by 2 if
3026 the previous instruction was an extend. */
3027 return pc
- prev_extend_bytes
;
3033 /* To skip prologues, I use this predicate. Returns either PC itself
3034 if the code at PC does not look like a function prologue; otherwise
3035 returns an address that (if we're lucky) follows the prologue. If
3036 LENIENT, then we must skip everything which is involved in setting
3037 up the frame (it's OK to skip more, just so long as we don't skip
3038 anything which might clobber the registers which are being saved.
3039 We must skip more in the case where part of the prologue is in the
3040 delay slot of a non-prologue instruction). */
3043 mips_skip_prologue (CORE_ADDR pc
)
3045 /* See if we can determine the end of the prologue via the symbol table.
3046 If so, then return either PC, or the PC after the prologue, whichever
3049 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3051 if (post_prologue_pc
!= 0)
3052 return max (pc
, post_prologue_pc
);
3054 /* Can't determine prologue from the symbol table, need to examine
3057 if (pc_is_mips16 (pc
))
3058 return mips16_skip_prologue (pc
);
3060 return mips32_skip_prologue (pc
);
3063 /* Determine how a return value is stored within the MIPS register
3064 file, given the return type `valtype'. */
3066 struct return_value_word
3075 return_value_location (struct type
*valtype
,
3076 struct return_value_word
*hi
,
3077 struct return_value_word
*lo
)
3079 int len
= TYPE_LENGTH (valtype
);
3081 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3082 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3083 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3085 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3087 /* We need to break a 64bit float in two 32 bit halves and
3088 spread them across a floating-point register pair. */
3089 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3090 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3091 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3092 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3094 hi
->reg_offset
= lo
->reg_offset
;
3095 lo
->reg
= FP0_REGNUM
+ 0;
3096 hi
->reg
= FP0_REGNUM
+ 1;
3102 /* The floating point value fits in a single floating-point
3104 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3105 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3108 lo
->reg
= FP0_REGNUM
;
3119 /* Locate a result possibly spread across two registers. */
3121 lo
->reg
= regnum
+ 0;
3122 hi
->reg
= regnum
+ 1;
3123 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3124 && len
< MIPS_SAVED_REGSIZE
)
3126 /* "un-left-justify" the value in the low register */
3127 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3132 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3133 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3134 && len
< MIPS_SAVED_REGSIZE
* 2
3135 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3136 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3138 /* "un-left-justify" the value spread across two registers. */
3139 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3140 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3142 hi
->len
= len
- lo
->len
;
3146 /* Only perform a partial copy of the second register. */
3149 if (len
> MIPS_SAVED_REGSIZE
)
3151 lo
->len
= MIPS_SAVED_REGSIZE
;
3152 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3160 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3161 && REGISTER_RAW_SIZE (regnum
) == 8
3162 && MIPS_SAVED_REGSIZE
== 4)
3164 /* Account for the fact that only the least-signficant part
3165 of the register is being used */
3166 lo
->reg_offset
+= 4;
3167 hi
->reg_offset
+= 4;
3170 hi
->buf_offset
= lo
->len
;
3174 /* Given a return value in `regbuf' with a type `valtype', extract and
3175 copy its value into `valbuf'. */
3178 mips_extract_return_value (struct type
*valtype
,
3179 char regbuf
[REGISTER_BYTES
],
3182 struct return_value_word lo
;
3183 struct return_value_word hi
;
3184 return_value_location (valtype
, &lo
, &hi
);
3186 memcpy (valbuf
+ lo
.buf_offset
,
3187 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3191 memcpy (valbuf
+ hi
.buf_offset
,
3192 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3196 /* Given a return value in `valbuf' with a type `valtype', write it's
3197 value into the appropriate register. */
3200 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3202 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3203 struct return_value_word lo
;
3204 struct return_value_word hi
;
3205 return_value_location (valtype
, &lo
, &hi
);
3207 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3208 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3209 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3211 REGISTER_RAW_SIZE (lo
.reg
));
3215 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3216 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3217 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3219 REGISTER_RAW_SIZE (hi
.reg
));
3223 /* Exported procedure: Is PC in the signal trampoline code */
3226 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3228 if (sigtramp_address
== 0)
3230 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3233 /* Root of all "set mips "/"show mips " commands. This will eventually be
3234 used for all MIPS-specific commands. */
3237 show_mips_command (char *args
, int from_tty
)
3239 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3243 set_mips_command (char *args
, int from_tty
)
3245 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3246 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3249 /* Commands to show/set the MIPS FPU type. */
3252 show_mipsfpu_command (char *args
, int from_tty
)
3256 switch (MIPS_FPU_TYPE
)
3258 case MIPS_FPU_SINGLE
:
3259 fpu
= "single-precision";
3261 case MIPS_FPU_DOUBLE
:
3262 fpu
= "double-precision";
3265 fpu
= "absent (none)";
3268 if (mips_fpu_type_auto
)
3269 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3272 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3278 set_mipsfpu_command (char *args
, int from_tty
)
3280 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3281 show_mipsfpu_command (args
, from_tty
);
3285 set_mipsfpu_single_command (char *args
, int from_tty
)
3287 mips_fpu_type
= MIPS_FPU_SINGLE
;
3288 mips_fpu_type_auto
= 0;
3291 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3296 set_mipsfpu_double_command (char *args
, int from_tty
)
3298 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3299 mips_fpu_type_auto
= 0;
3302 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3307 set_mipsfpu_none_command (char *args
, int from_tty
)
3309 mips_fpu_type
= MIPS_FPU_NONE
;
3310 mips_fpu_type_auto
= 0;
3313 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3318 set_mipsfpu_auto_command (char *args
, int from_tty
)
3320 mips_fpu_type_auto
= 1;
3323 /* Command to set the processor type. */
3326 mips_set_processor_type_command (char *args
, int from_tty
)
3330 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3332 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3333 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3334 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3336 /* Restore the value. */
3337 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3342 if (!mips_set_processor_type (tmp_mips_processor_type
))
3344 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3345 /* Restore its value. */
3346 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3351 mips_show_processor_type_command (char *args
, int from_tty
)
3355 /* Modify the actual processor type. */
3358 mips_set_processor_type (char *str
)
3365 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3367 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3369 mips_processor_type
= str
;
3370 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3372 /* FIXME tweak fpu flag too */
3379 /* Attempt to identify the particular processor model by reading the
3383 mips_read_processor_type (void)
3387 prid
= read_register (PRID_REGNUM
);
3389 if ((prid
& ~0xf) == 0x700)
3390 return savestring ("r3041", strlen ("r3041"));
3395 /* Just like reinit_frame_cache, but with the right arguments to be
3396 callable as an sfunc. */
3399 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3400 struct cmd_list_element
*c
)
3402 reinit_frame_cache ();
3406 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3408 mips_extra_func_info_t proc_desc
;
3410 /* Search for the function containing this address. Set the low bit
3411 of the address when searching, in case we were given an even address
3412 that is the start of a 16-bit function. If we didn't do this,
3413 the search would fail because the symbol table says the function
3414 starts at an odd address, i.e. 1 byte past the given address. */
3415 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3416 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3418 /* Make an attempt to determine if this is a 16-bit function. If
3419 the procedure descriptor exists and the address therein is odd,
3420 it's definitely a 16-bit function. Otherwise, we have to just
3421 guess that if the address passed in is odd, it's 16-bits. */
3423 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3424 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3426 info
->mach
= pc_is_mips16 (memaddr
) ?
3427 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3429 /* Round down the instruction address to the appropriate boundary. */
3430 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3432 /* Call the appropriate disassembler based on the target endian-ness. */
3433 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3434 return print_insn_big_mips (memaddr
, info
);
3436 return print_insn_little_mips (memaddr
, info
);
3439 /* Old-style breakpoint macros.
3440 The IDT board uses an unusual breakpoint value, and sometimes gets
3441 confused when it sees the usual MIPS breakpoint instruction. */
3443 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3444 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3445 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3446 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3447 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3448 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3449 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3450 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3452 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3453 counter value to determine whether a 16- or 32-bit breakpoint should be
3454 used. It returns a pointer to a string of bytes that encode a breakpoint
3455 instruction, stores the length of the string to *lenptr, and adjusts pc
3456 (if necessary) to point to the actual memory location where the
3457 breakpoint should be inserted. */
3460 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3462 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3464 if (pc_is_mips16 (*pcptr
))
3466 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3467 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3468 *lenptr
= sizeof (mips16_big_breakpoint
);
3469 return mips16_big_breakpoint
;
3473 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3474 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3475 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3477 *lenptr
= sizeof (big_breakpoint
);
3479 if (strcmp (target_shortname
, "mips") == 0)
3480 return idt_big_breakpoint
;
3481 else if (strcmp (target_shortname
, "ddb") == 0
3482 || strcmp (target_shortname
, "pmon") == 0
3483 || strcmp (target_shortname
, "lsi") == 0)
3484 return pmon_big_breakpoint
;
3486 return big_breakpoint
;
3491 if (pc_is_mips16 (*pcptr
))
3493 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3494 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3495 *lenptr
= sizeof (mips16_little_breakpoint
);
3496 return mips16_little_breakpoint
;
3500 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3501 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3502 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3504 *lenptr
= sizeof (little_breakpoint
);
3506 if (strcmp (target_shortname
, "mips") == 0)
3507 return idt_little_breakpoint
;
3508 else if (strcmp (target_shortname
, "ddb") == 0
3509 || strcmp (target_shortname
, "pmon") == 0
3510 || strcmp (target_shortname
, "lsi") == 0)
3511 return pmon_little_breakpoint
;
3513 return little_breakpoint
;
3518 /* If PC is in a mips16 call or return stub, return the address of the target
3519 PC, which is either the callee or the caller. There are several
3520 cases which must be handled:
3522 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3523 target PC is in $31 ($ra).
3524 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3525 and the target PC is in $2.
3526 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3527 before the jal instruction, this is effectively a call stub
3528 and the the target PC is in $2. Otherwise this is effectively
3529 a return stub and the target PC is in $18.
3531 See the source code for the stubs in gcc/config/mips/mips16.S for
3534 This function implements the SKIP_TRAMPOLINE_CODE macro.
3538 mips_skip_stub (CORE_ADDR pc
)
3541 CORE_ADDR start_addr
;
3543 /* Find the starting address and name of the function containing the PC. */
3544 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3547 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3548 target PC is in $31 ($ra). */
3549 if (strcmp (name
, "__mips16_ret_sf") == 0
3550 || strcmp (name
, "__mips16_ret_df") == 0)
3551 return read_signed_register (RA_REGNUM
);
3553 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3555 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3556 and the target PC is in $2. */
3557 if (name
[19] >= '0' && name
[19] <= '9')
3558 return read_signed_register (2);
3560 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3561 before the jal instruction, this is effectively a call stub
3562 and the the target PC is in $2. Otherwise this is effectively
3563 a return stub and the target PC is in $18. */
3564 else if (name
[19] == 's' || name
[19] == 'd')
3566 if (pc
== start_addr
)
3568 /* Check if the target of the stub is a compiler-generated
3569 stub. Such a stub for a function bar might have a name
3570 like __fn_stub_bar, and might look like this:
3575 la $1,bar (becomes a lui/addiu pair)
3577 So scan down to the lui/addi and extract the target
3578 address from those two instructions. */
3580 CORE_ADDR target_pc
= read_signed_register (2);
3584 /* See if the name of the target function is __fn_stub_*. */
3585 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3587 if (strncmp (name
, "__fn_stub_", 10) != 0
3588 && strcmp (name
, "etext") != 0
3589 && strcmp (name
, "_etext") != 0)
3592 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3593 The limit on the search is arbitrarily set to 20
3594 instructions. FIXME. */
3595 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3597 inst
= mips_fetch_instruction (target_pc
);
3598 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3599 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3600 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3601 return pc
| (inst
& 0xffff); /* low word */
3604 /* Couldn't find the lui/addui pair, so return stub address. */
3608 /* This is the 'return' part of a call stub. The return
3609 address is in $r18. */
3610 return read_signed_register (18);
3613 return 0; /* not a stub */
3617 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3618 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3621 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3623 CORE_ADDR start_addr
;
3625 /* Find the starting address of the function containing the PC. If the
3626 caller didn't give us a name, look it up at the same time. */
3627 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3630 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3632 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3633 if (name
[19] >= '0' && name
[19] <= '9')
3635 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3636 before the jal instruction, this is effectively a call stub. */
3637 else if (name
[19] == 's' || name
[19] == 'd')
3638 return pc
== start_addr
;
3641 return 0; /* not a stub */
3645 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3646 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3649 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3651 CORE_ADDR start_addr
;
3653 /* Find the starting address of the function containing the PC. */
3654 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3657 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3658 if (strcmp (name
, "__mips16_ret_sf") == 0
3659 || strcmp (name
, "__mips16_ret_df") == 0)
3662 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3663 i.e. after the jal instruction, this is effectively a return stub. */
3664 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3665 && (name
[19] == 's' || name
[19] == 'd')
3666 && pc
!= start_addr
)
3669 return 0; /* not a stub */
3673 /* Return non-zero if the PC is in a library helper function that should
3674 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3677 mips_ignore_helper (CORE_ADDR pc
)
3681 /* Find the starting address and name of the function containing the PC. */
3682 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3685 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3686 that we want to ignore. */
3687 return (strcmp (name
, "__mips16_ret_sf") == 0
3688 || strcmp (name
, "__mips16_ret_df") == 0);
3692 /* Return a location where we can set a breakpoint that will be hit
3693 when an inferior function call returns. This is normally the
3694 program's entry point. Executables that don't have an entry
3695 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3696 whose address is the location where the breakpoint should be placed. */
3699 mips_call_dummy_address (void)
3701 struct minimal_symbol
*sym
;
3703 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3705 return SYMBOL_VALUE_ADDRESS (sym
);
3707 return entry_point_address ();
3711 /* If the current gcc for this target does not produce correct debugging
3712 information for float parameters, both prototyped and unprototyped, then
3713 define this macro. This forces gdb to always assume that floats are
3714 passed as doubles and then converted in the callee.
3716 For the mips chip, it appears that the debug info marks the parameters as
3717 floats regardless of whether the function is prototyped, but the actual
3718 values are passed as doubles for the non-prototyped case and floats for
3719 the prototyped case. Thus we choose to make the non-prototyped case work
3720 for C and break the prototyped case, since the non-prototyped case is
3721 probably much more common. (FIXME). */
3724 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3726 return current_language
->la_language
== language_c
;
3729 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3730 the register stored on the stack (32) is different to its real raw
3731 size (64). The below ensures that registers are fetched from the
3732 stack using their ABI size and then stored into the RAW_BUFFER
3733 using their raw size.
3735 The alternative to adding this function would be to add an ABI
3736 macro - REGISTER_STACK_SIZE(). */
3739 mips_get_saved_register (char *raw_buffer
,
3742 struct frame_info
*frame
,
3744 enum lval_type
*lval
)
3748 if (!target_has_registers
)
3749 error ("No registers.");
3751 /* Normal systems don't optimize out things with register numbers. */
3752 if (optimized
!= NULL
)
3754 addr
= find_saved_register (frame
, regnum
);
3758 *lval
= lval_memory
;
3759 if (regnum
== SP_REGNUM
)
3761 if (raw_buffer
!= NULL
)
3763 /* Put it back in target format. */
3764 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3771 if (raw_buffer
!= NULL
)
3775 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3777 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3779 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3780 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3786 *lval
= lval_register
;
3787 addr
= REGISTER_BYTE (regnum
);
3788 if (raw_buffer
!= NULL
)
3789 read_register_gen (regnum
, raw_buffer
);
3795 /* Immediately after a function call, return the saved pc.
3796 Can't always go through the frames for this because on some machines
3797 the new frame is not set up until the new function executes
3798 some instructions. */
3801 mips_saved_pc_after_call (struct frame_info
*frame
)
3803 return read_signed_register (RA_REGNUM
);
3807 /* Convert a dbx stab register number (from `r' declaration) to a gdb
3811 mips_stab_reg_to_regnum (int num
)
3816 return num
+ FP0_REGNUM
- 38;
3819 /* Convert a ecoff register number to a gdb REGNUM */
3822 mips_ecoff_reg_to_regnum (int num
)
3827 return num
+ FP0_REGNUM
- 32;
3830 static struct gdbarch
*
3831 mips_gdbarch_init (struct gdbarch_info info
,
3832 struct gdbarch_list
*arches
)
3834 static LONGEST mips_call_dummy_words
[] =
3836 struct gdbarch
*gdbarch
;
3837 struct gdbarch_tdep
*tdep
;
3839 enum mips_abi mips_abi
;
3841 /* Extract the elf_flags if available */
3842 if (info
.abfd
!= NULL
3843 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3844 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3848 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3849 switch ((elf_flags
& EF_MIPS_ABI
))
3851 case E_MIPS_ABI_O32
:
3852 mips_abi
= MIPS_ABI_O32
;
3854 case E_MIPS_ABI_O64
:
3855 mips_abi
= MIPS_ABI_O64
;
3857 case E_MIPS_ABI_EABI32
:
3858 mips_abi
= MIPS_ABI_EABI32
;
3860 case E_MIPS_ABI_EABI64
:
3861 mips_abi
= MIPS_ABI_EABI64
;
3864 if ((elf_flags
& EF_MIPS_ABI2
))
3865 mips_abi
= MIPS_ABI_N32
;
3867 mips_abi
= MIPS_ABI_UNKNOWN
;
3871 /* Try the architecture for any hint of the corect ABI */
3872 if (mips_abi
== MIPS_ABI_UNKNOWN
3873 && info
.bfd_arch_info
!= NULL
3874 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3876 switch (info
.bfd_arch_info
->mach
)
3878 case bfd_mach_mips3900
:
3879 mips_abi
= MIPS_ABI_EABI32
;
3881 case bfd_mach_mips4100
:
3882 case bfd_mach_mips5000
:
3883 mips_abi
= MIPS_ABI_EABI64
;
3887 #ifdef MIPS_DEFAULT_ABI
3888 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3889 mips_abi
= MIPS_DEFAULT_ABI
;
3894 fprintf_unfiltered (gdb_stdlog
,
3895 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3897 fprintf_unfiltered (gdb_stdlog
,
3898 "mips_gdbarch_init: mips_abi = %d\n",
3902 /* try to find a pre-existing architecture */
3903 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3905 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3907 /* MIPS needs to be pedantic about which ABI the object is
3909 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
3911 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
3913 return arches
->gdbarch
;
3916 /* Need a new architecture. Fill in a target specific vector. */
3917 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3918 gdbarch
= gdbarch_alloc (&info
, tdep
);
3919 tdep
->elf_flags
= elf_flags
;
3921 /* Initially set everything according to the ABI. */
3922 set_gdbarch_short_bit (gdbarch
, 16);
3923 set_gdbarch_int_bit (gdbarch
, 32);
3924 set_gdbarch_float_bit (gdbarch
, 32);
3925 set_gdbarch_double_bit (gdbarch
, 64);
3926 set_gdbarch_long_double_bit (gdbarch
, 64);
3927 tdep
->mips_abi
= mips_abi
;
3931 tdep
->mips_abi_string
= "o32";
3932 tdep
->mips_default_saved_regsize
= 4;
3933 tdep
->mips_default_stack_argsize
= 4;
3934 tdep
->mips_fp_register_double
= 0;
3935 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3936 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3937 tdep
->mips_regs_have_home_p
= 1;
3938 tdep
->gdb_target_is_mips64
= 0;
3939 tdep
->default_mask_address_p
= 0;
3940 set_gdbarch_long_bit (gdbarch
, 32);
3941 set_gdbarch_ptr_bit (gdbarch
, 32);
3942 set_gdbarch_long_long_bit (gdbarch
, 64);
3945 tdep
->mips_abi_string
= "o64";
3946 tdep
->mips_default_saved_regsize
= 8;
3947 tdep
->mips_default_stack_argsize
= 8;
3948 tdep
->mips_fp_register_double
= 1;
3949 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
3950 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
3951 tdep
->mips_regs_have_home_p
= 1;
3952 tdep
->gdb_target_is_mips64
= 1;
3953 tdep
->default_mask_address_p
= 0;
3954 set_gdbarch_long_bit (gdbarch
, 32);
3955 set_gdbarch_ptr_bit (gdbarch
, 32);
3956 set_gdbarch_long_long_bit (gdbarch
, 64);
3958 case MIPS_ABI_EABI32
:
3959 tdep
->mips_abi_string
= "eabi32";
3960 tdep
->mips_default_saved_regsize
= 4;
3961 tdep
->mips_default_stack_argsize
= 4;
3962 tdep
->mips_fp_register_double
= 0;
3963 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3964 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3965 tdep
->mips_regs_have_home_p
= 0;
3966 tdep
->gdb_target_is_mips64
= 0;
3967 tdep
->default_mask_address_p
= 0;
3968 set_gdbarch_long_bit (gdbarch
, 32);
3969 set_gdbarch_ptr_bit (gdbarch
, 32);
3970 set_gdbarch_long_long_bit (gdbarch
, 64);
3972 case MIPS_ABI_EABI64
:
3973 tdep
->mips_abi_string
= "eabi64";
3974 tdep
->mips_default_saved_regsize
= 8;
3975 tdep
->mips_default_stack_argsize
= 8;
3976 tdep
->mips_fp_register_double
= 1;
3977 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3978 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3979 tdep
->mips_regs_have_home_p
= 0;
3980 tdep
->gdb_target_is_mips64
= 1;
3981 tdep
->default_mask_address_p
= 0;
3982 set_gdbarch_long_bit (gdbarch
, 64);
3983 set_gdbarch_ptr_bit (gdbarch
, 64);
3984 set_gdbarch_long_long_bit (gdbarch
, 64);
3987 tdep
->mips_abi_string
= "n32";
3988 tdep
->mips_default_saved_regsize
= 4;
3989 tdep
->mips_default_stack_argsize
= 8;
3990 tdep
->mips_fp_register_double
= 1;
3991 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
3992 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
3993 tdep
->mips_regs_have_home_p
= 0;
3994 tdep
->gdb_target_is_mips64
= 0;
3995 tdep
->default_mask_address_p
= 0;
3996 set_gdbarch_long_bit (gdbarch
, 32);
3997 set_gdbarch_ptr_bit (gdbarch
, 32);
3998 set_gdbarch_long_long_bit (gdbarch
, 64);
4001 tdep
->mips_abi_string
= "default";
4002 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4003 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4004 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4005 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4006 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4007 tdep
->mips_regs_have_home_p
= 1;
4008 tdep
->gdb_target_is_mips64
= 0;
4009 tdep
->default_mask_address_p
= 0;
4010 set_gdbarch_long_bit (gdbarch
, 32);
4011 set_gdbarch_ptr_bit (gdbarch
, 32);
4012 set_gdbarch_long_long_bit (gdbarch
, 64);
4016 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4017 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4020 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4021 flag in object files because to do so would make it impossible to
4022 link with libraries compiled without "-gp32". This is
4023 unnecessarily restrictive.
4025 We could solve this problem by adding "-gp32" multilibs to gcc,
4026 but to set this flag before gcc is built with such multilibs will
4027 break too many systems.''
4029 But even more unhelpfully, the default linker output target for
4030 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4031 for 64-bit programs - you need to change the ABI to change this,
4032 and not all gcc targets support that currently. Therefore using
4033 this flag to detect 32-bit mode would do the wrong thing given
4034 the current gcc - it would make GDB treat these 64-bit programs
4035 as 32-bit programs by default. */
4037 /* enable/disable the MIPS FPU */
4038 if (!mips_fpu_type_auto
)
4039 tdep
->mips_fpu_type
= mips_fpu_type
;
4040 else if (info
.bfd_arch_info
!= NULL
4041 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4042 switch (info
.bfd_arch_info
->mach
)
4044 case bfd_mach_mips3900
:
4045 case bfd_mach_mips4100
:
4046 case bfd_mach_mips4111
:
4047 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4049 case bfd_mach_mips4650
:
4050 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4053 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4057 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4059 /* MIPS version of register names. NOTE: At present the MIPS
4060 register name management is part way between the old -
4061 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4062 Further work on it is required. */
4063 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4064 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4065 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4066 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4067 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4068 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4069 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4071 /* Map debug register numbers onto internal register numbers. */
4072 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4073 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4075 /* Initialize a frame */
4076 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4078 /* MIPS version of CALL_DUMMY */
4080 set_gdbarch_call_dummy_p (gdbarch
, 1);
4081 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4082 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4083 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4084 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4085 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4086 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4087 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4088 set_gdbarch_call_dummy_length (gdbarch
, 0);
4089 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4090 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4091 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4092 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4093 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4094 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4095 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4097 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4098 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4100 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4101 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4102 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4103 set_gdbarch_ieee_float (gdbarch
, 1);
4105 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4106 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4112 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4118 int ef_mips_32bitmode
;
4119 /* determine the ISA */
4120 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4137 /* determine the size of a pointer */
4138 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4139 fprintf_unfiltered (file
,
4140 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4142 fprintf_unfiltered (file
,
4143 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4145 fprintf_unfiltered (file
,
4146 "mips_dump_tdep: ef_mips_arch = %d\n",
4148 fprintf_unfiltered (file
,
4149 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4151 tdep
->mips_abi_string
);
4152 fprintf_unfiltered (file
,
4153 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4154 mips_mask_address_p (),
4155 tdep
->default_mask_address_p
);
4157 fprintf_unfiltered (file
,
4158 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4159 FP_REGISTER_DOUBLE
);
4160 fprintf_unfiltered (file
,
4161 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4162 MIPS_DEFAULT_FPU_TYPE
,
4163 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4164 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4165 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4167 fprintf_unfiltered (file
,
4168 "mips_dump_tdep: MIPS_EABI = %d\n",
4170 fprintf_unfiltered (file
,
4171 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4172 MIPS_LAST_FP_ARG_REGNUM
,
4173 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4174 fprintf_unfiltered (file
,
4175 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4177 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4178 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4179 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4181 fprintf_unfiltered (file
,
4182 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4183 MIPS_DEFAULT_SAVED_REGSIZE
);
4184 fprintf_unfiltered (file
,
4185 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4186 FP_REGISTER_DOUBLE
);
4187 fprintf_unfiltered (file
,
4188 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4189 MIPS_REGS_HAVE_HOME_P
);
4190 fprintf_unfiltered (file
,
4191 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4192 MIPS_DEFAULT_STACK_ARGSIZE
);
4193 fprintf_unfiltered (file
,
4194 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4195 MIPS_STACK_ARGSIZE
);
4196 fprintf_unfiltered (file
,
4197 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4199 fprintf_unfiltered (file
,
4200 "mips_dump_tdep: A0_REGNUM = %d\n",
4202 fprintf_unfiltered (file
,
4203 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4204 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4205 fprintf_unfiltered (file
,
4206 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4207 XSTRING (ATTACH_DETACH
));
4208 fprintf_unfiltered (file
,
4209 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4211 fprintf_unfiltered (file
,
4212 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4213 fprintf_unfiltered (file
,
4214 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4216 fprintf_unfiltered (file
,
4217 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4219 fprintf_unfiltered (file
,
4220 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4222 fprintf_unfiltered (file
,
4223 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4224 XSTRING (DO_REGISTERS_INFO
));
4225 fprintf_unfiltered (file
,
4226 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4227 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4228 fprintf_unfiltered (file
,
4229 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4230 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4231 fprintf_unfiltered (file
,
4232 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4233 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4234 fprintf_unfiltered (file
,
4235 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4237 fprintf_unfiltered (file
,
4238 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4240 fprintf_unfiltered (file
,
4241 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4242 FIRST_EMBED_REGNUM
);
4243 fprintf_unfiltered (file
,
4244 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4246 fprintf_unfiltered (file
,
4247 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4248 GDB_TARGET_IS_MIPS64
);
4249 fprintf_unfiltered (file
,
4250 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4251 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4252 fprintf_unfiltered (file
,
4253 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4254 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4255 fprintf_unfiltered (file
,
4256 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4258 fprintf_unfiltered (file
,
4259 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4260 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4261 fprintf_unfiltered (file
,
4262 "mips_dump_tdep: HI_REGNUM = %d\n",
4264 fprintf_unfiltered (file
,
4265 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4266 fprintf_unfiltered (file
,
4267 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4268 fprintf_unfiltered (file
,
4269 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4270 XSTRING (IGNORE_HELPER_CALL (PC
)));
4271 fprintf_unfiltered (file
,
4272 "mips_dump_tdep: INIT_FRAME_PC # %s\n",
4273 XSTRING (INIT_FRAME_PC (FROMLEAF
, PREV
)));
4274 fprintf_unfiltered (file
,
4275 "mips_dump_tdep: INIT_FRAME_PC_FIRST # %s\n",
4276 XSTRING (INIT_FRAME_PC_FIRST (FROMLEAF
, PREV
)));
4277 fprintf_unfiltered (file
,
4278 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4279 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4280 fprintf_unfiltered (file
,
4281 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4282 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4283 fprintf_unfiltered (file
,
4284 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4285 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4286 fprintf_unfiltered (file
,
4287 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4288 fprintf_unfiltered (file
,
4289 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4291 fprintf_unfiltered (file
,
4292 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4293 fprintf_unfiltered (file
,
4294 "mips_dump_tdep: LO_REGNUM = %d\n",
4296 #ifdef MACHINE_CPROC_FP_OFFSET
4297 fprintf_unfiltered (file
,
4298 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4299 MACHINE_CPROC_FP_OFFSET
);
4301 #ifdef MACHINE_CPROC_PC_OFFSET
4302 fprintf_unfiltered (file
,
4303 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4304 MACHINE_CPROC_PC_OFFSET
);
4306 #ifdef MACHINE_CPROC_SP_OFFSET
4307 fprintf_unfiltered (file
,
4308 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4309 MACHINE_CPROC_SP_OFFSET
);
4311 fprintf_unfiltered (file
,
4312 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4313 fprintf_unfiltered (file
,
4314 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4315 fprintf_unfiltered (file
,
4316 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4318 fprintf_unfiltered (file
,
4319 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4320 fprintf_unfiltered (file
,
4321 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4322 fprintf_unfiltered (file
,
4323 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4324 fprintf_unfiltered (file
,
4325 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4327 fprintf_unfiltered (file
,
4328 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4329 MIPS_LAST_ARG_REGNUM
,
4330 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4331 fprintf_unfiltered (file
,
4332 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4334 fprintf_unfiltered (file
,
4335 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4336 fprintf_unfiltered (file
,
4337 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4338 MIPS_SAVED_REGSIZE
);
4339 fprintf_unfiltered (file
,
4340 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4341 fprintf_unfiltered (file
,
4342 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4343 XSTRING (MSYMBOL_SIZE (MSYM
)));
4344 fprintf_unfiltered (file
,
4345 "mips_dump_tdep: OP_LDFPR = used?\n");
4346 fprintf_unfiltered (file
,
4347 "mips_dump_tdep: OP_LDGPR = used?\n");
4348 fprintf_unfiltered (file
,
4349 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4350 fprintf_unfiltered (file
,
4351 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4352 fprintf_unfiltered (file
,
4353 "mips_dump_tdep: PRID_REGNUM = %d\n",
4355 fprintf_unfiltered (file
,
4356 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4357 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4358 fprintf_unfiltered (file
,
4359 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4360 fprintf_unfiltered (file
,
4361 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4362 fprintf_unfiltered (file
,
4363 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4364 fprintf_unfiltered (file
,
4365 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4368 fprintf_unfiltered (file
,
4369 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4370 fprintf_unfiltered (file
,
4371 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4372 fprintf_unfiltered (file
,
4373 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4374 fprintf_unfiltered (file
,
4375 "mips_dump_tdep: PROC_PC_REG = function?\n");
4376 fprintf_unfiltered (file
,
4377 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4378 fprintf_unfiltered (file
,
4379 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4380 fprintf_unfiltered (file
,
4381 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4382 fprintf_unfiltered (file
,
4383 "mips_dump_tdep: PS_REGNUM = %d\n",
4385 fprintf_unfiltered (file
,
4386 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4388 fprintf_unfiltered (file
,
4389 "mips_dump_tdep: RA_REGNUM = %d\n",
4391 fprintf_unfiltered (file
,
4392 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4393 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4394 fprintf_unfiltered (file
,
4395 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4396 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4397 fprintf_unfiltered (file
,
4398 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4399 fprintf_unfiltered (file
,
4400 "mips_dump_tdep: ROUND_DOWN = function?\n");
4401 fprintf_unfiltered (file
,
4402 "mips_dump_tdep: ROUND_UP = function?\n");
4404 fprintf_unfiltered (file
,
4405 "mips_dump_tdep: SAVED_BYTES = %d\n",
4409 fprintf_unfiltered (file
,
4410 "mips_dump_tdep: SAVED_FP = %d\n",
4414 fprintf_unfiltered (file
,
4415 "mips_dump_tdep: SAVED_PC = %d\n",
4418 fprintf_unfiltered (file
,
4419 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4420 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4421 fprintf_unfiltered (file
,
4422 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4423 fprintf_unfiltered (file
,
4424 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4426 fprintf_unfiltered (file
,
4427 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4428 SIGFRAME_FPREGSAVE_OFF
);
4429 fprintf_unfiltered (file
,
4430 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4432 fprintf_unfiltered (file
,
4433 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4434 SIGFRAME_REGSAVE_OFF
);
4435 fprintf_unfiltered (file
,
4436 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4438 fprintf_unfiltered (file
,
4439 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4440 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4441 fprintf_unfiltered (file
,
4442 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4443 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4444 fprintf_unfiltered (file
,
4445 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4446 SOFTWARE_SINGLE_STEP_P
);
4447 fprintf_unfiltered (file
,
4448 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P = %d\n",
4449 SOFTWARE_SINGLE_STEP_P
);
4450 fprintf_unfiltered (file
,
4451 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4452 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4453 #ifdef STACK_END_ADDR
4454 fprintf_unfiltered (file
,
4455 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4458 fprintf_unfiltered (file
,
4459 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4460 XSTRING (STEP_SKIPS_DELAY (PC
)));
4461 fprintf_unfiltered (file
,
4462 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4463 STEP_SKIPS_DELAY_P
);
4464 fprintf_unfiltered (file
,
4465 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4466 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4467 fprintf_unfiltered (file
,
4468 "mips_dump_tdep: T9_REGNUM = %d\n",
4470 fprintf_unfiltered (file
,
4471 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4472 fprintf_unfiltered (file
,
4473 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4474 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4475 fprintf_unfiltered (file
,
4476 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4477 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4478 fprintf_unfiltered (file
,
4479 "mips_dump_tdep: TARGET_MIPS = used?\n");
4480 fprintf_unfiltered (file
,
4481 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4482 XSTRING (TM_PRINT_INSN_MACH
));
4484 fprintf_unfiltered (file
,
4485 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4486 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4489 fprintf_unfiltered (file
,
4490 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4493 #ifdef TRACE_FLAVOR_SIZE
4494 fprintf_unfiltered (file
,
4495 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4499 fprintf_unfiltered (file
,
4500 "mips_dump_tdep: TRACE_SET # %s\n",
4501 XSTRING (TRACE_SET (X
,STATE
)));
4503 fprintf_unfiltered (file
,
4504 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4505 #ifdef UNUSED_REGNUM
4506 fprintf_unfiltered (file
,
4507 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4510 fprintf_unfiltered (file
,
4511 "mips_dump_tdep: V0_REGNUM = %d\n",
4513 fprintf_unfiltered (file
,
4514 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4515 (long) VM_MIN_ADDRESS
);
4517 fprintf_unfiltered (file
,
4518 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4521 fprintf_unfiltered (file
,
4522 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4524 fprintf_unfiltered (file
,
4525 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4530 _initialize_mips_tdep (void)
4532 static struct cmd_list_element
*mipsfpulist
= NULL
;
4533 struct cmd_list_element
*c
;
4535 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4536 if (!tm_print_insn
) /* Someone may have already set it */
4537 tm_print_insn
= gdb_print_insn_mips
;
4539 /* Add root prefix command for all "set mips"/"show mips" commands */
4540 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4541 "Various MIPS specific commands.",
4542 &setmipscmdlist
, "set mips ", 0, &setlist
);
4544 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4545 "Various MIPS specific commands.",
4546 &showmipscmdlist
, "show mips ", 0, &showlist
);
4548 /* Allow the user to override the saved register size. */
4549 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4552 &mips_saved_regsize_string
, "\
4553 Set size of general purpose registers saved on the stack.\n\
4554 This option can be set to one of:\n\
4555 32 - Force GDB to treat saved GP registers as 32-bit\n\
4556 64 - Force GDB to treat saved GP registers as 64-bit\n\
4557 auto - Allow GDB to use the target's default setting or autodetect the\n\
4558 saved GP register size from information contained in the executable.\n\
4563 /* Allow the user to override the argument stack size. */
4564 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4567 &mips_stack_argsize_string
, "\
4568 Set the amount of stack space reserved for each argument.\n\
4569 This option can be set to one of:\n\
4570 32 - Force GDB to allocate 32-bit chunks per argument\n\
4571 64 - Force GDB to allocate 64-bit chunks per argument\n\
4572 auto - Allow GDB to determine the correct setting from the current\n\
4573 target and executable (default)",
4577 /* Let the user turn off floating point and set the fence post for
4578 heuristic_proc_start. */
4580 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4581 "Set use of MIPS floating-point coprocessor.",
4582 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4583 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4584 "Select single-precision MIPS floating-point coprocessor.",
4586 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4587 "Select double-precision MIPS floating-point coprocessor.",
4589 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4590 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4591 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4592 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4593 "Select no MIPS floating-point coprocessor.",
4595 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4596 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4597 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4598 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4599 "Select MIPS floating-point coprocessor automatically.",
4601 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4602 "Show current use of MIPS floating-point coprocessor target.",
4606 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4607 (char *) &tmp_mips_processor_type
,
4608 "Set the type of MIPS processor in use.\n\
4609 Set this to be able to access processor-type-specific registers.\n\
4612 c
->function
.cfunc
= mips_set_processor_type_command
;
4613 c
= add_show_from_set (c
, &showlist
);
4614 c
->function
.cfunc
= mips_show_processor_type_command
;
4616 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4617 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4620 /* We really would like to have both "0" and "unlimited" work, but
4621 command.c doesn't deal with that. So make it a var_zinteger
4622 because the user can always use "999999" or some such for unlimited. */
4623 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4624 (char *) &heuristic_fence_post
,
4626 Set the distance searched for the start of a function.\n\
4627 If you are debugging a stripped executable, GDB needs to search through the\n\
4628 program for the start of a function. This command sets the distance of the\n\
4629 search. The only need to set it is when debugging a stripped executable.",
4631 /* We need to throw away the frame cache when we set this, since it
4632 might change our ability to get backtraces. */
4633 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4634 add_show_from_set (c
, &showlist
);
4636 /* Allow the user to control whether the upper bits of 64-bit
4637 addresses should be zeroed. */
4638 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4639 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4640 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4641 the correct value.\n",
4643 add_cmd ("mask-address", no_class
, show_mask_address
,
4644 "Show current mask-address value", &showmipscmdlist
);
4646 /* Allow the user to control the size of 32 bit registers within the
4647 raw remote packet. */
4648 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4651 (char *)&mips64_transfers_32bit_regs_p
, "\
4652 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4653 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4654 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4655 64 bits for others. Use \"off\" to disable compatibility mode",
4659 /* Debug this files internals. */
4660 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4661 &mips_debug
, "Set mips debugging.\n\
4662 When non-zero, mips specific debugging is enabled.", &setdebuglist
),