1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2023 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 frame_info_ptr
, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (_("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
439 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
440 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
442 else if (ELF_ST_IS_MIPS16 (st_other
))
444 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
445 CORE_ADDR fixed
= CORE_ADDR (msym
->unrelocated_address ()) | 1;
446 msym
->set_unrelocated_address (unrelocated_addr (fixed
));
450 /* Return one iff MSYM refers to standard ISA code. */
453 msymbol_is_mips (struct minimal_symbol
*msym
)
455 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
456 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
459 /* Return one iff MSYM refers to MIPS16 code. */
462 msymbol_is_mips16 (struct minimal_symbol
*msym
)
464 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
467 /* Return one iff MSYM refers to microMIPS code. */
470 msymbol_is_micromips (struct minimal_symbol
*msym
)
472 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
475 /* Set the ISA bit in the main symbol too, complementing the corresponding
476 minimal symbol setting and reflecting the run-time value of the symbol.
477 The need for comes from the ISA bit having been cleared as code in
478 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
479 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
480 of symbols referring to compressed code different in GDB to the values
481 used by actual code. That in turn makes them evaluate incorrectly in
482 expressions, producing results different to what the same expressions
483 yield when compiled into the program being debugged. */
486 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
488 if (sym
->aclass () == LOC_BLOCK
)
490 /* We are in symbol reading so it is OK to cast away constness. */
491 struct block
*block
= (struct block
*) sym
->value_block ();
492 CORE_ADDR compact_block_start
;
493 struct bound_minimal_symbol msym
;
495 compact_block_start
= block
->start () | 1;
496 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
497 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
499 block
->set_start (compact_block_start
);
504 /* XFER a value from the big/little/left end of the register.
505 Depending on the size of the value it might occupy the entire
506 register or just part of it. Make an allowance for this, aligning
507 things accordingly. */
510 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
511 int reg_num
, int length
,
512 enum bfd_endian endian
, gdb_byte
*in
,
513 const gdb_byte
*out
, int buf_offset
)
517 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
518 /* Need to transfer the left or right part of the register, based on
519 the targets byte order. */
523 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
525 case BFD_ENDIAN_LITTLE
:
528 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
532 internal_error (_("bad switch"));
535 gdb_printf (gdb_stderr
,
536 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
537 reg_num
, reg_offset
, buf_offset
, length
);
538 if (mips_debug
&& out
!= NULL
)
541 gdb_printf (gdb_stdlog
, "out ");
542 for (i
= 0; i
< length
; i
++)
543 gdb_printf (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
546 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
548 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
549 if (mips_debug
&& in
!= NULL
)
552 gdb_printf (gdb_stdlog
, "in ");
553 for (i
= 0; i
< length
; i
++)
554 gdb_printf (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
557 gdb_printf (gdb_stdlog
, "\n");
560 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
561 compatiblity mode. A return value of 1 means that we have
562 physical 64-bit registers, but should treat them as 32-bit registers. */
565 mips2_fp_compat (frame_info_ptr frame
)
567 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
568 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
570 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
574 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
575 in all the places we deal with FP registers. PR gdb/413. */
576 /* Otherwise check the FR bit in the status register - it controls
577 the FP compatiblity mode. If it is clear we are in compatibility
579 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
586 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
588 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
590 /* The list of available "set mips " and "show mips " commands. */
592 static struct cmd_list_element
*setmipscmdlist
= NULL
;
593 static struct cmd_list_element
*showmipscmdlist
= NULL
;
595 /* Integer registers 0 thru 31 are handled explicitly by
596 mips_register_name(). Processor specific registers 32 and above
597 are listed in the following tables. */
600 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
604 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
613 /* Names of tx39 registers. */
615 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
616 "sr", "lo", "hi", "bad", "cause", "pc",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
619 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
622 "", "", "", "", "", "", "", "",
623 "", "", "config", "cache", "debug", "depc", "epc",
626 /* Names of registers with Linux kernels. */
627 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
628 "sr", "lo", "hi", "bad", "cause", "pc",
629 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
630 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
631 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
632 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
637 /* Return the name of the register corresponding to REGNO. */
639 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
641 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
642 /* GPR names for all ABIs other than n32/n64. */
643 static const char *mips_gpr_names
[] = {
644 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
645 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
646 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
647 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
650 /* GPR names for n32 and n64 ABIs. */
651 static const char *mips_n32_n64_gpr_names
[] = {
652 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
653 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
654 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
655 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
658 enum mips_abi abi
= mips_abi (gdbarch
);
660 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
661 but then don't make the raw register names visible. This (upper)
662 range of user visible register numbers are the pseudo-registers.
664 This approach was adopted accommodate the following scenario:
665 It is possible to debug a 64-bit device using a 32-bit
666 programming model. In such instances, the raw registers are
667 configured to be 64-bits wide, while the pseudo registers are
668 configured to be 32-bits wide. The registers that the user
669 sees - the pseudo registers - match the users expectations
670 given the programming model being used. */
671 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
672 if (regno
< gdbarch_num_regs (gdbarch
))
675 /* The MIPS integer registers are always mapped from 0 to 31. The
676 names of the registers (which reflects the conventions regarding
677 register use) vary depending on the ABI. */
678 if (0 <= rawnum
&& rawnum
< 32)
680 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
681 return mips_n32_n64_gpr_names
[rawnum
];
683 return mips_gpr_names
[rawnum
];
685 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
686 return tdesc_register_name (gdbarch
, rawnum
);
687 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
689 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
690 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
691 return tdep
->mips_processor_reg_names
[rawnum
- 32];
695 internal_error (_("mips_register_name: bad register number %d"), rawnum
);
698 /* Return the groups that a MIPS register can be categorised into. */
701 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
702 const struct reggroup
*reggroup
)
707 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
708 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
709 if (reggroup
== all_reggroup
)
711 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
712 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
713 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
714 (gdbarch), as not all architectures are multi-arch. */
715 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
716 if (gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 const struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (_("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (_("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (_("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& type
->length () == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && type
->length () < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (frame_info_ptr frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= type
->length ();
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (_("mips_register_to_value: unrecognized case"));
986 mips_value_to_register (frame_info_ptr frame
, int regnum
,
987 struct type
*type
, const gdb_byte
*from
)
989 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
991 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
993 put_frame_register (frame
, regnum
+ 0, from
+ 4);
994 put_frame_register (frame
, regnum
+ 1, from
+ 0);
996 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
999 size_t len
= type
->length ();
1001 /* Sign extend values, irrespective of type, that are stored to
1002 a 64-bit general purpose register. (32-bit unsigned values
1003 are stored as signed quantities within a 64-bit register.
1004 When performing an operation, in compiled code, that combines
1005 a 32-bit unsigned value with a signed 64-bit value, a type
1006 conversion is first performed that zeroes out the high 32 bits.) */
1007 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1010 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1012 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1013 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1014 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1018 if (from
[len
-1] & 0x80)
1019 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1021 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1022 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1023 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1028 internal_error (_("mips_value_to_register: unrecognized case"));
1032 /* Return the GDB type object for the "standard" data type of data in
1035 static struct type
*
1036 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1038 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1039 if (mips_float_register_p (gdbarch
, regnum
))
1041 /* The floating-point registers raw, or cooked, always match
1042 mips_isa_regsize(), and also map 1:1, byte for byte. */
1043 if (mips_isa_regsize (gdbarch
) == 4)
1044 return builtin_type (gdbarch
)->builtin_float
;
1046 return builtin_type (gdbarch
)->builtin_double
;
1048 else if (regnum
< gdbarch_num_regs (gdbarch
))
1050 /* The raw or ISA registers. These are all sized according to
1052 if (mips_isa_regsize (gdbarch
) == 4)
1053 return builtin_type (gdbarch
)->builtin_int32
;
1055 return builtin_type (gdbarch
)->builtin_int64
;
1059 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1060 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1062 /* The cooked or ABI registers. These are sized according to
1063 the ABI (with a few complications). */
1064 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1065 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1066 return builtin_type (gdbarch
)->builtin_int32
;
1067 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1068 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1069 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1070 /* The pseudo/cooked view of the embedded registers is always
1071 32-bit. The raw view is handled below. */
1072 return builtin_type (gdbarch
)->builtin_int32
;
1073 else if (tdep
->mips64_transfers_32bit_regs_p
)
1074 /* The target, while possibly using a 64-bit register buffer,
1075 is only transfering 32-bits of each integer register.
1076 Reflect this in the cooked/pseudo (ABI) register value. */
1077 return builtin_type (gdbarch
)->builtin_int32
;
1078 else if (mips_abi_regsize (gdbarch
) == 4)
1079 /* The ABI is restricted to 32-bit registers (the ISA could be
1081 return builtin_type (gdbarch
)->builtin_int32
;
1084 return builtin_type (gdbarch
)->builtin_int64
;
1088 /* Return the GDB type for the pseudo register REGNUM, which is the
1089 ABI-level view. This function is only called if there is a target
1090 description which includes registers, so we know precisely the
1091 types of hardware registers. */
1093 static struct type
*
1094 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1096 const int num_regs
= gdbarch_num_regs (gdbarch
);
1097 int rawnum
= regnum
% num_regs
;
1098 struct type
*rawtype
;
1100 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1102 /* Absent registers are still absent. */
1103 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1104 if (rawtype
->length () == 0)
1107 /* Present the floating point registers however the hardware did;
1108 do not try to convert between FPU layouts. */
1109 if (mips_float_register_p (gdbarch
, rawnum
))
1112 /* Floating-point control registers are always 32-bit even though for
1113 backwards compatibility reasons 64-bit targets will transfer them
1114 as 64-bit quantities even if using XML descriptions. */
1115 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1116 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1117 return builtin_type (gdbarch
)->builtin_int32
;
1119 /* Use pointer types for registers if we can. For n32 we can not,
1120 since we do not have a 64-bit pointer type. */
1121 if (mips_abi_regsize (gdbarch
)
1122 == builtin_type (gdbarch
)->builtin_data_ptr
->length())
1124 if (rawnum
== MIPS_SP_REGNUM
1125 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1126 return builtin_type (gdbarch
)->builtin_data_ptr
;
1127 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1128 return builtin_type (gdbarch
)->builtin_func_ptr
;
1131 if (mips_abi_regsize (gdbarch
) == 4 && rawtype
->length () == 8
1132 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1133 || rawnum
== mips_regnum (gdbarch
)->lo
1134 || rawnum
== mips_regnum (gdbarch
)->hi
1135 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1136 || rawnum
== mips_regnum (gdbarch
)->cause
1137 || rawnum
== mips_regnum (gdbarch
)->pc
1138 || (mips_regnum (gdbarch
)->dspacc
!= -1
1139 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1140 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1141 return builtin_type (gdbarch
)->builtin_int32
;
1143 /* The pseudo/cooked view of embedded registers is always
1144 32-bit, even if the target transfers 64-bit values for them.
1145 New targets relying on XML descriptions should only transfer
1146 the necessary 32 bits, but older versions of GDB expected 64,
1147 so allow the target to provide 64 bits without interfering
1148 with the displayed type. */
1149 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1150 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1151 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1152 return builtin_type (gdbarch
)->builtin_int32
;
1154 /* For all other registers, pass through the hardware type. */
1158 /* Should the upper word of 64-bit addresses be zeroed? */
1159 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1162 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1164 switch (mask_address_var
)
1166 case AUTO_BOOLEAN_TRUE
:
1168 case AUTO_BOOLEAN_FALSE
:
1171 case AUTO_BOOLEAN_AUTO
:
1172 return tdep
->default_mask_address_p
;
1174 internal_error (_("mips_mask_address_p: bad switch"));
1180 show_mask_address (struct ui_file
*file
, int from_tty
,
1181 struct cmd_list_element
*c
, const char *value
)
1183 const char *additional_text
= "";
1184 if (mask_address_var
== AUTO_BOOLEAN_AUTO
)
1186 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
1187 additional_text
= _(" (current architecture is not MIPS)");
1190 mips_gdbarch_tdep
*tdep
1191 = gdbarch_tdep
<mips_gdbarch_tdep
> (target_gdbarch ());
1193 if (mips_mask_address_p (tdep
))
1194 additional_text
= _(" (currently \"on\")");
1196 additional_text
= _(" (currently \"off\")");
1200 gdb_printf (file
, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
1201 value
, additional_text
);
1204 /* Tell if the program counter value in MEMADDR is in a standard ISA
1208 mips_pc_is_mips (CORE_ADDR memaddr
)
1210 struct bound_minimal_symbol sym
;
1212 /* Flags indicating that this is a MIPS16 or microMIPS function is
1213 stored by elfread.c in the high bit of the info field. Use this
1214 to decide if the function is standard MIPS. Otherwise if bit 0
1215 of the address is clear, then this is a standard MIPS function. */
1216 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1218 return msymbol_is_mips (sym
.minsym
);
1220 return is_mips_addr (memaddr
);
1223 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1226 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1228 struct bound_minimal_symbol sym
;
1230 /* A flag indicating that this is a MIPS16 function is stored by
1231 elfread.c in the high bit of the info field. Use this to decide
1232 if the function is MIPS16. Otherwise if bit 0 of the address is
1233 set, then ELF file flags will tell if this is a MIPS16 function. */
1234 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1236 return msymbol_is_mips16 (sym
.minsym
);
1238 return is_mips16_addr (gdbarch
, memaddr
);
1241 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1244 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1246 struct bound_minimal_symbol sym
;
1248 /* A flag indicating that this is a microMIPS function is stored by
1249 elfread.c in the high bit of the info field. Use this to decide
1250 if the function is microMIPS. Otherwise if bit 0 of the address
1251 is set, then ELF file flags will tell if this is a microMIPS
1253 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1255 return msymbol_is_micromips (sym
.minsym
);
1257 return is_micromips_addr (gdbarch
, memaddr
);
1260 /* Tell the ISA type of the function the program counter value in MEMADDR
1263 static enum mips_isa
1264 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1266 struct bound_minimal_symbol sym
;
1268 /* A flag indicating that this is a MIPS16 or a microMIPS function
1269 is stored by elfread.c in the high bit of the info field. Use
1270 this to decide if the function is MIPS16 or microMIPS or normal
1271 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1272 flags will tell if this is a MIPS16 or a microMIPS function. */
1273 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1276 if (msymbol_is_micromips (sym
.minsym
))
1277 return ISA_MICROMIPS
;
1278 else if (msymbol_is_mips16 (sym
.minsym
))
1285 if (is_mips_addr (memaddr
))
1287 else if (is_micromips_addr (gdbarch
, memaddr
))
1288 return ISA_MICROMIPS
;
1294 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1295 The need for comes from the ISA bit having been cleared, making
1296 addresses in FDE, range records, etc. referring to compressed code
1297 different to those in line information, the symbol table and finally
1298 the PC register. That in turn confuses many operations. */
1301 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1303 pc
= unmake_compact_addr (pc
);
1304 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1307 /* Recalculate the line record requested so that the resulting PC has
1308 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1309 this adjustment comes from some records associated with compressed
1310 code having the ISA bit cleared, most notably at function prologue
1311 ends. The ISA bit is in this context retrieved from the minimal
1312 symbol covering the address requested, which in turn has been
1313 constructed from the binary's symbol table rather than DWARF-2
1314 information. The correct setting of the ISA bit is required for
1315 breakpoint addresses to correctly match against the stop PC.
1317 As line entries can specify relative address adjustments we need to
1318 keep track of the absolute value of the last line address recorded
1319 in line information, so that we can calculate the actual address to
1320 apply the ISA bit adjustment to. We use PC for this tracking and
1321 keep the original address there.
1323 As such relative address adjustments can be odd within compressed
1324 code we need to keep track of the last line address with the ISA
1325 bit adjustment applied too, as the original address may or may not
1326 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1327 the adjusted address there.
1329 For relative address adjustments we then use these variables to
1330 calculate the address intended by line information, which will be
1331 PC-relative, and return an updated adjustment carrying ISA bit
1332 information, which will be ADJ_PC-relative. For absolute address
1333 adjustments we just return the same address that we store in ADJ_PC
1336 As the first line entry can be relative to an implied address value
1337 of 0 we need to have the initial address set up that we store in PC
1338 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1339 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1342 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1344 static CORE_ADDR adj_pc
;
1345 static CORE_ADDR pc
;
1348 pc
= rel
? pc
+ addr
: addr
;
1349 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1350 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1355 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1357 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1358 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1359 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1360 static const char mips_str_call_stub
[] = "__call_stub_";
1361 static const char mips_str_fn_stub
[] = "__fn_stub_";
1363 /* This is used as a PIC thunk prefix. */
1365 static const char mips_str_pic
[] = ".pic.";
1367 /* Return non-zero if the PC is inside a call thunk (aka stub or
1368 trampoline) that should be treated as a temporary frame. */
1371 mips_in_frame_stub (CORE_ADDR pc
)
1373 CORE_ADDR start_addr
;
1376 /* Find the starting address of the function containing the PC. */
1377 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1380 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1381 if (startswith (name
, mips_str_mips16_call_stub
))
1383 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1384 if (startswith (name
, mips_str_call_stub
))
1386 /* If the PC is in __fn_stub_*, this is a call stub. */
1387 if (startswith (name
, mips_str_fn_stub
))
1390 return 0; /* Not a stub. */
1393 /* MIPS believes that the PC has a sign extended value. Perhaps the
1394 all registers should be sign extended for simplicity? */
1397 mips_read_pc (readable_regcache
*regcache
)
1399 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1402 regcache
->cooked_read (regnum
, &pc
);
1407 mips_unwind_pc (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1411 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1412 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1413 intermediate frames. In this case we can get the caller's address
1414 from $ra, or if $ra contains an address within a thunk as well, then
1415 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1416 and thus the caller's address is in $s2. */
1417 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1419 pc
= frame_unwind_register_signed
1420 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1421 if (mips_in_frame_stub (pc
))
1422 pc
= frame_unwind_register_signed
1423 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1429 mips_unwind_sp (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1431 return frame_unwind_register_signed
1432 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1435 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1436 dummy frame. The frame ID's base needs to match the TOS value
1437 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1440 static struct frame_id
1441 mips_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
1443 return frame_id_build
1444 (get_frame_register_signed (this_frame
,
1445 gdbarch_num_regs (gdbarch
)
1447 get_frame_pc (this_frame
));
1450 /* Implement the "write_pc" gdbarch method. */
1453 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1455 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1457 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1460 /* Fetch and return instruction from the specified location. Handle
1461 MIPS16/microMIPS as appropriate. */
1464 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1465 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1467 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1468 gdb_byte buf
[MIPS_INSN32_SIZE
];
1476 instlen
= MIPS_INSN16_SIZE
;
1477 addr
= unmake_compact_addr (addr
);
1480 instlen
= MIPS_INSN32_SIZE
;
1483 internal_error (_("invalid ISA"));
1486 err
= target_read_memory (addr
, buf
, instlen
);
1492 memory_error (TARGET_XFER_E_IO
, addr
);
1495 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1498 /* These are the fields of 32 bit mips instructions. */
1499 #define mips32_op(x) (x >> 26)
1500 #define itype_op(x) (x >> 26)
1501 #define itype_rs(x) ((x >> 21) & 0x1f)
1502 #define itype_rt(x) ((x >> 16) & 0x1f)
1503 #define itype_immediate(x) (x & 0xffff)
1505 #define jtype_op(x) (x >> 26)
1506 #define jtype_target(x) (x & 0x03ffffff)
1508 #define rtype_op(x) (x >> 26)
1509 #define rtype_rs(x) ((x >> 21) & 0x1f)
1510 #define rtype_rt(x) ((x >> 16) & 0x1f)
1511 #define rtype_rd(x) ((x >> 11) & 0x1f)
1512 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1513 #define rtype_funct(x) (x & 0x3f)
1515 /* MicroMIPS instruction fields. */
1516 #define micromips_op(x) ((x) >> 10)
1518 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1519 bit and the size respectively of the field extracted. */
1520 #define b0s4_imm(x) ((x) & 0xf)
1521 #define b0s5_imm(x) ((x) & 0x1f)
1522 #define b0s5_reg(x) ((x) & 0x1f)
1523 #define b0s7_imm(x) ((x) & 0x7f)
1524 #define b0s10_imm(x) ((x) & 0x3ff)
1525 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1526 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1527 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1528 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1529 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1530 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1531 #define b6s4_op(x) (((x) >> 6) & 0xf)
1532 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1534 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1535 respectively of the field extracted. */
1536 #define b0s6_op(x) ((x) & 0x3f)
1537 #define b0s11_op(x) ((x) & 0x7ff)
1538 #define b0s12_imm(x) ((x) & 0xfff)
1539 #define b0s16_imm(x) ((x) & 0xffff)
1540 #define b0s26_imm(x) ((x) & 0x3ffffff)
1541 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1542 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1543 #define b12s4_op(x) (((x) >> 12) & 0xf)
1545 /* Return the size in bytes of the instruction INSN encoded in the ISA
1549 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1554 if ((micromips_op (insn
) & 0x4) == 0x4
1555 || (micromips_op (insn
) & 0x7) == 0x0)
1556 return 2 * MIPS_INSN16_SIZE
;
1558 return MIPS_INSN16_SIZE
;
1560 if ((insn
& 0xf800) == 0xf000)
1561 return 2 * MIPS_INSN16_SIZE
;
1563 return MIPS_INSN16_SIZE
;
1565 return MIPS_INSN32_SIZE
;
1567 internal_error (_("invalid ISA"));
1571 mips32_relative_offset (ULONGEST inst
)
1573 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1576 /* Determine the address of the next instruction executed after the INST
1577 floating condition branch instruction at PC. COUNT specifies the
1578 number of the floating condition bits tested by the branch. */
1581 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1582 ULONGEST inst
, CORE_ADDR pc
, int count
)
1584 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1585 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1586 int tf
= itype_rt (inst
) & 1;
1587 int mask
= (1 << count
) - 1;
1592 /* No way to handle; it'll most likely trap anyway. */
1595 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1596 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1598 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1599 pc
+= mips32_relative_offset (inst
);
1606 /* Return nonzero if the gdbarch is an Octeon series. */
1609 is_octeon (struct gdbarch
*gdbarch
)
1611 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1613 return (info
->mach
== bfd_mach_mips_octeon
1614 || info
->mach
== bfd_mach_mips_octeonp
1615 || info
->mach
== bfd_mach_mips_octeon2
);
1618 /* Return true if the OP represents the Octeon's BBIT instruction. */
1621 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1623 if (!is_octeon (gdbarch
))
1625 /* BBIT0 is encoded as LWC2: 110 010. */
1626 /* BBIT032 is encoded as LDC2: 110 110. */
1627 /* BBIT1 is encoded as SWC2: 111 010. */
1628 /* BBIT132 is encoded as SDC2: 111 110. */
1629 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1635 /* Determine where to set a single step breakpoint while considering
1636 branch prediction. */
1639 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1641 struct gdbarch
*gdbarch
= regcache
->arch ();
1644 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1645 op
= itype_op (inst
);
1646 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1650 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1661 goto greater_branch
;
1666 else if (op
== 17 && itype_rs (inst
) == 8)
1667 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1668 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1669 else if (op
== 17 && itype_rs (inst
) == 9
1670 && (itype_rt (inst
) & 2) == 0)
1671 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1672 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1673 else if (op
== 17 && itype_rs (inst
) == 10
1674 && (itype_rt (inst
) & 2) == 0)
1675 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1676 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1679 /* The new PC will be alternate mode. */
1683 reg
= jtype_target (inst
) << 2;
1684 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1685 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1687 else if (is_octeon_bbit_op (op
, gdbarch
))
1691 branch_if
= op
== 58 || op
== 62;
1692 bit
= itype_rt (inst
);
1694 /* Take into account the *32 instructions. */
1695 if (op
== 54 || op
== 62)
1698 if (((regcache_raw_get_signed (regcache
,
1699 itype_rs (inst
)) >> bit
) & 1)
1701 pc
+= mips32_relative_offset (inst
) + 4;
1703 pc
+= 8; /* After the delay slot. */
1707 pc
+= 4; /* Not a branch, next instruction is easy. */
1710 { /* This gets way messy. */
1712 /* Further subdivide into SPECIAL, REGIMM and other. */
1713 switch (op
& 0x07) /* Extract bits 28,27,26. */
1715 case 0: /* SPECIAL */
1716 op
= rtype_funct (inst
);
1721 /* Set PC to that address. */
1722 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1724 case 12: /* SYSCALL */
1726 mips_gdbarch_tdep
*tdep
1727 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1729 if (tdep
->syscall_next_pc
!= NULL
)
1730 pc
= tdep
->syscall_next_pc (get_current_frame ());
1739 break; /* end SPECIAL */
1740 case 1: /* REGIMM */
1742 op
= itype_rt (inst
); /* branch condition */
1747 case 16: /* BLTZAL */
1748 case 18: /* BLTZALL */
1750 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1751 pc
+= mips32_relative_offset (inst
) + 4;
1753 pc
+= 8; /* after the delay slot */
1757 case 17: /* BGEZAL */
1758 case 19: /* BGEZALL */
1759 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1760 pc
+= mips32_relative_offset (inst
) + 4;
1762 pc
+= 8; /* after the delay slot */
1764 case 0x1c: /* BPOSGE32 */
1765 case 0x1e: /* BPOSGE64 */
1767 if (itype_rs (inst
) == 0)
1769 unsigned int pos
= (op
& 2) ? 64 : 32;
1770 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1773 /* No way to handle; it'll most likely trap anyway. */
1776 if ((regcache_raw_get_unsigned (regcache
,
1777 dspctl
) & 0x7f) >= pos
)
1778 pc
+= mips32_relative_offset (inst
);
1783 /* All of the other instructions in the REGIMM category */
1788 break; /* end REGIMM */
1793 reg
= jtype_target (inst
) << 2;
1794 /* Upper four bits get never changed... */
1795 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1798 case 4: /* BEQ, BEQL */
1800 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1801 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1802 pc
+= mips32_relative_offset (inst
) + 4;
1806 case 5: /* BNE, BNEL */
1808 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1809 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1810 pc
+= mips32_relative_offset (inst
) + 4;
1814 case 6: /* BLEZ, BLEZL */
1815 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1816 pc
+= mips32_relative_offset (inst
) + 4;
1822 greater_branch
: /* BGTZ, BGTZL */
1823 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1824 pc
+= mips32_relative_offset (inst
) + 4;
1831 } /* mips32_next_pc */
1833 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1837 micromips_relative_offset7 (ULONGEST insn
)
1839 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1842 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1846 micromips_relative_offset10 (ULONGEST insn
)
1848 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1851 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1855 micromips_relative_offset16 (ULONGEST insn
)
1857 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1860 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1863 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1867 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1868 return mips_insn_size (ISA_MICROMIPS
, insn
);
1871 /* Calculate the address of the next microMIPS instruction to execute
1872 after the INSN coprocessor 1 conditional branch instruction at the
1873 address PC. COUNT denotes the number of coprocessor condition bits
1874 examined by the branch. */
1877 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1878 ULONGEST insn
, CORE_ADDR pc
, int count
)
1880 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1881 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1882 int tf
= b5s5_op (insn
>> 16) & 1;
1883 int mask
= (1 << count
) - 1;
1888 /* No way to handle; it'll most likely trap anyway. */
1891 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1892 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1894 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1895 pc
+= micromips_relative_offset16 (insn
);
1897 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1902 /* Calculate the address of the next microMIPS instruction to execute
1903 after the instruction at the address PC. */
1906 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1908 struct gdbarch
*gdbarch
= regcache
->arch ();
1911 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1912 pc
+= MIPS_INSN16_SIZE
;
1913 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1915 /* 32-bit instructions. */
1916 case 2 * MIPS_INSN16_SIZE
:
1918 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1919 pc
+= MIPS_INSN16_SIZE
;
1920 switch (micromips_op (insn
>> 16))
1922 case 0x00: /* POOL32A: bits 000000 */
1923 switch (b0s6_op (insn
))
1925 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1926 switch (b6s10_ext (insn
))
1928 case 0x3c: /* JALR: 000000 0000111100 111100 */
1929 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1930 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1931 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1932 pc
= regcache_raw_get_signed (regcache
,
1933 b0s5_reg (insn
>> 16));
1935 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1937 mips_gdbarch_tdep
*tdep
1938 = gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
1940 if (tdep
->syscall_next_pc
!= NULL
)
1941 pc
= tdep
->syscall_next_pc (get_current_frame ());
1949 case 0x10: /* POOL32I: bits 010000 */
1950 switch (b5s5_op (insn
>> 16))
1952 case 0x00: /* BLTZ: bits 010000 00000 */
1953 case 0x01: /* BLTZAL: bits 010000 00001 */
1954 case 0x11: /* BLTZALS: bits 010000 10001 */
1955 if (regcache_raw_get_signed (regcache
,
1956 b0s5_reg (insn
>> 16)) < 0)
1957 pc
+= micromips_relative_offset16 (insn
);
1959 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1962 case 0x02: /* BGEZ: bits 010000 00010 */
1963 case 0x03: /* BGEZAL: bits 010000 00011 */
1964 case 0x13: /* BGEZALS: bits 010000 10011 */
1965 if (regcache_raw_get_signed (regcache
,
1966 b0s5_reg (insn
>> 16)) >= 0)
1967 pc
+= micromips_relative_offset16 (insn
);
1969 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1972 case 0x04: /* BLEZ: bits 010000 00100 */
1973 if (regcache_raw_get_signed (regcache
,
1974 b0s5_reg (insn
>> 16)) <= 0)
1975 pc
+= micromips_relative_offset16 (insn
);
1977 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1980 case 0x05: /* BNEZC: bits 010000 00101 */
1981 if (regcache_raw_get_signed (regcache
,
1982 b0s5_reg (insn
>> 16)) != 0)
1983 pc
+= micromips_relative_offset16 (insn
);
1986 case 0x06: /* BGTZ: bits 010000 00110 */
1987 if (regcache_raw_get_signed (regcache
,
1988 b0s5_reg (insn
>> 16)) > 0)
1989 pc
+= micromips_relative_offset16 (insn
);
1991 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1994 case 0x07: /* BEQZC: bits 010000 00111 */
1995 if (regcache_raw_get_signed (regcache
,
1996 b0s5_reg (insn
>> 16)) == 0)
1997 pc
+= micromips_relative_offset16 (insn
);
2000 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2001 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2002 if (((insn
>> 16) & 0x3) == 0x0)
2003 /* BC2F, BC2T: don't know how to handle these. */
2007 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2008 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2010 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2011 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2014 /* No way to handle; it'll most likely trap anyway. */
2017 if ((regcache_raw_get_unsigned (regcache
,
2018 dspctl
) & 0x7f) >= pos
)
2019 pc
+= micromips_relative_offset16 (insn
);
2021 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2025 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2026 /* BC1ANY2F: bits 010000 11100 xxx01 */
2027 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2028 /* BC1ANY2T: bits 010000 11101 xxx01 */
2029 if (((insn
>> 16) & 0x2) == 0x0)
2030 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2031 ((insn
>> 16) & 0x1) + 1);
2034 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2035 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2036 if (((insn
>> 16) & 0x3) == 0x1)
2037 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2042 case 0x1d: /* JALS: bits 011101 */
2043 case 0x35: /* J: bits 110101 */
2044 case 0x3d: /* JAL: bits 111101 */
2045 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2048 case 0x25: /* BEQ: bits 100101 */
2049 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2050 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2051 pc
+= micromips_relative_offset16 (insn
);
2053 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2056 case 0x2d: /* BNE: bits 101101 */
2057 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2058 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2059 pc
+= micromips_relative_offset16 (insn
);
2061 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2064 case 0x3c: /* JALX: bits 111100 */
2065 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2070 /* 16-bit instructions. */
2071 case MIPS_INSN16_SIZE
:
2072 switch (micromips_op (insn
))
2074 case 0x11: /* POOL16C: bits 010001 */
2075 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2076 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2077 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2078 else if (b5s5_op (insn
) == 0x18)
2079 /* JRADDIUSP: bits 010001 11000 */
2080 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2083 case 0x23: /* BEQZ16: bits 100011 */
2085 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2087 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2088 pc
+= micromips_relative_offset7 (insn
);
2090 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2094 case 0x2b: /* BNEZ16: bits 101011 */
2096 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2098 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2099 pc
+= micromips_relative_offset7 (insn
);
2101 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2105 case 0x33: /* B16: bits 110011 */
2106 pc
+= micromips_relative_offset10 (insn
);
2115 /* Decoding the next place to set a breakpoint is irregular for the
2116 mips 16 variant, but fortunately, there fewer instructions. We have
2117 to cope ith extensions for 16 bit instructions and a pair of actual
2118 32 bit instructions. We dont want to set a single step instruction
2119 on the extend instruction either. */
2121 /* Lots of mips16 instruction formats */
2122 /* Predicting jumps requires itype,ritype,i8type
2123 and their extensions extItype,extritype,extI8type. */
2124 enum mips16_inst_fmts
2126 itype
, /* 0 immediate 5,10 */
2127 ritype
, /* 1 5,3,8 */
2128 rrtype
, /* 2 5,3,3,5 */
2129 rritype
, /* 3 5,3,3,5 */
2130 rrrtype
, /* 4 5,3,3,3,2 */
2131 rriatype
, /* 5 5,3,3,1,4 */
2132 shifttype
, /* 6 5,3,3,3,2 */
2133 i8type
, /* 7 5,3,8 */
2134 i8movtype
, /* 8 5,3,3,5 */
2135 i8mov32rtype
, /* 9 5,3,5,3 */
2136 i64type
, /* 10 5,3,8 */
2137 ri64type
, /* 11 5,3,3,5 */
2138 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2139 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2140 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2141 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2142 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2143 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2144 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2145 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2146 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2147 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2149 /* I am heaping all the fields of the formats into one structure and
2150 then, only the fields which are involved in instruction extension. */
2154 unsigned int regx
; /* Function in i8 type. */
2159 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2160 for the bits which make up the immediate extension. */
2163 extended_offset (unsigned int extension
)
2167 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2169 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2171 value
|= extension
& 0x1f; /* Extract 4:0. */
2176 /* Only call this function if you know that this is an extendable
2177 instruction. It won't malfunction, but why make excess remote memory
2178 references? If the immediate operands get sign extended or something,
2179 do it after the extension is performed. */
2180 /* FIXME: Every one of these cases needs to worry about sign extension
2181 when the offset is to be used in relative addressing. */
2184 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2186 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2189 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2190 target_read_memory (pc
, buf
, 2);
2191 return extract_unsigned_integer (buf
, 2, byte_order
);
2195 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2196 unsigned int extension
,
2198 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2203 switch (insn_format
)
2210 value
= extended_offset ((extension
<< 16) | inst
);
2211 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2215 value
= inst
& 0x7ff;
2216 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2225 { /* A register identifier and an offset. */
2226 /* Most of the fields are the same as I type but the
2227 immediate value is of a different length. */
2231 value
= extended_offset ((extension
<< 16) | inst
);
2232 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2236 value
= inst
& 0xff; /* 8 bits */
2237 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2240 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2246 unsigned long value
;
2247 unsigned int nexthalf
;
2248 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2249 value
= value
<< 16;
2250 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2251 /* Low bit still set. */
2259 internal_error (_("bad switch"));
2261 upk
->offset
= offset
;
2267 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2268 and having a signed 16-bit OFFSET. */
2271 add_offset_16 (CORE_ADDR pc
, int offset
)
2273 return pc
+ (offset
<< 1) + 2;
2277 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2278 unsigned int extension
, unsigned int insn
)
2280 struct gdbarch
*gdbarch
= regcache
->arch ();
2281 int op
= (insn
>> 11);
2284 case 2: /* Branch */
2286 struct upk_mips16 upk
;
2287 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2288 pc
= add_offset_16 (pc
, upk
.offset
);
2291 case 3: /* JAL , JALX - Watch out, these are 32 bit
2294 struct upk_mips16 upk
;
2295 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2296 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2297 if ((insn
>> 10) & 0x01) /* Exchange mode */
2298 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2305 struct upk_mips16 upk
;
2307 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2308 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2310 pc
= add_offset_16 (pc
, upk
.offset
);
2317 struct upk_mips16 upk
;
2319 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2320 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2322 pc
= add_offset_16 (pc
, upk
.offset
);
2327 case 12: /* I8 Formats btez btnez */
2329 struct upk_mips16 upk
;
2331 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2332 /* upk.regx contains the opcode */
2333 /* Test register is 24 */
2334 reg
= regcache_raw_get_signed (regcache
, 24);
2335 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2336 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2337 pc
= add_offset_16 (pc
, upk
.offset
);
2342 case 29: /* RR Formats JR, JALR, JALR-RA */
2344 struct upk_mips16 upk
;
2345 /* upk.fmt = rrtype; */
2350 upk
.regx
= (insn
>> 8) & 0x07;
2351 upk
.regy
= (insn
>> 5) & 0x07;
2352 if ((upk
.regy
& 1) == 0)
2353 reg
= mips_reg3_to_reg
[upk
.regx
];
2355 reg
= 31; /* Function return instruction. */
2356 pc
= regcache_raw_get_signed (regcache
, reg
);
2363 /* This is an instruction extension. Fetch the real instruction
2364 (which follows the extension) and decode things based on
2368 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2369 fetch_mips_16 (gdbarch
, pc
));
2382 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2384 struct gdbarch
*gdbarch
= regcache
->arch ();
2385 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2386 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2389 /* The mips_next_pc function supports single_step when the remote
2390 target monitor or stub is not developed enough to do a single_step.
2391 It works by decoding the current instruction and predicting where a
2392 branch will go. This isn't hard because all the data is available.
2393 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2395 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2397 struct gdbarch
*gdbarch
= regcache
->arch ();
2399 if (mips_pc_is_mips16 (gdbarch
, pc
))
2400 return mips16_next_pc (regcache
, pc
);
2401 else if (mips_pc_is_micromips (gdbarch
, pc
))
2402 return micromips_next_pc (regcache
, pc
);
2404 return mips32_next_pc (regcache
, pc
);
2407 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2411 mips16_instruction_is_compact_branch (unsigned short insn
)
2413 switch (insn
& 0xf800)
2416 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2418 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2419 case 0x2800: /* BNEZ */
2420 case 0x2000: /* BEQZ */
2421 case 0x1000: /* B */
2428 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2432 micromips_instruction_is_compact_branch (unsigned short insn
)
2434 switch (micromips_op (insn
))
2436 case 0x11: /* POOL16C: bits 010001 */
2437 return (b5s5_op (insn
) == 0x18
2438 /* JRADDIUSP: bits 010001 11000 */
2439 || b5s5_op (insn
) == 0xd);
2440 /* JRC: bits 010011 01101 */
2441 case 0x10: /* POOL32I: bits 010000 */
2442 return (b5s5_op (insn
) & 0x1d) == 0x5;
2443 /* BEQZC/BNEZC: bits 010000 001x1 */
2449 struct mips_frame_cache
2452 trad_frame_saved_reg
*saved_regs
;
2455 /* Set a register's saved stack address in temp_saved_regs. If an
2456 address has already been set for this register, do nothing; this
2457 way we will only recognize the first save of a given register in a
2460 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2461 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2462 Strictly speaking, only the second range is used as it is only second
2463 range (the ABI instead of ISA registers) that comes into play when finding
2464 saved registers in a frame. */
2467 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2468 int regnum
, CORE_ADDR offset
)
2470 if (this_cache
!= NULL
2471 && this_cache
->saved_regs
[regnum
].is_realreg ()
2472 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2474 this_cache
->saved_regs
[regnum
+ 0
2475 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2476 this_cache
->saved_regs
[regnum
+ 1
2477 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2482 /* Fetch the immediate value from a MIPS16 instruction.
2483 If the previous instruction was an EXTEND, use it to extend
2484 the upper bits of the immediate value. This is a helper function
2485 for mips16_scan_prologue. */
2488 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2489 unsigned short inst
, /* current instruction */
2490 int nbits
, /* number of bits in imm field */
2491 int scale
, /* scale factor to be applied to imm */
2492 int is_signed
) /* is the imm field signed? */
2496 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2498 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2499 if (offset
& 0x8000) /* check for negative extend */
2500 offset
= 0 - (0x10000 - (offset
& 0xffff));
2501 return offset
| (inst
& 0x1f);
2505 int max_imm
= 1 << nbits
;
2506 int mask
= max_imm
- 1;
2507 int sign_bit
= max_imm
>> 1;
2509 offset
= inst
& mask
;
2510 if (is_signed
&& (offset
& sign_bit
))
2511 offset
= 0 - (max_imm
- offset
);
2512 return offset
* scale
;
2517 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2518 the associated FRAME_CACHE if not null.
2519 Return the address of the first instruction past the prologue. */
2522 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2523 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2524 frame_info_ptr this_frame
,
2525 struct mips_frame_cache
*this_cache
)
2527 int prev_non_prologue_insn
= 0;
2528 int this_non_prologue_insn
;
2529 int non_prologue_insns
= 0;
2532 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2534 long frame_offset
= 0; /* Size of stack frame. */
2535 long frame_adjust
= 0; /* Offset of FP from SP. */
2536 int frame_reg
= MIPS_SP_REGNUM
;
2537 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2538 unsigned inst
= 0; /* current instruction */
2539 unsigned entry_inst
= 0; /* the entry instruction */
2540 unsigned save_inst
= 0; /* the save instruction */
2541 int prev_delay_slot
= 0;
2545 int extend_bytes
= 0;
2546 int prev_extend_bytes
= 0;
2547 CORE_ADDR end_prologue_addr
;
2549 /* Can be called when there's no process, and hence when there's no
2551 if (this_frame
!= NULL
)
2552 sp
= get_frame_register_signed (this_frame
,
2553 gdbarch_num_regs (gdbarch
)
2558 if (limit_pc
> start_pc
+ 200)
2559 limit_pc
= start_pc
+ 200;
2562 /* Permit at most one non-prologue non-control-transfer instruction
2563 in the middle which may have been reordered by the compiler for
2565 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2567 this_non_prologue_insn
= 0;
2570 /* Save the previous instruction. If it's an EXTEND, we'll extract
2571 the immediate offset extension from it in mips16_get_imm. */
2574 /* Fetch and decode the instruction. */
2575 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2578 /* Normally we ignore extend instructions. However, if it is
2579 not followed by a valid prologue instruction, then this
2580 instruction is not part of the prologue either. We must
2581 remember in this case to adjust the end_prologue_addr back
2583 if ((inst
& 0xf800) == 0xf000) /* extend */
2585 extend_bytes
= MIPS_INSN16_SIZE
;
2589 prev_extend_bytes
= extend_bytes
;
2592 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2593 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2595 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2596 if (offset
< 0) /* Negative stack adjustment? */
2597 frame_offset
-= offset
;
2599 /* Exit loop if a positive stack adjustment is found, which
2600 usually means that the stack cleanup code in the function
2601 epilogue is reached. */
2604 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2606 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2607 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2608 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2610 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2612 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2613 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2614 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2616 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2618 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2619 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2621 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2623 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2624 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2626 else if (inst
== 0x673d) /* move $s1, $sp */
2631 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2633 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2634 frame_addr
= sp
+ offset
;
2636 frame_adjust
= offset
;
2638 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2640 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2641 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2642 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2644 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2646 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2647 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2648 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2650 else if ((inst
& 0xf81f) == 0xe809
2651 && (inst
& 0x700) != 0x700) /* entry */
2652 entry_inst
= inst
; /* Save for later processing. */
2653 else if ((inst
& 0xff80) == 0x6480) /* save */
2655 save_inst
= inst
; /* Save for later processing. */
2656 if (prev_extend_bytes
) /* extend */
2657 save_inst
|= prev_inst
<< 16;
2659 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2661 /* This instruction is part of the prologue, but we don't
2662 need to do anything special to handle it. */
2664 else if (mips16_instruction_has_delay_slot (inst
, 0))
2665 /* JAL/JALR/JALX/JR */
2667 /* The instruction in the delay slot can be a part
2668 of the prologue, so move forward once more. */
2670 if (mips16_instruction_has_delay_slot (inst
, 1))
2673 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2674 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2679 this_non_prologue_insn
= 1;
2682 non_prologue_insns
+= this_non_prologue_insn
;
2684 /* A jump or branch, or enough non-prologue insns seen? If so,
2685 then we must have reached the end of the prologue by now. */
2686 if (prev_delay_slot
|| non_prologue_insns
> 1
2687 || mips16_instruction_is_compact_branch (inst
))
2690 prev_non_prologue_insn
= this_non_prologue_insn
;
2691 prev_delay_slot
= in_delay_slot
;
2692 prev_pc
= cur_pc
- prev_extend_bytes
;
2695 /* The entry instruction is typically the first instruction in a function,
2696 and it stores registers at offsets relative to the value of the old SP
2697 (before the prologue). But the value of the sp parameter to this
2698 function is the new SP (after the prologue has been executed). So we
2699 can't calculate those offsets until we've seen the entire prologue,
2700 and can calculate what the old SP must have been. */
2701 if (entry_inst
!= 0)
2703 int areg_count
= (entry_inst
>> 8) & 7;
2704 int sreg_count
= (entry_inst
>> 6) & 3;
2706 /* The entry instruction always subtracts 32 from the SP. */
2709 /* Now we can calculate what the SP must have been at the
2710 start of the function prologue. */
2713 /* Check if a0-a3 were saved in the caller's argument save area. */
2714 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2716 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2717 offset
+= mips_abi_regsize (gdbarch
);
2720 /* Check if the ra register was pushed on the stack. */
2722 if (entry_inst
& 0x20)
2724 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2725 offset
-= mips_abi_regsize (gdbarch
);
2728 /* Check if the s0 and s1 registers were pushed on the stack. */
2729 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2731 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2732 offset
-= mips_abi_regsize (gdbarch
);
2736 /* The SAVE instruction is similar to ENTRY, except that defined by the
2737 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2738 size of the frame is specified as an immediate field of instruction
2739 and an extended variation exists which lets additional registers and
2740 frame space to be specified. The instruction always treats registers
2741 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2742 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2744 static int args_table
[16] = {
2745 0, 0, 0, 0, 1, 1, 1, 1,
2746 2, 2, 2, 0, 3, 3, 4, -1,
2748 static int astatic_table
[16] = {
2749 0, 1, 2, 3, 0, 1, 2, 3,
2750 0, 1, 2, 4, 0, 1, 0, -1,
2752 int aregs
= (save_inst
>> 16) & 0xf;
2753 int xsregs
= (save_inst
>> 24) & 0x7;
2754 int args
= args_table
[aregs
];
2755 int astatic
= astatic_table
[aregs
];
2760 warning (_("Invalid number of argument registers encoded in SAVE."));
2765 warning (_("Invalid number of static registers encoded in SAVE."));
2769 /* For standard SAVE the frame size of 0 means 128. */
2770 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2771 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2774 frame_offset
+= frame_size
;
2776 /* Now we can calculate what the SP must have been at the
2777 start of the function prologue. */
2780 /* Check if A0-A3 were saved in the caller's argument save area. */
2781 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2783 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2784 offset
+= mips_abi_regsize (gdbarch
);
2789 /* Check if the RA register was pushed on the stack. */
2790 if (save_inst
& 0x40)
2792 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2793 offset
-= mips_abi_regsize (gdbarch
);
2796 /* Check if the S8 register was pushed on the stack. */
2799 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2800 offset
-= mips_abi_regsize (gdbarch
);
2803 /* Check if S2-S7 were pushed on the stack. */
2804 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2806 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2807 offset
-= mips_abi_regsize (gdbarch
);
2810 /* Check if the S1 register was pushed on the stack. */
2811 if (save_inst
& 0x10)
2813 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2814 offset
-= mips_abi_regsize (gdbarch
);
2816 /* Check if the S0 register was pushed on the stack. */
2817 if (save_inst
& 0x20)
2819 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2820 offset
-= mips_abi_regsize (gdbarch
);
2823 /* Check if A0-A3 were pushed on the stack. */
2824 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2826 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2827 offset
-= mips_abi_regsize (gdbarch
);
2831 if (this_cache
!= NULL
)
2834 (get_frame_register_signed (this_frame
,
2835 gdbarch_num_regs (gdbarch
) + frame_reg
)
2836 + frame_offset
- frame_adjust
);
2837 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2838 be able to get rid of the assignment below, evetually. But it's
2839 still needed for now. */
2840 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2841 + mips_regnum (gdbarch
)->pc
]
2842 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2845 /* Set end_prologue_addr to the address of the instruction immediately
2846 after the last one we scanned. Unless the last one looked like a
2847 non-prologue instruction (and we looked ahead), in which case use
2848 its address instead. */
2849 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2850 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2852 return end_prologue_addr
;
2855 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2856 Procedures that use the 32-bit instruction set are handled by the
2857 mips_insn32 unwinder. */
2859 static struct mips_frame_cache
*
2860 mips_insn16_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2862 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2863 struct mips_frame_cache
*cache
;
2865 if ((*this_cache
) != NULL
)
2866 return (struct mips_frame_cache
*) (*this_cache
);
2867 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2868 (*this_cache
) = cache
;
2869 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2871 /* Analyze the function prologue. */
2873 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2874 CORE_ADDR start_addr
;
2876 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2877 if (start_addr
== 0)
2878 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2879 /* We can't analyze the prologue if we couldn't find the begining
2881 if (start_addr
== 0)
2884 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2885 (struct mips_frame_cache
*) *this_cache
);
2888 /* gdbarch_sp_regnum contains the value and not the address. */
2889 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2890 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2892 return (struct mips_frame_cache
*) (*this_cache
);
2896 mips_insn16_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2897 struct frame_id
*this_id
)
2899 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2901 /* This marks the outermost frame. */
2902 if (info
->base
== 0)
2904 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2907 static struct value
*
2908 mips_insn16_frame_prev_register (frame_info_ptr this_frame
,
2909 void **this_cache
, int regnum
)
2911 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2913 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2917 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2918 frame_info_ptr this_frame
, void **this_cache
)
2920 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2921 CORE_ADDR pc
= get_frame_pc (this_frame
);
2922 if (mips_pc_is_mips16 (gdbarch
, pc
))
2927 static const struct frame_unwind mips_insn16_frame_unwind
=
2929 "mips insn16 prologue",
2931 default_frame_unwind_stop_reason
,
2932 mips_insn16_frame_this_id
,
2933 mips_insn16_frame_prev_register
,
2935 mips_insn16_frame_sniffer
2939 mips_insn16_frame_base_address (frame_info_ptr this_frame
,
2942 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2947 static const struct frame_base mips_insn16_frame_base
=
2949 &mips_insn16_frame_unwind
,
2950 mips_insn16_frame_base_address
,
2951 mips_insn16_frame_base_address
,
2952 mips_insn16_frame_base_address
2955 static const struct frame_base
*
2956 mips_insn16_frame_base_sniffer (frame_info_ptr this_frame
)
2958 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2959 CORE_ADDR pc
= get_frame_pc (this_frame
);
2960 if (mips_pc_is_mips16 (gdbarch
, pc
))
2961 return &mips_insn16_frame_base
;
2966 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2967 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2968 interpreted directly, and then multiplied by 4. */
2971 micromips_decode_imm9 (int imm
)
2973 imm
= (imm
^ 0x100) - 0x100;
2974 if (imm
> -3 && imm
< 2)
2979 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2980 the address of the first instruction past the prologue. */
2983 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2984 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2985 frame_info_ptr this_frame
,
2986 struct mips_frame_cache
*this_cache
)
2988 CORE_ADDR end_prologue_addr
;
2989 int prev_non_prologue_insn
= 0;
2990 int frame_reg
= MIPS_SP_REGNUM
;
2991 int this_non_prologue_insn
;
2992 int non_prologue_insns
= 0;
2993 long frame_offset
= 0; /* Size of stack frame. */
2994 long frame_adjust
= 0; /* Offset of FP from SP. */
2995 int prev_delay_slot
= 0;
2999 ULONGEST insn
; /* current instruction */
3003 long v1_off
= 0; /* The assumption is LUI will replace it. */
3014 /* Can be called when there's no process, and hence when there's no
3016 if (this_frame
!= NULL
)
3017 sp
= get_frame_register_signed (this_frame
,
3018 gdbarch_num_regs (gdbarch
)
3023 if (limit_pc
> start_pc
+ 200)
3024 limit_pc
= start_pc
+ 200;
3027 /* Permit at most one non-prologue non-control-transfer instruction
3028 in the middle which may have been reordered by the compiler for
3030 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3032 this_non_prologue_insn
= 0;
3036 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3037 loc
+= MIPS_INSN16_SIZE
;
3038 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3040 /* 32-bit instructions. */
3041 case 2 * MIPS_INSN16_SIZE
:
3043 insn
|= mips_fetch_instruction (gdbarch
,
3044 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3045 loc
+= MIPS_INSN16_SIZE
;
3046 switch (micromips_op (insn
>> 16))
3048 /* Record $sp/$fp adjustment. */
3049 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3050 case 0x0: /* POOL32A: bits 000000 */
3051 case 0x16: /* POOL32S: bits 010110 */
3052 op
= b0s11_op (insn
);
3053 sreg
= b0s5_reg (insn
>> 16);
3054 treg
= b5s5_reg (insn
>> 16);
3055 dreg
= b11s5_reg (insn
);
3057 /* SUBU: bits 000000 00111010000 */
3058 /* DSUBU: bits 010110 00111010000 */
3059 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3061 /* (D)SUBU $sp, $v1 */
3063 else if (op
!= 0x150
3064 /* ADDU: bits 000000 00101010000 */
3065 /* DADDU: bits 010110 00101010000 */
3066 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3067 this_non_prologue_insn
= 1;
3070 case 0x8: /* POOL32B: bits 001000 */
3071 op
= b12s4_op (insn
);
3072 breg
= b0s5_reg (insn
>> 16);
3073 reglist
= sreg
= b5s5_reg (insn
>> 16);
3074 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3075 if ((op
== 0x9 || op
== 0xc)
3076 /* SWP: bits 001000 1001 */
3077 /* SDP: bits 001000 1100 */
3078 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3079 /* S[DW]P reg,offset($sp) */
3081 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3082 set_reg_offset (gdbarch
, this_cache
,
3084 set_reg_offset (gdbarch
, this_cache
,
3085 sreg
+ 1, sp
+ offset
+ s
);
3087 else if ((op
== 0xd || op
== 0xf)
3088 /* SWM: bits 001000 1101 */
3089 /* SDM: bits 001000 1111 */
3090 && breg
== MIPS_SP_REGNUM
3091 /* SWM reglist,offset($sp) */
3092 && ((reglist
>= 1 && reglist
<= 9)
3093 || (reglist
>= 16 && reglist
<= 25)))
3095 int sreglist
= std::min(reglist
& 0xf, 8);
3097 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3098 for (i
= 0; i
< sreglist
; i
++)
3099 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3100 if ((reglist
& 0xf) > 8)
3101 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3102 if ((reglist
& 0x10) == 0x10)
3103 set_reg_offset (gdbarch
, this_cache
,
3104 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3107 this_non_prologue_insn
= 1;
3110 /* Record $sp/$fp adjustment. */
3111 /* Discard (D)ADDIU $gp used for PIC code. */
3112 case 0xc: /* ADDIU: bits 001100 */
3113 case 0x17: /* DADDIU: bits 010111 */
3114 sreg
= b0s5_reg (insn
>> 16);
3115 dreg
= b5s5_reg (insn
>> 16);
3116 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3117 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3118 /* (D)ADDIU $sp, imm */
3120 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3121 /* (D)ADDIU $fp, $sp, imm */
3123 frame_adjust
= offset
;
3126 else if (sreg
!= 28 || dreg
!= 28)
3127 /* (D)ADDIU $gp, imm */
3128 this_non_prologue_insn
= 1;
3131 /* LUI $v1 is used for larger $sp adjustments. */
3132 /* Discard LUI $gp used for PIC code. */
3133 case 0x10: /* POOL32I: bits 010000 */
3134 if (b5s5_op (insn
>> 16) == 0xd
3135 /* LUI: bits 010000 001101 */
3136 && b0s5_reg (insn
>> 16) == 3)
3138 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3139 else if (b5s5_op (insn
>> 16) != 0xd
3140 /* LUI: bits 010000 001101 */
3141 || b0s5_reg (insn
>> 16) != 28)
3143 this_non_prologue_insn
= 1;
3146 /* ORI $v1 is used for larger $sp adjustments. */
3147 case 0x14: /* ORI: bits 010100 */
3148 sreg
= b0s5_reg (insn
>> 16);
3149 dreg
= b5s5_reg (insn
>> 16);
3150 if (sreg
== 3 && dreg
== 3)
3152 v1_off
|= b0s16_imm (insn
);
3154 this_non_prologue_insn
= 1;
3157 case 0x26: /* SWC1: bits 100110 */
3158 case 0x2e: /* SDC1: bits 101110 */
3159 breg
= b0s5_reg (insn
>> 16);
3160 if (breg
!= MIPS_SP_REGNUM
)
3161 /* S[DW]C1 reg,offset($sp) */
3162 this_non_prologue_insn
= 1;
3165 case 0x36: /* SD: bits 110110 */
3166 case 0x3e: /* SW: bits 111110 */
3167 breg
= b0s5_reg (insn
>> 16);
3168 sreg
= b5s5_reg (insn
>> 16);
3169 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3170 if (breg
== MIPS_SP_REGNUM
)
3171 /* S[DW] reg,offset($sp) */
3172 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3174 this_non_prologue_insn
= 1;
3178 /* The instruction in the delay slot can be a part
3179 of the prologue, so move forward once more. */
3180 if (micromips_instruction_has_delay_slot (insn
, 0))
3183 this_non_prologue_insn
= 1;
3189 /* 16-bit instructions. */
3190 case MIPS_INSN16_SIZE
:
3191 switch (micromips_op (insn
))
3193 case 0x3: /* MOVE: bits 000011 */
3194 sreg
= b0s5_reg (insn
);
3195 dreg
= b5s5_reg (insn
);
3196 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3199 else if ((sreg
& 0x1c) != 0x4)
3200 /* MOVE reg, $a0-$a3 */
3201 this_non_prologue_insn
= 1;
3204 case 0x11: /* POOL16C: bits 010001 */
3205 if (b6s4_op (insn
) == 0x5)
3206 /* SWM: bits 010001 0101 */
3208 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3209 reglist
= b4s2_regl (insn
);
3210 for (i
= 0; i
<= reglist
; i
++)
3211 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3212 set_reg_offset (gdbarch
, this_cache
,
3213 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3216 this_non_prologue_insn
= 1;
3219 case 0x13: /* POOL16D: bits 010011 */
3220 if ((insn
& 0x1) == 0x1)
3221 /* ADDIUSP: bits 010011 1 */
3222 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3223 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3224 /* ADDIUS5: bits 010011 0 */
3225 /* ADDIUS5 $sp, imm */
3226 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3228 this_non_prologue_insn
= 1;
3231 case 0x32: /* SWSP: bits 110010 */
3232 offset
= b0s5_imm (insn
) << 2;
3233 sreg
= b5s5_reg (insn
);
3234 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3238 /* The instruction in the delay slot can be a part
3239 of the prologue, so move forward once more. */
3240 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3243 this_non_prologue_insn
= 1;
3249 frame_offset
-= sp_adj
;
3251 non_prologue_insns
+= this_non_prologue_insn
;
3253 /* A jump or branch, enough non-prologue insns seen or positive
3254 stack adjustment? If so, then we must have reached the end
3255 of the prologue by now. */
3256 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3257 || micromips_instruction_is_compact_branch (insn
))
3260 prev_non_prologue_insn
= this_non_prologue_insn
;
3261 prev_delay_slot
= in_delay_slot
;
3265 if (this_cache
!= NULL
)
3268 (get_frame_register_signed (this_frame
,
3269 gdbarch_num_regs (gdbarch
) + frame_reg
)
3270 + frame_offset
- frame_adjust
);
3271 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3272 be able to get rid of the assignment below, evetually. But it's
3273 still needed for now. */
3274 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3275 + mips_regnum (gdbarch
)->pc
]
3276 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3279 /* Set end_prologue_addr to the address of the instruction immediately
3280 after the last one we scanned. Unless the last one looked like a
3281 non-prologue instruction (and we looked ahead), in which case use
3282 its address instead. */
3284 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3286 return end_prologue_addr
;
3289 /* Heuristic unwinder for procedures using microMIPS instructions.
3290 Procedures that use the 32-bit instruction set are handled by the
3291 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3293 static struct mips_frame_cache
*
3294 mips_micro_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3296 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3297 struct mips_frame_cache
*cache
;
3299 if ((*this_cache
) != NULL
)
3300 return (struct mips_frame_cache
*) (*this_cache
);
3302 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3303 (*this_cache
) = cache
;
3304 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3306 /* Analyze the function prologue. */
3308 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3309 CORE_ADDR start_addr
;
3311 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3312 if (start_addr
== 0)
3313 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3314 /* We can't analyze the prologue if we couldn't find the begining
3316 if (start_addr
== 0)
3319 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3320 (struct mips_frame_cache
*) *this_cache
);
3323 /* gdbarch_sp_regnum contains the value and not the address. */
3324 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3325 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3327 return (struct mips_frame_cache
*) (*this_cache
);
3331 mips_micro_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3332 struct frame_id
*this_id
)
3334 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3336 /* This marks the outermost frame. */
3337 if (info
->base
== 0)
3339 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3342 static struct value
*
3343 mips_micro_frame_prev_register (frame_info_ptr this_frame
,
3344 void **this_cache
, int regnum
)
3346 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3348 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3352 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3353 frame_info_ptr this_frame
, void **this_cache
)
3355 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3356 CORE_ADDR pc
= get_frame_pc (this_frame
);
3358 if (mips_pc_is_micromips (gdbarch
, pc
))
3363 static const struct frame_unwind mips_micro_frame_unwind
=
3365 "mips micro prologue",
3367 default_frame_unwind_stop_reason
,
3368 mips_micro_frame_this_id
,
3369 mips_micro_frame_prev_register
,
3371 mips_micro_frame_sniffer
3375 mips_micro_frame_base_address (frame_info_ptr this_frame
,
3378 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3383 static const struct frame_base mips_micro_frame_base
=
3385 &mips_micro_frame_unwind
,
3386 mips_micro_frame_base_address
,
3387 mips_micro_frame_base_address
,
3388 mips_micro_frame_base_address
3391 static const struct frame_base
*
3392 mips_micro_frame_base_sniffer (frame_info_ptr this_frame
)
3394 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3395 CORE_ADDR pc
= get_frame_pc (this_frame
);
3397 if (mips_pc_is_micromips (gdbarch
, pc
))
3398 return &mips_micro_frame_base
;
3403 /* Mark all the registers as unset in the saved_regs array
3404 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3407 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3409 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3413 const int num_regs
= gdbarch_num_regs (gdbarch
);
3416 /* Reset the register values to their default state. Register i's value
3417 is in register i. */
3418 for (i
= 0; i
< num_regs
; i
++)
3419 this_cache
->saved_regs
[i
].set_realreg (i
);
3423 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3424 the associated FRAME_CACHE if not null.
3425 Return the address of the first instruction past the prologue. */
3428 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3429 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3430 frame_info_ptr this_frame
,
3431 struct mips_frame_cache
*this_cache
)
3433 int prev_non_prologue_insn
;
3434 int this_non_prologue_insn
;
3435 int non_prologue_insns
;
3436 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3438 int prev_delay_slot
;
3443 int frame_reg
= MIPS_SP_REGNUM
;
3445 CORE_ADDR end_prologue_addr
;
3446 int seen_sp_adjust
= 0;
3447 int load_immediate_bytes
= 0;
3449 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3451 /* Can be called when there's no process, and hence when there's no
3453 if (this_frame
!= NULL
)
3454 sp
= get_frame_register_signed (this_frame
,
3455 gdbarch_num_regs (gdbarch
)
3460 if (limit_pc
> start_pc
+ 200)
3461 limit_pc
= start_pc
+ 200;
3464 prev_non_prologue_insn
= 0;
3465 non_prologue_insns
= 0;
3466 prev_delay_slot
= 0;
3469 /* Permit at most one non-prologue non-control-transfer instruction
3470 in the middle which may have been reordered by the compiler for
3473 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3475 unsigned long inst
, high_word
;
3479 this_non_prologue_insn
= 0;
3482 /* Fetch the instruction. */
3483 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3486 /* Save some code by pre-extracting some useful fields. */
3487 high_word
= (inst
>> 16) & 0xffff;
3488 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3489 reg
= high_word
& 0x1f;
3491 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3492 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3493 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3495 if (offset
< 0) /* Negative stack adjustment? */
3496 frame_offset
-= offset
;
3498 /* Exit loop if a positive stack adjustment is found, which
3499 usually means that the stack cleanup code in the function
3500 epilogue is reached. */
3504 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3505 && !regsize_is_64_bits
)
3507 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3509 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3510 && regsize_is_64_bits
)
3512 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3513 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3515 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3517 /* Old gcc frame, r30 is virtual frame pointer. */
3518 if (offset
!= frame_offset
)
3519 frame_addr
= sp
+ offset
;
3520 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3522 unsigned alloca_adjust
;
3525 frame_addr
= get_frame_register_signed
3526 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3529 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3530 if (alloca_adjust
> 0)
3532 /* FP > SP + frame_size. This may be because of
3533 an alloca or somethings similar. Fix sp to
3534 "pre-alloca" value, and try again. */
3535 sp
+= alloca_adjust
;
3536 /* Need to reset the status of all registers. Otherwise,
3537 we will hit a guard that prevents the new address
3538 for each register to be recomputed during the second
3540 reset_saved_regs (gdbarch
, this_cache
);
3545 /* move $30,$sp. With different versions of gas this will be either
3546 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3547 Accept any one of these. */
3548 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3550 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3551 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3553 unsigned alloca_adjust
;
3556 frame_addr
= get_frame_register_signed
3557 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3559 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3560 if (alloca_adjust
> 0)
3562 /* FP > SP + frame_size. This may be because of
3563 an alloca or somethings similar. Fix sp to
3564 "pre-alloca" value, and try again. */
3566 /* Need to reset the status of all registers. Otherwise,
3567 we will hit a guard that prevents the new address
3568 for each register to be recomputed during the second
3570 reset_saved_regs (gdbarch
, this_cache
);
3575 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3576 && !regsize_is_64_bits
)
3578 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3580 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3581 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3582 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3583 || high_word
== 0x3c1c /* lui $gp,n */
3584 || high_word
== 0x279c /* addiu $gp,$gp,n */
3585 || high_word
== 0x679c /* daddiu $gp,$gp,n */
3586 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3587 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3588 || inst
== 0x0399e02d /* daddu $gp,$gp,$t9 */
3589 || inst
== 0x033ce02d /* daddu $gp,$t9,$gp */
3592 /* These instructions are part of the prologue, but we don't
3593 need to do anything special to handle them. */
3595 /* The instructions below load $at or $t0 with an immediate
3596 value in preparation for a stack adjustment via
3597 subu $sp,$sp,[$at,$t0]. These instructions could also
3598 initialize a local variable, so we accept them only before
3599 a stack adjustment instruction was seen. */
3600 else if (!seen_sp_adjust
3602 && (high_word
== 0x3c01 /* lui $at,n */
3603 || high_word
== 0x3c08 /* lui $t0,n */
3604 || high_word
== 0x3421 /* ori $at,$at,n */
3605 || high_word
== 0x3508 /* ori $t0,$t0,n */
3606 || high_word
== 0x3401 /* ori $at,$zero,n */
3607 || high_word
== 0x3408 /* ori $t0,$zero,n */
3610 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3612 /* Check for branches and jumps. The instruction in the delay
3613 slot can be a part of the prologue, so move forward once more. */
3614 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3618 /* This instruction is not an instruction typically found
3619 in a prologue, so we must have reached the end of the
3623 this_non_prologue_insn
= 1;
3626 non_prologue_insns
+= this_non_prologue_insn
;
3628 /* A jump or branch, or enough non-prologue insns seen? If so,
3629 then we must have reached the end of the prologue by now. */
3630 if (prev_delay_slot
|| non_prologue_insns
> 1)
3633 prev_non_prologue_insn
= this_non_prologue_insn
;
3634 prev_delay_slot
= in_delay_slot
;
3638 if (this_cache
!= NULL
)
3641 (get_frame_register_signed (this_frame
,
3642 gdbarch_num_regs (gdbarch
) + frame_reg
)
3644 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3645 this assignment below, eventually. But it's still needed
3647 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3648 + mips_regnum (gdbarch
)->pc
]
3649 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3653 /* Set end_prologue_addr to the address of the instruction immediately
3654 after the last one we scanned. Unless the last one looked like a
3655 non-prologue instruction (and we looked ahead), in which case use
3656 its address instead. */
3658 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3660 /* In a frameless function, we might have incorrectly
3661 skipped some load immediate instructions. Undo the skipping
3662 if the load immediate was not followed by a stack adjustment. */
3663 if (load_immediate_bytes
&& !seen_sp_adjust
)
3664 end_prologue_addr
-= load_immediate_bytes
;
3666 return end_prologue_addr
;
3669 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3670 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3671 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3672 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3674 static struct mips_frame_cache
*
3675 mips_insn32_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3677 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3678 struct mips_frame_cache
*cache
;
3680 if ((*this_cache
) != NULL
)
3681 return (struct mips_frame_cache
*) (*this_cache
);
3683 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3684 (*this_cache
) = cache
;
3685 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3687 /* Analyze the function prologue. */
3689 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3690 CORE_ADDR start_addr
;
3692 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3693 if (start_addr
== 0)
3694 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3695 /* We can't analyze the prologue if we couldn't find the begining
3697 if (start_addr
== 0)
3700 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3701 (struct mips_frame_cache
*) *this_cache
);
3704 /* gdbarch_sp_regnum contains the value and not the address. */
3705 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3706 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3708 return (struct mips_frame_cache
*) (*this_cache
);
3712 mips_insn32_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3713 struct frame_id
*this_id
)
3715 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3717 /* This marks the outermost frame. */
3718 if (info
->base
== 0)
3720 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3723 static struct value
*
3724 mips_insn32_frame_prev_register (frame_info_ptr this_frame
,
3725 void **this_cache
, int regnum
)
3727 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3729 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3733 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3734 frame_info_ptr this_frame
, void **this_cache
)
3736 CORE_ADDR pc
= get_frame_pc (this_frame
);
3737 if (mips_pc_is_mips (pc
))
3742 static const struct frame_unwind mips_insn32_frame_unwind
=
3744 "mips insn32 prologue",
3746 default_frame_unwind_stop_reason
,
3747 mips_insn32_frame_this_id
,
3748 mips_insn32_frame_prev_register
,
3750 mips_insn32_frame_sniffer
3754 mips_insn32_frame_base_address (frame_info_ptr this_frame
,
3757 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3762 static const struct frame_base mips_insn32_frame_base
=
3764 &mips_insn32_frame_unwind
,
3765 mips_insn32_frame_base_address
,
3766 mips_insn32_frame_base_address
,
3767 mips_insn32_frame_base_address
3770 static const struct frame_base
*
3771 mips_insn32_frame_base_sniffer (frame_info_ptr this_frame
)
3773 CORE_ADDR pc
= get_frame_pc (this_frame
);
3774 if (mips_pc_is_mips (pc
))
3775 return &mips_insn32_frame_base
;
3780 static struct trad_frame_cache
*
3781 mips_stub_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
3784 CORE_ADDR start_addr
;
3785 CORE_ADDR stack_addr
;
3786 struct trad_frame_cache
*this_trad_cache
;
3787 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3788 int num_regs
= gdbarch_num_regs (gdbarch
);
3790 if ((*this_cache
) != NULL
)
3791 return (struct trad_frame_cache
*) (*this_cache
);
3792 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3793 (*this_cache
) = this_trad_cache
;
3795 /* The return address is in the link register. */
3796 trad_frame_set_reg_realreg (this_trad_cache
,
3797 gdbarch_pc_regnum (gdbarch
),
3798 num_regs
+ MIPS_RA_REGNUM
);
3800 /* Frame ID, since it's a frameless / stackless function, no stack
3801 space is allocated and SP on entry is the current SP. */
3802 pc
= get_frame_pc (this_frame
);
3803 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3804 stack_addr
= get_frame_register_signed (this_frame
,
3805 num_regs
+ MIPS_SP_REGNUM
);
3806 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3808 /* Assume that the frame's base is the same as the
3810 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3812 return this_trad_cache
;
3816 mips_stub_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
3817 struct frame_id
*this_id
)
3819 struct trad_frame_cache
*this_trad_cache
3820 = mips_stub_frame_cache (this_frame
, this_cache
);
3821 trad_frame_get_id (this_trad_cache
, this_id
);
3824 static struct value
*
3825 mips_stub_frame_prev_register (frame_info_ptr this_frame
,
3826 void **this_cache
, int regnum
)
3828 struct trad_frame_cache
*this_trad_cache
3829 = mips_stub_frame_cache (this_frame
, this_cache
);
3830 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3834 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3835 frame_info_ptr this_frame
, void **this_cache
)
3838 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3839 struct bound_minimal_symbol msym
;
3841 /* Use the stub unwinder for unreadable code. */
3842 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3845 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3848 /* Calling a PIC function from a non-PIC function passes through a
3849 stub. The stub for foo is named ".pic.foo". */
3850 msym
= lookup_minimal_symbol_by_pc (pc
);
3851 if (msym
.minsym
!= NULL
3852 && msym
.minsym
->linkage_name () != NULL
3853 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3859 static const struct frame_unwind mips_stub_frame_unwind
=
3863 default_frame_unwind_stop_reason
,
3864 mips_stub_frame_this_id
,
3865 mips_stub_frame_prev_register
,
3867 mips_stub_frame_sniffer
3871 mips_stub_frame_base_address (frame_info_ptr this_frame
,
3874 struct trad_frame_cache
*this_trad_cache
3875 = mips_stub_frame_cache (this_frame
, this_cache
);
3876 return trad_frame_get_this_base (this_trad_cache
);
3879 static const struct frame_base mips_stub_frame_base
=
3881 &mips_stub_frame_unwind
,
3882 mips_stub_frame_base_address
,
3883 mips_stub_frame_base_address
,
3884 mips_stub_frame_base_address
3887 static const struct frame_base
*
3888 mips_stub_frame_base_sniffer (frame_info_ptr this_frame
)
3890 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3891 return &mips_stub_frame_base
;
3896 /* mips_addr_bits_remove - remove useless address bits */
3899 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3901 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
3903 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3904 /* This hack is a work-around for existing boards using PMON, the
3905 simulator, and any other 64-bit targets that doesn't have true
3906 64-bit addressing. On these targets, the upper 32 bits of
3907 addresses are ignored by the hardware. Thus, the PC or SP are
3908 likely to have been sign extended to all 1s by instruction
3909 sequences that load 32-bit addresses. For example, a typical
3910 piece of code that loads an address is this:
3912 lui $r2, <upper 16 bits>
3913 ori $r2, <lower 16 bits>
3915 But the lui sign-extends the value such that the upper 32 bits
3916 may be all 1s. The workaround is simply to mask off these
3917 bits. In the future, gcc may be changed to support true 64-bit
3918 addressing, and this masking will have to be disabled. */
3919 return addr
&= 0xffffffffUL
;
3925 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3926 instruction and ending with a SC/SCD instruction. If such a sequence
3927 is found, attempt to step through it. A breakpoint is placed at the end of
3930 /* Instructions used during single-stepping of atomic sequences, standard
3932 #define LL_OPCODE 0x30
3933 #define LLD_OPCODE 0x34
3934 #define SC_OPCODE 0x38
3935 #define SCD_OPCODE 0x3c
3937 static std::vector
<CORE_ADDR
>
3938 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3940 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3942 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3946 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3947 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3949 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3950 /* Assume all atomic sequences start with a ll/lld instruction. */
3951 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3954 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3956 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3959 loc
+= MIPS_INSN32_SIZE
;
3960 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3962 /* Assume that there is at most one branch in the atomic
3963 sequence. If a branch is found, put a breakpoint in its
3964 destination address. */
3965 switch (itype_op (insn
))
3967 case 0: /* SPECIAL */
3968 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3969 return {}; /* fallback to the standard single-step code. */
3971 case 1: /* REGIMM */
3972 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3973 || ((itype_rt (insn
) & 0x1e) == 0
3974 && itype_rs (insn
) == 0)); /* BPOSGE* */
3978 return {}; /* fallback to the standard single-step code. */
3985 case 22: /* BLEZL */
3986 case 23: /* BGTTL */
3990 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3991 && (itype_rt (insn
) & 0x2) == 0);
3992 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3997 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4002 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4003 if (last_breakpoint
>= 1)
4004 return {}; /* More than one branch found, fallback to the
4005 standard single-step code. */
4006 breaks
[1] = branch_bp
;
4010 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4014 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4015 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4018 loc
+= MIPS_INSN32_SIZE
;
4020 /* Insert a breakpoint right after the end of the atomic sequence. */
4023 /* Check for duplicated breakpoints. Check also for a breakpoint
4024 placed (branch instruction's destination) in the atomic sequence. */
4025 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4026 last_breakpoint
= 0;
4028 std::vector
<CORE_ADDR
> next_pcs
;
4030 /* Effectively inserts the breakpoints. */
4031 for (index
= 0; index
<= last_breakpoint
; index
++)
4032 next_pcs
.push_back (breaks
[index
]);
4037 static std::vector
<CORE_ADDR
>
4038 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4041 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4042 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4043 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4044 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4052 /* Assume all atomic sequences start with a ll/lld instruction. */
4053 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4054 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4056 loc
+= MIPS_INSN16_SIZE
;
4058 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4059 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4061 loc
+= MIPS_INSN16_SIZE
;
4063 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4064 that no atomic sequence is longer than "atomic_sequence_length"
4066 for (insn_count
= 0;
4067 !sc_found
&& insn_count
< atomic_sequence_length
;
4072 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4073 loc
+= MIPS_INSN16_SIZE
;
4075 /* Assume that there is at most one conditional branch in the
4076 atomic sequence. If a branch is found, put a breakpoint in
4077 its destination address. */
4078 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4080 /* 32-bit instructions. */
4081 case 2 * MIPS_INSN16_SIZE
:
4082 switch (micromips_op (insn
))
4084 case 0x10: /* POOL32I: bits 010000 */
4085 if ((b5s5_op (insn
) & 0x18) != 0x0
4086 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4087 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4088 && (b5s5_op (insn
) & 0x1d) != 0x11
4089 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4090 && ((b5s5_op (insn
) & 0x1e) != 0x14
4091 || (insn
& 0x3) != 0x0)
4092 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4093 && (b5s5_op (insn
) & 0x1e) != 0x1a
4094 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4095 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4096 || (insn
& 0x3) != 0x0)
4097 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4098 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4099 || (insn
& 0x3) != 0x1))
4100 /* BC1ANY*: bits 010000 111xx xxx01 */
4104 case 0x25: /* BEQ: bits 100101 */
4105 case 0x2d: /* BNE: bits 101101 */
4107 insn
|= mips_fetch_instruction (gdbarch
,
4108 ISA_MICROMIPS
, loc
, NULL
);
4109 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4110 + micromips_relative_offset16 (insn
));
4114 case 0x00: /* POOL32A: bits 000000 */
4116 insn
|= mips_fetch_instruction (gdbarch
,
4117 ISA_MICROMIPS
, loc
, NULL
);
4118 if (b0s6_op (insn
) != 0x3c
4119 /* POOL32Axf: bits 000000 ... 111100 */
4120 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4121 /* JALR, JALR.HB: 000000 000x111100 111100 */
4122 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4126 case 0x1d: /* JALS: bits 011101 */
4127 case 0x35: /* J: bits 110101 */
4128 case 0x3d: /* JAL: bits 111101 */
4129 case 0x3c: /* JALX: bits 111100 */
4130 return {}; /* Fall back to the standard single-step code. */
4132 case 0x18: /* POOL32C: bits 011000 */
4133 if ((b12s4_op (insn
) & 0xb) == 0xb)
4134 /* SC, SCD: bits 011000 1x11 */
4138 loc
+= MIPS_INSN16_SIZE
;
4141 /* 16-bit instructions. */
4142 case MIPS_INSN16_SIZE
:
4143 switch (micromips_op (insn
))
4145 case 0x23: /* BEQZ16: bits 100011 */
4146 case 0x2b: /* BNEZ16: bits 101011 */
4147 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4151 case 0x11: /* POOL16C: bits 010001 */
4152 if ((b5s5_op (insn
) & 0x1c) != 0xc
4153 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4154 && b5s5_op (insn
) != 0x18)
4155 /* JRADDIUSP: bits 010001 11000 */
4157 return {}; /* Fall back to the standard single-step code. */
4159 case 0x33: /* B16: bits 110011 */
4160 return {}; /* Fall back to the standard single-step code. */
4166 if (last_breakpoint
>= 1)
4167 return {}; /* More than one branch found, fallback to the
4168 standard single-step code. */
4169 breaks
[1] = branch_bp
;
4176 /* Insert a breakpoint right after the end of the atomic sequence. */
4179 /* Check for duplicated breakpoints. Check also for a breakpoint
4180 placed (branch instruction's destination) in the atomic sequence */
4181 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4182 last_breakpoint
= 0;
4184 std::vector
<CORE_ADDR
> next_pcs
;
4186 /* Effectively inserts the breakpoints. */
4187 for (index
= 0; index
<= last_breakpoint
; index
++)
4188 next_pcs
.push_back (breaks
[index
]);
4193 static std::vector
<CORE_ADDR
>
4194 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4196 if (mips_pc_is_mips (pc
))
4197 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4198 else if (mips_pc_is_micromips (gdbarch
, pc
))
4199 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4204 /* mips_software_single_step() is called just before we want to resume
4205 the inferior, if we want to single-step it but there is no hardware
4206 or kernel single-step support (MIPS on GNU/Linux for example). We find
4207 the target of the coming instruction and breakpoint it. */
4209 std::vector
<CORE_ADDR
>
4210 mips_software_single_step (struct regcache
*regcache
)
4212 struct gdbarch
*gdbarch
= regcache
->arch ();
4213 CORE_ADDR pc
, next_pc
;
4215 pc
= regcache_read_pc (regcache
);
4216 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4218 if (!next_pcs
.empty ())
4221 next_pc
= mips_next_pc (regcache
, pc
);
4226 /* Test whether the PC points to the return instruction at the
4227 end of a function. */
4230 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4235 /* This used to check for MIPS16, but this piece of code is never
4236 called for MIPS16 functions. And likewise microMIPS ones. */
4237 gdb_assert (mips_pc_is_mips (pc
));
4239 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4241 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4245 /* This fencepost looks highly suspicious to me. Removing it also
4246 seems suspicious as it could affect remote debugging across serial
4250 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4256 struct inferior
*inf
;
4258 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4260 fence
= start_pc
- heuristic_fence_post
;
4264 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4265 fence
= VM_MIN_ADDRESS
;
4267 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4269 inf
= current_inferior ();
4271 /* Search back for previous return. */
4272 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4273 if (start_pc
< fence
)
4275 /* It's not clear to me why we reach this point when
4276 stop_soon, but with this test, at least we
4277 don't print out warnings for every child forked (eg, on
4278 decstation). 22apr93 rich@cygnus.com. */
4279 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4281 static int blurb_printed
= 0;
4283 warning (_("GDB can't find the start of the function at %s."),
4284 paddress (gdbarch
, pc
));
4288 /* This actually happens frequently in embedded
4289 development, when you first connect to a board
4290 and your stack pointer and pc are nowhere in
4291 particular. This message needs to give people
4292 in that situation enough information to
4293 determine that it's no big deal. */
4295 GDB is unable to find the start of the function at %s\n\
4296 and thus can't determine the size of that function's stack frame.\n\
4297 This means that GDB may be unable to access that stack frame, or\n\
4298 the frames below it.\n\
4299 This problem is most likely caused by an invalid program counter or\n\
4301 However, if you think GDB should simply search farther back\n\
4302 from %s for code which looks like the beginning of a\n\
4303 function, you can increase the range of the search using the `set\n\
4304 heuristic-fence-post' command.\n",
4305 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4312 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4314 unsigned short inst
;
4316 /* On MIPS16, any one of the following is likely to be the
4317 start of a function:
4323 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4324 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4325 if ((inst
& 0xff80) == 0x6480) /* save */
4327 if (start_pc
- instlen
>= fence
)
4329 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4330 start_pc
- instlen
, NULL
);
4331 if ((inst
& 0xf800) == 0xf000) /* extend */
4332 start_pc
-= instlen
;
4336 else if (((inst
& 0xf81f) == 0xe809
4337 && (inst
& 0x700) != 0x700) /* entry */
4338 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4339 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4340 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4342 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4343 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4348 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4356 /* On microMIPS, any one of the following is likely to be the
4357 start of a function:
4361 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4362 switch (micromips_op (insn
))
4364 case 0xc: /* ADDIU: bits 001100 */
4365 case 0x17: /* DADDIU: bits 010111 */
4366 sreg
= b0s5_reg (insn
);
4367 dreg
= b5s5_reg (insn
);
4369 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4370 pc
+ MIPS_INSN16_SIZE
, NULL
);
4371 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4372 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4373 /* (D)ADDIU $sp, imm */
4378 case 0x10: /* POOL32I: bits 010000 */
4379 if (b5s5_op (insn
) == 0xd
4380 /* LUI: bits 010000 001101 */
4381 && b0s5_reg (insn
>> 16) == 28)
4386 case 0x13: /* POOL16D: bits 010011 */
4387 if ((insn
& 0x1) == 0x1)
4388 /* ADDIUSP: bits 010011 1 */
4390 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4396 /* ADDIUS5: bits 010011 0 */
4398 dreg
= b5s5_reg (insn
);
4399 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4400 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4401 /* ADDIUS5 $sp, -imm */
4409 else if (mips_about_to_return (gdbarch
, start_pc
))
4411 /* Skip return and its delay slot. */
4412 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4419 struct mips_objfile_private
4425 /* According to the current ABI, should the type be passed in a
4426 floating-point register (assuming that there is space)? When there
4427 is no FPU, FP are not even considered as possible candidates for
4428 FP registers and, consequently this returns false - forces FP
4429 arguments into integer registers. */
4432 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4433 struct type
*arg_type
)
4435 return ((typecode
== TYPE_CODE_FLT
4436 || (mips_eabi (gdbarch
)
4437 && (typecode
== TYPE_CODE_STRUCT
4438 || typecode
== TYPE_CODE_UNION
)
4439 && arg_type
->num_fields () == 1
4440 && check_typedef (arg_type
->field (0).type ())->code ()
4442 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4445 /* On o32, argument passing in GPRs depends on the alignment of the type being
4446 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4449 mips_type_needs_double_align (struct type
*type
)
4451 enum type_code typecode
= type
->code ();
4453 if (typecode
== TYPE_CODE_FLT
&& type
->length () == 8)
4455 else if (typecode
== TYPE_CODE_STRUCT
)
4457 if (type
->num_fields () < 1)
4459 return mips_type_needs_double_align (type
->field (0).type ());
4461 else if (typecode
== TYPE_CODE_UNION
)
4465 n
= type
->num_fields ();
4466 for (i
= 0; i
< n
; i
++)
4467 if (mips_type_needs_double_align (type
->field (i
).type ()))
4474 /* Adjust the address downward (direction of stack growth) so that it
4475 is correctly aligned for a new stack frame. */
4477 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4479 return align_down (addr
, 16);
4482 /* Implement the "push_dummy_code" gdbarch method. */
4485 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4486 CORE_ADDR funaddr
, struct value
**args
,
4487 int nargs
, struct type
*value_type
,
4488 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4489 struct regcache
*regcache
)
4491 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4495 /* Reserve enough room on the stack for our breakpoint instruction. */
4496 bp_slot
= sp
- sizeof (nop_insn
);
4498 /* Return to microMIPS mode if calling microMIPS code to avoid
4499 triggering an address error exception on processors that only
4500 support microMIPS execution. */
4501 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4502 ? make_compact_addr (bp_slot
) : bp_slot
);
4504 /* The breakpoint layer automatically adjusts the address of
4505 breakpoints inserted in a branch delay slot. With enough
4506 bad luck, the 4 bytes located just before our breakpoint
4507 instruction could look like a branch instruction, and thus
4508 trigger the adjustement, and break the function call entirely.
4509 So, we reserve those 4 bytes and write a nop instruction
4510 to prevent that from happening. */
4511 nop_addr
= bp_slot
- sizeof (nop_insn
);
4512 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4513 sp
= mips_frame_align (gdbarch
, nop_addr
);
4515 /* Inferior resumes at the function entry point. */
4522 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4523 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4524 int nargs
, struct value
**args
, CORE_ADDR sp
,
4525 function_call_return_method return_method
,
4526 CORE_ADDR struct_addr
)
4532 int stack_offset
= 0;
4533 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4534 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4535 int abi_regsize
= mips_abi_regsize (gdbarch
);
4537 /* For shared libraries, "t9" needs to point at the function
4539 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4541 /* Set the return address register to point to the entry point of
4542 the program, where a breakpoint lies in wait. */
4543 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4545 /* First ensure that the stack and structure return address (if any)
4546 are properly aligned. The stack has to be at least 64-bit
4547 aligned even on 32-bit machines, because doubles must be 64-bit
4548 aligned. For n32 and n64, stack frames need to be 128-bit
4549 aligned, so we round to this widest known alignment. */
4551 sp
= align_down (sp
, 16);
4552 struct_addr
= align_down (struct_addr
, 16);
4554 /* Now make space on the stack for the args. We allocate more
4555 than necessary for EABI, because the first few arguments are
4556 passed in registers, but that's OK. */
4557 for (argnum
= 0; argnum
< nargs
; argnum
++)
4558 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4560 sp
-= align_up (arg_space
, 16);
4563 gdb_printf (gdb_stdlog
,
4564 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4565 paddress (gdbarch
, sp
),
4566 (long) align_up (arg_space
, 16));
4568 /* Initialize the integer and float register pointers. */
4569 argreg
= MIPS_A0_REGNUM
;
4570 float_argreg
= mips_fpa0_regnum (gdbarch
);
4572 /* The struct_return pointer occupies the first parameter-passing reg. */
4573 if (return_method
== return_method_struct
)
4576 gdb_printf (gdb_stdlog
,
4577 "mips_eabi_push_dummy_call: "
4578 "struct_return reg=%d %s\n",
4579 argreg
, paddress (gdbarch
, struct_addr
));
4580 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4583 /* Now load as many as possible of the first arguments into
4584 registers, and push the rest onto the stack. Loop thru args
4585 from first to last. */
4586 for (argnum
= 0; argnum
< nargs
; argnum
++)
4588 const gdb_byte
*val
;
4589 /* This holds the address of structures that are passed by
4591 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4592 struct value
*arg
= args
[argnum
];
4593 struct type
*arg_type
= check_typedef (arg
->type ());
4594 int len
= arg_type
->length ();
4595 enum type_code typecode
= arg_type
->code ();
4598 gdb_printf (gdb_stdlog
,
4599 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4600 argnum
+ 1, len
, (int) typecode
);
4602 /* The EABI passes structures that do not fit in a register by
4604 if (len
> abi_regsize
4605 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4607 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4608 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4610 typecode
= TYPE_CODE_PTR
;
4614 gdb_printf (gdb_stdlog
, " push");
4617 val
= arg
->contents ().data ();
4619 /* 32-bit ABIs always start floating point arguments in an
4620 even-numbered floating point register. Round the FP register
4621 up before the check to see if there are any FP registers
4622 left. Non MIPS_EABI targets also pass the FP in the integer
4623 registers so also round up normal registers. */
4624 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4626 if ((float_argreg
& 1))
4630 /* Floating point arguments passed in registers have to be
4631 treated specially. On 32-bit architectures, doubles
4632 are passed in register pairs; the even register gets
4633 the low word, and the odd register gets the high word.
4634 On non-EABI processors, the first two floating point arguments are
4635 also copied to general registers, because MIPS16 functions
4636 don't use float registers for arguments. This duplication of
4637 arguments in general registers can't hurt non-MIPS16 functions
4638 because those registers are normally skipped. */
4639 /* MIPS_EABI squeezes a struct that contains a single floating
4640 point value into an FP register instead of pushing it onto the
4642 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4643 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4645 /* EABI32 will pass doubles in consecutive registers, even on
4646 64-bit cores. At one time, we used to check the size of
4647 `float_argreg' to determine whether or not to pass doubles
4648 in consecutive registers, but this is not sufficient for
4649 making the ABI determination. */
4650 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4652 int low_offset
= gdbarch_byte_order (gdbarch
)
4653 == BFD_ENDIAN_BIG
? 4 : 0;
4656 /* Write the low word of the double to the even register(s). */
4657 regval
= extract_signed_integer (val
+ low_offset
,
4660 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4661 float_argreg
, phex (regval
, 4));
4662 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4664 /* Write the high word of the double to the odd register(s). */
4665 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4668 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4669 float_argreg
, phex (regval
, 4));
4670 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4674 /* This is a floating point value that fits entirely
4675 in a single register. */
4676 /* On 32 bit ABI's the float_argreg is further adjusted
4677 above to ensure that it is even register aligned. */
4678 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4680 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
4681 float_argreg
, phex (regval
, len
));
4682 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4687 /* Copy the argument to general registers or the stack in
4688 register-sized pieces. Large arguments are split between
4689 registers and stack. */
4690 /* Note: structs whose size is not a multiple of abi_regsize
4691 are treated specially: Irix cc passes
4692 them in registers where gcc sometimes puts them on the
4693 stack. For maximum compatibility, we will put them in
4695 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4697 /* Note: Floating-point values that didn't fit into an FP
4698 register are only written to memory. */
4701 /* Remember if the argument was written to the stack. */
4702 int stack_used_p
= 0;
4703 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4706 gdb_printf (gdb_stdlog
, " -- partial=%d",
4709 /* Write this portion of the argument to the stack. */
4710 if (argreg
> mips_last_arg_regnum (gdbarch
)
4712 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4714 /* Should shorter than int integer values be
4715 promoted to int before being stored? */
4716 int longword_offset
= 0;
4719 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4721 if (abi_regsize
== 8
4722 && (typecode
== TYPE_CODE_INT
4723 || typecode
== TYPE_CODE_PTR
4724 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4725 longword_offset
= abi_regsize
- len
;
4726 else if ((typecode
== TYPE_CODE_STRUCT
4727 || typecode
== TYPE_CODE_UNION
)
4728 && arg_type
->length () < abi_regsize
)
4729 longword_offset
= abi_regsize
- len
;
4734 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
4735 paddress (gdbarch
, stack_offset
));
4736 gdb_printf (gdb_stdlog
, " longword_offset=%s",
4737 paddress (gdbarch
, longword_offset
));
4740 addr
= sp
+ stack_offset
+ longword_offset
;
4745 gdb_printf (gdb_stdlog
, " @%s ",
4746 paddress (gdbarch
, addr
));
4747 for (i
= 0; i
< partial_len
; i
++)
4749 gdb_printf (gdb_stdlog
, "%02x",
4753 write_memory (addr
, val
, partial_len
);
4756 /* Note!!! This is NOT an else clause. Odd sized
4757 structs may go thru BOTH paths. Floating point
4758 arguments will not. */
4759 /* Write this portion of the argument to a general
4760 purpose register. */
4761 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4762 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4765 extract_signed_integer (val
, partial_len
, byte_order
);
4768 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
4770 phex (regval
, abi_regsize
));
4771 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4778 /* Compute the offset into the stack at which we will
4779 copy the next parameter.
4781 In the new EABI (and the NABI32), the stack_offset
4782 only needs to be adjusted when it has been used. */
4785 stack_offset
+= align_up (partial_len
, abi_regsize
);
4789 gdb_printf (gdb_stdlog
, "\n");
4792 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4794 /* Return adjusted stack pointer. */
4798 /* Determine the return value convention being used. */
4800 static enum return_value_convention
4801 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4802 struct type
*type
, struct regcache
*regcache
,
4803 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4805 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
4806 int fp_return_type
= 0;
4807 int offset
, regnum
, xfer
;
4809 if (type
->length () > 2 * mips_abi_regsize (gdbarch
))
4810 return RETURN_VALUE_STRUCT_CONVENTION
;
4812 /* Floating point type? */
4813 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4815 if (type
->code () == TYPE_CODE_FLT
)
4817 /* Structs with a single field of float type
4818 are returned in a floating point register. */
4819 if ((type
->code () == TYPE_CODE_STRUCT
4820 || type
->code () == TYPE_CODE_UNION
)
4821 && type
->num_fields () == 1)
4823 struct type
*fieldtype
= type
->field (0).type ();
4825 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4832 /* A floating-point value belongs in the least significant part
4835 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
4836 regnum
= mips_regnum (gdbarch
)->fp0
;
4840 /* An integer value goes in V0/V1. */
4842 gdb_printf (gdb_stderr
, "Return scalar in $v0\n");
4843 regnum
= MIPS_V0_REGNUM
;
4846 offset
< type
->length ();
4847 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4849 xfer
= mips_abi_regsize (gdbarch
);
4850 if (offset
+ xfer
> type
->length ())
4851 xfer
= type
->length () - offset
;
4852 mips_xfer_register (gdbarch
, regcache
,
4853 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4854 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4858 return RETURN_VALUE_REGISTER_CONVENTION
;
4862 /* N32/N64 ABI stuff. */
4864 /* Search for a naturally aligned double at OFFSET inside a struct
4865 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4869 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4874 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4877 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4880 if (arg_type
->length () < offset
+ MIPS64_REGSIZE
)
4883 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4886 struct type
*field_type
;
4888 /* We're only looking at normal fields. */
4889 if (arg_type
->field (i
).is_static ()
4890 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4893 /* If we have gone past the offset, there is no double to pass. */
4894 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4898 field_type
= check_typedef (arg_type
->field (i
).type ());
4900 /* If this field is entirely before the requested offset, go
4901 on to the next one. */
4902 if (pos
+ field_type
->length () <= offset
)
4905 /* If this is our special aligned double, we can stop. */
4906 if (field_type
->code () == TYPE_CODE_FLT
4907 && field_type
->length () == MIPS64_REGSIZE
)
4910 /* This field starts at or before the requested offset, and
4911 overlaps it. If it is a structure, recurse inwards. */
4912 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4919 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4920 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4921 int nargs
, struct value
**args
, CORE_ADDR sp
,
4922 function_call_return_method return_method
,
4923 CORE_ADDR struct_addr
)
4929 int stack_offset
= 0;
4930 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4931 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4933 /* For shared libraries, "t9" needs to point at the function
4935 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4937 /* Set the return address register to point to the entry point of
4938 the program, where a breakpoint lies in wait. */
4939 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4941 /* First ensure that the stack and structure return address (if any)
4942 are properly aligned. The stack has to be at least 64-bit
4943 aligned even on 32-bit machines, because doubles must be 64-bit
4944 aligned. For n32 and n64, stack frames need to be 128-bit
4945 aligned, so we round to this widest known alignment. */
4947 sp
= align_down (sp
, 16);
4948 struct_addr
= align_down (struct_addr
, 16);
4950 /* Now make space on the stack for the args. */
4951 for (argnum
= 0; argnum
< nargs
; argnum
++)
4952 arg_space
+= align_up (args
[argnum
]->type ()->length (),
4954 sp
-= align_up (arg_space
, 16);
4957 gdb_printf (gdb_stdlog
,
4958 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4959 paddress (gdbarch
, sp
),
4960 (long) align_up (arg_space
, 16));
4962 /* Initialize the integer and float register pointers. */
4963 argreg
= MIPS_A0_REGNUM
;
4964 float_argreg
= mips_fpa0_regnum (gdbarch
);
4966 /* The struct_return pointer occupies the first parameter-passing reg. */
4967 if (return_method
== return_method_struct
)
4970 gdb_printf (gdb_stdlog
,
4971 "mips_n32n64_push_dummy_call: "
4972 "struct_return reg=%d %s\n",
4973 argreg
, paddress (gdbarch
, struct_addr
));
4974 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4977 /* Now load as many as possible of the first arguments into
4978 registers, and push the rest onto the stack. Loop thru args
4979 from first to last. */
4980 for (argnum
= 0; argnum
< nargs
; argnum
++)
4982 const gdb_byte
*val
;
4983 struct value
*arg
= args
[argnum
];
4984 struct type
*arg_type
= check_typedef (arg
->type ());
4985 int len
= arg_type
->length ();
4986 enum type_code typecode
= arg_type
->code ();
4989 gdb_printf (gdb_stdlog
,
4990 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4991 argnum
+ 1, len
, (int) typecode
);
4993 val
= arg
->contents ().data ();
4995 /* A 128-bit long double value requires an even-odd pair of
4996 floating-point registers. */
4998 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4999 && (float_argreg
& 1))
5005 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5006 && argreg
<= mips_last_arg_regnum (gdbarch
))
5008 /* This is a floating point value that fits entirely
5009 in a single register or a pair of registers. */
5010 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5011 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5013 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5014 float_argreg
, phex (regval
, reglen
));
5015 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5018 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5019 argreg
, phex (regval
, reglen
));
5020 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5025 regval
= extract_unsigned_integer (val
+ reglen
,
5026 reglen
, byte_order
);
5028 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5029 float_argreg
, phex (regval
, reglen
));
5030 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5033 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5034 argreg
, phex (regval
, reglen
));
5035 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5042 /* Copy the argument to general registers or the stack in
5043 register-sized pieces. Large arguments are split between
5044 registers and stack. */
5045 /* For N32/N64, structs, unions, or other composite types are
5046 treated as a sequence of doublewords, and are passed in integer
5047 or floating point registers as though they were simple scalar
5048 parameters to the extent that they fit, with any excess on the
5049 stack packed according to the normal memory layout of the
5051 The caller does not reserve space for the register arguments;
5052 the callee is responsible for reserving it if required. */
5053 /* Note: Floating-point values that didn't fit into an FP
5054 register are only written to memory. */
5057 /* Remember if the argument was written to the stack. */
5058 int stack_used_p
= 0;
5059 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5062 gdb_printf (gdb_stdlog
, " -- partial=%d",
5065 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5066 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5068 /* Write this portion of the argument to the stack. */
5069 if (argreg
> mips_last_arg_regnum (gdbarch
))
5071 /* Should shorter than int integer values be
5072 promoted to int before being stored? */
5073 int longword_offset
= 0;
5076 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5078 if ((typecode
== TYPE_CODE_INT
5079 || typecode
== TYPE_CODE_PTR
)
5081 longword_offset
= MIPS64_REGSIZE
- len
;
5086 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5087 paddress (gdbarch
, stack_offset
));
5088 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5089 paddress (gdbarch
, longword_offset
));
5092 addr
= sp
+ stack_offset
+ longword_offset
;
5097 gdb_printf (gdb_stdlog
, " @%s ",
5098 paddress (gdbarch
, addr
));
5099 for (i
= 0; i
< partial_len
; i
++)
5101 gdb_printf (gdb_stdlog
, "%02x",
5105 write_memory (addr
, val
, partial_len
);
5108 /* Note!!! This is NOT an else clause. Odd sized
5109 structs may go thru BOTH paths. */
5110 /* Write this portion of the argument to a general
5111 purpose register. */
5112 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5116 /* Sign extend pointers, 32-bit integers and signed
5117 16-bit and 8-bit integers; everything else is taken
5120 if ((partial_len
== 4
5121 && (typecode
== TYPE_CODE_PTR
5122 || typecode
== TYPE_CODE_INT
))
5124 && typecode
== TYPE_CODE_INT
5125 && !arg_type
->is_unsigned ()))
5126 regval
= extract_signed_integer (val
, partial_len
,
5129 regval
= extract_unsigned_integer (val
, partial_len
,
5132 /* A non-floating-point argument being passed in a
5133 general register. If a struct or union, and if
5134 the remaining length is smaller than the register
5135 size, we have to adjust the register value on
5138 It does not seem to be necessary to do the
5139 same for integral types. */
5141 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5142 && partial_len
< MIPS64_REGSIZE
5143 && (typecode
== TYPE_CODE_STRUCT
5144 || typecode
== TYPE_CODE_UNION
))
5145 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5149 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5151 phex (regval
, MIPS64_REGSIZE
));
5152 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5154 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5155 arg_type
->length () - len
))
5158 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5160 phex (regval
, MIPS64_REGSIZE
));
5161 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5172 /* Compute the offset into the stack at which we will
5173 copy the next parameter.
5175 In N32 (N64?), the stack_offset only needs to be
5176 adjusted when it has been used. */
5179 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5183 gdb_printf (gdb_stdlog
, "\n");
5186 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5188 /* Return adjusted stack pointer. */
5192 static enum return_value_convention
5193 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5194 struct type
*type
, struct regcache
*regcache
,
5195 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5197 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5199 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5201 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5202 if needed), as appropriate for the type. Composite results (struct,
5203 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5206 * A struct with only one or two floating point fields is returned in $f0
5207 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5210 * Any other composite results of at most 128 bits are returned in
5211 $2 (first 64 bits) and $3 (remainder, if necessary).
5213 * Larger composite results are handled by converting the function to a
5214 procedure with an implicit first parameter, which is a pointer to an area
5215 reserved by the caller to receive the result. [The o32-bit ABI requires
5216 that all composite results be handled by conversion to implicit first
5217 parameters. The MIPS/SGI Fortran implementation has always made a
5218 specific exception to return COMPLEX results in the floating point
5221 From MIPSpro Assembly Language Programmer's Guide, Document Number:
5226 Name fgregdef.h) Use and Linkage
5227 -----------------------------------------------------------------
5228 $f0, $f2 fv0, fv1 Hold results of floating-point type function
5229 ($f0) and complex type function ($f0 has the
5230 real part, $f2 has the imaginary part.) */
5232 if (type
->length () > 2 * MIPS64_REGSIZE
)
5233 return RETURN_VALUE_STRUCT_CONVENTION
;
5234 else if ((type
->code () == TYPE_CODE_COMPLEX
5235 || (type
->code () == TYPE_CODE_FLT
&& type
->length () == 16))
5236 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5238 /* A complex value of up to 128 bits in width as well as a 128-bit
5239 floating-point value goes in both $f0 and $f2. A single complex
5240 value is held in the lower halves only of the respective registers.
5241 The two registers are used in the same as memory order, so the
5242 bytes with the lower memory address are in $f0. */
5244 gdb_printf (gdb_stderr
, "Return float in $f0 and $f2\n");
5245 mips_xfer_register (gdbarch
, regcache
,
5246 (gdbarch_num_regs (gdbarch
)
5247 + mips_regnum (gdbarch
)->fp0
),
5248 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5249 readbuf
, writebuf
, 0);
5250 mips_xfer_register (gdbarch
, regcache
,
5251 (gdbarch_num_regs (gdbarch
)
5252 + mips_regnum (gdbarch
)->fp0
+ 2),
5253 type
->length () / 2, gdbarch_byte_order (gdbarch
),
5254 readbuf
? readbuf
+ type
->length () / 2 : readbuf
,
5256 ? writebuf
+ type
->length () / 2 : writebuf
), 0);
5257 return RETURN_VALUE_REGISTER_CONVENTION
;
5259 else if (type
->code () == TYPE_CODE_FLT
5260 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5262 /* A single or double floating-point value that fits in FP0. */
5264 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5265 mips_xfer_register (gdbarch
, regcache
,
5266 (gdbarch_num_regs (gdbarch
)
5267 + mips_regnum (gdbarch
)->fp0
),
5269 gdbarch_byte_order (gdbarch
),
5270 readbuf
, writebuf
, 0);
5271 return RETURN_VALUE_REGISTER_CONVENTION
;
5273 else if (type
->code () == TYPE_CODE_STRUCT
5274 && type
->num_fields () <= 2
5275 && type
->num_fields () >= 1
5276 && ((type
->num_fields () == 1
5277 && (check_typedef (type
->field (0).type ())->code ()
5279 || (type
->num_fields () == 2
5280 && (check_typedef (type
->field (0).type ())->code ()
5282 && (check_typedef (type
->field (1).type ())->code ()
5283 == TYPE_CODE_FLT
))))
5285 /* A struct that contains one or two floats. Each value is part
5286 in the least significant part of their floating point
5287 register (or GPR, for soft float). */
5290 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5291 ? mips_regnum (gdbarch
)->fp0
5293 field
< type
->num_fields (); field
++, regnum
+= 2)
5295 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5297 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5299 if (type
->field (field
).type ()->length () == 16)
5301 /* A 16-byte long double field goes in two consecutive
5303 mips_xfer_register (gdbarch
, regcache
,
5304 gdbarch_num_regs (gdbarch
) + regnum
,
5306 gdbarch_byte_order (gdbarch
),
5307 readbuf
, writebuf
, offset
);
5308 mips_xfer_register (gdbarch
, regcache
,
5309 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5311 gdbarch_byte_order (gdbarch
),
5312 readbuf
, writebuf
, offset
+ 8);
5315 mips_xfer_register (gdbarch
, regcache
,
5316 gdbarch_num_regs (gdbarch
) + regnum
,
5317 type
->field (field
).type ()->length (),
5318 gdbarch_byte_order (gdbarch
),
5319 readbuf
, writebuf
, offset
);
5321 return RETURN_VALUE_REGISTER_CONVENTION
;
5323 else if (type
->code () == TYPE_CODE_STRUCT
5324 || type
->code () == TYPE_CODE_UNION
5325 || type
->code () == TYPE_CODE_ARRAY
)
5327 /* A composite type. Extract the left justified value,
5328 regardless of the byte order. I.e. DO NOT USE
5332 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5333 offset
< type
->length ();
5334 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5336 int xfer
= register_size (gdbarch
, regnum
);
5337 if (offset
+ xfer
> type
->length ())
5338 xfer
= type
->length () - offset
;
5340 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5341 offset
, xfer
, regnum
);
5342 mips_xfer_register (gdbarch
, regcache
,
5343 gdbarch_num_regs (gdbarch
) + regnum
,
5344 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5347 return RETURN_VALUE_REGISTER_CONVENTION
;
5351 /* A scalar extract each part but least-significant-byte
5355 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5356 offset
< type
->length ();
5357 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5359 int xfer
= register_size (gdbarch
, regnum
);
5360 if (offset
+ xfer
> type
->length ())
5361 xfer
= type
->length () - offset
;
5363 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5364 offset
, xfer
, regnum
);
5365 mips_xfer_register (gdbarch
, regcache
,
5366 gdbarch_num_regs (gdbarch
) + regnum
,
5367 xfer
, gdbarch_byte_order (gdbarch
),
5368 readbuf
, writebuf
, offset
);
5370 return RETURN_VALUE_REGISTER_CONVENTION
;
5374 /* Which registers to use for passing floating-point values between
5375 function calls, one of floating-point, general and both kinds of
5376 registers. O32 and O64 use different register kinds for standard
5377 MIPS and MIPS16 code; to make the handling of cases where we may
5378 not know what kind of code is being used (e.g. no debug information)
5379 easier we sometimes use both kinds. */
5388 /* O32 ABI stuff. */
5391 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5392 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5393 int nargs
, struct value
**args
, CORE_ADDR sp
,
5394 function_call_return_method return_method
,
5395 CORE_ADDR struct_addr
)
5401 int stack_offset
= 0;
5402 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5403 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5405 /* For shared libraries, "t9" needs to point at the function
5407 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5409 /* Set the return address register to point to the entry point of
5410 the program, where a breakpoint lies in wait. */
5411 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5413 /* First ensure that the stack and structure return address (if any)
5414 are properly aligned. The stack has to be at least 64-bit
5415 aligned even on 32-bit machines, because doubles must be 64-bit
5416 aligned. For n32 and n64, stack frames need to be 128-bit
5417 aligned, so we round to this widest known alignment. */
5419 sp
= align_down (sp
, 16);
5420 struct_addr
= align_down (struct_addr
, 16);
5422 /* Now make space on the stack for the args. */
5423 for (argnum
= 0; argnum
< nargs
; argnum
++)
5425 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5427 /* Align to double-word if necessary. */
5428 if (mips_type_needs_double_align (arg_type
))
5429 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5430 /* Allocate space on the stack. */
5431 arg_space
+= align_up (arg_type
->length (), MIPS32_REGSIZE
);
5433 sp
-= align_up (arg_space
, 16);
5436 gdb_printf (gdb_stdlog
,
5437 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5438 paddress (gdbarch
, sp
),
5439 (long) align_up (arg_space
, 16));
5441 /* Initialize the integer and float register pointers. */
5442 argreg
= MIPS_A0_REGNUM
;
5443 float_argreg
= mips_fpa0_regnum (gdbarch
);
5445 /* The struct_return pointer occupies the first parameter-passing reg. */
5446 if (return_method
== return_method_struct
)
5449 gdb_printf (gdb_stdlog
,
5450 "mips_o32_push_dummy_call: "
5451 "struct_return reg=%d %s\n",
5452 argreg
, paddress (gdbarch
, struct_addr
));
5453 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5454 stack_offset
+= MIPS32_REGSIZE
;
5457 /* Now load as many as possible of the first arguments into
5458 registers, and push the rest onto the stack. Loop thru args
5459 from first to last. */
5460 for (argnum
= 0; argnum
< nargs
; argnum
++)
5462 const gdb_byte
*val
;
5463 struct value
*arg
= args
[argnum
];
5464 struct type
*arg_type
= check_typedef (arg
->type ());
5465 int len
= arg_type
->length ();
5466 enum type_code typecode
= arg_type
->code ();
5469 gdb_printf (gdb_stdlog
,
5470 "mips_o32_push_dummy_call: %d len=%d type=%d",
5471 argnum
+ 1, len
, (int) typecode
);
5473 val
= arg
->contents ().data ();
5475 /* 32-bit ABIs always start floating point arguments in an
5476 even-numbered floating point register. Round the FP register
5477 up before the check to see if there are any FP registers
5478 left. O32 targets also pass the FP in the integer registers
5479 so also round up normal registers. */
5480 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5482 if ((float_argreg
& 1))
5486 /* Floating point arguments passed in registers have to be
5487 treated specially. On 32-bit architectures, doubles are
5488 passed in register pairs; the even FP register gets the
5489 low word, and the odd FP register gets the high word.
5490 On O32, the first two floating point arguments are also
5491 copied to general registers, following their memory order,
5492 because MIPS16 functions don't use float registers for
5493 arguments. This duplication of arguments in general
5494 registers can't hurt non-MIPS16 functions, because those
5495 registers are normally skipped. */
5497 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5498 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5500 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5502 int freg_offset
= gdbarch_byte_order (gdbarch
)
5503 == BFD_ENDIAN_BIG
? 1 : 0;
5504 unsigned long regval
;
5507 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5509 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5510 float_argreg
+ freg_offset
,
5512 regcache_cooked_write_unsigned (regcache
,
5513 float_argreg
++ + freg_offset
,
5516 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5517 argreg
, phex (regval
, 4));
5518 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5521 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5523 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5524 float_argreg
- freg_offset
,
5526 regcache_cooked_write_unsigned (regcache
,
5527 float_argreg
++ - freg_offset
,
5530 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5531 argreg
, phex (regval
, 4));
5532 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5536 /* This is a floating point value that fits entirely
5537 in a single register. */
5538 /* On 32 bit ABI's the float_argreg is further adjusted
5539 above to ensure that it is even register aligned. */
5540 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5542 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
5543 float_argreg
, phex (regval
, len
));
5544 regcache_cooked_write_unsigned (regcache
,
5545 float_argreg
++, regval
);
5546 /* Although two FP registers are reserved for each
5547 argument, only one corresponding integer register is
5550 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5551 argreg
, phex (regval
, len
));
5552 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5554 /* Reserve space for the FP register. */
5555 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5559 /* Copy the argument to general registers or the stack in
5560 register-sized pieces. Large arguments are split between
5561 registers and stack. */
5562 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5563 are treated specially: Irix cc passes
5564 them in registers where gcc sometimes puts them on the
5565 stack. For maximum compatibility, we will put them in
5567 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5568 && len
% MIPS32_REGSIZE
!= 0);
5569 /* Structures should be aligned to eight bytes (even arg registers)
5570 on MIPS_ABI_O32, if their first member has double precision. */
5571 if (mips_type_needs_double_align (arg_type
))
5576 stack_offset
+= MIPS32_REGSIZE
;
5581 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5584 gdb_printf (gdb_stdlog
, " -- partial=%d",
5587 /* Write this portion of the argument to the stack. */
5588 if (argreg
> mips_last_arg_regnum (gdbarch
)
5589 || odd_sized_struct
)
5591 /* Should shorter than int integer values be
5592 promoted to int before being stored? */
5593 int longword_offset
= 0;
5598 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
5599 paddress (gdbarch
, stack_offset
));
5600 gdb_printf (gdb_stdlog
, " longword_offset=%s",
5601 paddress (gdbarch
, longword_offset
));
5604 addr
= sp
+ stack_offset
+ longword_offset
;
5609 gdb_printf (gdb_stdlog
, " @%s ",
5610 paddress (gdbarch
, addr
));
5611 for (i
= 0; i
< partial_len
; i
++)
5613 gdb_printf (gdb_stdlog
, "%02x",
5617 write_memory (addr
, val
, partial_len
);
5620 /* Note!!! This is NOT an else clause. Odd sized
5621 structs may go thru BOTH paths. */
5622 /* Write this portion of the argument to a general
5623 purpose register. */
5624 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5626 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5628 /* Value may need to be sign extended, because
5629 mips_isa_regsize() != mips_abi_regsize(). */
5631 /* A non-floating-point argument being passed in a
5632 general register. If a struct or union, and if
5633 the remaining length is smaller than the register
5634 size, we have to adjust the register value on
5637 It does not seem to be necessary to do the
5638 same for integral types.
5640 Also don't do this adjustment on O64 binaries.
5642 cagney/2001-07-23: gdb/179: Also, GCC, when
5643 outputting LE O32 with sizeof (struct) <
5644 mips_abi_regsize(), generates a left shift
5645 as part of storing the argument in a register
5646 (the left shift isn't generated when
5647 sizeof (struct) >= mips_abi_regsize()). Since
5648 it is quite possible that this is GCC
5649 contradicting the LE/O32 ABI, GDB has not been
5650 adjusted to accommodate this. Either someone
5651 needs to demonstrate that the LE/O32 ABI
5652 specifies such a left shift OR this new ABI gets
5653 identified as such and GDB gets tweaked
5656 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5657 && partial_len
< MIPS32_REGSIZE
5658 && (typecode
== TYPE_CODE_STRUCT
5659 || typecode
== TYPE_CODE_UNION
))
5660 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5664 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
5666 phex (regval
, MIPS32_REGSIZE
));
5667 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5670 /* Prevent subsequent floating point arguments from
5671 being passed in floating point registers. */
5672 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5678 /* Compute the offset into the stack at which we will
5679 copy the next parameter.
5681 In older ABIs, the caller reserved space for
5682 registers that contained arguments. This was loosely
5683 referred to as their "home". Consequently, space is
5684 always allocated. */
5686 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5690 gdb_printf (gdb_stdlog
, "\n");
5693 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5695 /* Return adjusted stack pointer. */
5699 static enum return_value_convention
5700 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5701 struct type
*type
, struct regcache
*regcache
,
5702 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5704 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5705 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5706 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
5707 enum mips_fval_reg fval_reg
;
5709 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5710 if (type
->code () == TYPE_CODE_STRUCT
5711 || type
->code () == TYPE_CODE_UNION
5712 || type
->code () == TYPE_CODE_ARRAY
)
5713 return RETURN_VALUE_STRUCT_CONVENTION
;
5714 else if (type
->code () == TYPE_CODE_FLT
5715 && type
->length () == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5717 /* A single-precision floating-point value. If reading in or copying,
5718 then we get it from/put it to FP0 for standard MIPS code or GPR2
5719 for MIPS16 code. If writing out only, then we put it to both FP0
5720 and GPR2. We do not support reading in with no function known, if
5721 this safety check ever triggers, then we'll have to try harder. */
5722 gdb_assert (function
|| !readbuf
);
5727 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
5730 gdb_printf (gdb_stderr
, "Return float in $2\n");
5732 case mips_fval_both
:
5733 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
5736 if (fval_reg
!= mips_fval_gpr
)
5737 mips_xfer_register (gdbarch
, regcache
,
5738 (gdbarch_num_regs (gdbarch
)
5739 + mips_regnum (gdbarch
)->fp0
),
5741 gdbarch_byte_order (gdbarch
),
5742 readbuf
, writebuf
, 0);
5743 if (fval_reg
!= mips_fval_fpr
)
5744 mips_xfer_register (gdbarch
, regcache
,
5745 gdbarch_num_regs (gdbarch
) + 2,
5747 gdbarch_byte_order (gdbarch
),
5748 readbuf
, writebuf
, 0);
5749 return RETURN_VALUE_REGISTER_CONVENTION
;
5751 else if (type
->code () == TYPE_CODE_FLT
5752 && type
->length () == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5754 /* A double-precision floating-point value. If reading in or copying,
5755 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5756 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5757 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5758 no function known, if this safety check ever triggers, then we'll
5759 have to try harder. */
5760 gdb_assert (function
|| !readbuf
);
5765 gdb_printf (gdb_stderr
, "Return float in $fp1/$fp0\n");
5768 gdb_printf (gdb_stderr
, "Return float in $2/$3\n");
5770 case mips_fval_both
:
5771 gdb_printf (gdb_stderr
,
5772 "Return float in $fp1/$fp0 and $2/$3\n");
5775 if (fval_reg
!= mips_fval_gpr
)
5777 /* The most significant part goes in FP1, and the least significant
5779 switch (gdbarch_byte_order (gdbarch
))
5781 case BFD_ENDIAN_LITTLE
:
5782 mips_xfer_register (gdbarch
, regcache
,
5783 (gdbarch_num_regs (gdbarch
)
5784 + mips_regnum (gdbarch
)->fp0
+ 0),
5785 4, gdbarch_byte_order (gdbarch
),
5786 readbuf
, writebuf
, 0);
5787 mips_xfer_register (gdbarch
, regcache
,
5788 (gdbarch_num_regs (gdbarch
)
5789 + mips_regnum (gdbarch
)->fp0
+ 1),
5790 4, gdbarch_byte_order (gdbarch
),
5791 readbuf
, writebuf
, 4);
5793 case BFD_ENDIAN_BIG
:
5794 mips_xfer_register (gdbarch
, regcache
,
5795 (gdbarch_num_regs (gdbarch
)
5796 + mips_regnum (gdbarch
)->fp0
+ 1),
5797 4, gdbarch_byte_order (gdbarch
),
5798 readbuf
, writebuf
, 0);
5799 mips_xfer_register (gdbarch
, regcache
,
5800 (gdbarch_num_regs (gdbarch
)
5801 + mips_regnum (gdbarch
)->fp0
+ 0),
5802 4, gdbarch_byte_order (gdbarch
),
5803 readbuf
, writebuf
, 4);
5806 internal_error (_("bad switch"));
5809 if (fval_reg
!= mips_fval_fpr
)
5811 /* The two 32-bit parts are always placed in GPR2 and GPR3
5812 following these registers' memory order. */
5813 mips_xfer_register (gdbarch
, regcache
,
5814 gdbarch_num_regs (gdbarch
) + 2,
5815 4, gdbarch_byte_order (gdbarch
),
5816 readbuf
, writebuf
, 0);
5817 mips_xfer_register (gdbarch
, regcache
,
5818 gdbarch_num_regs (gdbarch
) + 3,
5819 4, gdbarch_byte_order (gdbarch
),
5820 readbuf
, writebuf
, 4);
5822 return RETURN_VALUE_REGISTER_CONVENTION
;
5825 else if (type
->code () == TYPE_CODE_STRUCT
5826 && type
->num_fields () <= 2
5827 && type
->num_fields () >= 1
5828 && ((type
->num_fields () == 1
5829 && (TYPE_CODE (type
->field (0).type ())
5831 || (type
->num_fields () == 2
5832 && (TYPE_CODE (type
->field (0).type ())
5834 && (TYPE_CODE (type
->field (1).type ())
5836 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5838 /* A struct that contains one or two floats. Each value is part
5839 in the least significant part of their floating point
5843 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5844 field
< type
->num_fields (); field
++, regnum
+= 2)
5846 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5848 gdb_printf (gdb_stderr
, "Return float struct+%d\n",
5850 mips_xfer_register (gdbarch
, regcache
,
5851 gdbarch_num_regs (gdbarch
) + regnum
,
5852 TYPE_LENGTH (type
->field (field
).type ()),
5853 gdbarch_byte_order (gdbarch
),
5854 readbuf
, writebuf
, offset
);
5856 return RETURN_VALUE_REGISTER_CONVENTION
;
5860 else if (type
->code () == TYPE_CODE_STRUCT
5861 || type
->code () == TYPE_CODE_UNION
)
5863 /* A structure or union. Extract the left justified value,
5864 regardless of the byte order. I.e. DO NOT USE
5868 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5869 offset
< type
->length ();
5870 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5872 int xfer
= register_size (gdbarch
, regnum
);
5873 if (offset
+ xfer
> type
->length ())
5874 xfer
= type
->length () - offset
;
5876 gdb_printf (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5877 offset
, xfer
, regnum
);
5878 mips_xfer_register (gdbarch
, regcache
,
5879 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5880 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5882 return RETURN_VALUE_REGISTER_CONVENTION
;
5887 /* A scalar extract each part but least-significant-byte
5888 justified. o32 thinks registers are 4 byte, regardless of
5892 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5893 offset
< type
->length ();
5894 offset
+= MIPS32_REGSIZE
, regnum
++)
5896 int xfer
= MIPS32_REGSIZE
;
5897 if (offset
+ xfer
> type
->length ())
5898 xfer
= type
->length () - offset
;
5900 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5901 offset
, xfer
, regnum
);
5902 mips_xfer_register (gdbarch
, regcache
,
5903 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5904 gdbarch_byte_order (gdbarch
),
5905 readbuf
, writebuf
, offset
);
5907 return RETURN_VALUE_REGISTER_CONVENTION
;
5911 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5915 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5916 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5918 struct value
**args
, CORE_ADDR sp
,
5919 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5925 int stack_offset
= 0;
5926 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5927 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5929 /* For shared libraries, "t9" needs to point at the function
5931 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5933 /* Set the return address register to point to the entry point of
5934 the program, where a breakpoint lies in wait. */
5935 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5937 /* First ensure that the stack and structure return address (if any)
5938 are properly aligned. The stack has to be at least 64-bit
5939 aligned even on 32-bit machines, because doubles must be 64-bit
5940 aligned. For n32 and n64, stack frames need to be 128-bit
5941 aligned, so we round to this widest known alignment. */
5943 sp
= align_down (sp
, 16);
5944 struct_addr
= align_down (struct_addr
, 16);
5946 /* Now make space on the stack for the args. */
5947 for (argnum
= 0; argnum
< nargs
; argnum
++)
5949 struct type
*arg_type
= check_typedef (args
[argnum
]->type ());
5951 /* Allocate space on the stack. */
5952 arg_space
+= align_up (arg_type
->length (), MIPS64_REGSIZE
);
5954 sp
-= align_up (arg_space
, 16);
5957 gdb_printf (gdb_stdlog
,
5958 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5959 paddress (gdbarch
, sp
),
5960 (long) align_up (arg_space
, 16));
5962 /* Initialize the integer and float register pointers. */
5963 argreg
= MIPS_A0_REGNUM
;
5964 float_argreg
= mips_fpa0_regnum (gdbarch
);
5966 /* The struct_return pointer occupies the first parameter-passing reg. */
5967 if (return_method
== return_method_struct
)
5970 gdb_printf (gdb_stdlog
,
5971 "mips_o64_push_dummy_call: "
5972 "struct_return reg=%d %s\n",
5973 argreg
, paddress (gdbarch
, struct_addr
));
5974 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5975 stack_offset
+= MIPS64_REGSIZE
;
5978 /* Now load as many as possible of the first arguments into
5979 registers, and push the rest onto the stack. Loop thru args
5980 from first to last. */
5981 for (argnum
= 0; argnum
< nargs
; argnum
++)
5983 const gdb_byte
*val
;
5984 struct value
*arg
= args
[argnum
];
5985 struct type
*arg_type
= check_typedef (arg
->type ());
5986 int len
= arg_type
->length ();
5987 enum type_code typecode
= arg_type
->code ();
5990 gdb_printf (gdb_stdlog
,
5991 "mips_o64_push_dummy_call: %d len=%d type=%d",
5992 argnum
+ 1, len
, (int) typecode
);
5994 val
= arg
->contents ().data ();
5996 /* Floating point arguments passed in registers have to be
5997 treated specially. On 32-bit architectures, doubles are
5998 passed in register pairs; the even FP register gets the
5999 low word, and the odd FP register gets the high word.
6000 On O64, the first two floating point arguments are also
6001 copied to general registers, because MIPS16 functions
6002 don't use float registers for arguments. This duplication
6003 of arguments in general registers can't hurt non-MIPS16
6004 functions because those registers are normally skipped. */
6006 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
6007 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
6009 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
6011 gdb_printf (gdb_stdlog
, " - fpreg=%d val=%s",
6012 float_argreg
, phex (regval
, len
));
6013 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6015 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6016 argreg
, phex (regval
, len
));
6017 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6019 /* Reserve space for the FP register. */
6020 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6024 /* Copy the argument to general registers or the stack in
6025 register-sized pieces. Large arguments are split between
6026 registers and stack. */
6027 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6028 are treated specially: Irix cc passes them in registers
6029 where gcc sometimes puts them on the stack. For maximum
6030 compatibility, we will put them in both places. */
6031 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6032 && len
% MIPS64_REGSIZE
!= 0);
6035 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6038 gdb_printf (gdb_stdlog
, " -- partial=%d",
6041 /* Write this portion of the argument to the stack. */
6042 if (argreg
> mips_last_arg_regnum (gdbarch
)
6043 || odd_sized_struct
)
6045 /* Should shorter than int integer values be
6046 promoted to int before being stored? */
6047 int longword_offset
= 0;
6049 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6051 if ((typecode
== TYPE_CODE_INT
6052 || typecode
== TYPE_CODE_PTR
6053 || typecode
== TYPE_CODE_FLT
)
6055 longword_offset
= MIPS64_REGSIZE
- len
;
6060 gdb_printf (gdb_stdlog
, " - stack_offset=%s",
6061 paddress (gdbarch
, stack_offset
));
6062 gdb_printf (gdb_stdlog
, " longword_offset=%s",
6063 paddress (gdbarch
, longword_offset
));
6066 addr
= sp
+ stack_offset
+ longword_offset
;
6071 gdb_printf (gdb_stdlog
, " @%s ",
6072 paddress (gdbarch
, addr
));
6073 for (i
= 0; i
< partial_len
; i
++)
6075 gdb_printf (gdb_stdlog
, "%02x",
6079 write_memory (addr
, val
, partial_len
);
6082 /* Note!!! This is NOT an else clause. Odd sized
6083 structs may go thru BOTH paths. */
6084 /* Write this portion of the argument to a general
6085 purpose register. */
6086 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6088 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6090 /* Value may need to be sign extended, because
6091 mips_isa_regsize() != mips_abi_regsize(). */
6093 /* A non-floating-point argument being passed in a
6094 general register. If a struct or union, and if
6095 the remaining length is smaller than the register
6096 size, we have to adjust the register value on
6099 It does not seem to be necessary to do the
6100 same for integral types. */
6102 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6103 && partial_len
< MIPS64_REGSIZE
6104 && (typecode
== TYPE_CODE_STRUCT
6105 || typecode
== TYPE_CODE_UNION
))
6106 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6110 gdb_printf (gdb_stdlog
, " - reg=%d val=%s",
6112 phex (regval
, MIPS64_REGSIZE
));
6113 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6116 /* Prevent subsequent floating point arguments from
6117 being passed in floating point registers. */
6118 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6124 /* Compute the offset into the stack at which we will
6125 copy the next parameter.
6127 In older ABIs, the caller reserved space for
6128 registers that contained arguments. This was loosely
6129 referred to as their "home". Consequently, space is
6130 always allocated. */
6132 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6136 gdb_printf (gdb_stdlog
, "\n");
6139 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6141 /* Return adjusted stack pointer. */
6145 static enum return_value_convention
6146 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6147 struct type
*type
, struct regcache
*regcache
,
6148 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6150 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6151 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6152 enum mips_fval_reg fval_reg
;
6154 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6155 if (type
->code () == TYPE_CODE_STRUCT
6156 || type
->code () == TYPE_CODE_UNION
6157 || type
->code () == TYPE_CODE_ARRAY
)
6158 return RETURN_VALUE_STRUCT_CONVENTION
;
6159 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6161 /* A floating-point value. If reading in or copying, then we get it
6162 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6163 If writing out only, then we put it to both FP0 and GPR2. We do
6164 not support reading in with no function known, if this safety
6165 check ever triggers, then we'll have to try harder. */
6166 gdb_assert (function
|| !readbuf
);
6171 gdb_printf (gdb_stderr
, "Return float in $fp0\n");
6174 gdb_printf (gdb_stderr
, "Return float in $2\n");
6176 case mips_fval_both
:
6177 gdb_printf (gdb_stderr
, "Return float in $fp0 and $2\n");
6180 if (fval_reg
!= mips_fval_gpr
)
6181 mips_xfer_register (gdbarch
, regcache
,
6182 (gdbarch_num_regs (gdbarch
)
6183 + mips_regnum (gdbarch
)->fp0
),
6185 gdbarch_byte_order (gdbarch
),
6186 readbuf
, writebuf
, 0);
6187 if (fval_reg
!= mips_fval_fpr
)
6188 mips_xfer_register (gdbarch
, regcache
,
6189 gdbarch_num_regs (gdbarch
) + 2,
6191 gdbarch_byte_order (gdbarch
),
6192 readbuf
, writebuf
, 0);
6193 return RETURN_VALUE_REGISTER_CONVENTION
;
6197 /* A scalar extract each part but least-significant-byte
6201 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6202 offset
< type
->length ();
6203 offset
+= MIPS64_REGSIZE
, regnum
++)
6205 int xfer
= MIPS64_REGSIZE
;
6206 if (offset
+ xfer
> type
->length ())
6207 xfer
= type
->length () - offset
;
6209 gdb_printf (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6210 offset
, xfer
, regnum
);
6211 mips_xfer_register (gdbarch
, regcache
,
6212 gdbarch_num_regs (gdbarch
) + regnum
,
6213 xfer
, gdbarch_byte_order (gdbarch
),
6214 readbuf
, writebuf
, offset
);
6216 return RETURN_VALUE_REGISTER_CONVENTION
;
6220 /* Floating point register management.
6222 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6223 64bit operations, these early MIPS cpus treat fp register pairs
6224 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6225 registers and offer a compatibility mode that emulates the MIPS2 fp
6226 model. When operating in MIPS2 fp compat mode, later cpu's split
6227 double precision floats into two 32-bit chunks and store them in
6228 consecutive fp regs. To display 64-bit floats stored in this
6229 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6230 Throw in user-configurable endianness and you have a real mess.
6232 The way this works is:
6233 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6234 double-precision value will be split across two logical registers.
6235 The lower-numbered logical register will hold the low-order bits,
6236 regardless of the processor's endianness.
6237 - If we are on a 64-bit processor, and we are looking for a
6238 single-precision value, it will be in the low ordered bits
6239 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6240 save slot in memory.
6241 - If we are in 64-bit mode, everything is straightforward.
6243 Note that this code only deals with "live" registers at the top of the
6244 stack. We will attempt to deal with saved registers later, when
6245 the raw/cooked register interface is in place. (We need a general
6246 interface that can deal with dynamic saved register sizes -- fp
6247 regs could be 32 bits wide in one frame and 64 on the frame above
6250 /* Copy a 32-bit single-precision value from the current frame
6251 into rare_buffer. */
6254 mips_read_fp_register_single (frame_info_ptr frame
, int regno
,
6255 gdb_byte
*rare_buffer
)
6257 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6258 int raw_size
= register_size (gdbarch
, regno
);
6259 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6261 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6262 error (_("can't read register %d (%s)"),
6263 regno
, gdbarch_register_name (gdbarch
, regno
));
6266 /* We have a 64-bit value for this register. Find the low-order
6270 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6275 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6279 memcpy (rare_buffer
, raw_buffer
, 4);
6283 /* Copy a 64-bit double-precision value from the current frame into
6284 rare_buffer. This may include getting half of it from the next
6288 mips_read_fp_register_double (frame_info_ptr frame
, int regno
,
6289 gdb_byte
*rare_buffer
)
6291 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6292 int raw_size
= register_size (gdbarch
, regno
);
6294 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6296 /* We have a 64-bit value for this register, and we should use
6298 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6299 error (_("can't read register %d (%s)"),
6300 regno
, gdbarch_register_name (gdbarch
, regno
));
6304 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6306 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6307 internal_error (_("mips_read_fp_register_double: bad access to "
6308 "odd-numbered FP register"));
6310 /* mips_read_fp_register_single will find the correct 32 bits from
6312 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6314 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6315 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6319 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6320 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6326 mips_print_fp_register (struct ui_file
*file
, frame_info_ptr frame
,
6328 { /* Do values for FP (float) regs. */
6329 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6330 gdb_byte
*raw_buffer
;
6331 std::string flt_str
, dbl_str
;
6333 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6334 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6338 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6340 gdb_printf (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6341 gdb_printf (file
, "%*s",
6342 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6345 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6347 struct value_print_options opts
;
6349 /* 4-byte registers: Print hex and floating. Also print even
6350 numbered registers as doubles. */
6351 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6352 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6354 get_formatted_print_options (&opts
, 'x');
6355 print_scalar_formatted (raw_buffer
,
6356 builtin_type (gdbarch
)->builtin_uint32
,
6359 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6361 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6363 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6364 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6366 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6371 struct value_print_options opts
;
6373 /* Eight byte registers: print each one as hex, float and double. */
6374 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6375 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6377 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6378 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6380 get_formatted_print_options (&opts
, 'x');
6381 print_scalar_formatted (raw_buffer
,
6382 builtin_type (gdbarch
)->builtin_uint64
,
6385 gdb_printf (file
, " flt: %s", flt_str
.c_str ());
6386 gdb_printf (file
, " dbl: %s", dbl_str
.c_str ());
6391 mips_print_register (struct ui_file
*file
, frame_info_ptr frame
,
6394 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6395 struct value_print_options opts
;
6398 if (mips_float_register_p (gdbarch
, regnum
))
6400 mips_print_fp_register (file
, frame
, regnum
);
6404 val
= get_frame_register_value (frame
, regnum
);
6406 gdb_puts (gdbarch_register_name (gdbarch
, regnum
), file
);
6408 /* The problem with printing numeric register names (r26, etc.) is that
6409 the user can't use them on input. Probably the best solution is to
6410 fix it so that either the numeric or the funky (a2, etc.) names
6411 are accepted on input. */
6412 if (regnum
< MIPS_NUMREGS
)
6413 gdb_printf (file
, "(r%d): ", regnum
);
6415 gdb_printf (file
, ": ");
6417 get_formatted_print_options (&opts
, 'x');
6418 value_print_scalar_formatted (val
, &opts
, 0, file
);
6421 /* Print IEEE exception condition bits in FLAGS. */
6424 print_fpu_flags (struct ui_file
*file
, int flags
)
6426 if (flags
& (1 << 0))
6427 gdb_puts (" inexact", file
);
6428 if (flags
& (1 << 1))
6429 gdb_puts (" uflow", file
);
6430 if (flags
& (1 << 2))
6431 gdb_puts (" oflow", file
);
6432 if (flags
& (1 << 3))
6433 gdb_puts (" div0", file
);
6434 if (flags
& (1 << 4))
6435 gdb_puts (" inval", file
);
6436 if (flags
& (1 << 5))
6437 gdb_puts (" unimp", file
);
6438 gdb_putc ('\n', file
);
6441 /* Print interesting information about the floating point processor
6442 (if present) or emulator. */
6445 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6446 frame_info_ptr frame
, const char *args
)
6448 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6449 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6453 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6454 type
= MIPS_FPU_NONE
;
6456 gdb_printf (file
, "fpu type: %s\n",
6457 type
== MIPS_FPU_DOUBLE
? "double-precision"
6458 : type
== MIPS_FPU_SINGLE
? "single-precision"
6461 if (type
== MIPS_FPU_NONE
)
6464 gdb_printf (file
, "reg size: %d bits\n",
6465 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6467 gdb_puts ("cond :", file
);
6468 if (fcs
& (1 << 23))
6469 gdb_puts (" 0", file
);
6470 for (i
= 1; i
<= 7; i
++)
6471 if (fcs
& (1 << (24 + i
)))
6472 gdb_printf (file
, " %d", i
);
6473 gdb_putc ('\n', file
);
6475 gdb_puts ("cause :", file
);
6476 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6477 fputs ("mask :", stdout
);
6478 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6479 fputs ("flags :", stdout
);
6480 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6482 gdb_puts ("rounding: ", file
);
6485 case 0: gdb_puts ("nearest\n", file
); break;
6486 case 1: gdb_puts ("zero\n", file
); break;
6487 case 2: gdb_puts ("+inf\n", file
); break;
6488 case 3: gdb_puts ("-inf\n", file
); break;
6491 gdb_puts ("flush :", file
);
6492 if (fcs
& (1 << 21))
6493 gdb_puts (" nearest", file
);
6494 if (fcs
& (1 << 22))
6495 gdb_puts (" override", file
);
6496 if (fcs
& (1 << 24))
6497 gdb_puts (" zero", file
);
6498 if ((fcs
& (0xb << 21)) == 0)
6499 gdb_puts (" no", file
);
6500 gdb_putc ('\n', file
);
6502 gdb_printf (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6503 gdb_printf (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6504 gdb_putc ('\n', file
);
6506 default_print_float_info (gdbarch
, file
, frame
, args
);
6509 /* Replacement for generic do_registers_info.
6510 Print regs in pretty columns. */
6513 print_fp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6516 gdb_printf (file
, " ");
6517 mips_print_fp_register (file
, frame
, regnum
);
6518 gdb_printf (file
, "\n");
6523 /* Print a row's worth of GP (int) registers, with name labels above. */
6526 print_gp_register_row (struct ui_file
*file
, frame_info_ptr frame
,
6529 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6530 /* Do values for GP (int) regs. */
6531 const gdb_byte
*raw_buffer
;
6532 struct value
*value
;
6533 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6538 /* For GP registers, we print a separate row of names above the vals. */
6539 for (col
= 0, regnum
= start_regnum
;
6540 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6543 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6544 continue; /* unused register */
6545 if (mips_float_register_p (gdbarch
, regnum
))
6546 break; /* End the row: reached FP register. */
6547 /* Large registers are handled separately. */
6548 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6551 break; /* End the row before this register. */
6553 /* Print this register on a row by itself. */
6554 mips_print_register (file
, frame
, regnum
);
6555 gdb_printf (file
, "\n");
6559 gdb_printf (file
, " ");
6561 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6562 gdbarch_register_name (gdbarch
, regnum
));
6569 /* Print the R0 to R31 names. */
6570 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6571 gdb_printf (file
, "\n R%-4d",
6572 start_regnum
% gdbarch_num_regs (gdbarch
));
6574 gdb_printf (file
, "\n ");
6576 /* Now print the values in hex, 4 or 8 to the row. */
6577 for (col
= 0, regnum
= start_regnum
;
6578 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6581 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6582 continue; /* unused register */
6583 if (mips_float_register_p (gdbarch
, regnum
))
6584 break; /* End row: reached FP register. */
6585 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6586 break; /* End row: large register. */
6588 /* OK: get the data in raw format. */
6589 value
= get_frame_register_value (frame
, regnum
);
6590 if (value
->optimized_out ()
6591 || !value
->entirely_available ())
6593 gdb_printf (file
, "%*s ",
6594 (int) mips_abi_regsize (gdbarch
) * 2,
6595 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6596 : "<unavailable>"));
6600 raw_buffer
= value
->contents_all ().data ();
6601 /* pad small registers */
6603 byte
< (mips_abi_regsize (gdbarch
)
6604 - register_size (gdbarch
, regnum
)); byte
++)
6605 gdb_printf (file
, " ");
6606 /* Now print the register value in hex, endian order. */
6607 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6609 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6610 byte
< register_size (gdbarch
, regnum
); byte
++)
6611 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6613 for (byte
= register_size (gdbarch
, regnum
) - 1;
6615 gdb_printf (file
, "%02x", raw_buffer
[byte
]);
6616 gdb_printf (file
, " ");
6619 if (col
> 0) /* ie. if we actually printed anything... */
6620 gdb_printf (file
, "\n");
6625 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6628 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6629 frame_info_ptr frame
, int regnum
, int all
)
6631 if (regnum
!= -1) /* Do one specified register. */
6633 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6634 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6635 error (_("Not a valid register for the current processor type"));
6637 mips_print_register (file
, frame
, regnum
);
6638 gdb_printf (file
, "\n");
6641 /* Do all (or most) registers. */
6643 regnum
= gdbarch_num_regs (gdbarch
);
6644 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6646 if (mips_float_register_p (gdbarch
, regnum
))
6648 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6649 regnum
= print_fp_register_row (file
, frame
, regnum
);
6651 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6654 regnum
= print_gp_register_row (file
, frame
, regnum
);
6660 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6661 frame_info_ptr frame
)
6663 CORE_ADDR pc
= get_frame_pc (frame
);
6668 if ((mips_pc_is_mips (pc
)
6669 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6670 || (mips_pc_is_micromips (gdbarch
, pc
)
6671 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6672 || (mips_pc_is_mips16 (gdbarch
, pc
)
6673 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6676 isa
= mips_pc_isa (gdbarch
, pc
);
6677 /* _has_delay_slot above will have validated the read. */
6678 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6679 size
= mips_insn_size (isa
, insn
);
6681 const address_space
*aspace
= get_frame_address_space (frame
);
6683 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6686 /* To skip prologues, I use this predicate. Returns either PC itself
6687 if the code at PC does not look like a function prologue; otherwise
6688 returns an address that (if we're lucky) follows the prologue. If
6689 LENIENT, then we must skip everything which is involved in setting
6690 up the frame (it's OK to skip more, just so long as we don't skip
6691 anything which might clobber the registers which are being saved.
6692 We must skip more in the case where part of the prologue is in the
6693 delay slot of a non-prologue instruction). */
6696 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6699 CORE_ADDR func_addr
;
6701 /* See if we can determine the end of the prologue via the symbol table.
6702 If so, then return either PC, or the PC after the prologue, whichever
6704 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6706 CORE_ADDR post_prologue_pc
6707 = skip_prologue_using_sal (gdbarch
, func_addr
);
6708 if (post_prologue_pc
!= 0)
6709 return std::max (pc
, post_prologue_pc
);
6712 /* Can't determine prologue from the symbol table, need to examine
6715 /* Find an upper limit on the function prologue using the debug
6716 information. If the debug information could not be used to provide
6717 that bound, then use an arbitrary large number as the upper bound. */
6718 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6720 limit_pc
= pc
+ 100; /* Magic. */
6722 if (mips_pc_is_mips16 (gdbarch
, pc
))
6723 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6724 else if (mips_pc_is_micromips (gdbarch
, pc
))
6725 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6727 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6730 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6731 This is a helper function for mips_stack_frame_destroyed_p. */
6734 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6736 CORE_ADDR func_addr
= 0, func_end
= 0;
6738 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6740 /* The MIPS epilogue is max. 12 bytes long. */
6741 CORE_ADDR addr
= func_end
- 12;
6743 if (addr
< func_addr
+ 4)
6744 addr
= func_addr
+ 4;
6748 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6750 unsigned long high_word
;
6753 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6754 high_word
= (inst
>> 16) & 0xffff;
6756 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6757 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6758 && inst
!= 0x03e00008 /* jr $ra */
6759 && inst
!= 0x00000000) /* nop */
6769 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6770 This is a helper function for mips_stack_frame_destroyed_p. */
6773 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6775 CORE_ADDR func_addr
= 0;
6776 CORE_ADDR func_end
= 0;
6784 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6787 /* The microMIPS epilogue is max. 12 bytes long. */
6788 addr
= func_end
- 12;
6790 if (addr
< func_addr
+ 2)
6791 addr
= func_addr
+ 2;
6795 for (; pc
< func_end
; pc
+= loc
)
6798 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6799 loc
+= MIPS_INSN16_SIZE
;
6800 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6802 /* 32-bit instructions. */
6803 case 2 * MIPS_INSN16_SIZE
:
6805 insn
|= mips_fetch_instruction (gdbarch
,
6806 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6807 loc
+= MIPS_INSN16_SIZE
;
6808 switch (micromips_op (insn
>> 16))
6810 case 0xc: /* ADDIU: bits 001100 */
6811 case 0x17: /* DADDIU: bits 010111 */
6812 sreg
= b0s5_reg (insn
>> 16);
6813 dreg
= b5s5_reg (insn
>> 16);
6814 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6815 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6816 /* (D)ADDIU $sp, imm */
6826 /* 16-bit instructions. */
6827 case MIPS_INSN16_SIZE
:
6828 switch (micromips_op (insn
))
6830 case 0x3: /* MOVE: bits 000011 */
6831 sreg
= b0s5_reg (insn
);
6832 dreg
= b5s5_reg (insn
);
6833 if (sreg
== 0 && dreg
== 0)
6834 /* MOVE $zero, $zero aka NOP */
6838 case 0x11: /* POOL16C: bits 010001 */
6839 if (b5s5_op (insn
) == 0x18
6840 /* JRADDIUSP: bits 010011 11000 */
6841 || (b5s5_op (insn
) == 0xd
6842 /* JRC: bits 010011 01101 */
6843 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6848 case 0x13: /* POOL16D: bits 010011 */
6849 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6850 if ((insn
& 0x1) == 0x1
6851 /* ADDIUSP: bits 010011 1 */
6865 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6866 This is a helper function for mips_stack_frame_destroyed_p. */
6869 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6871 CORE_ADDR func_addr
= 0, func_end
= 0;
6873 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6875 /* The MIPS epilogue is max. 12 bytes long. */
6876 CORE_ADDR addr
= func_end
- 12;
6878 if (addr
< func_addr
+ 4)
6879 addr
= func_addr
+ 4;
6883 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6885 unsigned short inst
;
6887 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6889 if ((inst
& 0xf800) == 0xf000) /* extend */
6892 if (inst
!= 0x6300 /* addiu $sp,offset */
6893 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6894 && inst
!= 0xe820 /* jr $ra */
6895 && inst
!= 0xe8a0 /* jrc $ra */
6896 && inst
!= 0x6500) /* nop */
6906 /* Implement the stack_frame_destroyed_p gdbarch method.
6908 The epilogue is defined here as the area at the end of a function,
6909 after an instruction which destroys the function's stack frame. */
6912 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6914 if (mips_pc_is_mips16 (gdbarch
, pc
))
6915 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6916 else if (mips_pc_is_micromips (gdbarch
, pc
))
6917 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6919 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6922 /* Commands to show/set the MIPS FPU type. */
6925 show_mipsfpu_command (const char *args
, int from_tty
)
6929 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6932 ("The MIPS floating-point coprocessor is unknown "
6933 "because the current architecture is not MIPS.\n");
6937 switch (mips_get_fpu_type (target_gdbarch ()))
6939 case MIPS_FPU_SINGLE
:
6940 fpu
= "single-precision";
6942 case MIPS_FPU_DOUBLE
:
6943 fpu
= "double-precision";
6946 fpu
= "absent (none)";
6949 internal_error (_("bad switch"));
6951 if (mips_fpu_type_auto
)
6952 gdb_printf ("The MIPS floating-point coprocessor "
6953 "is set automatically (currently %s)\n",
6957 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6962 set_mipsfpu_single_command (const char *args
, int from_tty
)
6964 struct gdbarch_info info
;
6965 mips_fpu_type
= MIPS_FPU_SINGLE
;
6966 mips_fpu_type_auto
= 0;
6967 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6968 instead of relying on globals. Doing that would let generic code
6969 handle the search for this specific architecture. */
6970 if (!gdbarch_update_p (info
))
6971 internal_error (_("set mipsfpu failed"));
6975 set_mipsfpu_double_command (const char *args
, int from_tty
)
6977 struct gdbarch_info info
;
6978 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6979 mips_fpu_type_auto
= 0;
6980 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6981 instead of relying on globals. Doing that would let generic code
6982 handle the search for this specific architecture. */
6983 if (!gdbarch_update_p (info
))
6984 internal_error (_("set mipsfpu failed"));
6988 set_mipsfpu_none_command (const char *args
, int from_tty
)
6990 struct gdbarch_info info
;
6991 mips_fpu_type
= MIPS_FPU_NONE
;
6992 mips_fpu_type_auto
= 0;
6993 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6994 instead of relying on globals. Doing that would let generic code
6995 handle the search for this specific architecture. */
6996 if (!gdbarch_update_p (info
))
6997 internal_error (_("set mipsfpu failed"));
7001 set_mipsfpu_auto_command (const char *args
, int from_tty
)
7003 mips_fpu_type_auto
= 1;
7006 /* Just like reinit_frame_cache, but with the right arguments to be
7007 callable as an sfunc. */
7010 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
7011 struct cmd_list_element
*c
)
7013 reinit_frame_cache ();
7017 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7019 gdb_disassemble_info
*di
7020 = static_cast<gdb_disassemble_info
*> (info
->application_data
);
7021 struct gdbarch
*gdbarch
= di
->arch ();
7023 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7024 disassembler needs to be able to locally determine the ISA, and
7025 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7027 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7028 info
->mach
= bfd_mach_mips16
;
7029 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7030 info
->mach
= bfd_mach_mips_micromips
;
7032 /* Round down the instruction address to the appropriate boundary. */
7033 memaddr
&= (info
->mach
== bfd_mach_mips16
7034 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7036 return default_print_insn (memaddr
, info
);
7039 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7042 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7044 CORE_ADDR pc
= *pcptr
;
7046 if (mips_pc_is_mips16 (gdbarch
, pc
))
7048 *pcptr
= unmake_compact_addr (pc
);
7049 return MIPS_BP_KIND_MIPS16
;
7051 else if (mips_pc_is_micromips (gdbarch
, pc
))
7056 *pcptr
= unmake_compact_addr (pc
);
7057 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7058 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7059 return MIPS_BP_KIND_MICROMIPS16
;
7061 return MIPS_BP_KIND_MICROMIPS32
;
7064 return MIPS_BP_KIND_MIPS32
;
7067 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7069 static const gdb_byte
*
7070 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7072 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7076 case MIPS_BP_KIND_MIPS16
:
7078 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7079 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7082 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7083 return mips16_big_breakpoint
;
7085 return mips16_little_breakpoint
;
7087 case MIPS_BP_KIND_MICROMIPS16
:
7089 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7090 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7094 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7095 return micromips16_big_breakpoint
;
7097 return micromips16_little_breakpoint
;
7099 case MIPS_BP_KIND_MICROMIPS32
:
7101 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7102 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7105 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7106 return micromips32_big_breakpoint
;
7108 return micromips32_little_breakpoint
;
7110 case MIPS_BP_KIND_MIPS32
:
7112 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7113 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7116 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7117 return big_breakpoint
;
7119 return little_breakpoint
;
7122 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7126 /* Return non-zero if the standard MIPS instruction INST has a branch
7127 delay slot (i.e. it is a jump or branch instruction). This function
7128 is based on mips32_next_pc. */
7131 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7137 op
= itype_op (inst
);
7138 if ((inst
& 0xe0000000) != 0)
7140 rs
= itype_rs (inst
);
7141 rt
= itype_rt (inst
);
7142 return (is_octeon_bbit_op (op
, gdbarch
)
7143 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7144 || op
== 29 /* JALX: bits 011101 */
7147 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7148 || (rs
== 9 && (rt
& 0x2) == 0)
7149 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7150 || (rs
== 10 && (rt
& 0x2) == 0))));
7151 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7154 switch (op
& 0x07) /* extract bits 28,27,26 */
7156 case 0: /* SPECIAL */
7157 op
= rtype_funct (inst
);
7158 return (op
== 8 /* JR */
7159 || op
== 9); /* JALR */
7160 break; /* end SPECIAL */
7161 case 1: /* REGIMM */
7162 rs
= itype_rs (inst
);
7163 rt
= itype_rt (inst
); /* branch condition */
7164 return ((rt
& 0xc) == 0
7165 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7166 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7167 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7168 /* BPOSGE32, BPOSGE64: bits 1110x */
7169 break; /* end REGIMM */
7170 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7176 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7177 delay slot (i.e. it is a jump or branch instruction). */
7180 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7185 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7189 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7192 /* Return non-zero if the microMIPS instruction INSN, comprising the
7193 16-bit major opcode word in the high 16 bits and any second word
7194 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7195 jump or branch instruction). The instruction must be 32-bit if
7196 MUSTBE32 is set or can be any instruction otherwise. */
7199 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7201 ULONGEST major
= insn
>> 16;
7203 switch (micromips_op (major
))
7205 /* 16-bit instructions. */
7206 case 0x33: /* B16: bits 110011 */
7207 case 0x2b: /* BNEZ16: bits 101011 */
7208 case 0x23: /* BEQZ16: bits 100011 */
7210 case 0x11: /* POOL16C: bits 010001 */
7212 && ((b5s5_op (major
) == 0xc
7213 /* JR16: bits 010001 01100 */
7214 || (b5s5_op (major
) & 0x1e) == 0xe)));
7215 /* JALR16, JALRS16: bits 010001 0111x */
7216 /* 32-bit instructions. */
7217 case 0x3d: /* JAL: bits 111101 */
7218 case 0x3c: /* JALX: bits 111100 */
7219 case 0x35: /* J: bits 110101 */
7220 case 0x2d: /* BNE: bits 101101 */
7221 case 0x25: /* BEQ: bits 100101 */
7222 case 0x1d: /* JALS: bits 011101 */
7224 case 0x10: /* POOL32I: bits 010000 */
7225 return ((b5s5_op (major
) & 0x1c) == 0x0
7226 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7227 || (b5s5_op (major
) & 0x1d) == 0x4
7228 /* BLEZ, BGTZ: bits 010000 001x0 */
7229 || (b5s5_op (major
) & 0x1d) == 0x11
7230 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7231 || ((b5s5_op (major
) & 0x1e) == 0x14
7232 && (major
& 0x3) == 0x0)
7233 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7234 || (b5s5_op (major
) & 0x1e) == 0x1a
7235 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7236 || ((b5s5_op (major
) & 0x1e) == 0x1c
7237 && (major
& 0x3) == 0x0)
7238 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7239 || ((b5s5_op (major
) & 0x1c) == 0x1c
7240 && (major
& 0x3) == 0x1));
7241 /* BC1ANY*: bits 010000 111xx xxx01 */
7242 case 0x0: /* POOL32A: bits 000000 */
7243 return (b0s6_op (insn
) == 0x3c
7244 /* POOL32Axf: bits 000000 ... 111100 */
7245 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7246 /* JALR, JALR.HB: 000000 000x111100 111100 */
7247 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7253 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7254 slot (i.e. it is a non-compact jump instruction). The instruction
7255 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7258 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7259 CORE_ADDR addr
, int mustbe32
)
7265 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7268 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7270 if (size
== 2 * MIPS_INSN16_SIZE
)
7272 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7277 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7280 /* Return non-zero if the MIPS16 instruction INST, which must be
7281 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7282 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7283 instruction). This function is based on mips16_next_pc. */
7286 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7288 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7290 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7293 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7294 slot (i.e. it is a non-compact jump instruction). The instruction
7295 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7298 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7299 CORE_ADDR addr
, int mustbe32
)
7301 unsigned short insn
;
7304 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7308 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7311 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7312 This assumes KSSEG exists. */
7315 mips_segment_boundary (CORE_ADDR bpaddr
)
7317 CORE_ADDR mask
= CORE_ADDR_MAX
;
7320 if (sizeof (CORE_ADDR
) == 8)
7321 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7322 a compiler warning produced where CORE_ADDR is a 32-bit type even
7323 though in that case this is dead code). */
7324 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7327 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7328 segsize
= 29; /* 32-bit compatibility segment */
7330 segsize
= 62; /* xkseg */
7332 case 2: /* xkphys */
7335 default: /* xksseg (1), xkuseg/kuseg (0) */
7339 else if (bpaddr
& 0x80000000) /* kernel segment */
7342 segsize
= 31; /* user segment */
7344 return bpaddr
& mask
;
7347 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7348 it backwards if necessary. Return the address of the new location. */
7351 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7353 CORE_ADDR prev_addr
;
7355 CORE_ADDR func_addr
;
7357 /* If a breakpoint is set on the instruction in a branch delay slot,
7358 GDB gets confused. When the breakpoint is hit, the PC isn't on
7359 the instruction in the branch delay slot, the PC will point to
7360 the branch instruction. Since the PC doesn't match any known
7361 breakpoints, GDB reports a trap exception.
7363 There are two possible fixes for this problem.
7365 1) When the breakpoint gets hit, see if the BD bit is set in the
7366 Cause register (which indicates the last exception occurred in a
7367 branch delay slot). If the BD bit is set, fix the PC to point to
7368 the instruction in the branch delay slot.
7370 2) When the user sets the breakpoint, don't allow him to set the
7371 breakpoint on the instruction in the branch delay slot. Instead
7372 move the breakpoint to the branch instruction (which will have
7375 The problem with the first solution is that if the user then
7376 single-steps the processor, the branch instruction will get
7377 skipped (since GDB thinks the PC is on the instruction in the
7380 So, we'll use the second solution. To do this we need to know if
7381 the instruction we're trying to set the breakpoint on is in the
7382 branch delay slot. */
7384 boundary
= mips_segment_boundary (bpaddr
);
7386 /* Make sure we don't scan back before the beginning of the current
7387 function, since we may fetch constant data or insns that look like
7388 a jump. Of course we might do that anyway if the compiler has
7389 moved constants inline. :-( */
7390 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7391 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7392 boundary
= func_addr
;
7394 if (mips_pc_is_mips (bpaddr
))
7396 if (bpaddr
== boundary
)
7399 /* If the previous instruction has a branch delay slot, we have
7400 to move the breakpoint to the branch instruction. */
7401 prev_addr
= bpaddr
- 4;
7402 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7407 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7408 CORE_ADDR addr
, jmpaddr
;
7411 boundary
= unmake_compact_addr (boundary
);
7413 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7414 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7415 so try for that first, then try the 2 byte JALR/JR.
7416 The microMIPS ASE has a whole range of jumps and branches
7417 with delay slots, some of which take 4 bytes and some take
7418 2 bytes, so the idea is the same.
7419 FIXME: We have to assume that bpaddr is not the second half
7420 of an extended instruction. */
7421 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7422 ? micromips_insn_at_pc_has_delay_slot
7423 : mips16_insn_at_pc_has_delay_slot
);
7427 for (i
= 1; i
< 4; i
++)
7429 if (unmake_compact_addr (addr
) == boundary
)
7431 addr
-= MIPS_INSN16_SIZE
;
7432 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7433 /* Looks like a JR/JALR at [target-1], but it could be
7434 the second word of a previous JAL/JALX, so record it
7435 and check back one more. */
7437 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7440 /* Looks like a JAL/JALX at [target-2], but it could also
7441 be the second word of a previous JAL/JALX, record it,
7442 and check back one more. */
7445 /* Looks like a JAL/JALX at [target-3], so any previously
7446 recorded JAL/JALX or JR/JALR must be wrong, because:
7449 -2: JAL-ext (can't be JAL/JALX)
7450 -1: bdslot (can't be JR/JALR)
7453 Of course it could be another JAL-ext which looks
7454 like a JAL, but in that case we'd have broken out
7455 of this loop at [target-2]:
7459 -2: bdslot (can't be jmp)
7466 /* Not a jump instruction: if we're at [target-1] this
7467 could be the second word of a JAL/JALX, so continue;
7468 otherwise we're done. */
7481 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7482 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7485 mips_is_stub_suffix (const char *suffix
, int zero
)
7490 return zero
&& suffix
[1] == '\0';
7492 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7497 return suffix
[1] == '\0';
7503 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7504 call stubs, one of sf, df, sc, or dc. */
7507 mips_is_stub_mode (const char *mode
)
7509 return ((mode
[0] == 's' || mode
[0] == 'd')
7510 && (mode
[1] == 'f' || mode
[1] == 'c'));
7513 /* Code at PC is a compiler-generated stub. Such a stub for a function
7514 bar might have a name like __fn_stub_bar, and might look like this:
7521 followed by (or interspersed with):
7528 addiu $25, $25, %lo(bar)
7531 ($1 may be used in old code; for robustness we accept any register)
7534 lui $28, %hi(_gp_disp)
7535 addiu $28, $28, %lo(_gp_disp)
7538 addiu $25, $25, %lo(bar)
7541 In the case of a __call_stub_bar stub, the sequence to set up
7542 arguments might look like this:
7549 followed by (or interspersed with) one of the jump sequences above.
7551 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7552 of J or JR, respectively, followed by:
7558 We are at the beginning of the stub here, and scan down and extract
7559 the target address from the jump immediate instruction or, if a jump
7560 register instruction is used, from the register referred. Return
7561 the value of PC calculated or 0 if inconclusive.
7563 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7566 mips_get_mips16_fn_stub_pc (frame_info_ptr frame
, CORE_ADDR pc
)
7568 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7569 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7570 int addrreg
= MIPS_ZERO_REGNUM
;
7571 CORE_ADDR start_pc
= pc
;
7572 CORE_ADDR target_pc
= 0;
7579 status
== 0 && target_pc
== 0 && i
< 20;
7580 i
++, pc
+= MIPS_INSN32_SIZE
)
7582 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7588 switch (itype_op (inst
))
7590 case 0: /* SPECIAL */
7591 switch (rtype_funct (inst
))
7595 rs
= rtype_rs (inst
);
7596 if (rs
== MIPS_GP_REGNUM
)
7597 target_pc
= gp
; /* Hmm... */
7598 else if (rs
== addrreg
)
7602 case 0x21: /* ADDU */
7603 rt
= rtype_rt (inst
);
7604 rs
= rtype_rs (inst
);
7605 rd
= rtype_rd (inst
);
7606 if (rd
== MIPS_GP_REGNUM
7607 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7608 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7616 target_pc
= jtype_target (inst
) << 2;
7617 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7621 rt
= itype_rt (inst
);
7622 rs
= itype_rs (inst
);
7625 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7626 if (rt
== MIPS_GP_REGNUM
)
7628 else if (rt
== addrreg
)
7634 rt
= itype_rt (inst
);
7635 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7636 if (rt
== MIPS_GP_REGNUM
)
7638 else if (rt
!= MIPS_ZERO_REGNUM
)
7646 rt
= itype_rt (inst
);
7647 rs
= itype_rs (inst
);
7648 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7649 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7653 memset (buf
, 0, sizeof (buf
));
7654 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7656 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7665 /* If PC is in a MIPS16 call or return stub, return the address of the
7666 target PC, which is either the callee or the caller. There are several
7667 cases which must be handled:
7669 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7670 and the target PC is in $31 ($ra).
7671 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7672 and the target PC is in $2.
7673 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7674 i.e. before the JALR instruction, this is effectively a call stub
7675 and the target PC is in $2. Otherwise this is effectively
7676 a return stub and the target PC is in $18.
7677 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7678 JAL or JALR instruction, this is effectively a call stub and the
7679 target PC is buried in the instruction stream. Otherwise this
7680 is effectively a return stub and the target PC is in $18.
7681 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7682 stub and the target PC is buried in the instruction stream.
7684 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7685 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7689 mips_skip_mips16_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7691 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7692 CORE_ADDR start_addr
;
7696 /* Find the starting address and name of the function containing the PC. */
7697 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7700 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7701 and the target PC is in $31 ($ra). */
7702 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7703 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7704 && mips_is_stub_mode (name
+ prefixlen
)
7705 && name
[prefixlen
+ 2] == '\0')
7706 return get_frame_register_signed
7707 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7709 /* If the PC is in __mips16_call_stub_*, this is one of the call
7710 call/return stubs. */
7711 prefixlen
= strlen (mips_str_mips16_call_stub
);
7712 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7714 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7715 and the target PC is in $2. */
7716 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7717 return get_frame_register_signed
7718 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7720 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7721 i.e. before the JALR instruction, this is effectively a call stub
7722 and the target PC is in $2. Otherwise this is effectively
7723 a return stub and the target PC is in $18. */
7724 else if (mips_is_stub_mode (name
+ prefixlen
)
7725 && name
[prefixlen
+ 2] == '_'
7726 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7728 if (pc
== start_addr
)
7729 /* This is the 'call' part of a call stub. The return
7730 address is in $2. */
7731 return get_frame_register_signed
7732 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7734 /* This is the 'return' part of a call stub. The return
7735 address is in $18. */
7736 return get_frame_register_signed
7737 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7740 return 0; /* Not a stub. */
7743 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7744 compiler-generated call or call/return stubs. */
7745 if (startswith (name
, mips_str_fn_stub
)
7746 || startswith (name
, mips_str_call_stub
))
7748 if (pc
== start_addr
)
7749 /* This is the 'call' part of a call stub. Call this helper
7750 to scan through this code for interesting instructions
7751 and determine the final PC. */
7752 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7754 /* This is the 'return' part of a call stub. The return address
7756 return get_frame_register_signed
7757 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7760 return 0; /* Not a stub. */
7763 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7764 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7767 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7769 CORE_ADDR start_addr
;
7772 /* Find the starting address of the function containing the PC. */
7773 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7776 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7777 the start, i.e. after the JALR instruction, this is effectively
7779 prefixlen
= strlen (mips_str_mips16_call_stub
);
7780 if (pc
!= start_addr
7781 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7782 && mips_is_stub_mode (name
+ prefixlen
)
7783 && name
[prefixlen
+ 2] == '_'
7784 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7787 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7788 the JAL or JALR instruction, this is effectively a return stub. */
7789 prefixlen
= strlen (mips_str_call_fp_stub
);
7790 if (pc
!= start_addr
7791 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7794 /* Consume the .pic. prefix of any PIC stub, this function must return
7795 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7796 or the call stub path will trigger in handle_inferior_event causing
7798 prefixlen
= strlen (mips_str_pic
);
7799 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7802 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7803 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7804 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7805 && mips_is_stub_mode (name
+ prefixlen
)
7806 && name
[prefixlen
+ 2] == '\0')
7809 return 0; /* Not a stub. */
7812 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7813 PC of the stub target. The stub just loads $t9 and jumps to it,
7814 so that $t9 has the correct value at function entry. */
7817 mips_skip_pic_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7819 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7820 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7821 struct bound_minimal_symbol msym
;
7823 gdb_byte stub_code
[16];
7824 int32_t stub_words
[4];
7826 /* The stub for foo is named ".pic.foo", and is either two
7827 instructions inserted before foo or a three instruction sequence
7828 which jumps to foo. */
7829 msym
= lookup_minimal_symbol_by_pc (pc
);
7830 if (msym
.minsym
== NULL
7831 || msym
.value_address () != pc
7832 || msym
.minsym
->linkage_name () == NULL
7833 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7836 /* A two-instruction header. */
7837 if (msym
.minsym
->size () == 8)
7840 /* A three-instruction (plus delay slot) trampoline. */
7841 if (msym
.minsym
->size () == 16)
7843 if (target_read_memory (pc
, stub_code
, 16) != 0)
7845 for (i
= 0; i
< 4; i
++)
7846 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7849 /* A stub contains these instructions:
7852 addiu t9, t9, %lo(target)
7855 This works even for N64, since stubs are only generated with
7857 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7858 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7859 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7860 && stub_words
[3] == 0x00000000)
7861 return ((((stub_words
[0] & 0x0000ffff) << 16)
7862 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7865 /* Not a recognized stub. */
7870 mips_skip_trampoline_code (frame_info_ptr frame
, CORE_ADDR pc
)
7872 CORE_ADDR requested_pc
= pc
;
7873 CORE_ADDR target_pc
;
7880 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7884 new_pc
= find_solib_trampoline_target (frame
, pc
);
7888 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7892 while (pc
!= target_pc
);
7894 return pc
!= requested_pc
? pc
: 0;
7897 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7898 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7901 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7904 if (num
>= 0 && num
< 32)
7906 else if (num
>= 38 && num
< 70)
7907 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7909 regnum
= mips_regnum (gdbarch
)->hi
;
7911 regnum
= mips_regnum (gdbarch
)->lo
;
7912 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7913 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7916 return gdbarch_num_regs (gdbarch
) + regnum
;
7920 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7921 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7924 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7927 if (num
>= 0 && num
< 32)
7929 else if (num
>= 32 && num
< 64)
7930 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7932 regnum
= mips_regnum (gdbarch
)->hi
;
7934 regnum
= mips_regnum (gdbarch
)->lo
;
7935 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7936 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7939 return gdbarch_num_regs (gdbarch
) + regnum
;
7943 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7945 /* Only makes sense to supply raw registers. */
7946 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7947 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7948 decide if it is valid. Should instead define a standard sim/gdb
7949 register numbering scheme. */
7950 if (gdbarch_register_name (gdbarch
,
7951 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
7954 return LEGACY_SIM_REGNO_IGNORE
;
7958 /* Convert an integer into an address. Extracting the value signed
7959 guarantees a correctly sign extended address. */
7962 mips_integer_to_address (struct gdbarch
*gdbarch
,
7963 struct type
*type
, const gdb_byte
*buf
)
7965 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7966 return extract_signed_integer (buf
, type
->length (), byte_order
);
7969 /* Dummy virtual frame pointer method. This is no more or less accurate
7970 than most other architectures; we just need to be explicit about it,
7971 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7972 an assertion failure. */
7975 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7976 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7978 *reg
= MIPS_SP_REGNUM
;
7983 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7985 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7986 const char *name
= bfd_section_name (sect
);
7988 if (*abip
!= MIPS_ABI_UNKNOWN
)
7991 if (!startswith (name
, ".mdebug."))
7994 if (strcmp (name
, ".mdebug.abi32") == 0)
7995 *abip
= MIPS_ABI_O32
;
7996 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7997 *abip
= MIPS_ABI_N32
;
7998 else if (strcmp (name
, ".mdebug.abi64") == 0)
7999 *abip
= MIPS_ABI_N64
;
8000 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8001 *abip
= MIPS_ABI_O64
;
8002 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8003 *abip
= MIPS_ABI_EABI32
;
8004 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8005 *abip
= MIPS_ABI_EABI64
;
8007 warning (_("unsupported ABI %s."), name
+ 8);
8011 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8013 int *lbp
= (int *) obj
;
8014 const char *name
= bfd_section_name (sect
);
8016 if (startswith (name
, ".gcc_compiled_long32"))
8018 else if (startswith (name
, ".gcc_compiled_long64"))
8020 else if (startswith (name
, ".gcc_compiled_long"))
8021 warning (_("unrecognized .gcc_compiled_longXX"));
8024 static enum mips_abi
8025 global_mips_abi (void)
8029 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8030 if (mips_abi_strings
[i
] == mips_abi_string
)
8031 return (enum mips_abi
) i
;
8033 internal_error (_("unknown ABI string"));
8036 /* Return the default compressed instruction set, either of MIPS16
8037 or microMIPS, selected when none could have been determined from
8038 the ELF header of the binary being executed (or no binary has been
8041 static enum mips_isa
8042 global_mips_compression (void)
8046 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8047 if (mips_compression_strings
[i
] == mips_compression_string
)
8048 return (enum mips_isa
) i
;
8050 internal_error (_("unknown compressed ISA string"));
8054 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8056 /* If the size matches the set of 32-bit or 64-bit integer registers,
8057 assume that's what we've got. */
8058 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8059 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8061 /* If the size matches the full set of registers GDB traditionally
8062 knows about, including floating point, for either 32-bit or
8063 64-bit, assume that's what we've got. */
8064 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8065 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8067 /* Otherwise we don't have a useful guess. */
8070 static struct value
*
8071 value_of_mips_user_reg (frame_info_ptr frame
, const void *baton
)
8073 const int *reg_p
= (const int *) baton
;
8074 return value_of_register (*reg_p
, frame
);
8077 static struct gdbarch
*
8078 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8081 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8083 enum mips_fpu_type fpu_type
;
8084 tdesc_arch_data_up tdesc_data
;
8085 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8086 const char * const *reg_names
;
8087 struct mips_regnum mips_regnum
, *regnum
;
8088 enum mips_isa mips_isa
;
8092 /* First of all, extract the elf_flags, if available. */
8093 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8094 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8095 else if (arches
!= NULL
)
8097 mips_gdbarch_tdep
*tdep
8098 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8099 elf_flags
= tdep
->elf_flags
;
8104 gdb_printf (gdb_stdlog
,
8105 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8107 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8108 switch ((elf_flags
& EF_MIPS_ABI
))
8110 case E_MIPS_ABI_O32
:
8111 found_abi
= MIPS_ABI_O32
;
8113 case E_MIPS_ABI_O64
:
8114 found_abi
= MIPS_ABI_O64
;
8116 case E_MIPS_ABI_EABI32
:
8117 found_abi
= MIPS_ABI_EABI32
;
8119 case E_MIPS_ABI_EABI64
:
8120 found_abi
= MIPS_ABI_EABI64
;
8123 if ((elf_flags
& EF_MIPS_ABI2
))
8124 found_abi
= MIPS_ABI_N32
;
8126 found_abi
= MIPS_ABI_UNKNOWN
;
8130 /* GCC creates a pseudo-section whose name describes the ABI. */
8131 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8132 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8134 /* If we have no useful BFD information, use the ABI from the last
8135 MIPS architecture (if there is one). */
8136 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8138 mips_gdbarch_tdep
*tdep
8139 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8140 found_abi
= tdep
->found_abi
;
8143 /* Try the architecture for any hint of the correct ABI. */
8144 if (found_abi
== MIPS_ABI_UNKNOWN
8145 && info
.bfd_arch_info
!= NULL
8146 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8148 switch (info
.bfd_arch_info
->mach
)
8150 case bfd_mach_mips3900
:
8151 found_abi
= MIPS_ABI_EABI32
;
8153 case bfd_mach_mips4100
:
8154 case bfd_mach_mips5000
:
8155 found_abi
= MIPS_ABI_EABI64
;
8157 case bfd_mach_mips8000
:
8158 case bfd_mach_mips10000
:
8159 /* On Irix, ELF64 executables use the N64 ABI. The
8160 pseudo-sections which describe the ABI aren't present
8161 on IRIX. (Even for executables created by gcc.) */
8162 if (info
.abfd
!= NULL
8163 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8164 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8165 found_abi
= MIPS_ABI_N64
;
8167 found_abi
= MIPS_ABI_N32
;
8172 /* Default 64-bit objects to N64 instead of O32. */
8173 if (found_abi
== MIPS_ABI_UNKNOWN
8174 && info
.abfd
!= NULL
8175 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8176 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8177 found_abi
= MIPS_ABI_N64
;
8180 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8183 /* What has the user specified from the command line? */
8184 wanted_abi
= global_mips_abi ();
8186 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8189 /* Now that we have found what the ABI for this binary would be,
8190 check whether the user is overriding it. */
8191 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8192 mips_abi
= wanted_abi
;
8193 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8194 mips_abi
= found_abi
;
8196 mips_abi
= MIPS_ABI_O32
;
8198 gdb_printf (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8201 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8202 if (mips_abi
!= MIPS_ABI_EABI32
8203 && mips_abi
!= MIPS_ABI_O32
8204 && info
.bfd_arch_info
!= NULL
8205 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8206 && info
.bfd_arch_info
->bits_per_word
< 64)
8207 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8209 /* Determine the default compressed ISA. */
8210 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8211 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8212 mips_isa
= ISA_MICROMIPS
;
8213 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8214 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8215 mips_isa
= ISA_MIPS16
;
8217 mips_isa
= global_mips_compression ();
8218 mips_compression_string
= mips_compression_strings
[mips_isa
];
8220 /* Also used when doing an architecture lookup. */
8222 gdb_printf (gdb_stdlog
,
8223 "mips_gdbarch_init: "
8224 "mips64_transfers_32bit_regs_p = %d\n",
8225 mips64_transfers_32bit_regs_p
);
8227 /* Determine the MIPS FPU type. */
8230 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8231 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8232 Tag_GNU_MIPS_ABI_FP
);
8233 #endif /* HAVE_ELF */
8235 if (!mips_fpu_type_auto
)
8236 fpu_type
= mips_fpu_type
;
8237 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8239 switch (elf_fpu_type
)
8241 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8242 fpu_type
= MIPS_FPU_DOUBLE
;
8244 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8245 fpu_type
= MIPS_FPU_SINGLE
;
8247 case Val_GNU_MIPS_ABI_FP_SOFT
:
8249 /* Soft float or unknown. */
8250 fpu_type
= MIPS_FPU_NONE
;
8254 else if (info
.bfd_arch_info
!= NULL
8255 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8256 switch (info
.bfd_arch_info
->mach
)
8258 case bfd_mach_mips3900
:
8259 case bfd_mach_mips4100
:
8260 case bfd_mach_mips4111
:
8261 case bfd_mach_mips4120
:
8262 fpu_type
= MIPS_FPU_NONE
;
8264 case bfd_mach_mips4650
:
8265 fpu_type
= MIPS_FPU_SINGLE
;
8268 fpu_type
= MIPS_FPU_DOUBLE
;
8271 else if (arches
!= NULL
)
8272 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8274 fpu_type
= MIPS_FPU_DOUBLE
;
8276 gdb_printf (gdb_stdlog
,
8277 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8279 /* Check for blatant incompatibilities. */
8281 /* If we have only 32-bit registers, then we can't debug a 64-bit
8283 if (info
.target_desc
8284 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8285 && mips_abi
!= MIPS_ABI_EABI32
8286 && mips_abi
!= MIPS_ABI_O32
)
8289 /* Fill in the OS dependent register numbers and names. */
8290 if (info
.osabi
== GDB_OSABI_LINUX
)
8292 mips_regnum
.fp0
= 38;
8293 mips_regnum
.pc
= 37;
8294 mips_regnum
.cause
= 36;
8295 mips_regnum
.badvaddr
= 35;
8296 mips_regnum
.hi
= 34;
8297 mips_regnum
.lo
= 33;
8298 mips_regnum
.fp_control_status
= 70;
8299 mips_regnum
.fp_implementation_revision
= 71;
8300 mips_regnum
.dspacc
= -1;
8301 mips_regnum
.dspctl
= -1;
8305 reg_names
= mips_linux_reg_names
;
8309 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8310 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8311 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8312 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8313 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8314 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8315 mips_regnum
.fp_control_status
= 70;
8316 mips_regnum
.fp_implementation_revision
= 71;
8317 mips_regnum
.dspacc
= dspacc
= -1;
8318 mips_regnum
.dspctl
= dspctl
= -1;
8319 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8320 if (info
.bfd_arch_info
!= NULL
8321 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8322 reg_names
= mips_tx39_reg_names
;
8324 reg_names
= mips_generic_reg_names
;
8327 /* Check any target description for validity. */
8328 if (tdesc_has_registers (info
.target_desc
))
8330 static const char *const mips_gprs
[] = {
8331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8333 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8334 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8336 static const char *const mips_fprs
[] = {
8337 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8338 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8339 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8340 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8343 const struct tdesc_feature
*feature
;
8346 feature
= tdesc_find_feature (info
.target_desc
,
8347 "org.gnu.gdb.mips.cpu");
8348 if (feature
== NULL
)
8351 tdesc_data
= tdesc_data_alloc ();
8354 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8355 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8359 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8360 mips_regnum
.lo
, "lo");
8361 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8362 mips_regnum
.hi
, "hi");
8363 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8364 mips_regnum
.pc
, "pc");
8369 feature
= tdesc_find_feature (info
.target_desc
,
8370 "org.gnu.gdb.mips.cp0");
8371 if (feature
== NULL
)
8375 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8376 mips_regnum
.badvaddr
, "badvaddr");
8377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8378 MIPS_PS_REGNUM
, "status");
8379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8380 mips_regnum
.cause
, "cause");
8385 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8386 backend is not prepared for that, though. */
8387 feature
= tdesc_find_feature (info
.target_desc
,
8388 "org.gnu.gdb.mips.fpu");
8389 if (feature
== NULL
)
8393 for (i
= 0; i
< 32; i
++)
8394 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8395 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8397 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8398 mips_regnum
.fp_control_status
,
8401 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8402 mips_regnum
.fp_implementation_revision
,
8408 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8412 feature
= tdesc_find_feature (info
.target_desc
,
8413 "org.gnu.gdb.mips.dsp");
8414 /* The DSP registers are optional; it's OK if they are absent. */
8415 if (feature
!= NULL
)
8419 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8420 dspacc
+ i
++, "hi1");
8421 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8422 dspacc
+ i
++, "lo1");
8423 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8424 dspacc
+ i
++, "hi2");
8425 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8426 dspacc
+ i
++, "lo2");
8427 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8428 dspacc
+ i
++, "hi3");
8429 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8430 dspacc
+ i
++, "lo3");
8432 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8438 mips_regnum
.dspacc
= dspacc
;
8439 mips_regnum
.dspctl
= dspctl
;
8441 num_regs
= mips_regnum
.dspctl
+ 1;
8445 /* It would be nice to detect an attempt to use a 64-bit ABI
8446 when only 32-bit registers are provided. */
8450 /* Try to find a pre-existing architecture. */
8451 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8453 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8455 mips_gdbarch_tdep
*tdep
8456 = gdbarch_tdep
<mips_gdbarch_tdep
> (arches
->gdbarch
);
8458 /* MIPS needs to be pedantic about which ABI and the compressed
8459 ISA variation the object is using. */
8460 if (tdep
->elf_flags
!= elf_flags
)
8462 if (tdep
->mips_abi
!= mips_abi
)
8464 if (tdep
->mips_isa
!= mips_isa
)
8466 /* Need to be pedantic about which register virtual size is
8468 if (tdep
->mips64_transfers_32bit_regs_p
8469 != mips64_transfers_32bit_regs_p
)
8471 /* Be pedantic about which FPU is selected. */
8472 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8475 return arches
->gdbarch
;
8478 /* Need a new architecture. Fill in a target specific vector. */
8480 = gdbarch_alloc (&info
, gdbarch_tdep_up (new mips_gdbarch_tdep
));
8481 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8483 tdep
->elf_flags
= elf_flags
;
8484 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8485 tdep
->found_abi
= found_abi
;
8486 tdep
->mips_abi
= mips_abi
;
8487 tdep
->mips_isa
= mips_isa
;
8488 tdep
->mips_fpu_type
= fpu_type
;
8489 tdep
->register_size_valid_p
= 0;
8490 tdep
->register_size
= 0;
8492 if (info
.target_desc
)
8494 /* Some useful properties can be inferred from the target. */
8495 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8497 tdep
->register_size_valid_p
= 1;
8498 tdep
->register_size
= 4;
8500 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8502 tdep
->register_size_valid_p
= 1;
8503 tdep
->register_size
= 8;
8507 /* Initially set everything according to the default ABI/ISA. */
8508 set_gdbarch_short_bit (gdbarch
, 16);
8509 set_gdbarch_int_bit (gdbarch
, 32);
8510 set_gdbarch_float_bit (gdbarch
, 32);
8511 set_gdbarch_double_bit (gdbarch
, 64);
8512 set_gdbarch_long_double_bit (gdbarch
, 64);
8513 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8514 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8515 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8517 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8518 mips_ax_pseudo_register_collect
);
8519 set_gdbarch_ax_pseudo_register_push_stack
8520 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8522 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8523 mips_elf_make_msymbol_special
);
8524 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8525 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8526 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8528 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8529 *regnum
= mips_regnum
;
8530 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8531 set_gdbarch_num_regs (gdbarch
, num_regs
);
8532 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8533 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8534 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8535 tdep
->mips_processor_reg_names
= reg_names
;
8536 tdep
->regnum
= regnum
;
8541 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8542 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8543 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8544 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8545 tdep
->default_mask_address_p
= 0;
8546 set_gdbarch_long_bit (gdbarch
, 32);
8547 set_gdbarch_ptr_bit (gdbarch
, 32);
8548 set_gdbarch_long_long_bit (gdbarch
, 64);
8551 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8552 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8553 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8554 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8555 tdep
->default_mask_address_p
= 0;
8556 set_gdbarch_long_bit (gdbarch
, 32);
8557 set_gdbarch_ptr_bit (gdbarch
, 32);
8558 set_gdbarch_long_long_bit (gdbarch
, 64);
8560 case MIPS_ABI_EABI32
:
8561 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8562 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8563 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8564 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8565 tdep
->default_mask_address_p
= 0;
8566 set_gdbarch_long_bit (gdbarch
, 32);
8567 set_gdbarch_ptr_bit (gdbarch
, 32);
8568 set_gdbarch_long_long_bit (gdbarch
, 64);
8570 case MIPS_ABI_EABI64
:
8571 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8572 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8573 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8574 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8575 tdep
->default_mask_address_p
= 0;
8576 set_gdbarch_long_bit (gdbarch
, 64);
8577 set_gdbarch_ptr_bit (gdbarch
, 64);
8578 set_gdbarch_long_long_bit (gdbarch
, 64);
8581 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8582 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8583 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8584 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8585 tdep
->default_mask_address_p
= 0;
8586 set_gdbarch_long_bit (gdbarch
, 32);
8587 set_gdbarch_ptr_bit (gdbarch
, 32);
8588 set_gdbarch_long_long_bit (gdbarch
, 64);
8589 set_gdbarch_long_double_bit (gdbarch
, 128);
8590 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8593 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8594 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8595 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8596 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8597 tdep
->default_mask_address_p
= 0;
8598 set_gdbarch_long_bit (gdbarch
, 64);
8599 set_gdbarch_ptr_bit (gdbarch
, 64);
8600 set_gdbarch_long_long_bit (gdbarch
, 64);
8601 set_gdbarch_long_double_bit (gdbarch
, 128);
8602 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8605 internal_error (_("unknown ABI in switch"));
8608 /* GCC creates a pseudo-section whose name specifies the size of
8609 longs, since -mlong32 or -mlong64 may be used independent of
8610 other options. How those options affect pointer sizes is ABI and
8611 architecture dependent, so use them to override the default sizes
8612 set by the ABI. This table shows the relationship between ABI,
8613 -mlongXX, and size of pointers:
8615 ABI -mlongXX ptr bits
8616 --- -------- --------
8630 Note that for o32 and eabi32, pointers are always 32 bits
8631 regardless of any -mlongXX option. For all others, pointers and
8632 longs are the same, as set by -mlongXX or set by defaults. */
8634 if (info
.abfd
!= NULL
)
8638 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8641 set_gdbarch_long_bit (gdbarch
, long_bit
);
8645 case MIPS_ABI_EABI32
:
8650 case MIPS_ABI_EABI64
:
8651 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8654 internal_error (_("unknown ABI in switch"));
8659 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8660 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8663 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8664 flag in object files because to do so would make it impossible to
8665 link with libraries compiled without "-gp32". This is
8666 unnecessarily restrictive.
8668 We could solve this problem by adding "-gp32" multilibs to gcc,
8669 but to set this flag before gcc is built with such multilibs will
8670 break too many systems.''
8672 But even more unhelpfully, the default linker output target for
8673 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8674 for 64-bit programs - you need to change the ABI to change this,
8675 and not all gcc targets support that currently. Therefore using
8676 this flag to detect 32-bit mode would do the wrong thing given
8677 the current gcc - it would make GDB treat these 64-bit programs
8678 as 32-bit programs by default. */
8680 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8681 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8683 /* Add/remove bits from an address. The MIPS needs be careful to
8684 ensure that all 32 bit addresses are sign extended to 64 bits. */
8685 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8687 /* Unwind the frame. */
8688 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8689 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8690 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8692 /* Map debug register numbers onto internal register numbers. */
8693 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8694 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8695 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8696 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8697 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8698 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8700 /* MIPS version of CALL_DUMMY. */
8702 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8703 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8704 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8706 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8708 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8709 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8710 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8712 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8713 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8714 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8715 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8716 mips_adjust_breakpoint_address
);
8718 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8720 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8722 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8723 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8724 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8726 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8728 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8730 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8731 if (mips_abi
== MIPS_ABI_N64
)
8732 set_gdbarch_disassembler_options_implicit
8733 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8734 else if (mips_abi
== MIPS_ABI_N32
)
8735 set_gdbarch_disassembler_options_implicit
8736 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8738 set_gdbarch_disassembler_options_implicit
8739 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8740 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8741 set_gdbarch_valid_disassembler_options (gdbarch
,
8742 disassembler_options_mips ());
8744 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8745 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8746 need to all be folded into the target vector. Since they are
8747 being used as guards for target_stopped_by_watchpoint, why not have
8748 target_stopped_by_watchpoint return the type of watchpoint that the code
8750 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8752 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8754 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8755 to support MIPS16. This is a bad thing. Make sure not to do it
8756 if we have an OS ABI that actually supports shared libraries, since
8757 shared library support is more important. If we have an OS someday
8758 that supports both shared libraries and MIPS16, we'll have to find
8759 a better place for these.
8760 macro/2012-04-25: But that applies to return trampolines only and
8761 currently no MIPS OS ABI uses shared libraries that have them. */
8762 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8764 set_gdbarch_single_step_through_delay (gdbarch
,
8765 mips_single_step_through_delay
);
8767 /* Virtual tables. */
8768 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8770 mips_register_g_packet_guesses (gdbarch
);
8772 /* Hook in OS ABI-specific overrides, if they have been registered. */
8773 info
.tdesc_data
= tdesc_data
.get ();
8774 gdbarch_init_osabi (info
, gdbarch
);
8776 /* The hook may have adjusted num_regs, fetch the final value and
8777 set pc_regnum and sp_regnum now that it has been fixed. */
8778 num_regs
= gdbarch_num_regs (gdbarch
);
8779 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8780 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8782 /* Unwind the frame. */
8783 dwarf2_append_unwinders (gdbarch
);
8784 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8785 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8786 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8787 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8788 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8789 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8790 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8791 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8792 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8794 if (tdesc_data
!= nullptr)
8796 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8797 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8799 /* Override the normal target description methods to handle our
8800 dual real and pseudo registers. */
8801 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8802 set_gdbarch_register_reggroup_p (gdbarch
,
8803 mips_tdesc_register_reggroup_p
);
8805 num_regs
= gdbarch_num_regs (gdbarch
);
8806 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8807 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8808 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8811 /* Add ABI-specific aliases for the registers. */
8812 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8813 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8814 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8815 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8817 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8818 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8819 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8821 /* Add some other standard aliases. */
8822 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8823 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8824 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8826 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8827 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8828 value_of_mips_user_reg
,
8829 &mips_numeric_register_aliases
[i
].regnum
);
8835 mips_abi_update (const char *ignore_args
,
8836 int from_tty
, struct cmd_list_element
*c
)
8838 struct gdbarch_info info
;
8840 /* Force the architecture to update, and (if it's a MIPS architecture)
8841 mips_gdbarch_init will take care of the rest. */
8842 gdbarch_update_p (info
);
8845 /* Print out which MIPS ABI is in use. */
8848 show_mips_abi (struct ui_file
*file
,
8850 struct cmd_list_element
*ignored_cmd
,
8851 const char *ignored_value
)
8853 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8856 "The MIPS ABI is unknown because the current architecture "
8860 enum mips_abi global_abi
= global_mips_abi ();
8861 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8862 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8864 if (global_abi
== MIPS_ABI_UNKNOWN
)
8867 "The MIPS ABI is set automatically (currently \"%s\").\n",
8869 else if (global_abi
== actual_abi
)
8872 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8876 /* Probably shouldn't happen... */
8878 "The (auto detected) MIPS ABI \"%s\" is in use "
8879 "even though the user setting was \"%s\".\n",
8880 actual_abi_str
, mips_abi_strings
[global_abi
]);
8885 /* Print out which MIPS compressed ISA encoding is used. */
8888 show_mips_compression (struct ui_file
*file
, int from_tty
,
8889 struct cmd_list_element
*c
, const char *value
)
8891 gdb_printf (file
, _("The compressed ISA encoding used is %s.\n"),
8895 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8898 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8904 case MIPS_FPU_SINGLE
:
8906 case MIPS_FPU_DOUBLE
:
8914 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8916 mips_gdbarch_tdep
*tdep
= gdbarch_tdep
<mips_gdbarch_tdep
> (gdbarch
);
8920 int ef_mips_32bitmode
;
8921 /* Determine the ISA. */
8922 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8940 /* Determine the size of a pointer. */
8941 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8943 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8946 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8949 "mips_dump_tdep: ef_mips_arch = %d\n",
8952 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8953 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8956 "mips_mask_address_p() %d (default %d)\n",
8957 mips_mask_address_p (tdep
),
8958 tdep
->default_mask_address_p
);
8961 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8962 MIPS_DEFAULT_FPU_TYPE
,
8963 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8964 gdb_printf (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8965 mips_eabi (gdbarch
));
8967 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8968 mips_get_fpu_type (gdbarch
),
8969 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8972 void _initialize_mips_tdep ();
8974 _initialize_mips_tdep ()
8976 static struct cmd_list_element
*mipsfpulist
= NULL
;
8978 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8979 if (MIPS_ABI_LAST
+ 1
8980 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8981 internal_error (_("mips_abi_strings out of sync"));
8983 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8985 /* Create feature sets with the appropriate properties. The values
8986 are not important. */
8987 mips_tdesc_gp32
= allocate_target_description ().release ();
8988 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8990 mips_tdesc_gp64
= allocate_target_description ().release ();
8991 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8993 /* Add root prefix command for all "set mips"/"show mips" commands. */
8994 add_setshow_prefix_cmd ("mips", no_class
,
8995 _("Various MIPS specific commands."),
8996 _("Various MIPS specific commands."),
8997 &setmipscmdlist
, &showmipscmdlist
,
8998 &setlist
, &showlist
);
9000 /* Allow the user to override the ABI. */
9001 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9002 &mips_abi_string
, _("\
9003 Set the MIPS ABI used by this program."), _("\
9004 Show the MIPS ABI used by this program."), _("\
9005 This option can be set to one of:\n\
9006 auto - the default ABI associated with the current binary\n\
9015 &setmipscmdlist
, &showmipscmdlist
);
9017 /* Allow the user to set the ISA to assume for compressed code if ELF
9018 file flags don't tell or there is no program file selected. This
9019 setting is updated whenever unambiguous ELF file flags are interpreted,
9020 and carried over to subsequent sessions. */
9021 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9022 &mips_compression_string
, _("\
9023 Set the compressed ISA encoding used by MIPS code."), _("\
9024 Show the compressed ISA encoding used by MIPS code."), _("\
9025 Select the compressed ISA encoding used in functions that have no symbol\n\
9026 information available. The encoding can be set to either of:\n\
9029 and is updated automatically from ELF file flags if available."),
9031 show_mips_compression
,
9032 &setmipscmdlist
, &showmipscmdlist
);
9034 /* Let the user turn off floating point and set the fence post for
9035 heuristic_proc_start. */
9037 add_basic_prefix_cmd ("mipsfpu", class_support
,
9038 _("Set use of MIPS floating-point coprocessor."),
9039 &mipsfpulist
, 0, &setlist
);
9040 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9041 _("Select single-precision MIPS floating-point coprocessor."),
9043 cmd_list_element
*set_mipsfpu_double_cmd
9044 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9045 _("Select double-precision MIPS floating-point coprocessor."),
9047 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9048 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9049 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9051 cmd_list_element
*set_mipsfpu_none_cmd
9052 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9053 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9054 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9055 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9056 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9057 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9058 _("Select MIPS floating-point coprocessor automatically."),
9060 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9061 _("Show current use of MIPS floating-point coprocessor target."),
9064 /* We really would like to have both "0" and "unlimited" work, but
9065 command.c doesn't deal with that. So make it a var_zinteger
9066 because the user can always use "999999" or some such for unlimited. */
9067 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9068 &heuristic_fence_post
, _("\
9069 Set the distance searched for the start of a function."), _("\
9070 Show the distance searched for the start of a function."), _("\
9071 If you are debugging a stripped executable, GDB needs to search through the\n\
9072 program for the start of a function. This command sets the distance of the\n\
9073 search. The only need to set it is when debugging a stripped executable."),
9074 reinit_frame_cache_sfunc
,
9075 NULL
, /* FIXME: i18n: The distance searched for
9076 the start of a function is %s. */
9077 &setlist
, &showlist
);
9079 /* Allow the user to control whether the upper bits of 64-bit
9080 addresses should be zeroed. */
9081 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9082 &mask_address_var
, _("\
9083 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9084 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9085 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9086 allow GDB to determine the correct value."),
9087 NULL
, show_mask_address
,
9088 &setmipscmdlist
, &showmipscmdlist
);
9090 /* Allow the user to control the size of 32 bit registers within the
9091 raw remote packet. */
9092 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9093 &mips64_transfers_32bit_regs_p
, _("\
9094 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9096 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9098 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9099 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9100 64 bits for others. Use \"off\" to disable compatibility mode"),
9101 set_mips64_transfers_32bit_regs
,
9102 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9103 MIPS target that transfers 32-bit
9104 quantities is %s. */
9105 &setlist
, &showlist
);
9107 /* Debug this files internals. */
9108 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9110 Set mips debugging."), _("\
9111 Show mips debugging."), _("\
9112 When non-zero, mips specific debugging is enabled."),
9114 NULL
, /* FIXME: i18n: Mips debugging is
9116 &setdebuglist
, &showdebuglist
);