1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
44 /* FIXME! this code assumes 4-byte instructions. */
45 #define MIPS_INSTLEN 4 /* Length of an instruction */
46 #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16*/
47 #define MIPS_NUMREGS 32 /* Number of integer or float registers */
48 typedef unsigned long t_inst
; /* Integer big enough to hold an instruction */
51 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
54 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
56 static void mips_print_register
PARAMS ((int, int));
58 static mips_extra_func_info_t
59 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
61 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
63 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
65 static void mips_set_fpu_command
PARAMS ((char *, int,
66 struct cmd_list_element
*));
68 static void mips_show_fpu_command
PARAMS ((char *, int,
69 struct cmd_list_element
*));
71 void mips_set_processor_type_command
PARAMS ((char *, int));
73 int mips_set_processor_type
PARAMS ((char *));
75 static void mips_show_processor_type_command
PARAMS ((char *, int));
77 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
78 struct cmd_list_element
*));
80 static mips_extra_func_info_t
81 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
83 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
84 mips_extra_func_info_t proc_desc
));
86 /* This value is the model of MIPS in use. It is derived from the value
87 of the PrID register. */
89 char *mips_processor_type
;
91 char *tmp_mips_processor_type
;
93 /* Some MIPS boards don't support floating point, so we permit the
94 user to turn it off. */
96 enum mips_fpu_type mips_fpu
;
98 static char *mips_fpu_string
;
100 /* A set of original names, to be used when restoring back to generic
101 registers from a specific set. */
103 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
105 /* Names of IDT R3041 registers. */
107 char *mips_r3041_reg_names
[] = {
108 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
109 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
110 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
111 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
112 "sr", "lo", "hi", "bad", "cause","pc",
113 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
114 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
115 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
116 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
117 "fsr", "fir", "fp", "",
118 "", "", "bus", "ccfg", "", "", "", "",
119 "", "", "port", "cmp", "", "", "epc", "prid",
122 /* Names of IDT R3051 registers. */
124 char *mips_r3051_reg_names
[] = {
125 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
126 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
127 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
128 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
129 "sr", "lo", "hi", "bad", "cause","pc",
130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
134 "fsr", "fir", "fp", "",
135 "inx", "rand", "elo", "", "ctxt", "", "", "",
136 "", "", "ehi", "", "", "", "epc", "prid",
139 /* Names of IDT R3081 registers. */
141 char *mips_r3081_reg_names
[] = {
142 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
143 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
144 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
145 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
146 "sr", "lo", "hi", "bad", "cause","pc",
147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
151 "fsr", "fir", "fp", "",
152 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
153 "", "", "ehi", "", "", "", "epc", "prid",
156 /* Names of LSI 33k registers. */
158 char *mips_lsi33k_reg_names
[] = {
159 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
160 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
162 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
163 "epc", "hi", "lo", "sr", "cause","badvaddr",
164 "dcic", "bpc", "bda", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
176 } mips_processor_type_table
[] = {
177 { "generic", mips_generic_reg_names
},
178 { "r3041", mips_r3041_reg_names
},
179 { "r3051", mips_r3051_reg_names
},
180 { "r3071", mips_r3081_reg_names
},
181 { "r3081", mips_r3081_reg_names
},
182 { "lsi33k", mips_lsi33k_reg_names
},
186 /* Table to translate MIPS16 register field to actual register number. */
187 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
189 /* Heuristic_proc_start may hunt through the text section for a long
190 time across a 2400 baud serial line. Allows the user to limit this
193 static unsigned int heuristic_fence_post
= 0;
195 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
196 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
197 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
198 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
199 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
200 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
201 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
202 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
203 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
204 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
205 #define _PROC_MAGIC_ 0x0F0F0F0F
206 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
207 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
209 struct linked_proc_info
211 struct mips_extra_func_info info
;
212 struct linked_proc_info
*next
;
213 } *linked_proc_desc_table
= NULL
;
216 /* This returns the PC of the first inst after the prologue. If we can't
217 find the prologue, then return 0. */
220 after_prologue (pc
, proc_desc
)
222 mips_extra_func_info_t proc_desc
;
224 struct symtab_and_line sal
;
225 CORE_ADDR func_addr
, func_end
;
228 proc_desc
= find_proc_desc (pc
, NULL
);
232 /* If function is frameless, then we need to do it the hard way. I
233 strongly suspect that frameless always means prologueless... */
234 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
235 && PROC_FRAME_OFFSET (proc_desc
) == 0)
239 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
240 return 0; /* Unknown */
242 sal
= find_pc_line (func_addr
, 0);
244 if (sal
.end
< func_end
)
247 /* The line after the prologue is after the end of the function. In this
248 case, tell the caller to find the prologue the hard way. */
253 /* Decode a MIPS32 instruction that saves a register in the stack, and
254 set the appropriate bit in the general register mask or float register mask
255 to indicate which register is saved. This is a helper function
256 for mips_find_saved_regs. */
259 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
261 unsigned long *gen_mask
;
262 unsigned long *float_mask
;
266 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
267 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
268 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
270 /* It might be possible to use the instruction to
271 find the offset, rather than the code below which
272 is based on things being in a certain order in the
273 frame, but figuring out what the instruction's offset
274 is relative to might be a little tricky. */
275 reg
= (inst
& 0x001f0000) >> 16;
276 *gen_mask
|= (1 << reg
);
278 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
279 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
280 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
283 reg
= ((inst
& 0x001f0000) >> 16);
284 *float_mask
|= (1 << reg
);
288 /* Decode a MIPS16 instruction that saves a register in the stack, and
289 set the appropriate bit in the general register or float register mask
290 to indicate which register is saved. This is a helper function
291 for mips_find_saved_regs. */
294 mips16_decode_reg_save (inst
, gen_mask
)
296 unsigned long *gen_mask
;
298 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
300 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
301 *gen_mask
|= (1 << reg
);
303 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
305 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
306 *gen_mask
|= (1 << reg
);
308 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
309 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
310 *gen_mask
|= (1 << 31);
313 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
317 mips_find_saved_regs (fci
)
318 struct frame_info
*fci
;
321 CORE_ADDR reg_position
;
322 /* r0 bit means kernel trap */
324 /* What registers have been saved? Bitmasks. */
325 unsigned long gen_mask
, float_mask
;
326 mips_extra_func_info_t proc_desc
;
328 fci
->saved_regs
= (struct frame_saved_regs
*)
329 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
330 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
332 /* If it is the frame for sigtramp, the saved registers are located
333 in a sigcontext structure somewhere on the stack.
334 If the stack layout for sigtramp changes we might have to change these
335 constants and the companion fixup_sigtramp in mdebugread.c */
336 #ifndef SIGFRAME_BASE
337 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
338 above the sigtramp frame. */
339 #define SIGFRAME_BASE MIPS_REGSIZE
340 /* FIXME! Are these correct?? */
341 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
342 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
343 #define SIGFRAME_FPREGSAVE_OFF \
344 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
346 #ifndef SIGFRAME_REG_SIZE
347 /* FIXME! Is this correct?? */
348 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
350 if (fci
->signal_handler_caller
)
352 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
354 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
355 + ireg
* SIGFRAME_REG_SIZE
;
356 fci
->saved_regs
->regs
[ireg
] = reg_position
;
358 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
360 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
361 + ireg
* SIGFRAME_REG_SIZE
;
362 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
364 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
368 proc_desc
= fci
->proc_desc
;
369 if (proc_desc
== NULL
)
370 /* I'm not sure how/whether this can happen. Normally when we can't
371 find a proc_desc, we "synthesize" one using heuristic_proc_desc
372 and set the saved_regs right away. */
375 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
376 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
377 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
379 if (/* In any frame other than the innermost or a frame interrupted by
380 a signal, we assume that all registers have been saved.
381 This assumes that all register saves in a function happen before
382 the first function call. */
383 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
385 /* In a dummy frame we know exactly where things are saved. */
386 && !PROC_DESC_IS_DUMMY (proc_desc
)
388 /* Don't bother unless we are inside a function prologue. Outside the
389 prologue, we know where everything is. */
391 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
393 /* Not sure exactly what kernel_trap means, but if it means
394 the kernel saves the registers without a prologue doing it,
395 we better not examine the prologue to see whether registers
396 have been saved yet. */
399 /* We need to figure out whether the registers that the proc_desc
400 claims are saved have been saved yet. */
404 char buf
[MIPS_INSTLEN
];
408 /* Bitmasks; set if we have found a save for the register. */
409 unsigned long gen_save_found
= 0;
410 unsigned long float_save_found
= 0;
412 if ((addr
= PROC_LOW_ADDR (proc_desc
)) & 1)
414 instlen
= MIPS16_INSTLEN
; /* MIPS16 */
418 instlen
= MIPS_INSTLEN
; /* MIPS32 */
420 /* Scan through this function's instructions preceding the current
421 PC, and look for those that save registers. */
422 while (addr
< fci
->pc
)
424 status
= read_memory_nobpt (addr
, buf
, instlen
);
426 memory_error (status
, addr
);
427 inst
= extract_unsigned_integer (buf
, instlen
);
428 if (instlen
== MIPS16_INSTLEN
)
429 mips16_decode_reg_save (inst
, &gen_save_found
);
431 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
434 gen_mask
= gen_save_found
;
435 float_mask
= float_save_found
;
438 /* Fill in the offsets for the registers which gen_mask says
440 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
441 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
442 if (gen_mask
& 0x80000000)
444 fci
->saved_regs
->regs
[ireg
] = reg_position
;
445 reg_position
-= MIPS_REGSIZE
;
447 /* Fill in the offsets for the registers which float_mask says
449 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
451 /* The freg_offset points to where the first *double* register
452 is saved. So skip to the high-order word. */
453 if (! GDB_TARGET_IS_MIPS64
)
456 /* Fill in the offsets for the float registers which float_mask says
458 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
459 if (float_mask
& 0x80000000)
461 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
462 reg_position
-= MIPS_REGSIZE
;
465 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
469 read_next_frame_reg(fi
, regno
)
470 struct frame_info
*fi
;
473 for (; fi
; fi
= fi
->next
)
475 /* We have to get the saved sp from the sigcontext
476 if it is a signal handler frame. */
477 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
481 if (fi
->saved_regs
== NULL
)
482 mips_find_saved_regs (fi
);
483 if (fi
->saved_regs
->regs
[regno
])
484 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
487 return read_register (regno
);
490 /* mips_addr_bits_remove - remove useless address bits */
493 mips_addr_bits_remove (addr
)
496 #if GDB_TARGET_IS_MIPS64
497 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
498 && (strcmp(target_shortname
,"pmon")==0
499 || strcmp(target_shortname
,"ddb")==0
500 || strcmp(target_shortname
,"sim")==0))
502 /* This hack is a work-around for existing boards using PMON,
503 the simulator, and any other 64-bit targets that doesn't have
504 true 64-bit addressing. On these targets, the upper 32 bits
505 of addresses are ignored by the hardware. Thus, the PC or SP
506 are likely to have been sign extended to all 1s by instruction
507 sequences that load 32-bit addresses. For example, a typical
508 piece of code that loads an address is this:
509 lui $r2, <upper 16 bits>
510 ori $r2, <lower 16 bits>
511 But the lui sign-extends the value such that the upper 32 bits
512 may be all 1s. The workaround is simply to mask off these bits.
513 In the future, gcc may be changed to support true 64-bit
514 addressing, and this masking will have to be disabled. */
515 addr
&= (CORE_ADDR
)0xffffffff;
518 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
519 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
520 So we still have to mask off useless bits from addresses. */
521 addr
&= (CORE_ADDR
)0xffffffff;
528 mips_frame_saved_pc(frame
)
529 struct frame_info
*frame
;
532 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
533 /* We have to get the saved pc from the sigcontext
534 if it is a signal handler frame. */
535 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
536 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
538 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
539 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
541 saved_pc
= read_next_frame_reg(frame
, pcreg
);
543 return ADDR_BITS_REMOVE (saved_pc
);
546 static struct mips_extra_func_info temp_proc_desc
;
547 static struct frame_saved_regs temp_saved_regs
;
549 /* This fencepost looks highly suspicious to me. Removing it also
550 seems suspicious as it could affect remote debugging across serial
554 heuristic_proc_start(pc
)
557 CORE_ADDR start_pc
= pc
;
558 CORE_ADDR fence
= start_pc
- heuristic_fence_post
;
562 if (start_pc
== 0) return 0;
564 if (heuristic_fence_post
== UINT_MAX
565 || fence
< VM_MIN_ADDRESS
)
566 fence
= VM_MIN_ADDRESS
;
568 instlen
= pc
& 1 ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
570 /* search back for previous return */
571 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
572 if (start_pc
< fence
)
574 /* It's not clear to me why we reach this point when
575 stop_soon_quietly, but with this test, at least we
576 don't print out warnings for every child forked (eg, on
577 decstation). 22apr93 rich@cygnus.com. */
578 if (!stop_soon_quietly
)
580 static int blurb_printed
= 0;
582 if (fence
== VM_MIN_ADDRESS
)
583 warning("Hit beginning of text section without finding");
585 warning("Hit heuristic-fence-post without finding");
587 warning("enclosing function for address 0x%s", paddr (pc
));
591 This warning occurs if you are debugging a function without any symbols\n\
592 (for example, in a stripped executable). In that case, you may wish to\n\
593 increase the size of the search with the `set heuristic-fence-post' command.\n\
595 Otherwise, you told GDB there was a function where there isn't one, or\n\
596 (more likely) you have encountered a bug in GDB.\n");
603 else if (start_pc
& 1)
605 /* On MIPS16, any one of the following is likely to be the
610 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
611 unsigned short inst
= read_memory_integer (start_pc
& ~1, 2);
612 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
613 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
614 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
615 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
617 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
618 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
623 else if (ABOUT_TO_RETURN(start_pc
))
625 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
630 /* skip nops (usually 1) 0 - is this */
631 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
632 start_pc
+= MIPS_INSTLEN
;
637 /* Fetch the immediate value from the current instruction.
638 If the previous instruction was an EXTEND, use it to extend
639 the upper bits of the immediate value. This is a helper function
640 for mips16_heuristic_proc_desc. */
643 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
644 unsigned short prev_inst
; /* previous instruction */
645 unsigned short inst
; /* current current instruction */
646 int nbits
; /* number of bits in imm field */
647 int scale
; /* scale factor to be applied to imm */
648 int is_signed
; /* is the imm field signed? */
652 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
654 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
655 if (offset
& 0x8000) /* check for negative extend */
656 offset
= 0 - (0x10000 - (offset
& 0xffff));
657 return offset
| (inst
& 0x1f);
661 int max_imm
= 1 << nbits
;
662 int mask
= max_imm
- 1;
663 int sign_bit
= max_imm
>> 1;
665 offset
= inst
& mask
;
666 if (is_signed
&& (offset
& sign_bit
))
667 offset
= 0 - (max_imm
- offset
);
668 return offset
* scale
;
673 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
674 stream from start_pc to limit_pc. */
677 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
678 CORE_ADDR start_pc
, limit_pc
;
679 struct frame_info
*next_frame
;
683 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
684 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
685 unsigned inst
= 0; /* current instruction */
687 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
689 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
691 char buf
[MIPS16_INSTLEN
];
692 int status
, reg
, offset
;
694 /* Save the previous instruction. If it's an EXTEND, we'll extract
695 the immediate offset extension from it in mips16_get_imm. */
698 /* Fetch the instruction. */
699 status
= read_memory_nobpt (cur_pc
& ~1, buf
, MIPS16_INSTLEN
);
700 if (status
) memory_error (status
, cur_pc
);
701 inst
= (unsigned short) extract_unsigned_integer (buf
, MIPS16_INSTLEN
);
703 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
704 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
706 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
707 if (offset
< 0) /* negative stack adjustment? */
708 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
710 /* Exit loop if a positive stack adjustment is found, which
711 usually means that the stack cleanup code in the function
712 epilogue is reached. */
715 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
717 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
718 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
719 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
720 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
722 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
724 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
725 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
726 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
727 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
729 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
731 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
732 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
733 temp_saved_regs
.regs
[31] = sp
+ offset
;
735 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
737 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
738 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
739 temp_saved_regs
.regs
[31] = sp
+ offset
;
741 else if (inst
== 0x673d) /* move $s1, $sp */
743 frame_addr
= read_next_frame_reg(next_frame
, 30);
744 PROC_FRAME_REG (&temp_proc_desc
) = 17;
746 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
748 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
749 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
750 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
751 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
753 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
755 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
756 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
757 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
758 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
760 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
762 int areg_count
= (inst
>> 8) & 7;
763 int sreg_count
= (inst
>> 6) & 3;
765 /* The entry instruction always subtracts 32 from the SP. */
766 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
768 /* Check if a0-a3 were saved in the caller's argument save area. */
769 for (reg
= 4, offset
= 32; reg
< areg_count
+4; reg
++, offset
+= 4)
771 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
772 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
775 /* Check if the ra register was pushed on the stack. */
779 PROC_REG_MASK(&temp_proc_desc
) |= 1 << 31;
780 temp_saved_regs
.regs
[31] = sp
+ offset
;
784 /* Check if the s0 and s1 registers were pushed on the stack. */
785 for (reg
= 16; reg
< sreg_count
+16; reg
++, offset
-= 4)
787 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
788 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
791 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
792 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
797 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
798 CORE_ADDR start_pc
, limit_pc
;
799 struct frame_info
*next_frame
;
803 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
805 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
806 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
808 char buf
[MIPS_INSTLEN
];
809 unsigned long inst
, high_word
, low_word
;
812 /* Fetch the instruction. */
813 status
= (unsigned long) read_memory_nobpt (cur_pc
, buf
, MIPS_INSTLEN
);
814 if (status
) memory_error (status
, cur_pc
);
815 inst
= (unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
);
817 /* Save some code by pre-extracting some useful fields. */
818 high_word
= (inst
>> 16) & 0xffff;
819 low_word
= inst
& 0xffff;
820 reg
= high_word
& 0x1f;
822 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
823 || high_word
== 0x23bd /* addi $sp,$sp,-i */
824 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
826 if (low_word
& 0x8000) /* negative stack adjustment? */
827 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
829 /* Exit loop if a positive stack adjustment is found, which
830 usually means that the stack cleanup code in the function
831 epilogue is reached. */
834 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
836 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
837 temp_saved_regs
.regs
[reg
] = sp
+ low_word
;
839 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
841 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
842 but the register size used is only 32 bits. Make the address
843 for the saved register point to the lower 32 bits. */
844 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
845 temp_saved_regs
.regs
[reg
] = sp
+ low_word
+ 8 - MIPS_REGSIZE
;
847 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
849 /* Old gcc frame, r30 is virtual frame pointer. */
850 if (low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
851 frame_addr
= sp
+ low_word
;
852 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
854 unsigned alloca_adjust
;
855 PROC_FRAME_REG (&temp_proc_desc
) = 30;
856 frame_addr
= read_next_frame_reg(next_frame
, 30);
857 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
858 if (alloca_adjust
> 0)
860 /* FP > SP + frame_size. This may be because
861 * of an alloca or somethings similar.
862 * Fix sp to "pre-alloca" value, and try again.
869 /* move $30,$sp. With different versions of gas this will be either
870 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
871 Accept any one of these. */
872 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
874 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
875 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
877 unsigned alloca_adjust
;
878 PROC_FRAME_REG (&temp_proc_desc
) = 30;
879 frame_addr
= read_next_frame_reg(next_frame
, 30);
880 alloca_adjust
= (unsigned)(frame_addr
- sp
);
881 if (alloca_adjust
> 0)
883 /* FP > SP + frame_size. This may be because
884 * of an alloca or somethings similar.
885 * Fix sp to "pre-alloca" value, and try again.
892 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
894 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
895 temp_saved_regs
.regs
[reg
] = frame_addr
+ low_word
;
900 static mips_extra_func_info_t
901 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
902 CORE_ADDR start_pc
, limit_pc
;
903 struct frame_info
*next_frame
;
905 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
907 if (start_pc
== 0) return NULL
;
908 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
909 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
910 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
911 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
912 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
914 if (start_pc
+ 200 < limit_pc
)
915 limit_pc
= start_pc
+ 200;
917 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
919 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
920 return &temp_proc_desc
;
923 static mips_extra_func_info_t
924 find_proc_desc (pc
, next_frame
)
926 struct frame_info
*next_frame
;
928 mips_extra_func_info_t proc_desc
;
929 struct block
*b
= block_for_pc(pc
);
933 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
934 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
938 if (startaddr
> BLOCK_START (b
))
939 /* This is the "pathological" case referred to in a comment in
940 print_frame_info. It might be better to move this check into
944 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
,
948 /* If we never found a PDR for this function in symbol reading, then
949 examine prologues to find the information. */
950 if (sym
&& ((mips_extra_func_info_t
) SYMBOL_VALUE (sym
))->pdr
.framereg
== -1)
955 /* IF this is the topmost frame AND
956 * (this proc does not have debugging information OR
957 * the PC is in the procedure prologue)
958 * THEN create a "heuristic" proc_desc (by analyzing
959 * the actual code) to replace the "official" proc_desc.
961 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
962 if (next_frame
== NULL
) {
963 struct symtab_and_line val
;
964 struct symbol
*proc_symbol
=
965 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
968 val
= find_pc_line (BLOCK_START
969 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
971 val
.pc
= val
.end
? val
.end
: pc
;
973 if (!proc_symbol
|| pc
< val
.pc
) {
974 mips_extra_func_info_t found_heuristic
=
975 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
978 proc_desc
= found_heuristic
;
984 /* Is linked_proc_desc_table really necessary? It only seems to be used
985 by procedure call dummys. However, the procedures being called ought
986 to have their own proc_descs, and even if they don't,
987 heuristic_proc_desc knows how to create them! */
989 register struct linked_proc_info
*link
;
991 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
992 if (PROC_LOW_ADDR(&link
->info
) <= pc
993 && PROC_HIGH_ADDR(&link
->info
) > pc
)
997 startaddr
= heuristic_proc_start (pc
);
1000 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1006 get_frame_pointer(frame
, proc_desc
)
1007 struct frame_info
*frame
;
1008 mips_extra_func_info_t proc_desc
;
1010 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
1011 PROC_FRAME_REG(proc_desc
)) + PROC_FRAME_OFFSET(proc_desc
));
1014 mips_extra_func_info_t cached_proc_desc
;
1017 mips_frame_chain(frame
)
1018 struct frame_info
*frame
;
1020 mips_extra_func_info_t proc_desc
;
1021 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1023 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1026 proc_desc
= find_proc_desc(saved_pc
, frame
);
1030 cached_proc_desc
= proc_desc
;
1032 /* If no frame pointer and frame size is zero, we must be at end
1033 of stack (or otherwise hosed). If we don't check frame size,
1034 we loop forever if we see a zero size frame. */
1035 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1036 && PROC_FRAME_OFFSET (proc_desc
) == 0
1037 /* The previous frame from a sigtramp frame might be frameless
1038 and have frame size zero. */
1039 && !frame
->signal_handler_caller
)
1042 return get_frame_pointer (frame
, proc_desc
);
1046 init_extra_frame_info(fci
)
1047 struct frame_info
*fci
;
1051 /* Use proc_desc calculated in frame_chain */
1052 mips_extra_func_info_t proc_desc
=
1053 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1055 fci
->saved_regs
= NULL
;
1057 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1060 /* Fixup frame-pointer - only needed for top frame */
1061 /* This may not be quite right, if proc has a real frame register.
1062 Get the value of the frame relative sp, procedure might have been
1063 interrupted by a signal at it's very start. */
1064 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1065 && !PROC_DESC_IS_DUMMY (proc_desc
))
1066 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1068 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1070 if (proc_desc
== &temp_proc_desc
)
1074 /* Do not set the saved registers for a sigtramp frame,
1075 mips_find_saved_registers will do that for us.
1076 We can't use fci->signal_handler_caller, it is not yet set. */
1077 find_pc_partial_function (fci
->pc
, &name
,
1078 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1079 if (!IN_SIGTRAMP (fci
->pc
, name
))
1081 fci
->saved_regs
= (struct frame_saved_regs
*)
1082 obstack_alloc (&frame_cache_obstack
,
1083 sizeof (struct frame_saved_regs
));
1084 *fci
->saved_regs
= temp_saved_regs
;
1085 fci
->saved_regs
->regs
[PC_REGNUM
]
1086 = fci
->saved_regs
->regs
[RA_REGNUM
];
1090 /* hack: if argument regs are saved, guess these contain args */
1091 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1092 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1094 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1096 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1103 /* MIPS stack frames are almost impenetrable. When execution stops,
1104 we basically have to look at symbol information for the function
1105 that we stopped in, which tells us *which* register (if any) is
1106 the base of the frame pointer, and what offset from that register
1107 the frame itself is at.
1109 This presents a problem when trying to examine a stack in memory
1110 (that isn't executing at the moment), using the "frame" command. We
1111 don't have a PC, nor do we have any registers except SP.
1113 This routine takes two arguments, SP and PC, and tries to make the
1114 cached frames look as if these two arguments defined a frame on the
1115 cache. This allows the rest of info frame to extract the important
1116 arguments without difficulty. */
1119 setup_arbitrary_frame (argc
, argv
)
1124 error ("MIPS frame specifications require two arguments: sp and pc");
1126 return create_new_frame (argv
[0], argv
[1]);
1130 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1135 CORE_ADDR struct_addr
;
1143 /* Macros to round N up or down to the next A boundary; A must be
1145 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1146 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1148 /* First ensure that the stack and structure return address (if any)
1149 are properly aligned. The stack has to be 64-bit aligned even
1150 on 32-bit machines, because doubles must be 64-bit aligned. */
1151 sp
= ROUND_DOWN (sp
, 8);
1152 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1154 /* Now make space on the stack for the args. We allocate more
1155 than necessary for EABI, because the first few arguments are
1156 passed in registers, but that's OK. */
1157 for (argnum
= 0; argnum
< nargs
; argnum
++)
1158 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1159 sp
-= ROUND_UP (len
, 8);
1161 /* Initialize the integer and float register pointers. */
1163 float_argreg
= FPA0_REGNUM
;
1165 /* the struct_return pointer occupies the first parameter-passing reg */
1167 write_register (argreg
++, struct_addr
);
1169 /* The offset onto the stack at which we will start copying parameters
1170 (after the registers are used up) begins at 16 in the old ABI.
1171 This leaves room for the "home" area for register parameters. */
1172 stack_offset
= MIPS_EABI
? 0 : MIPS_REGSIZE
* 4;
1174 /* Now load as many as possible of the first arguments into
1175 registers, and push the rest onto the stack. Loop thru args
1176 from first to last. */
1177 for (argnum
= 0; argnum
< nargs
; argnum
++)
1180 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1181 value_ptr arg
= args
[argnum
];
1182 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1183 int len
= TYPE_LENGTH (arg_type
);
1184 enum type_code typecode
= TYPE_CODE (arg_type
);
1186 /* The EABI passes structures that do not fit in a register by
1187 reference. In all other cases, pass the structure by value. */
1188 if (typecode
== TYPE_CODE_STRUCT
&& MIPS_EABI
&& len
> MIPS_REGSIZE
)
1190 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1195 val
= (char *)VALUE_CONTENTS (arg
);
1197 /* 32-bit ABIs always start floating point arguments in an
1198 even-numbered floating point register. */
1199 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1200 && (float_argreg
& 1))
1203 /* Floating point arguments passed in registers have to be
1204 treated specially. On 32-bit architectures, doubles
1205 are passed in register pairs; the even register gets
1206 the low word, and the odd register gets the high word. */
1207 if (typecode
== TYPE_CODE_FLT
1208 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1209 && mips_fpu
!= MIPS_FPU_NONE
)
1211 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1213 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1214 unsigned long regval
;
1216 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1217 write_register (float_argreg
++, regval
); /* low word */
1218 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1219 write_register (float_argreg
++, regval
); /* high word */
1224 CORE_ADDR regval
= extract_address (val
, len
);
1225 write_register (float_argreg
++, regval
);
1228 /* If this is the old ABI, skip one or two general registers. */
1230 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1234 /* Copy the argument to general registers or the stack in
1235 register-sized pieces. Large arguments are split between
1236 registers and stack. */
1239 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1241 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1243 CORE_ADDR regval
= extract_address (val
, partial_len
);
1245 /* It's a simple argument being passed in a general
1247 If the argument length is smaller than the register size,
1248 we have to adjust the argument on big endian targets.
1249 But don't do this adjustment on EABI targets. */
1250 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1251 && partial_len
< MIPS_REGSIZE
1253 regval
<<= ((MIPS_REGSIZE
- partial_len
) * TARGET_CHAR_BIT
);
1254 write_register (argreg
, regval
);
1257 /* If this is the old ABI, prevent subsequent floating
1258 point arguments from being passed in floating point
1261 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1265 /* Write this portion of the argument to the stack. */
1267 write_memory (sp
+ stack_offset
, val
, partial_len
);
1268 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1277 /* Set the return address register to point to the entry
1278 point of the program, where a breakpoint lies in wait. */
1279 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1281 /* Return adjusted stack pointer. */
1286 mips_push_register(CORE_ADDR
*sp
, int regno
)
1288 char buffer
[MAX_REGISTER_RAW_SIZE
];
1289 int regsize
= REGISTER_RAW_SIZE (regno
);
1292 read_register_gen (regno
, buffer
);
1293 write_memory (*sp
, buffer
, regsize
);
1296 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1297 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1300 mips_push_dummy_frame()
1303 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1304 xmalloc(sizeof(struct linked_proc_info
));
1305 mips_extra_func_info_t proc_desc
= &link
->info
;
1306 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1307 CORE_ADDR old_sp
= sp
;
1308 link
->next
= linked_proc_desc_table
;
1309 linked_proc_desc_table
= link
;
1311 /* FIXME! are these correct ? */
1312 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1313 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1314 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1315 #define FLOAT_SINGLE_REG_SAVE_MASK \
1316 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1318 * The registers we must save are all those not preserved across
1319 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1320 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1321 * and FP Control/Status registers.
1324 * Dummy frame layout:
1327 * Saved MMHI, MMLO, FPC_CSR
1332 * Saved D18 (i.e. F19, F18)
1334 * Saved D0 (i.e. F1, F0)
1335 * Argument build area and stack arguments written via mips_push_arguments
1339 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1340 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1341 PROC_FRAME_OFFSET(proc_desc
) = 0;
1342 mips_push_register (&sp
, PC_REGNUM
);
1343 mips_push_register (&sp
, HI_REGNUM
);
1344 mips_push_register (&sp
, LO_REGNUM
);
1345 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1347 /* Save general CPU registers */
1348 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1349 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1350 for (ireg
= 32; --ireg
>= 0; )
1351 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1352 mips_push_register (&sp
, ireg
);
1354 /* Save floating point registers starting with high order word */
1355 PROC_FREG_MASK(proc_desc
) =
1356 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1357 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1358 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1359 for (ireg
= 32; --ireg
>= 0; )
1360 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1361 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1363 /* Update the frame pointer for the call dummy and the stack pointer.
1364 Set the procedure's starting and ending addresses to point to the
1365 call dummy address at the entry point. */
1366 write_register (PUSH_FP_REGNUM
, old_sp
);
1367 write_register (SP_REGNUM
, sp
);
1368 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1369 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1370 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1371 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1377 register int regnum
;
1378 struct frame_info
*frame
= get_current_frame ();
1379 CORE_ADDR new_sp
= FRAME_FP (frame
);
1381 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1383 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1384 if (frame
->saved_regs
== NULL
)
1385 mips_find_saved_regs (frame
);
1386 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1388 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1389 && frame
->saved_regs
->regs
[regnum
])
1390 write_register (regnum
,
1391 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1394 write_register (SP_REGNUM
, new_sp
);
1395 flush_cached_frames ();
1397 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1399 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1401 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1403 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1405 if (&pi_ptr
->info
== proc_desc
)
1410 error ("Can't locate dummy extra frame info\n");
1412 if (prev_ptr
!= NULL
)
1413 prev_ptr
->next
= pi_ptr
->next
;
1415 linked_proc_desc_table
= pi_ptr
->next
;
1419 write_register (HI_REGNUM
,
1420 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1421 write_register (LO_REGNUM
,
1422 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1423 if (mips_fpu
!= MIPS_FPU_NONE
)
1424 write_register (FCRCS_REGNUM
,
1425 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1430 mips_print_register (regnum
, all
)
1433 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1435 /* Get the data in raw format. */
1436 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1438 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1442 /* If an even floating pointer register, also print as double. */
1443 if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+MIPS_NUMREGS
1444 && !((regnum
-FP0_REGNUM
) & 1))
1446 char dbuffer
[MAX_REGISTER_RAW_SIZE
];
1448 read_relative_register_raw_bytes (regnum
, dbuffer
);
1449 read_relative_register_raw_bytes (regnum
+1, dbuffer
+4); /* FIXME!! */
1450 #ifdef REGISTER_CONVERT_TO_TYPE
1451 REGISTER_CONVERT_TO_TYPE(regnum
, builtin_type_double
, dbuffer
);
1453 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1454 val_print (builtin_type_double
, dbuffer
, 0,
1455 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1456 printf_filtered ("); ");
1458 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1460 /* The problem with printing numeric register names (r26, etc.) is that
1461 the user can't use them on input. Probably the best solution is to
1462 fix it so that either the numeric or the funky (a2, etc.) names
1463 are accepted on input. */
1464 if (regnum
< MIPS_NUMREGS
)
1465 printf_filtered ("(r%d): ", regnum
);
1467 printf_filtered (": ");
1469 /* If virtual format is floating, print it that way. */
1470 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1471 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1472 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1473 /* Else print as integer in hex. */
1475 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1476 'x', 0, gdb_stdout
);
1479 /* Replacement for generic do_registers_info. */
1482 mips_do_registers_info (regnum
, fpregs
)
1488 if (*(reg_names
[regnum
]) == '\0')
1489 error ("Not a valid register for the current processor type");
1491 mips_print_register (regnum
, 0);
1492 printf_filtered ("\n");
1496 int did_newline
= 0;
1498 for (regnum
= 0; regnum
< NUM_REGS
; )
1500 if (((!fpregs
) && regnum
>= FP0_REGNUM
&& regnum
<= FCRIR_REGNUM
)
1501 || *(reg_names
[regnum
]) == '\0')
1506 mips_print_register (regnum
, 1);
1508 printf_filtered ("; ");
1510 if ((regnum
& 3) == 0)
1512 printf_filtered ("\n");
1517 printf_filtered ("\n");
1521 /* Return number of args passed to a frame. described by FIP.
1522 Can return -1, meaning no way to tell. */
1525 mips_frame_num_args (frame
)
1526 struct frame_info
*frame
;
1528 #if 0 /* FIXME Use or lose this! */
1529 struct chain_info_t
*p
;
1531 p
= mips_find_cached_frame (FRAME_FP (frame
));
1533 return p
->the_info
.numargs
;
1538 /* Is this a branch with a delay slot? */
1540 static int is_delayed
PARAMS ((unsigned long));
1547 for (i
= 0; i
< NUMOPCODES
; ++i
)
1548 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1549 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1551 return (i
< NUMOPCODES
1552 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1553 | INSN_COND_BRANCH_DELAY
1554 | INSN_COND_BRANCH_LIKELY
)));
1558 mips_step_skips_delay (pc
)
1561 char buf
[MIPS_INSTLEN
];
1563 /* There is no branch delay slot on MIPS16. */
1567 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1568 /* If error reading memory, guess that it is not a delayed branch. */
1570 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1574 /* Skip the PC past function prologue instructions (32-bit version).
1575 This is a helper function for mips_skip_prologue. */
1578 mips32_skip_prologue (pc
, lenient
)
1579 CORE_ADDR pc
; /* starting PC to search from */
1584 int seen_sp_adjust
= 0;
1585 int load_immediate_bytes
= 0;
1587 /* Skip the typical prologue instructions. These are the stack adjustment
1588 instruction and the instructions that save registers on the stack
1589 or in the gcc frame. */
1590 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1592 char buf
[MIPS_INSTLEN
];
1594 unsigned long high_word
;
1596 status
= read_memory_nobpt (pc
, buf
, MIPS_INSTLEN
);
1598 memory_error (status
, pc
);
1599 inst
= (unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
);
1600 high_word
= (inst
>> 16) & 0xffff;
1603 if (lenient
&& is_delayed (inst
))
1607 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1608 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1610 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1611 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1613 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1614 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1615 && (inst
& 0x001F0000)) /* reg != $zero */
1618 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1620 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1622 continue; /* reg != $zero */
1624 /* move $s8,$sp. With different versions of gas this will be either
1625 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1626 Accept any one of these. */
1627 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1630 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1632 else if (high_word
== 0x3c1c) /* lui $gp,n */
1634 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1636 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1637 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1639 /* The following instructions load $at or $t0 with an immediate
1640 value in preparation for a stack adjustment via
1641 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1642 a local variable, so we accept them only before a stack adjustment
1643 instruction was seen. */
1644 else if (!seen_sp_adjust
)
1646 if (high_word
== 0x3c01 || /* lui $at,n */
1647 high_word
== 0x3c08) /* lui $t0,n */
1649 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1652 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1653 high_word
== 0x3508 || /* ori $t0,$t0,n */
1654 high_word
== 0x3401 || /* ori $at,$zero,n */
1655 high_word
== 0x3408) /* ori $t0,$zero,n */
1657 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1667 /* In a frameless function, we might have incorrectly
1668 skipped some load immediate instructions. Undo the skipping
1669 if the load immediate was not followed by a stack adjustment. */
1670 if (load_immediate_bytes
&& !seen_sp_adjust
)
1671 pc
-= load_immediate_bytes
;
1675 /* Skip the PC past function prologue instructions (16-bit version).
1676 This is a helper function for mips_skip_prologue. */
1679 mips16_skip_prologue (pc
, lenient
)
1680 CORE_ADDR pc
; /* starting PC to search from */
1685 /* Table of instructions likely to be found in a function prologue. */
1688 unsigned short inst
;
1689 unsigned short mask
;
1692 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1693 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1694 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1695 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1696 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1697 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1698 { 0x673d, 0xffff }, /* move $s1,sp */
1699 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1700 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1701 { 0xe809, 0xf81f }, /* entry pseudo-op */
1702 { 0, 0 } /* end of table marker */
1705 /* Skip the typical prologue instructions. These are the stack adjustment
1706 instruction and the instructions that save registers on the stack
1707 or in the gcc frame. */
1708 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
1710 char buf
[MIPS16_INSTLEN
];
1712 unsigned short inst
;
1714 int prev_extend_bytes
;
1717 status
= read_memory_nobpt (pc
& ~1, buf
, MIPS16_INSTLEN
);
1719 memory_error (status
, pc
);
1720 inst
= (unsigned long)extract_unsigned_integer (buf
, MIPS16_INSTLEN
);
1723 if (lenient
&& is_delayed (inst
))
1727 /* Normally we ignore an extend instruction. However, if it is
1728 not followed by a valid prologue instruction, we must adjust
1729 the pc back over the extend so that it won't be considered
1730 part of the prologue. */
1731 if ((inst
& 0xf800) == 0xf000) /* extend */
1733 extend_bytes
= MIPS16_INSTLEN
;
1736 prev_extend_bytes
= extend_bytes
;
1739 /* Check for other valid prologue instructions besides extend. */
1740 for (i
= 0; table
[i
].mask
!= 0; i
++)
1741 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
1743 if (table
[i
].mask
!= 0) /* it was in table? */
1744 continue; /* ignore it
1745 else /* non-prologue */
1747 /* Return the current pc, adjusted backwards by 2 if
1748 the previous instruction was an extend. */
1749 return pc
- prev_extend_bytes
;
1754 /* To skip prologues, I use this predicate. Returns either PC itself
1755 if the code at PC does not look like a function prologue; otherwise
1756 returns an address that (if we're lucky) follows the prologue. If
1757 LENIENT, then we must skip everything which is involved in setting
1758 up the frame (it's OK to skip more, just so long as we don't skip
1759 anything which might clobber the registers which are being saved.
1760 We must skip more in the case where part of the prologue is in the
1761 delay slot of a non-prologue instruction). */
1764 mips_skip_prologue (pc
, lenient
)
1768 /* See if we can determine the end of the prologue via the symbol table.
1769 If so, then return either PC, or the PC after the prologue, whichever
1772 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
1774 if (post_prologue_pc
!= 0)
1775 return max (pc
, post_prologue_pc
);
1777 /* Can't determine prologue from the symbol table, need to examine
1781 return mips16_skip_prologue (pc
, lenient
);
1783 return mips32_skip_prologue (pc
, lenient
);
1787 /* The lenient prologue stuff should be superseded by the code in
1788 init_extra_frame_info which looks to see whether the stores mentioned
1789 in the proc_desc have actually taken place. */
1791 /* Is address PC in the prologue (loosely defined) for function at
1795 mips_in_lenient_prologue (startaddr
, pc
)
1796 CORE_ADDR startaddr
;
1799 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
1800 return pc
>= startaddr
&& pc
< end_prologue
;
1804 /* Given a return value in `regbuf' with a type `valtype',
1805 extract and copy its value into `valbuf'. */
1807 mips_extract_return_value (valtype
, regbuf
, valbuf
)
1808 struct type
*valtype
;
1809 char regbuf
[REGISTER_BYTES
];
1816 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1817 && (mips_fpu
== MIPS_FPU_DOUBLE
1818 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1819 regnum
= FP0_REGNUM
;
1821 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1822 && TYPE_CODE (valtype
) != TYPE_CODE_FLT
1823 && TYPE_LENGTH (valtype
) < REGISTER_RAW_SIZE (regnum
))
1824 offset
= REGISTER_RAW_SIZE (regnum
) - TYPE_LENGTH (valtype
);
1826 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
,
1827 TYPE_LENGTH (valtype
));
1828 #ifdef REGISTER_CONVERT_TO_TYPE
1829 REGISTER_CONVERT_TO_TYPE(regnum
, valtype
, valbuf
);
1833 /* Given a return value in `regbuf' with a type `valtype',
1834 write it's value into the appropriate register. */
1836 mips_store_return_value (valtype
, valbuf
)
1837 struct type
*valtype
;
1841 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1844 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1845 && (mips_fpu
== MIPS_FPU_DOUBLE
1846 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1847 regnum
= FP0_REGNUM
;
1849 memcpy(raw_buffer
, valbuf
, TYPE_LENGTH (valtype
));
1851 #ifdef REGISTER_CONVERT_FROM_TYPE
1852 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
1855 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
, TYPE_LENGTH (valtype
));
1858 /* Exported procedure: Is PC in the signal trampoline code */
1861 in_sigtramp (pc
, ignore
)
1863 char *ignore
; /* function name */
1865 if (sigtramp_address
== 0)
1867 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
1870 /* Command to set FPU type. mips_fpu_string will have been set to the
1871 user's argument. Set mips_fpu based on mips_fpu_string, and then
1872 canonicalize mips_fpu_string. */
1876 mips_set_fpu_command (args
, from_tty
, c
)
1879 struct cmd_list_element
*c
;
1883 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
1884 mips_fpu
= MIPS_FPU_DOUBLE
;
1885 else if (strcasecmp (mips_fpu_string
, "double") == 0
1886 || strcasecmp (mips_fpu_string
, "on") == 0
1887 || strcasecmp (mips_fpu_string
, "1") == 0
1888 || strcasecmp (mips_fpu_string
, "yes") == 0)
1889 mips_fpu
= MIPS_FPU_DOUBLE
;
1890 else if (strcasecmp (mips_fpu_string
, "none") == 0
1891 || strcasecmp (mips_fpu_string
, "off") == 0
1892 || strcasecmp (mips_fpu_string
, "0") == 0
1893 || strcasecmp (mips_fpu_string
, "no") == 0)
1894 mips_fpu
= MIPS_FPU_NONE
;
1895 else if (strcasecmp (mips_fpu_string
, "single") == 0)
1896 mips_fpu
= MIPS_FPU_SINGLE
;
1898 err
= strsave (mips_fpu_string
);
1900 if (mips_fpu_string
!= NULL
)
1901 free (mips_fpu_string
);
1905 case MIPS_FPU_DOUBLE
:
1906 mips_fpu_string
= strsave ("double");
1908 case MIPS_FPU_SINGLE
:
1909 mips_fpu_string
= strsave ("single");
1912 mips_fpu_string
= strsave ("none");
1918 struct cleanup
*cleanups
= make_cleanup (free
, err
);
1919 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
1921 do_cleanups (cleanups
);
1926 mips_show_fpu_command (args
, from_tty
, c
)
1929 struct cmd_list_element
*c
;
1933 /* Command to set the processor type. */
1936 mips_set_processor_type_command (args
, from_tty
)
1942 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
1944 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
1945 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1946 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
1948 /* Restore the value. */
1949 tmp_mips_processor_type
= strsave (mips_processor_type
);
1954 if (!mips_set_processor_type (tmp_mips_processor_type
))
1956 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
1957 /* Restore its value. */
1958 tmp_mips_processor_type
= strsave (mips_processor_type
);
1963 mips_show_processor_type_command (args
, from_tty
)
1969 /* Modify the actual processor type. */
1972 mips_set_processor_type (str
)
1980 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1982 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
1984 mips_processor_type
= str
;
1986 for (j
= 0; j
< NUM_REGS
; ++j
)
1987 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
1991 /* FIXME tweak fpu flag too */
1998 /* Attempt to identify the particular processor model by reading the
2002 mips_read_processor_type ()
2006 prid
= read_register (PRID_REGNUM
);
2008 if ((prid
& ~0xf) == 0x700)
2009 return savestring ("r3041", strlen("r3041"));
2014 /* Just like reinit_frame_cache, but with the right arguments to be
2015 callable as an sfunc. */
2018 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2021 struct cmd_list_element
*c
;
2023 reinit_frame_cache ();
2027 gdb_print_insn_mips (memaddr
, info
)
2029 disassemble_info
*info
;
2031 mips_extra_func_info_t proc_desc
;
2033 /* Search for the function containing this address. Set the low bit
2034 of the address when searching, in case we were given an even address
2035 that is the start of a 16-bit function. If we didn't do this,
2036 the search would fail because the symbol table says the function
2037 starts at an odd address, i.e. 1 byte past the given address. */
2038 proc_desc
= find_proc_desc (memaddr
| 1, NULL
);
2040 /* Make an attempt to determine if this is a 16-bit function. If
2041 the procedure descriptor exists and the address therein is odd,
2042 it's definitely a 16-bit function. Otherwise, we have to just
2043 guess that if the address passed in is odd, it's 16-bits. */
2045 info
->mach
= PROC_LOW_ADDR (proc_desc
) & 1 ? 16 : 0;
2047 info
->mach
= memaddr
& 1 ? 16 : 0;
2049 /* Round down the instruction address to the appropriate boundary.
2050 Save the amount rounded down and subtract it from the returned size of
2051 the instruction so that the next time through the address won't
2053 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2055 /* Call the appropriate disassembler based on the target endian-ness. */
2056 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2057 return print_insn_big_mips (memaddr
, info
);
2059 return print_insn_little_mips (memaddr
, info
);
2062 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2063 counter value to determine whether a 16- or 32-bit breakpoint should be
2064 used. It returns a pointer to a string of bytes that encode a breakpoint
2065 instruction, stores the length of the string to *lenptr, and adjusts pc
2066 (if necessary) to point to the actual memory location where the
2067 breakpoint should be inserted. */
2069 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2073 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2077 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2079 *lenptr
= sizeof(mips16_big_breakpoint
);
2080 return mips16_big_breakpoint
;
2084 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2085 *lenptr
= sizeof(big_breakpoint
);
2086 return big_breakpoint
;
2093 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2095 *lenptr
= sizeof(mips16_little_breakpoint
);
2096 return mips16_little_breakpoint
;
2100 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2101 *lenptr
= sizeof(little_breakpoint
);
2102 return little_breakpoint
;
2107 /* Test whether the PC points to the return instruction at the
2108 end of a function. This implements the ABOUT_TO_RETURN macro. */
2111 mips_about_to_return (pc
)
2115 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2116 generates a "jr $ra"; other times it generates code to load
2117 the return address from the stack to an accessible register (such
2118 as $a3), then a "jr" using that register. This second case
2119 is almost impossible to distinguish from an indirect jump
2120 used for switch statements, so we don't even try. */
2121 return read_memory_integer (pc
& ~1, 2) == 0xe820; /* jr $ra */
2123 return read_memory_integer (pc
, 4) == 0x3e00008; /* jr $ra */
2128 _initialize_mips_tdep ()
2130 struct cmd_list_element
*c
;
2132 tm_print_insn
= gdb_print_insn_mips
;
2134 /* Let the user turn off floating point and set the fence post for
2135 heuristic_proc_start. */
2137 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2138 (char *) &mips_fpu_string
,
2139 "Set use of floating point coprocessor.\n\
2140 Set to `none' to avoid using floating point instructions when calling\n\
2141 functions or dealing with return values. Set to `single' to use only\n\
2142 single precision floating point as on the R4650. Set to `double' for\n\
2143 normal floating point support.",
2145 c
->function
.sfunc
= mips_set_fpu_command
;
2146 c
= add_show_from_set (c
, &showlist
);
2147 c
->function
.sfunc
= mips_show_fpu_command
;
2149 mips_fpu
= MIPS_FPU_DOUBLE
;
2150 mips_fpu_string
= strsave ("double");
2152 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2153 (char *) &tmp_mips_processor_type
,
2154 "Set the type of MIPS processor in use.\n\
2155 Set this to be able to access processor-type-specific registers.\n\
2158 c
->function
.cfunc
= mips_set_processor_type_command
;
2159 c
= add_show_from_set (c
, &showlist
);
2160 c
->function
.cfunc
= mips_show_processor_type_command
;
2162 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2163 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2165 /* We really would like to have both "0" and "unlimited" work, but
2166 command.c doesn't deal with that. So make it a var_zinteger
2167 because the user can always use "999999" or some such for unlimited. */
2168 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2169 (char *) &heuristic_fence_post
,
2171 Set the distance searched for the start of a function.\n\
2172 If you are debugging a stripped executable, GDB needs to search through the\n\
2173 program for the start of a function. This command sets the distance of the\n\
2174 search. The only need to set it is when debugging a stripped executable.",
2176 /* We need to throw away the frame cache when we set this, since it
2177 might change our ability to get backtraces. */
2178 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2179 add_show_from_set (c
, &showlist
);