1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_regs_have_home_p
;
142 int mips_default_stack_argsize
;
143 int gdb_target_is_mips64
;
144 int default_mask_address_p
;
146 enum gdb_osabi osabi
;
149 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
150 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
152 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
154 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
156 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
158 /* Return the currently configured (or set) saved register size. */
160 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
162 static const char *mips_saved_regsize_string
= size_auto
;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string
== size_auto
)
170 return MIPS_DEFAULT_SAVED_REGSIZE
;
171 else if (mips_saved_regsize_string
== size_64
)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
178 compatiblity mode. A return value of 1 means that we have
179 physical 64-bit registers, but should treat them as 32-bit registers. */
182 mips2_fp_compat (void)
184 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
186 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
190 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
191 in all the places we deal with FP registers. PR gdb/413. */
192 /* Otherwise check the FR bit in the status register - it controls
193 the FP compatiblity mode. If it is clear we are in compatibility
195 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
202 /* Indicate that the ABI makes use of double-precision registers
203 provided by the FPU (rather than combining pairs of registers to
204 form double-precision values). Do not use "TARGET_IS_MIPS64" to
205 determine if the ABI is using double-precision registers. See also
207 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
209 /* Does the caller allocate a ``home'' for each register used in the
210 function call? The N32 ABI and MIPS_EABI do not, the others do. */
212 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
214 /* The amount of space reserved on the stack for registers. This is
215 different to MIPS_SAVED_REGSIZE as it determines the alignment of
216 data allocated after the registers have run out. */
218 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
220 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
222 static const char *mips_stack_argsize_string
= size_auto
;
225 mips_stack_argsize (void)
227 if (mips_stack_argsize_string
== size_auto
)
228 return MIPS_DEFAULT_STACK_ARGSIZE
;
229 else if (mips_stack_argsize_string
== size_64
)
231 else /* if (mips_stack_argsize_string == size_32) */
235 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
237 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
239 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
241 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
243 static void mips_print_register (int, int);
245 static mips_extra_func_info_t
246 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
248 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
250 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
252 int mips_set_processor_type (char *);
254 static void mips_show_processor_type_command (char *, int);
256 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
258 static mips_extra_func_info_t
259 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
261 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
262 mips_extra_func_info_t proc_desc
);
264 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
265 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
267 static struct type
*mips_float_register_type (void);
268 static struct type
*mips_double_register_type (void);
270 /* This value is the model of MIPS in use. It is derived from the value
271 of the PrID register. */
273 char *mips_processor_type
;
275 char *tmp_mips_processor_type
;
277 /* The list of available "set mips " and "show mips " commands */
279 static struct cmd_list_element
*setmipscmdlist
= NULL
;
280 static struct cmd_list_element
*showmipscmdlist
= NULL
;
282 /* A set of original names, to be used when restoring back to generic
283 registers from a specific set. */
285 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
286 char **mips_processor_reg_names
= mips_generic_reg_names
;
289 mips_register_name (int i
)
291 return mips_processor_reg_names
[i
];
294 /* Names of IDT R3041 registers. */
296 char *mips_r3041_reg_names
[] = {
297 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
298 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
300 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
301 "sr", "lo", "hi", "bad", "cause","pc",
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
306 "fsr", "fir", "fp", "",
307 "", "", "bus", "ccfg", "", "", "", "",
308 "", "", "port", "cmp", "", "", "epc", "prid",
311 /* Names of IDT R3051 registers. */
313 char *mips_r3051_reg_names
[] = {
314 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
315 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
316 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
317 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
318 "sr", "lo", "hi", "bad", "cause","pc",
319 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
320 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
321 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
322 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
323 "fsr", "fir", "fp", "",
324 "inx", "rand", "elo", "", "ctxt", "", "", "",
325 "", "", "ehi", "", "", "", "epc", "prid",
328 /* Names of IDT R3081 registers. */
330 char *mips_r3081_reg_names
[] = {
331 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
332 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
334 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
335 "sr", "lo", "hi", "bad", "cause","pc",
336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
340 "fsr", "fir", "fp", "",
341 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
342 "", "", "ehi", "", "", "", "epc", "prid",
345 /* Names of LSI 33k registers. */
347 char *mips_lsi33k_reg_names
[] = {
348 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
349 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
350 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
351 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
352 "epc", "hi", "lo", "sr", "cause","badvaddr",
353 "dcic", "bpc", "bda", "", "", "", "", "",
354 "", "", "", "", "", "", "", "",
355 "", "", "", "", "", "", "", "",
356 "", "", "", "", "", "", "", "",
358 "", "", "", "", "", "", "", "",
359 "", "", "", "", "", "", "", "",
365 } mips_processor_type_table
[] = {
366 { "generic", mips_generic_reg_names
},
367 { "r3041", mips_r3041_reg_names
},
368 { "r3051", mips_r3051_reg_names
},
369 { "r3071", mips_r3081_reg_names
},
370 { "r3081", mips_r3081_reg_names
},
371 { "lsi33k", mips_lsi33k_reg_names
},
379 /* Table to translate MIPS16 register field to actual register number. */
380 static int mips16_to_32_reg
[8] =
381 {16, 17, 2, 3, 4, 5, 6, 7};
383 /* Heuristic_proc_start may hunt through the text section for a long
384 time across a 2400 baud serial line. Allows the user to limit this
387 static unsigned int heuristic_fence_post
= 0;
389 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
390 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
391 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
392 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
393 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
394 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
395 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
396 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
397 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
398 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
399 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
400 this will corrupt pdr.iline. Fortunately we don't use it. */
401 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
402 #define _PROC_MAGIC_ 0x0F0F0F0F
403 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
404 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
406 struct linked_proc_info
408 struct mips_extra_func_info info
;
409 struct linked_proc_info
*next
;
411 *linked_proc_desc_table
= NULL
;
414 mips_print_extra_frame_info (struct frame_info
*fi
)
418 && fi
->extra_info
->proc_desc
419 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
420 printf_filtered (" frame pointer is at %s+%s\n",
421 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
422 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
425 /* Number of bytes of storage in the actual machine representation for
426 register N. NOTE: This indirectly defines the register size
427 transfered by the GDB protocol. */
429 static int mips64_transfers_32bit_regs_p
= 0;
432 mips_register_raw_size (int reg_nr
)
434 if (mips64_transfers_32bit_regs_p
)
435 return REGISTER_VIRTUAL_SIZE (reg_nr
);
436 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
437 && FP_REGISTER_DOUBLE
)
438 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
445 /* Convert between RAW and VIRTUAL registers. The RAW register size
446 defines the remote-gdb packet. */
449 mips_register_convertible (int reg_nr
)
451 if (mips64_transfers_32bit_regs_p
)
454 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
458 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
459 char *raw_buf
, char *virt_buf
)
461 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
463 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
464 TYPE_LENGTH (virtual_type
));
468 TYPE_LENGTH (virtual_type
));
472 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
473 char *virt_buf
, char *raw_buf
)
475 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
476 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
477 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
479 TYPE_LENGTH (virtual_type
));
483 TYPE_LENGTH (virtual_type
));
486 /* Should the upper word of 64-bit addresses be zeroed? */
487 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
490 mips_mask_address_p (void)
492 switch (mask_address_var
)
494 case AUTO_BOOLEAN_TRUE
:
496 case AUTO_BOOLEAN_FALSE
:
499 case AUTO_BOOLEAN_AUTO
:
500 return MIPS_DEFAULT_MASK_ADDRESS_P
;
502 internal_error (__FILE__
, __LINE__
,
503 "mips_mask_address_p: bad switch");
509 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
511 switch (mask_address_var
)
513 case AUTO_BOOLEAN_TRUE
:
514 printf_filtered ("The 32 bit mips address mask is enabled\n");
516 case AUTO_BOOLEAN_FALSE
:
517 printf_filtered ("The 32 bit mips address mask is disabled\n");
519 case AUTO_BOOLEAN_AUTO
:
520 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
521 mips_mask_address_p () ? "enabled" : "disabled");
524 internal_error (__FILE__
, __LINE__
,
525 "show_mask_address: bad switch");
530 /* Should call_function allocate stack space for a struct return? */
532 mips_use_struct_convention (int gcc_p
, struct type
*type
)
535 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
537 return 1; /* Structures are returned by ref in extra arg0 */
540 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
543 pc_is_mips16 (bfd_vma memaddr
)
545 struct minimal_symbol
*sym
;
547 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
548 if (IS_MIPS16_ADDR (memaddr
))
551 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
552 the high bit of the info field. Use this to decide if the function is
553 MIPS16 or normal MIPS. */
554 sym
= lookup_minimal_symbol_by_pc (memaddr
);
556 return MSYMBOL_IS_SPECIAL (sym
);
561 /* MIPS believes that the PC has a sign extended value. Perhaphs the
562 all registers should be sign extended for simplicity? */
565 mips_read_pc (ptid_t ptid
)
567 return read_signed_register_pid (PC_REGNUM
, ptid
);
570 /* This returns the PC of the first inst after the prologue. If we can't
571 find the prologue, then return 0. */
574 after_prologue (CORE_ADDR pc
,
575 mips_extra_func_info_t proc_desc
)
577 struct symtab_and_line sal
;
578 CORE_ADDR func_addr
, func_end
;
580 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
581 to read the stack pointer from the current machine state, because
582 the current machine state has nothing to do with the information
583 we need from the proc_desc; and the process may or may not exist
586 proc_desc
= find_proc_desc (pc
, NULL
, 0);
590 /* If function is frameless, then we need to do it the hard way. I
591 strongly suspect that frameless always means prologueless... */
592 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
593 && PROC_FRAME_OFFSET (proc_desc
) == 0)
597 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
598 return 0; /* Unknown */
600 sal
= find_pc_line (func_addr
, 0);
602 if (sal
.end
< func_end
)
605 /* The line after the prologue is after the end of the function. In this
606 case, tell the caller to find the prologue the hard way. */
611 /* Decode a MIPS32 instruction that saves a register in the stack, and
612 set the appropriate bit in the general register mask or float register mask
613 to indicate which register is saved. This is a helper function
614 for mips_find_saved_regs. */
617 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
618 unsigned long *float_mask
)
622 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
623 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
624 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
626 /* It might be possible to use the instruction to
627 find the offset, rather than the code below which
628 is based on things being in a certain order in the
629 frame, but figuring out what the instruction's offset
630 is relative to might be a little tricky. */
631 reg
= (inst
& 0x001f0000) >> 16;
632 *gen_mask
|= (1 << reg
);
634 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
635 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
636 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
639 reg
= ((inst
& 0x001f0000) >> 16);
640 *float_mask
|= (1 << reg
);
644 /* Decode a MIPS16 instruction that saves a register in the stack, and
645 set the appropriate bit in the general register or float register mask
646 to indicate which register is saved. This is a helper function
647 for mips_find_saved_regs. */
650 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
652 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
654 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
655 *gen_mask
|= (1 << reg
);
657 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
659 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
660 *gen_mask
|= (1 << reg
);
662 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
663 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
664 *gen_mask
|= (1 << RA_REGNUM
);
668 /* Fetch and return instruction from the specified location. If the PC
669 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
672 mips_fetch_instruction (CORE_ADDR addr
)
674 char buf
[MIPS_INSTLEN
];
678 if (pc_is_mips16 (addr
))
680 instlen
= MIPS16_INSTLEN
;
681 addr
= UNMAKE_MIPS16_ADDR (addr
);
684 instlen
= MIPS_INSTLEN
;
685 status
= read_memory_nobpt (addr
, buf
, instlen
);
687 memory_error (status
, addr
);
688 return extract_unsigned_integer (buf
, instlen
);
692 /* These the fields of 32 bit mips instructions */
693 #define mips32_op(x) (x >> 26)
694 #define itype_op(x) (x >> 26)
695 #define itype_rs(x) ((x >> 21) & 0x1f)
696 #define itype_rt(x) ((x >> 16) & 0x1f)
697 #define itype_immediate(x) (x & 0xffff)
699 #define jtype_op(x) (x >> 26)
700 #define jtype_target(x) (x & 0x03ffffff)
702 #define rtype_op(x) (x >> 26)
703 #define rtype_rs(x) ((x >> 21) & 0x1f)
704 #define rtype_rt(x) ((x >> 16) & 0x1f)
705 #define rtype_rd(x) ((x >> 11) & 0x1f)
706 #define rtype_shamt(x) ((x >> 6) & 0x1f)
707 #define rtype_funct(x) (x & 0x3f)
710 mips32_relative_offset (unsigned long inst
)
713 x
= itype_immediate (inst
);
714 if (x
& 0x8000) /* sign bit set */
716 x
|= 0xffff0000; /* sign extension */
722 /* Determine whate to set a single step breakpoint while considering
725 mips32_next_pc (CORE_ADDR pc
)
729 inst
= mips_fetch_instruction (pc
);
730 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
732 if (itype_op (inst
) >> 2 == 5)
733 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
735 op
= (itype_op (inst
) & 0x03);
750 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
751 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
753 int tf
= itype_rt (inst
) & 0x01;
754 int cnum
= itype_rt (inst
) >> 2;
755 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
756 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
758 if (((cond
>> cnum
) & 0x01) == tf
)
759 pc
+= mips32_relative_offset (inst
) + 4;
764 pc
+= 4; /* Not a branch, next instruction is easy */
767 { /* This gets way messy */
769 /* Further subdivide into SPECIAL, REGIMM and other */
770 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
772 case 0: /* SPECIAL */
773 op
= rtype_funct (inst
);
778 /* Set PC to that address */
779 pc
= read_signed_register (rtype_rs (inst
));
785 break; /* end SPECIAL */
788 op
= itype_rt (inst
); /* branch condition */
793 case 16: /* BLTZAL */
794 case 18: /* BLTZALL */
796 if (read_signed_register (itype_rs (inst
)) < 0)
797 pc
+= mips32_relative_offset (inst
) + 4;
799 pc
+= 8; /* after the delay slot */
803 case 17: /* BGEZAL */
804 case 19: /* BGEZALL */
805 greater_equal_branch
:
806 if (read_signed_register (itype_rs (inst
)) >= 0)
807 pc
+= mips32_relative_offset (inst
) + 4;
809 pc
+= 8; /* after the delay slot */
811 /* All of the other instructions in the REGIMM category */
816 break; /* end REGIMM */
821 reg
= jtype_target (inst
) << 2;
822 /* Upper four bits get never changed... */
823 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
826 /* FIXME case JALX : */
829 reg
= jtype_target (inst
) << 2;
830 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
831 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
833 break; /* The new PC will be alternate mode */
834 case 4: /* BEQ, BEQL */
836 if (read_signed_register (itype_rs (inst
)) ==
837 read_signed_register (itype_rt (inst
)))
838 pc
+= mips32_relative_offset (inst
) + 4;
842 case 5: /* BNE, BNEL */
844 if (read_signed_register (itype_rs (inst
)) !=
845 read_signed_register (itype_rt (inst
)))
846 pc
+= mips32_relative_offset (inst
) + 4;
850 case 6: /* BLEZ, BLEZL */
852 if (read_signed_register (itype_rs (inst
) <= 0))
853 pc
+= mips32_relative_offset (inst
) + 4;
859 greater_branch
: /* BGTZ, BGTZL */
860 if (read_signed_register (itype_rs (inst
) > 0))
861 pc
+= mips32_relative_offset (inst
) + 4;
868 } /* mips32_next_pc */
870 /* Decoding the next place to set a breakpoint is irregular for the
871 mips 16 variant, but fortunately, there fewer instructions. We have to cope
872 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
873 We dont want to set a single step instruction on the extend instruction
877 /* Lots of mips16 instruction formats */
878 /* Predicting jumps requires itype,ritype,i8type
879 and their extensions extItype,extritype,extI8type
881 enum mips16_inst_fmts
883 itype
, /* 0 immediate 5,10 */
884 ritype
, /* 1 5,3,8 */
885 rrtype
, /* 2 5,3,3,5 */
886 rritype
, /* 3 5,3,3,5 */
887 rrrtype
, /* 4 5,3,3,3,2 */
888 rriatype
, /* 5 5,3,3,1,4 */
889 shifttype
, /* 6 5,3,3,3,2 */
890 i8type
, /* 7 5,3,8 */
891 i8movtype
, /* 8 5,3,3,5 */
892 i8mov32rtype
, /* 9 5,3,5,3 */
893 i64type
, /* 10 5,3,8 */
894 ri64type
, /* 11 5,3,3,5 */
895 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
896 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
897 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
898 extRRItype
, /* 15 5,5,5,5,3,3,5 */
899 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
900 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
901 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
902 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
903 extRi64type
, /* 20 5,6,5,5,3,3,5 */
904 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
906 /* I am heaping all the fields of the formats into one structure and
907 then, only the fields which are involved in instruction extension */
911 unsigned int regx
; /* Function in i8 type */
916 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
917 for the bits which make up the immediatate extension. */
920 extended_offset (unsigned int extension
)
923 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
925 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
927 value
|= extension
& 0x01f; /* extract 4:0 */
931 /* Only call this function if you know that this is an extendable
932 instruction, It wont malfunction, but why make excess remote memory references?
933 If the immediate operands get sign extended or somthing, do it after
934 the extension is performed.
936 /* FIXME: Every one of these cases needs to worry about sign extension
937 when the offset is to be used in relative addressing */
941 fetch_mips_16 (CORE_ADDR pc
)
944 pc
&= 0xfffffffe; /* clear the low order bit */
945 target_read_memory (pc
, buf
, 2);
946 return extract_unsigned_integer (buf
, 2);
950 unpack_mips16 (CORE_ADDR pc
,
951 unsigned int extension
,
953 enum mips16_inst_fmts insn_format
,
954 struct upk_mips16
*upk
)
966 value
= extended_offset (extension
);
967 value
= value
<< 11; /* rom for the original value */
968 value
|= inst
& 0x7ff; /* eleven bits from instruction */
972 value
= inst
& 0x7ff;
973 /* FIXME : Consider sign extension */
982 { /* A register identifier and an offset */
983 /* Most of the fields are the same as I type but the
984 immediate value is of a different length */
988 value
= extended_offset (extension
);
989 value
= value
<< 8; /* from the original instruction */
990 value
|= inst
& 0xff; /* eleven bits from instruction */
991 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
992 if (value
& 0x4000) /* test the sign bit , bit 26 */
994 value
&= ~0x3fff; /* remove the sign bit */
1000 value
= inst
& 0xff; /* 8 bits */
1001 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1002 /* FIXME: Do sign extension , this format needs it */
1003 if (value
& 0x80) /* THIS CONFUSES ME */
1005 value
&= 0xef; /* remove the sign bit */
1015 unsigned long value
;
1016 unsigned int nexthalf
;
1017 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1018 value
= value
<< 16;
1019 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1027 internal_error (__FILE__
, __LINE__
,
1030 upk
->offset
= offset
;
1037 add_offset_16 (CORE_ADDR pc
, int offset
)
1039 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1044 extended_mips16_next_pc (CORE_ADDR pc
,
1045 unsigned int extension
,
1048 int op
= (insn
>> 11);
1051 case 2: /* Branch */
1054 struct upk_mips16 upk
;
1055 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1056 offset
= upk
.offset
;
1062 pc
+= (offset
<< 1) + 2;
1065 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1067 struct upk_mips16 upk
;
1068 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1069 pc
= add_offset_16 (pc
, upk
.offset
);
1070 if ((insn
>> 10) & 0x01) /* Exchange mode */
1071 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1078 struct upk_mips16 upk
;
1080 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1081 reg
= read_signed_register (upk
.regx
);
1083 pc
+= (upk
.offset
<< 1) + 2;
1090 struct upk_mips16 upk
;
1092 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1093 reg
= read_signed_register (upk
.regx
);
1095 pc
+= (upk
.offset
<< 1) + 2;
1100 case 12: /* I8 Formats btez btnez */
1102 struct upk_mips16 upk
;
1104 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1105 /* upk.regx contains the opcode */
1106 reg
= read_signed_register (24); /* Test register is 24 */
1107 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1108 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1109 /* pc = add_offset_16(pc,upk.offset) ; */
1110 pc
+= (upk
.offset
<< 1) + 2;
1115 case 29: /* RR Formats JR, JALR, JALR-RA */
1117 struct upk_mips16 upk
;
1118 /* upk.fmt = rrtype; */
1123 upk
.regx
= (insn
>> 8) & 0x07;
1124 upk
.regy
= (insn
>> 5) & 0x07;
1132 break; /* Function return instruction */
1138 break; /* BOGUS Guess */
1140 pc
= read_signed_register (reg
);
1147 /* This is an instruction extension. Fetch the real instruction
1148 (which follows the extension) and decode things based on
1152 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1165 mips16_next_pc (CORE_ADDR pc
)
1167 unsigned int insn
= fetch_mips_16 (pc
);
1168 return extended_mips16_next_pc (pc
, 0, insn
);
1171 /* The mips_next_pc function supports single_step when the remote
1172 target monitor or stub is not developed enough to do a single_step.
1173 It works by decoding the current instruction and predicting where a
1174 branch will go. This isnt hard because all the data is available.
1175 The MIPS32 and MIPS16 variants are quite different */
1177 mips_next_pc (CORE_ADDR pc
)
1180 return mips16_next_pc (pc
);
1182 return mips32_next_pc (pc
);
1185 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1189 mips_find_saved_regs (struct frame_info
*fci
)
1192 CORE_ADDR reg_position
;
1193 /* r0 bit means kernel trap */
1195 /* What registers have been saved? Bitmasks. */
1196 unsigned long gen_mask
, float_mask
;
1197 mips_extra_func_info_t proc_desc
;
1200 frame_saved_regs_zalloc (fci
);
1202 /* If it is the frame for sigtramp, the saved registers are located
1203 in a sigcontext structure somewhere on the stack.
1204 If the stack layout for sigtramp changes we might have to change these
1205 constants and the companion fixup_sigtramp in mdebugread.c */
1206 #ifndef SIGFRAME_BASE
1207 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1208 above the sigtramp frame. */
1209 #define SIGFRAME_BASE MIPS_REGSIZE
1210 /* FIXME! Are these correct?? */
1211 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1212 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1213 #define SIGFRAME_FPREGSAVE_OFF \
1214 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1216 #ifndef SIGFRAME_REG_SIZE
1217 /* FIXME! Is this correct?? */
1218 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1220 if (fci
->signal_handler_caller
)
1222 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1224 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1225 + ireg
* SIGFRAME_REG_SIZE
;
1226 fci
->saved_regs
[ireg
] = reg_position
;
1228 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1230 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1231 + ireg
* SIGFRAME_REG_SIZE
;
1232 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1234 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1238 proc_desc
= fci
->extra_info
->proc_desc
;
1239 if (proc_desc
== NULL
)
1240 /* I'm not sure how/whether this can happen. Normally when we can't
1241 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1242 and set the saved_regs right away. */
1245 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1246 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1247 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1249 if ( /* In any frame other than the innermost or a frame interrupted by
1250 a signal, we assume that all registers have been saved.
1251 This assumes that all register saves in a function happen before
1252 the first function call. */
1253 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1255 /* In a dummy frame we know exactly where things are saved. */
1256 && !PROC_DESC_IS_DUMMY (proc_desc
)
1258 /* Don't bother unless we are inside a function prologue. Outside the
1259 prologue, we know where everything is. */
1261 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1263 /* Not sure exactly what kernel_trap means, but if it means
1264 the kernel saves the registers without a prologue doing it,
1265 we better not examine the prologue to see whether registers
1266 have been saved yet. */
1269 /* We need to figure out whether the registers that the proc_desc
1270 claims are saved have been saved yet. */
1274 /* Bitmasks; set if we have found a save for the register. */
1275 unsigned long gen_save_found
= 0;
1276 unsigned long float_save_found
= 0;
1279 /* If the address is odd, assume this is MIPS16 code. */
1280 addr
= PROC_LOW_ADDR (proc_desc
);
1281 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1283 /* Scan through this function's instructions preceding the current
1284 PC, and look for those that save registers. */
1285 while (addr
< fci
->pc
)
1287 inst
= mips_fetch_instruction (addr
);
1288 if (pc_is_mips16 (addr
))
1289 mips16_decode_reg_save (inst
, &gen_save_found
);
1291 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1294 gen_mask
= gen_save_found
;
1295 float_mask
= float_save_found
;
1298 /* Fill in the offsets for the registers which gen_mask says
1300 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1301 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1302 if (gen_mask
& 0x80000000)
1304 fci
->saved_regs
[ireg
] = reg_position
;
1305 reg_position
-= MIPS_SAVED_REGSIZE
;
1308 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1309 of that normally used by gcc. Therefore, we have to fetch the first
1310 instruction of the function, and if it's an entry instruction that
1311 saves $s0 or $s1, correct their saved addresses. */
1312 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1314 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1315 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1318 int sreg_count
= (inst
>> 6) & 3;
1320 /* Check if the ra register was pushed on the stack. */
1321 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1323 reg_position
-= MIPS_SAVED_REGSIZE
;
1325 /* Check if the s0 and s1 registers were pushed on the stack. */
1326 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1328 fci
->saved_regs
[reg
] = reg_position
;
1329 reg_position
-= MIPS_SAVED_REGSIZE
;
1334 /* Fill in the offsets for the registers which float_mask says
1336 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1338 /* The freg_offset points to where the first *double* register
1339 is saved. So skip to the high-order word. */
1340 if (!GDB_TARGET_IS_MIPS64
)
1341 reg_position
+= MIPS_SAVED_REGSIZE
;
1343 /* Fill in the offsets for the float registers which float_mask says
1345 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1346 if (float_mask
& 0x80000000)
1348 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1349 reg_position
-= MIPS_SAVED_REGSIZE
;
1352 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1356 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1358 for (; fi
; fi
= fi
->next
)
1360 /* We have to get the saved sp from the sigcontext
1361 if it is a signal handler frame. */
1362 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1366 if (fi
->saved_regs
== NULL
)
1367 mips_find_saved_regs (fi
);
1368 if (fi
->saved_regs
[regno
])
1369 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1372 return read_signed_register (regno
);
1375 /* mips_addr_bits_remove - remove useless address bits */
1378 mips_addr_bits_remove (CORE_ADDR addr
)
1380 if (GDB_TARGET_IS_MIPS64
)
1382 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1384 /* This hack is a work-around for existing boards using
1385 PMON, the simulator, and any other 64-bit targets that
1386 doesn't have true 64-bit addressing. On these targets,
1387 the upper 32 bits of addresses are ignored by the
1388 hardware. Thus, the PC or SP are likely to have been
1389 sign extended to all 1s by instruction sequences that
1390 load 32-bit addresses. For example, a typical piece of
1391 code that loads an address is this:
1392 lui $r2, <upper 16 bits>
1393 ori $r2, <lower 16 bits>
1394 But the lui sign-extends the value such that the upper 32
1395 bits may be all 1s. The workaround is simply to mask off
1396 these bits. In the future, gcc may be changed to support
1397 true 64-bit addressing, and this masking will have to be
1399 addr
&= (CORE_ADDR
) 0xffffffff;
1402 else if (mips_mask_address_p ())
1404 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1405 masking off bits, instead, the actual target should be asking
1406 for the address to be converted to a valid pointer. */
1407 /* Even when GDB is configured for some 32-bit targets
1408 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1409 so CORE_ADDR is 64 bits. So we still have to mask off
1410 useless bits from addresses. */
1411 addr
&= (CORE_ADDR
) 0xffffffff;
1416 /* mips_software_single_step() is called just before we want to resume
1417 the inferior, if we want to single-step it but there is no hardware
1418 or kernel single-step support (MIPS on GNU/Linux for example). We find
1419 the target of the coming instruction and breakpoint it.
1421 single_step is also called just after the inferior stops. If we had
1422 set up a simulated single-step, we undo our damage. */
1425 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1427 static CORE_ADDR next_pc
;
1428 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1429 static binsn_quantum break_mem
;
1432 if (insert_breakpoints_p
)
1434 pc
= read_register (PC_REGNUM
);
1435 next_pc
= mips_next_pc (pc
);
1437 target_insert_breakpoint (next_pc
, break_mem
);
1440 target_remove_breakpoint (next_pc
, break_mem
);
1444 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1448 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1449 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1450 tmp
= mips_skip_stub (pc
);
1451 prev
->pc
= tmp
? tmp
: pc
;
1456 mips_frame_saved_pc (struct frame_info
*frame
)
1459 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1460 /* We have to get the saved pc from the sigcontext
1461 if it is a signal handler frame. */
1462 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1463 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1465 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1466 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1468 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1470 return ADDR_BITS_REMOVE (saved_pc
);
1473 static struct mips_extra_func_info temp_proc_desc
;
1474 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1476 /* Set a register's saved stack address in temp_saved_regs. If an address
1477 has already been set for this register, do nothing; this way we will
1478 only recognize the first save of a given register in a function prologue.
1479 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1482 set_reg_offset (int regno
, CORE_ADDR offset
)
1484 if (temp_saved_regs
[regno
] == 0)
1485 temp_saved_regs
[regno
] = offset
;
1489 /* Test whether the PC points to the return instruction at the
1490 end of a function. */
1493 mips_about_to_return (CORE_ADDR pc
)
1495 if (pc_is_mips16 (pc
))
1496 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1497 generates a "jr $ra"; other times it generates code to load
1498 the return address from the stack to an accessible register (such
1499 as $a3), then a "jr" using that register. This second case
1500 is almost impossible to distinguish from an indirect jump
1501 used for switch statements, so we don't even try. */
1502 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1504 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1508 /* This fencepost looks highly suspicious to me. Removing it also
1509 seems suspicious as it could affect remote debugging across serial
1513 heuristic_proc_start (CORE_ADDR pc
)
1520 pc
= ADDR_BITS_REMOVE (pc
);
1522 fence
= start_pc
- heuristic_fence_post
;
1526 if (heuristic_fence_post
== UINT_MAX
1527 || fence
< VM_MIN_ADDRESS
)
1528 fence
= VM_MIN_ADDRESS
;
1530 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1532 /* search back for previous return */
1533 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1534 if (start_pc
< fence
)
1536 /* It's not clear to me why we reach this point when
1537 stop_soon_quietly, but with this test, at least we
1538 don't print out warnings for every child forked (eg, on
1539 decstation). 22apr93 rich@cygnus.com. */
1540 if (!stop_soon_quietly
)
1542 static int blurb_printed
= 0;
1544 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1549 /* This actually happens frequently in embedded
1550 development, when you first connect to a board
1551 and your stack pointer and pc are nowhere in
1552 particular. This message needs to give people
1553 in that situation enough information to
1554 determine that it's no big deal. */
1555 printf_filtered ("\n\
1556 GDB is unable to find the start of the function at 0x%s\n\
1557 and thus can't determine the size of that function's stack frame.\n\
1558 This means that GDB may be unable to access that stack frame, or\n\
1559 the frames below it.\n\
1560 This problem is most likely caused by an invalid program counter or\n\
1562 However, if you think GDB should simply search farther back\n\
1563 from 0x%s for code which looks like the beginning of a\n\
1564 function, you can increase the range of the search using the `set\n\
1565 heuristic-fence-post' command.\n",
1566 paddr_nz (pc
), paddr_nz (pc
));
1573 else if (pc_is_mips16 (start_pc
))
1575 unsigned short inst
;
1577 /* On MIPS16, any one of the following is likely to be the
1578 start of a function:
1582 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1583 inst
= mips_fetch_instruction (start_pc
);
1584 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1585 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1586 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1587 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1589 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1590 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1595 else if (mips_about_to_return (start_pc
))
1597 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1604 /* Fetch the immediate value from a MIPS16 instruction.
1605 If the previous instruction was an EXTEND, use it to extend
1606 the upper bits of the immediate value. This is a helper function
1607 for mips16_heuristic_proc_desc. */
1610 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1611 unsigned short inst
, /* current instruction */
1612 int nbits
, /* number of bits in imm field */
1613 int scale
, /* scale factor to be applied to imm */
1614 int is_signed
) /* is the imm field signed? */
1618 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1620 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1621 if (offset
& 0x8000) /* check for negative extend */
1622 offset
= 0 - (0x10000 - (offset
& 0xffff));
1623 return offset
| (inst
& 0x1f);
1627 int max_imm
= 1 << nbits
;
1628 int mask
= max_imm
- 1;
1629 int sign_bit
= max_imm
>> 1;
1631 offset
= inst
& mask
;
1632 if (is_signed
&& (offset
& sign_bit
))
1633 offset
= 0 - (max_imm
- offset
);
1634 return offset
* scale
;
1639 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1640 stream from start_pc to limit_pc. */
1643 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1644 struct frame_info
*next_frame
, CORE_ADDR sp
)
1647 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1648 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1649 unsigned inst
= 0; /* current instruction */
1650 unsigned entry_inst
= 0; /* the entry instruction */
1653 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1654 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1656 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1658 /* Save the previous instruction. If it's an EXTEND, we'll extract
1659 the immediate offset extension from it in mips16_get_imm. */
1662 /* Fetch and decode the instruction. */
1663 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1664 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1665 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1667 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1668 if (offset
< 0) /* negative stack adjustment? */
1669 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1671 /* Exit loop if a positive stack adjustment is found, which
1672 usually means that the stack cleanup code in the function
1673 epilogue is reached. */
1676 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1678 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1679 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1680 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1681 set_reg_offset (reg
, sp
+ offset
);
1683 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1685 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1686 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1687 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1688 set_reg_offset (reg
, sp
+ offset
);
1690 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1692 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1693 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1694 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1696 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1698 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1699 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1700 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1702 else if (inst
== 0x673d) /* move $s1, $sp */
1705 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1707 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1709 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1710 frame_addr
= sp
+ offset
;
1711 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1712 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1714 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1716 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1717 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1718 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1719 set_reg_offset (reg
, frame_addr
+ offset
);
1721 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1723 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1724 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1725 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1726 set_reg_offset (reg
, frame_addr
+ offset
);
1728 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1729 entry_inst
= inst
; /* save for later processing */
1730 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1731 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1734 /* The entry instruction is typically the first instruction in a function,
1735 and it stores registers at offsets relative to the value of the old SP
1736 (before the prologue). But the value of the sp parameter to this
1737 function is the new SP (after the prologue has been executed). So we
1738 can't calculate those offsets until we've seen the entire prologue,
1739 and can calculate what the old SP must have been. */
1740 if (entry_inst
!= 0)
1742 int areg_count
= (entry_inst
>> 8) & 7;
1743 int sreg_count
= (entry_inst
>> 6) & 3;
1745 /* The entry instruction always subtracts 32 from the SP. */
1746 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1748 /* Now we can calculate what the SP must have been at the
1749 start of the function prologue. */
1750 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1752 /* Check if a0-a3 were saved in the caller's argument save area. */
1753 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1755 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1756 set_reg_offset (reg
, sp
+ offset
);
1757 offset
+= MIPS_SAVED_REGSIZE
;
1760 /* Check if the ra register was pushed on the stack. */
1762 if (entry_inst
& 0x20)
1764 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1765 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1766 offset
-= MIPS_SAVED_REGSIZE
;
1769 /* Check if the s0 and s1 registers were pushed on the stack. */
1770 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1772 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1773 set_reg_offset (reg
, sp
+ offset
);
1774 offset
-= MIPS_SAVED_REGSIZE
;
1780 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1781 struct frame_info
*next_frame
, CORE_ADDR sp
)
1784 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1786 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1787 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1788 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1789 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1791 unsigned long inst
, high_word
, low_word
;
1794 /* Fetch the instruction. */
1795 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1797 /* Save some code by pre-extracting some useful fields. */
1798 high_word
= (inst
>> 16) & 0xffff;
1799 low_word
= inst
& 0xffff;
1800 reg
= high_word
& 0x1f;
1802 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1803 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1804 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1806 if (low_word
& 0x8000) /* negative stack adjustment? */
1807 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1809 /* Exit loop if a positive stack adjustment is found, which
1810 usually means that the stack cleanup code in the function
1811 epilogue is reached. */
1814 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1816 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1817 set_reg_offset (reg
, sp
+ low_word
);
1819 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1821 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1822 but the register size used is only 32 bits. Make the address
1823 for the saved register point to the lower 32 bits. */
1824 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1825 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1827 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1829 /* Old gcc frame, r30 is virtual frame pointer. */
1830 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1831 frame_addr
= sp
+ low_word
;
1832 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1834 unsigned alloca_adjust
;
1835 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1836 frame_addr
= read_next_frame_reg (next_frame
, 30);
1837 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1838 if (alloca_adjust
> 0)
1840 /* FP > SP + frame_size. This may be because
1841 * of an alloca or somethings similar.
1842 * Fix sp to "pre-alloca" value, and try again.
1844 sp
+= alloca_adjust
;
1849 /* move $30,$sp. With different versions of gas this will be either
1850 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1851 Accept any one of these. */
1852 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1854 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1855 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1857 unsigned alloca_adjust
;
1858 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1859 frame_addr
= read_next_frame_reg (next_frame
, 30);
1860 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1861 if (alloca_adjust
> 0)
1863 /* FP > SP + frame_size. This may be because
1864 * of an alloca or somethings similar.
1865 * Fix sp to "pre-alloca" value, and try again.
1867 sp
+= alloca_adjust
;
1872 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1874 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1875 set_reg_offset (reg
, frame_addr
+ low_word
);
1880 static mips_extra_func_info_t
1881 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1882 struct frame_info
*next_frame
, int cur_frame
)
1887 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1893 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1894 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1895 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1896 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1897 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1899 if (start_pc
+ 200 < limit_pc
)
1900 limit_pc
= start_pc
+ 200;
1901 if (pc_is_mips16 (start_pc
))
1902 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1904 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1905 return &temp_proc_desc
;
1908 struct mips_objfile_private
1914 /* Global used to communicate between non_heuristic_proc_desc and
1915 compare_pdr_entries within qsort (). */
1916 static bfd
*the_bfd
;
1919 compare_pdr_entries (const void *a
, const void *b
)
1921 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
1922 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
1926 else if (lhs
== rhs
)
1932 static mips_extra_func_info_t
1933 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1935 CORE_ADDR startaddr
;
1936 mips_extra_func_info_t proc_desc
;
1937 struct block
*b
= block_for_pc (pc
);
1939 struct obj_section
*sec
;
1940 struct mips_objfile_private
*priv
;
1942 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
1945 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1947 *addrptr
= startaddr
;
1951 sec
= find_pc_section (pc
);
1954 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
1956 /* Search the ".pdr" section generated by GAS. This includes most of
1957 the information normally found in ECOFF PDRs. */
1959 the_bfd
= sec
->objfile
->obfd
;
1961 && (the_bfd
->format
== bfd_object
1962 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
1963 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
1965 /* Right now GAS only outputs the address as a four-byte sequence.
1966 This means that we should not bother with this method on 64-bit
1967 targets (until that is fixed). */
1969 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1970 sizeof (struct mips_objfile_private
));
1972 sec
->objfile
->obj_private
= priv
;
1974 else if (priv
== NULL
)
1978 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1979 sizeof (struct mips_objfile_private
));
1981 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
1984 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
1985 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
1987 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
1988 priv
->contents
, 0, priv
->size
);
1990 /* In general, the .pdr section is sorted. However, in the
1991 presence of multiple code sections (and other corner cases)
1992 it can become unsorted. Sort it so that we can use a faster
1994 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
1999 sec
->objfile
->obj_private
= priv
;
2003 if (priv
->size
!= 0)
2009 high
= priv
->size
/ 32;
2015 mid
= (low
+ high
) / 2;
2017 ptr
= priv
->contents
+ mid
* 32;
2018 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2019 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2020 SECT_OFF_TEXT (sec
->objfile
));
2021 if (pdr_pc
== startaddr
)
2023 if (pdr_pc
> startaddr
)
2028 while (low
!= high
);
2032 struct symbol
*sym
= find_pc_function (pc
);
2034 /* Fill in what we need of the proc_desc. */
2035 proc_desc
= (mips_extra_func_info_t
)
2036 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2037 sizeof (struct mips_extra_func_info
));
2038 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2040 /* Only used for dummy frames. */
2041 PROC_HIGH_ADDR (proc_desc
) = 0;
2043 PROC_FRAME_OFFSET (proc_desc
)
2044 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2045 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2047 PROC_FRAME_ADJUST (proc_desc
) = 0;
2048 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2050 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2052 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2054 PROC_FREG_OFFSET (proc_desc
)
2055 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2056 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2058 proc_desc
->pdr
.isym
= (long) sym
;
2068 if (startaddr
> BLOCK_START (b
))
2070 /* This is the "pathological" case referred to in a comment in
2071 print_frame_info. It might be better to move this check into
2076 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2078 /* If we never found a PDR for this function in symbol reading, then
2079 examine prologues to find the information. */
2082 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2083 if (PROC_FRAME_REG (proc_desc
) == -1)
2093 static mips_extra_func_info_t
2094 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2096 mips_extra_func_info_t proc_desc
;
2097 CORE_ADDR startaddr
;
2099 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2103 /* IF this is the topmost frame AND
2104 * (this proc does not have debugging information OR
2105 * the PC is in the procedure prologue)
2106 * THEN create a "heuristic" proc_desc (by analyzing
2107 * the actual code) to replace the "official" proc_desc.
2109 if (next_frame
== NULL
)
2111 struct symtab_and_line val
;
2112 struct symbol
*proc_symbol
=
2113 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2117 val
= find_pc_line (BLOCK_START
2118 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2120 val
.pc
= val
.end
? val
.end
: pc
;
2122 if (!proc_symbol
|| pc
< val
.pc
)
2124 mips_extra_func_info_t found_heuristic
=
2125 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2126 pc
, next_frame
, cur_frame
);
2127 if (found_heuristic
)
2128 proc_desc
= found_heuristic
;
2134 /* Is linked_proc_desc_table really necessary? It only seems to be used
2135 by procedure call dummys. However, the procedures being called ought
2136 to have their own proc_descs, and even if they don't,
2137 heuristic_proc_desc knows how to create them! */
2139 register struct linked_proc_info
*link
;
2141 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2142 if (PROC_LOW_ADDR (&link
->info
) <= pc
2143 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2147 startaddr
= heuristic_proc_start (pc
);
2150 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2156 get_frame_pointer (struct frame_info
*frame
,
2157 mips_extra_func_info_t proc_desc
)
2159 return ADDR_BITS_REMOVE (
2160 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
2161 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2164 mips_extra_func_info_t cached_proc_desc
;
2167 mips_frame_chain (struct frame_info
*frame
)
2169 mips_extra_func_info_t proc_desc
;
2171 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2173 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2176 /* Check if the PC is inside a call stub. If it is, fetch the
2177 PC of the caller of that stub. */
2178 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2181 /* Look up the procedure descriptor for this PC. */
2182 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2186 cached_proc_desc
= proc_desc
;
2188 /* If no frame pointer and frame size is zero, we must be at end
2189 of stack (or otherwise hosed). If we don't check frame size,
2190 we loop forever if we see a zero size frame. */
2191 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2192 && PROC_FRAME_OFFSET (proc_desc
) == 0
2193 /* The previous frame from a sigtramp frame might be frameless
2194 and have frame size zero. */
2195 && !frame
->signal_handler_caller
)
2198 return get_frame_pointer (frame
, proc_desc
);
2202 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2206 /* Use proc_desc calculated in frame_chain */
2207 mips_extra_func_info_t proc_desc
=
2208 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2210 fci
->extra_info
= (struct frame_extra_info
*)
2211 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2213 fci
->saved_regs
= NULL
;
2214 fci
->extra_info
->proc_desc
=
2215 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2218 /* Fixup frame-pointer - only needed for top frame */
2219 /* This may not be quite right, if proc has a real frame register.
2220 Get the value of the frame relative sp, procedure might have been
2221 interrupted by a signal at it's very start. */
2222 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2223 && !PROC_DESC_IS_DUMMY (proc_desc
))
2224 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2226 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2228 if (proc_desc
== &temp_proc_desc
)
2232 /* Do not set the saved registers for a sigtramp frame,
2233 mips_find_saved_registers will do that for us.
2234 We can't use fci->signal_handler_caller, it is not yet set. */
2235 find_pc_partial_function (fci
->pc
, &name
,
2236 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2237 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2239 frame_saved_regs_zalloc (fci
);
2240 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2241 fci
->saved_regs
[PC_REGNUM
]
2242 = fci
->saved_regs
[RA_REGNUM
];
2246 /* hack: if argument regs are saved, guess these contain args */
2247 /* assume we can't tell how many args for now */
2248 fci
->extra_info
->num_args
= -1;
2249 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2251 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2253 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2260 /* MIPS stack frames are almost impenetrable. When execution stops,
2261 we basically have to look at symbol information for the function
2262 that we stopped in, which tells us *which* register (if any) is
2263 the base of the frame pointer, and what offset from that register
2264 the frame itself is at.
2266 This presents a problem when trying to examine a stack in memory
2267 (that isn't executing at the moment), using the "frame" command. We
2268 don't have a PC, nor do we have any registers except SP.
2270 This routine takes two arguments, SP and PC, and tries to make the
2271 cached frames look as if these two arguments defined a frame on the
2272 cache. This allows the rest of info frame to extract the important
2273 arguments without difficulty. */
2276 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2279 error ("MIPS frame specifications require two arguments: sp and pc");
2281 return create_new_frame (argv
[0], argv
[1]);
2284 /* According to the current ABI, should the type be passed in a
2285 floating-point register (assuming that there is space)? When there
2286 is no FPU, FP are not even considered as possibile candidates for
2287 FP registers and, consequently this returns false - forces FP
2288 arguments into integer registers. */
2291 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2293 return ((typecode
== TYPE_CODE_FLT
2295 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2296 && TYPE_NFIELDS (arg_type
) == 1
2297 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2298 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2301 /* On o32, argument passing in GPRs depends on the alignment of the type being
2302 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2305 mips_type_needs_double_align (struct type
*type
)
2307 enum type_code typecode
= TYPE_CODE (type
);
2309 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2311 else if (typecode
== TYPE_CODE_STRUCT
)
2313 if (TYPE_NFIELDS (type
) < 1)
2315 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2317 else if (typecode
== TYPE_CODE_UNION
)
2321 n
= TYPE_NFIELDS (type
);
2322 for (i
= 0; i
< n
; i
++)
2323 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2331 mips_push_arguments (int nargs
,
2332 struct value
**args
,
2335 CORE_ADDR struct_addr
)
2341 int stack_offset
= 0;
2343 /* Macros to round N up or down to the next A boundary; A must be
2345 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2346 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2348 /* First ensure that the stack and structure return address (if any)
2349 are properly aligned. The stack has to be at least 64-bit aligned
2350 even on 32-bit machines, because doubles must be 64-bit aligned.
2351 On at least one MIPS variant, stack frames need to be 128-bit
2352 aligned, so we round to this widest known alignment. */
2353 sp
= ROUND_DOWN (sp
, 16);
2354 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2356 /* Now make space on the stack for the args. We allocate more
2357 than necessary for EABI, because the first few arguments are
2358 passed in registers, but that's OK. */
2359 for (argnum
= 0; argnum
< nargs
; argnum
++)
2360 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2361 sp
-= ROUND_UP (len
, 16);
2364 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2365 (long) sp
, ROUND_UP (len
, 16));
2367 /* Initialize the integer and float register pointers. */
2369 float_argreg
= FPA0_REGNUM
;
2371 /* the struct_return pointer occupies the first parameter-passing reg */
2375 fprintf_unfiltered (gdb_stdlog
,
2376 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2377 argreg
, (long) struct_addr
);
2378 write_register (argreg
++, struct_addr
);
2379 if (MIPS_REGS_HAVE_HOME_P
)
2380 stack_offset
+= MIPS_STACK_ARGSIZE
;
2383 /* Now load as many as possible of the first arguments into
2384 registers, and push the rest onto the stack. Loop thru args
2385 from first to last. */
2386 for (argnum
= 0; argnum
< nargs
; argnum
++)
2389 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2390 struct value
*arg
= args
[argnum
];
2391 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2392 int len
= TYPE_LENGTH (arg_type
);
2393 enum type_code typecode
= TYPE_CODE (arg_type
);
2396 fprintf_unfiltered (gdb_stdlog
,
2397 "mips_push_arguments: %d len=%d type=%d",
2398 argnum
+ 1, len
, (int) typecode
);
2400 /* The EABI passes structures that do not fit in a register by
2401 reference. In all other cases, pass the structure by value. */
2403 && len
> MIPS_SAVED_REGSIZE
2404 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2406 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2407 typecode
= TYPE_CODE_PTR
;
2408 len
= MIPS_SAVED_REGSIZE
;
2411 fprintf_unfiltered (gdb_stdlog
, " push");
2414 val
= (char *) VALUE_CONTENTS (arg
);
2416 /* 32-bit ABIs always start floating point arguments in an
2417 even-numbered floating point register. Round the FP register
2418 up before the check to see if there are any FP registers
2419 left. Non MIPS_EABI targets also pass the FP in the integer
2420 registers so also round up normal registers. */
2421 if (!FP_REGISTER_DOUBLE
2422 && fp_register_arg_p (typecode
, arg_type
))
2424 if ((float_argreg
& 1))
2428 /* Floating point arguments passed in registers have to be
2429 treated specially. On 32-bit architectures, doubles
2430 are passed in register pairs; the even register gets
2431 the low word, and the odd register gets the high word.
2432 On non-EABI processors, the first two floating point arguments are
2433 also copied to general registers, because MIPS16 functions
2434 don't use float registers for arguments. This duplication of
2435 arguments in general registers can't hurt non-MIPS16 functions
2436 because those registers are normally skipped. */
2437 /* MIPS_EABI squeezes a struct that contains a single floating
2438 point value into an FP register instead of pushing it onto the
2440 if (fp_register_arg_p (typecode
, arg_type
)
2441 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2443 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2445 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2446 unsigned long regval
;
2448 /* Write the low word of the double to the even register(s). */
2449 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2451 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2452 float_argreg
, phex (regval
, 4));
2453 write_register (float_argreg
++, regval
);
2457 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2458 argreg
, phex (regval
, 4));
2459 write_register (argreg
++, regval
);
2462 /* Write the high word of the double to the odd register(s). */
2463 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2465 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2466 float_argreg
, phex (regval
, 4));
2467 write_register (float_argreg
++, regval
);
2471 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2472 argreg
, phex (regval
, 4));
2473 write_register (argreg
++, regval
);
2479 /* This is a floating point value that fits entirely
2480 in a single register. */
2481 /* On 32 bit ABI's the float_argreg is further adjusted
2482 above to ensure that it is even register aligned. */
2483 LONGEST regval
= extract_unsigned_integer (val
, len
);
2485 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2486 float_argreg
, phex (regval
, len
));
2487 write_register (float_argreg
++, regval
);
2490 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2491 registers for each argument. The below is (my
2492 guess) to ensure that the corresponding integer
2493 register has reserved the same space. */
2495 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2496 argreg
, phex (regval
, len
));
2497 write_register (argreg
, regval
);
2498 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2501 /* Reserve space for the FP register. */
2502 if (MIPS_REGS_HAVE_HOME_P
)
2503 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2507 /* Copy the argument to general registers or the stack in
2508 register-sized pieces. Large arguments are split between
2509 registers and stack. */
2510 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2511 are treated specially: Irix cc passes them in registers
2512 where gcc sometimes puts them on the stack. For maximum
2513 compatibility, we will put them in both places. */
2514 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2515 (len
% MIPS_SAVED_REGSIZE
!= 0));
2516 /* Structures should be aligned to eight bytes (even arg registers)
2517 on MIPS_ABI_O32 if their first member has double precision. */
2518 if (gdbarch_tdep (current_gdbarch
)->mips_abi
== MIPS_ABI_O32
2519 && mips_type_needs_double_align (arg_type
))
2524 /* Note: Floating-point values that didn't fit into an FP
2525 register are only written to memory. */
2528 /* Rememer if the argument was written to the stack. */
2529 int stack_used_p
= 0;
2530 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2533 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2536 /* Write this portion of the argument to the stack. */
2537 if (argreg
> MIPS_LAST_ARG_REGNUM
2539 || fp_register_arg_p (typecode
, arg_type
))
2541 /* Should shorter than int integer values be
2542 promoted to int before being stored? */
2543 int longword_offset
= 0;
2546 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2548 if (MIPS_STACK_ARGSIZE
== 8 &&
2549 (typecode
== TYPE_CODE_INT
||
2550 typecode
== TYPE_CODE_PTR
||
2551 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2552 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2553 else if ((typecode
== TYPE_CODE_STRUCT
||
2554 typecode
== TYPE_CODE_UNION
) &&
2555 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2556 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2561 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2562 (long) stack_offset
);
2563 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2564 (long) longword_offset
);
2567 addr
= sp
+ stack_offset
+ longword_offset
;
2572 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2573 for (i
= 0; i
< partial_len
; i
++)
2575 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2578 write_memory (addr
, val
, partial_len
);
2581 /* Note!!! This is NOT an else clause. Odd sized
2582 structs may go thru BOTH paths. Floating point
2583 arguments will not. */
2584 /* Write this portion of the argument to a general
2585 purpose register. */
2586 if (argreg
<= MIPS_LAST_ARG_REGNUM
2587 && !fp_register_arg_p (typecode
, arg_type
))
2589 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2591 /* A non-floating-point argument being passed in a
2592 general register. If a struct or union, and if
2593 the remaining length is smaller than the register
2594 size, we have to adjust the register value on
2597 It does not seem to be necessary to do the
2598 same for integral types.
2600 Also don't do this adjustment on EABI and O64
2603 cagney/2001-07-23: gdb/179: Also, GCC, when
2604 outputting LE O32 with sizeof (struct) <
2605 MIPS_SAVED_REGSIZE, generates a left shift as
2606 part of storing the argument in a register a
2607 register (the left shift isn't generated when
2608 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2609 is quite possible that this is GCC contradicting
2610 the LE/O32 ABI, GDB has not been adjusted to
2611 accommodate this. Either someone needs to
2612 demonstrate that the LE/O32 ABI specifies such a
2613 left shift OR this new ABI gets identified as
2614 such and GDB gets tweaked accordingly. */
2617 && MIPS_SAVED_REGSIZE
< 8
2618 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2619 && partial_len
< MIPS_SAVED_REGSIZE
2620 && (typecode
== TYPE_CODE_STRUCT
||
2621 typecode
== TYPE_CODE_UNION
))
2622 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2626 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2628 phex (regval
, MIPS_SAVED_REGSIZE
));
2629 write_register (argreg
, regval
);
2632 /* If this is the old ABI, prevent subsequent floating
2633 point arguments from being passed in floating point
2636 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2642 /* Compute the the offset into the stack at which we
2643 will copy the next parameter.
2645 In older ABIs, the caller reserved space for
2646 registers that contained arguments. This was loosely
2647 refered to as their "home". Consequently, space is
2650 In the new EABI (and the NABI32), the stack_offset
2651 only needs to be adjusted when it has been used.. */
2653 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2654 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2658 fprintf_unfiltered (gdb_stdlog
, "\n");
2661 /* Return adjusted stack pointer. */
2666 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2668 /* Set the return address register to point to the entry
2669 point of the program, where a breakpoint lies in wait. */
2670 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2675 mips_push_register (CORE_ADDR
* sp
, int regno
)
2677 char buffer
[MAX_REGISTER_RAW_SIZE
];
2680 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2682 regsize
= MIPS_SAVED_REGSIZE
;
2683 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2684 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2689 regsize
= REGISTER_RAW_SIZE (regno
);
2693 read_register_gen (regno
, buffer
);
2694 write_memory (*sp
, buffer
+ offset
, regsize
);
2697 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2698 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2701 mips_push_dummy_frame (void)
2704 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2705 xmalloc (sizeof (struct linked_proc_info
));
2706 mips_extra_func_info_t proc_desc
= &link
->info
;
2707 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2708 CORE_ADDR old_sp
= sp
;
2709 link
->next
= linked_proc_desc_table
;
2710 linked_proc_desc_table
= link
;
2712 /* FIXME! are these correct ? */
2713 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2714 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2715 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2716 #define FLOAT_SINGLE_REG_SAVE_MASK \
2717 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2719 * The registers we must save are all those not preserved across
2720 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2721 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2722 * and FP Control/Status registers.
2725 * Dummy frame layout:
2728 * Saved MMHI, MMLO, FPC_CSR
2733 * Saved D18 (i.e. F19, F18)
2735 * Saved D0 (i.e. F1, F0)
2736 * Argument build area and stack arguments written via mips_push_arguments
2740 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2741 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2742 PROC_FRAME_OFFSET (proc_desc
) = 0;
2743 PROC_FRAME_ADJUST (proc_desc
) = 0;
2744 mips_push_register (&sp
, PC_REGNUM
);
2745 mips_push_register (&sp
, HI_REGNUM
);
2746 mips_push_register (&sp
, LO_REGNUM
);
2747 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2749 /* Save general CPU registers */
2750 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2751 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2752 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2753 for (ireg
= 32; --ireg
>= 0;)
2754 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2755 mips_push_register (&sp
, ireg
);
2757 /* Save floating point registers starting with high order word */
2758 PROC_FREG_MASK (proc_desc
) =
2759 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2760 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2761 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2763 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2764 for (ireg
= 32; --ireg
>= 0;)
2765 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2766 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2768 /* Update the frame pointer for the call dummy and the stack pointer.
2769 Set the procedure's starting and ending addresses to point to the
2770 call dummy address at the entry point. */
2771 write_register (PUSH_FP_REGNUM
, old_sp
);
2772 write_register (SP_REGNUM
, sp
);
2773 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2774 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2775 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2776 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2780 mips_pop_frame (void)
2782 register int regnum
;
2783 struct frame_info
*frame
= get_current_frame ();
2784 CORE_ADDR new_sp
= FRAME_FP (frame
);
2786 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2788 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2789 if (frame
->saved_regs
== NULL
)
2790 mips_find_saved_regs (frame
);
2791 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2793 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2794 && frame
->saved_regs
[regnum
])
2795 write_register (regnum
,
2796 read_memory_integer (frame
->saved_regs
[regnum
],
2797 MIPS_SAVED_REGSIZE
));
2799 write_register (SP_REGNUM
, new_sp
);
2800 flush_cached_frames ();
2802 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2804 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2806 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2808 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2810 if (&pi_ptr
->info
== proc_desc
)
2815 error ("Can't locate dummy extra frame info\n");
2817 if (prev_ptr
!= NULL
)
2818 prev_ptr
->next
= pi_ptr
->next
;
2820 linked_proc_desc_table
= pi_ptr
->next
;
2824 write_register (HI_REGNUM
,
2825 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2826 MIPS_SAVED_REGSIZE
));
2827 write_register (LO_REGNUM
,
2828 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2829 MIPS_SAVED_REGSIZE
));
2830 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2831 write_register (FCRCS_REGNUM
,
2832 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2833 MIPS_SAVED_REGSIZE
));
2837 /* Floating point register management.
2839 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
2840 64bit operations, these early MIPS cpus treat fp register pairs
2841 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
2842 registers and offer a compatibility mode that emulates the MIPS2 fp
2843 model. When operating in MIPS2 fp compat mode, later cpu's split
2844 double precision floats into two 32-bit chunks and store them in
2845 consecutive fp regs. To display 64-bit floats stored in this
2846 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
2847 Throw in user-configurable endianness and you have a real mess.
2849 The way this works is:
2850 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
2851 double-precision value will be split across two logical registers.
2852 The lower-numbered logical register will hold the low-order bits,
2853 regardless of the processor's endianness.
2854 - If we are on a 64-bit processor, and we are looking for a
2855 single-precision value, it will be in the low ordered bits
2856 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
2857 save slot in memory.
2858 - If we are in 64-bit mode, everything is straightforward.
2860 Note that this code only deals with "live" registers at the top of the
2861 stack. We will attempt to deal with saved registers later, when
2862 the raw/cooked register interface is in place. (We need a general
2863 interface that can deal with dynamic saved register sizes -- fp
2864 regs could be 32 bits wide in one frame and 64 on the frame above
2867 static struct type
*
2868 mips_float_register_type (void)
2870 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2871 return builtin_type_ieee_single_big
;
2873 return builtin_type_ieee_single_little
;
2876 static struct type
*
2877 mips_double_register_type (void)
2879 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2880 return builtin_type_ieee_double_big
;
2882 return builtin_type_ieee_double_little
;
2885 /* Copy a 32-bit single-precision value from the current frame
2886 into rare_buffer. */
2889 mips_read_fp_register_single (int regno
, char *rare_buffer
)
2891 int raw_size
= REGISTER_RAW_SIZE (regno
);
2892 char *raw_buffer
= alloca (raw_size
);
2894 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
2895 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2898 /* We have a 64-bit value for this register. Find the low-order
2902 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2907 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
2911 memcpy (rare_buffer
, raw_buffer
, 4);
2915 /* Copy a 64-bit double-precision value from the current frame into
2916 rare_buffer. This may include getting half of it from the next
2920 mips_read_fp_register_double (int regno
, char *rare_buffer
)
2922 int raw_size
= REGISTER_RAW_SIZE (regno
);
2924 if (raw_size
== 8 && !mips2_fp_compat ())
2926 /* We have a 64-bit value for this register, and we should use
2928 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
2929 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
2933 if ((regno
- FP0_REGNUM
) & 1)
2934 internal_error (__FILE__
, __LINE__
,
2935 "mips_read_fp_register_double: bad access to "
2936 "odd-numbered FP register");
2938 /* mips_read_fp_register_single will find the correct 32 bits from
2940 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2942 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
2943 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
2947 mips_read_fp_register_single (regno
, rare_buffer
);
2948 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
2954 mips_print_register (int regnum
, int all
)
2956 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2958 /* Get the data in raw format. */
2959 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
2961 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2965 /* If we have a actual 32-bit floating point register (or we are in
2966 32-bit compatibility mode), and the register is even-numbered,
2967 also print it as a double (spanning two registers). */
2968 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2969 && (REGISTER_RAW_SIZE (regnum
) == 4
2970 || mips2_fp_compat ())
2971 && !((regnum
- FP0_REGNUM
) & 1))
2973 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2975 mips_read_fp_register_double (regnum
, dbuffer
);
2977 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2978 val_print (mips_double_register_type (), dbuffer
, 0, 0,
2979 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2980 printf_filtered ("); ");
2982 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2984 /* The problem with printing numeric register names (r26, etc.) is that
2985 the user can't use them on input. Probably the best solution is to
2986 fix it so that either the numeric or the funky (a2, etc.) names
2987 are accepted on input. */
2988 if (regnum
< MIPS_NUMREGS
)
2989 printf_filtered ("(r%d): ", regnum
);
2991 printf_filtered (": ");
2993 /* If virtual format is floating, print it that way. */
2994 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2995 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
2997 /* We have a meaningful 64-bit value in this register. Show
2998 it as a 32-bit float and a 64-bit double. */
2999 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3001 printf_filtered (" (float) ");
3002 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3003 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3004 printf_filtered (", (double) ");
3005 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3006 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3009 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3010 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3011 /* Else print as integer in hex. */
3016 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3017 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3021 print_scalar_formatted (raw_buffer
+ offset
,
3022 REGISTER_VIRTUAL_TYPE (regnum
),
3023 'x', 0, gdb_stdout
);
3027 /* Replacement for generic do_registers_info.
3028 Print regs in pretty columns. */
3031 do_fp_register_row (int regnum
)
3032 { /* do values for FP (float) regs */
3034 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3035 int inv1
, inv2
, inv3
;
3037 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3039 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3041 /* 4-byte registers: we can fit two registers per row. */
3042 /* Also print every pair of 4-byte regs as an 8-byte double. */
3043 mips_read_fp_register_single (regnum
, raw_buffer
);
3044 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3046 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3047 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3049 mips_read_fp_register_double (regnum
, raw_buffer
);
3050 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3052 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
3054 printf_filtered (": <invalid float>");
3056 printf_filtered ("%-17.9g", flt1
);
3058 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
3060 printf_filtered (": <invalid float>");
3062 printf_filtered ("%-17.9g", flt2
);
3064 printf_filtered (" dbl: ");
3066 printf_filtered ("<invalid double>");
3068 printf_filtered ("%-24.17g", doub
);
3069 printf_filtered ("\n");
3071 /* may want to do hex display here (future enhancement) */
3076 /* Eight byte registers: print each one as float AND as double. */
3077 mips_read_fp_register_single (regnum
, raw_buffer
);
3078 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
3080 mips_read_fp_register_double (regnum
, raw_buffer
);
3081 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
3083 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
3085 printf_filtered ("<invalid float>");
3087 printf_filtered ("flt: %-17.9g", flt1
);
3089 printf_filtered (" dbl: ");
3091 printf_filtered ("<invalid double>");
3093 printf_filtered ("%-24.17g", doub
);
3095 printf_filtered ("\n");
3096 /* may want to do hex display here (future enhancement) */
3102 /* Print a row's worth of GP (int) registers, with name labels above */
3105 do_gp_register_row (int regnum
)
3107 /* do values for GP (int) regs */
3108 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3109 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
3111 int start_regnum
= regnum
;
3112 int numregs
= NUM_REGS
;
3115 /* For GP registers, we print a separate row of names above the vals */
3116 printf_filtered (" ");
3117 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3119 if (*REGISTER_NAME (regnum
) == '\0')
3120 continue; /* unused register */
3121 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3122 break; /* end the row: reached FP register */
3123 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
3124 REGISTER_NAME (regnum
));
3127 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
3128 start_regnum
); /* print the R0 to R31 names */
3130 regnum
= start_regnum
; /* go back to start of row */
3131 /* now print the values in hex, 4 or 8 to the row */
3132 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
3134 if (*REGISTER_NAME (regnum
) == '\0')
3135 continue; /* unused register */
3136 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3137 break; /* end row: reached FP register */
3138 /* OK: get the data in raw format. */
3139 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3140 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3141 /* pad small registers */
3142 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
3143 printf_filtered (" ");
3144 /* Now print the register value in hex, endian order. */
3145 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3146 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3147 byte
< REGISTER_RAW_SIZE (regnum
);
3149 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3151 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
3154 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
3155 printf_filtered (" ");
3158 if (col
> 0) /* ie. if we actually printed anything... */
3159 printf_filtered ("\n");
3164 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
3167 mips_do_registers_info (int regnum
, int fpregs
)
3169 if (regnum
!= -1) /* do one specified register */
3171 if (*(REGISTER_NAME (regnum
)) == '\0')
3172 error ("Not a valid register for the current processor type");
3174 mips_print_register (regnum
, 0);
3175 printf_filtered ("\n");
3178 /* do all (or most) registers */
3181 while (regnum
< NUM_REGS
)
3183 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3184 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
3185 regnum
= do_fp_register_row (regnum
); /* FP regs */
3187 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
3189 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
3194 /* Return number of args passed to a frame. described by FIP.
3195 Can return -1, meaning no way to tell. */
3198 mips_frame_num_args (struct frame_info
*frame
)
3203 /* Is this a branch with a delay slot? */
3205 static int is_delayed (unsigned long);
3208 is_delayed (unsigned long insn
)
3211 for (i
= 0; i
< NUMOPCODES
; ++i
)
3212 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
3213 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
3215 return (i
< NUMOPCODES
3216 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
3217 | INSN_COND_BRANCH_DELAY
3218 | INSN_COND_BRANCH_LIKELY
)));
3222 mips_step_skips_delay (CORE_ADDR pc
)
3224 char buf
[MIPS_INSTLEN
];
3226 /* There is no branch delay slot on MIPS16. */
3227 if (pc_is_mips16 (pc
))
3230 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
3231 /* If error reading memory, guess that it is not a delayed branch. */
3233 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
3237 /* Skip the PC past function prologue instructions (32-bit version).
3238 This is a helper function for mips_skip_prologue. */
3241 mips32_skip_prologue (CORE_ADDR pc
)
3245 int seen_sp_adjust
= 0;
3246 int load_immediate_bytes
= 0;
3248 /* Skip the typical prologue instructions. These are the stack adjustment
3249 instruction and the instructions that save registers on the stack
3250 or in the gcc frame. */
3251 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
3253 unsigned long high_word
;
3255 inst
= mips_fetch_instruction (pc
);
3256 high_word
= (inst
>> 16) & 0xffff;
3258 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
3259 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
3261 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
3262 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
3264 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
3265 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
3266 && (inst
& 0x001F0000)) /* reg != $zero */
3269 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
3271 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
3273 continue; /* reg != $zero */
3275 /* move $s8,$sp. With different versions of gas this will be either
3276 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
3277 Accept any one of these. */
3278 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3281 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
3283 else if (high_word
== 0x3c1c) /* lui $gp,n */
3285 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
3287 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3288 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
3290 /* The following instructions load $at or $t0 with an immediate
3291 value in preparation for a stack adjustment via
3292 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
3293 a local variable, so we accept them only before a stack adjustment
3294 instruction was seen. */
3295 else if (!seen_sp_adjust
)
3297 if (high_word
== 0x3c01 || /* lui $at,n */
3298 high_word
== 0x3c08) /* lui $t0,n */
3300 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3303 else if (high_word
== 0x3421 || /* ori $at,$at,n */
3304 high_word
== 0x3508 || /* ori $t0,$t0,n */
3305 high_word
== 0x3401 || /* ori $at,$zero,n */
3306 high_word
== 0x3408) /* ori $t0,$zero,n */
3308 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
3318 /* In a frameless function, we might have incorrectly
3319 skipped some load immediate instructions. Undo the skipping
3320 if the load immediate was not followed by a stack adjustment. */
3321 if (load_immediate_bytes
&& !seen_sp_adjust
)
3322 pc
-= load_immediate_bytes
;
3326 /* Skip the PC past function prologue instructions (16-bit version).
3327 This is a helper function for mips_skip_prologue. */
3330 mips16_skip_prologue (CORE_ADDR pc
)
3333 int extend_bytes
= 0;
3334 int prev_extend_bytes
;
3336 /* Table of instructions likely to be found in a function prologue. */
3339 unsigned short inst
;
3340 unsigned short mask
;
3347 , /* addiu $sp,offset */
3351 , /* daddiu $sp,offset */
3355 , /* sw reg,n($sp) */
3359 , /* sd reg,n($sp) */
3363 , /* sw $ra,n($sp) */
3367 , /* sd $ra,n($sp) */
3375 , /* sw $a0-$a3,n($s1) */
3379 , /* move reg,$a0-$a3 */
3383 , /* entry pseudo-op */
3387 , /* addiu $s1,$sp,n */
3390 } /* end of table marker */
3393 /* Skip the typical prologue instructions. These are the stack adjustment
3394 instruction and the instructions that save registers on the stack
3395 or in the gcc frame. */
3396 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3398 unsigned short inst
;
3401 inst
= mips_fetch_instruction (pc
);
3403 /* Normally we ignore an extend instruction. However, if it is
3404 not followed by a valid prologue instruction, we must adjust
3405 the pc back over the extend so that it won't be considered
3406 part of the prologue. */
3407 if ((inst
& 0xf800) == 0xf000) /* extend */
3409 extend_bytes
= MIPS16_INSTLEN
;
3412 prev_extend_bytes
= extend_bytes
;
3415 /* Check for other valid prologue instructions besides extend. */
3416 for (i
= 0; table
[i
].mask
!= 0; i
++)
3417 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3419 if (table
[i
].mask
!= 0) /* it was in table? */
3420 continue; /* ignore it */
3424 /* Return the current pc, adjusted backwards by 2 if
3425 the previous instruction was an extend. */
3426 return pc
- prev_extend_bytes
;
3432 /* To skip prologues, I use this predicate. Returns either PC itself
3433 if the code at PC does not look like a function prologue; otherwise
3434 returns an address that (if we're lucky) follows the prologue. If
3435 LENIENT, then we must skip everything which is involved in setting
3436 up the frame (it's OK to skip more, just so long as we don't skip
3437 anything which might clobber the registers which are being saved.
3438 We must skip more in the case where part of the prologue is in the
3439 delay slot of a non-prologue instruction). */
3442 mips_skip_prologue (CORE_ADDR pc
)
3444 /* See if we can determine the end of the prologue via the symbol table.
3445 If so, then return either PC, or the PC after the prologue, whichever
3448 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3450 if (post_prologue_pc
!= 0)
3451 return max (pc
, post_prologue_pc
);
3453 /* Can't determine prologue from the symbol table, need to examine
3456 if (pc_is_mips16 (pc
))
3457 return mips16_skip_prologue (pc
);
3459 return mips32_skip_prologue (pc
);
3462 /* Determine how a return value is stored within the MIPS register
3463 file, given the return type `valtype'. */
3465 struct return_value_word
3474 return_value_location (struct type
*valtype
,
3475 struct return_value_word
*hi
,
3476 struct return_value_word
*lo
)
3478 int len
= TYPE_LENGTH (valtype
);
3480 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3481 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3482 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3484 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3486 /* We need to break a 64bit float in two 32 bit halves and
3487 spread them across a floating-point register pair. */
3488 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3489 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3490 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3491 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3493 hi
->reg_offset
= lo
->reg_offset
;
3494 lo
->reg
= FP0_REGNUM
+ 0;
3495 hi
->reg
= FP0_REGNUM
+ 1;
3501 /* The floating point value fits in a single floating-point
3503 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3504 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3507 lo
->reg
= FP0_REGNUM
;
3518 /* Locate a result possibly spread across two registers. */
3520 lo
->reg
= regnum
+ 0;
3521 hi
->reg
= regnum
+ 1;
3522 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3523 && len
< MIPS_SAVED_REGSIZE
)
3525 /* "un-left-justify" the value in the low register */
3526 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3531 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3532 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3533 && len
< MIPS_SAVED_REGSIZE
* 2
3534 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3535 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3537 /* "un-left-justify" the value spread across two registers. */
3538 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3539 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3541 hi
->len
= len
- lo
->len
;
3545 /* Only perform a partial copy of the second register. */
3548 if (len
> MIPS_SAVED_REGSIZE
)
3550 lo
->len
= MIPS_SAVED_REGSIZE
;
3551 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3559 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3560 && REGISTER_RAW_SIZE (regnum
) == 8
3561 && MIPS_SAVED_REGSIZE
== 4)
3563 /* Account for the fact that only the least-signficant part
3564 of the register is being used */
3565 lo
->reg_offset
+= 4;
3566 hi
->reg_offset
+= 4;
3569 hi
->buf_offset
= lo
->len
;
3573 /* Given a return value in `regbuf' with a type `valtype', extract and
3574 copy its value into `valbuf'. */
3577 mips_extract_return_value (struct type
*valtype
,
3578 char regbuf
[REGISTER_BYTES
],
3581 struct return_value_word lo
;
3582 struct return_value_word hi
;
3583 return_value_location (valtype
, &hi
, &lo
);
3585 memcpy (valbuf
+ lo
.buf_offset
,
3586 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3590 memcpy (valbuf
+ hi
.buf_offset
,
3591 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3595 /* Given a return value in `valbuf' with a type `valtype', write it's
3596 value into the appropriate register. */
3599 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3601 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3602 struct return_value_word lo
;
3603 struct return_value_word hi
;
3604 return_value_location (valtype
, &hi
, &lo
);
3606 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3607 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3608 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3610 REGISTER_RAW_SIZE (lo
.reg
));
3614 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3615 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3616 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3618 REGISTER_RAW_SIZE (hi
.reg
));
3622 /* Exported procedure: Is PC in the signal trampoline code */
3625 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3627 if (sigtramp_address
== 0)
3629 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3632 /* Root of all "set mips "/"show mips " commands. This will eventually be
3633 used for all MIPS-specific commands. */
3636 show_mips_command (char *args
, int from_tty
)
3638 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3642 set_mips_command (char *args
, int from_tty
)
3644 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3645 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3648 /* Commands to show/set the MIPS FPU type. */
3651 show_mipsfpu_command (char *args
, int from_tty
)
3654 switch (MIPS_FPU_TYPE
)
3656 case MIPS_FPU_SINGLE
:
3657 fpu
= "single-precision";
3659 case MIPS_FPU_DOUBLE
:
3660 fpu
= "double-precision";
3663 fpu
= "absent (none)";
3666 internal_error (__FILE__
, __LINE__
, "bad switch");
3668 if (mips_fpu_type_auto
)
3669 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3672 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3678 set_mipsfpu_command (char *args
, int from_tty
)
3680 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3681 show_mipsfpu_command (args
, from_tty
);
3685 set_mipsfpu_single_command (char *args
, int from_tty
)
3687 mips_fpu_type
= MIPS_FPU_SINGLE
;
3688 mips_fpu_type_auto
= 0;
3689 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3693 set_mipsfpu_double_command (char *args
, int from_tty
)
3695 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3696 mips_fpu_type_auto
= 0;
3697 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3701 set_mipsfpu_none_command (char *args
, int from_tty
)
3703 mips_fpu_type
= MIPS_FPU_NONE
;
3704 mips_fpu_type_auto
= 0;
3705 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3709 set_mipsfpu_auto_command (char *args
, int from_tty
)
3711 mips_fpu_type_auto
= 1;
3714 /* Command to set the processor type. */
3717 mips_set_processor_type_command (char *args
, int from_tty
)
3721 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3723 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3724 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3725 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3727 /* Restore the value. */
3728 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3733 if (!mips_set_processor_type (tmp_mips_processor_type
))
3735 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3736 /* Restore its value. */
3737 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3742 mips_show_processor_type_command (char *args
, int from_tty
)
3746 /* Modify the actual processor type. */
3749 mips_set_processor_type (char *str
)
3756 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3758 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3760 mips_processor_type
= str
;
3761 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3763 /* FIXME tweak fpu flag too */
3770 /* Attempt to identify the particular processor model by reading the
3774 mips_read_processor_type (void)
3778 prid
= read_register (PRID_REGNUM
);
3780 if ((prid
& ~0xf) == 0x700)
3781 return savestring ("r3041", strlen ("r3041"));
3786 /* Just like reinit_frame_cache, but with the right arguments to be
3787 callable as an sfunc. */
3790 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3791 struct cmd_list_element
*c
)
3793 reinit_frame_cache ();
3797 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3799 mips_extra_func_info_t proc_desc
;
3801 /* Search for the function containing this address. Set the low bit
3802 of the address when searching, in case we were given an even address
3803 that is the start of a 16-bit function. If we didn't do this,
3804 the search would fail because the symbol table says the function
3805 starts at an odd address, i.e. 1 byte past the given address. */
3806 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3807 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3809 /* Make an attempt to determine if this is a 16-bit function. If
3810 the procedure descriptor exists and the address therein is odd,
3811 it's definitely a 16-bit function. Otherwise, we have to just
3812 guess that if the address passed in is odd, it's 16-bits. */
3814 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3815 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3817 info
->mach
= pc_is_mips16 (memaddr
) ?
3818 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3820 /* Round down the instruction address to the appropriate boundary. */
3821 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3823 /* Call the appropriate disassembler based on the target endian-ness. */
3824 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3825 return print_insn_big_mips (memaddr
, info
);
3827 return print_insn_little_mips (memaddr
, info
);
3830 /* Old-style breakpoint macros.
3831 The IDT board uses an unusual breakpoint value, and sometimes gets
3832 confused when it sees the usual MIPS breakpoint instruction. */
3834 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3835 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3836 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3837 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3838 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3839 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3840 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3841 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3843 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3844 counter value to determine whether a 16- or 32-bit breakpoint should be
3845 used. It returns a pointer to a string of bytes that encode a breakpoint
3846 instruction, stores the length of the string to *lenptr, and adjusts pc
3847 (if necessary) to point to the actual memory location where the
3848 breakpoint should be inserted. */
3850 const unsigned char *
3851 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3853 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3855 if (pc_is_mips16 (*pcptr
))
3857 static unsigned char mips16_big_breakpoint
[] =
3858 MIPS16_BIG_BREAKPOINT
;
3859 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3860 *lenptr
= sizeof (mips16_big_breakpoint
);
3861 return mips16_big_breakpoint
;
3865 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3866 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3867 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3869 *lenptr
= sizeof (big_breakpoint
);
3871 if (strcmp (target_shortname
, "mips") == 0)
3872 return idt_big_breakpoint
;
3873 else if (strcmp (target_shortname
, "ddb") == 0
3874 || strcmp (target_shortname
, "pmon") == 0
3875 || strcmp (target_shortname
, "lsi") == 0)
3876 return pmon_big_breakpoint
;
3878 return big_breakpoint
;
3883 if (pc_is_mips16 (*pcptr
))
3885 static unsigned char mips16_little_breakpoint
[] =
3886 MIPS16_LITTLE_BREAKPOINT
;
3887 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3888 *lenptr
= sizeof (mips16_little_breakpoint
);
3889 return mips16_little_breakpoint
;
3893 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3894 static unsigned char pmon_little_breakpoint
[] =
3895 PMON_LITTLE_BREAKPOINT
;
3896 static unsigned char idt_little_breakpoint
[] =
3897 IDT_LITTLE_BREAKPOINT
;
3899 *lenptr
= sizeof (little_breakpoint
);
3901 if (strcmp (target_shortname
, "mips") == 0)
3902 return idt_little_breakpoint
;
3903 else if (strcmp (target_shortname
, "ddb") == 0
3904 || strcmp (target_shortname
, "pmon") == 0
3905 || strcmp (target_shortname
, "lsi") == 0)
3906 return pmon_little_breakpoint
;
3908 return little_breakpoint
;
3913 /* If PC is in a mips16 call or return stub, return the address of the target
3914 PC, which is either the callee or the caller. There are several
3915 cases which must be handled:
3917 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3918 target PC is in $31 ($ra).
3919 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3920 and the target PC is in $2.
3921 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3922 before the jal instruction, this is effectively a call stub
3923 and the the target PC is in $2. Otherwise this is effectively
3924 a return stub and the target PC is in $18.
3926 See the source code for the stubs in gcc/config/mips/mips16.S for
3929 This function implements the SKIP_TRAMPOLINE_CODE macro.
3933 mips_skip_stub (CORE_ADDR pc
)
3936 CORE_ADDR start_addr
;
3938 /* Find the starting address and name of the function containing the PC. */
3939 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3942 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3943 target PC is in $31 ($ra). */
3944 if (strcmp (name
, "__mips16_ret_sf") == 0
3945 || strcmp (name
, "__mips16_ret_df") == 0)
3946 return read_signed_register (RA_REGNUM
);
3948 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3950 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3951 and the target PC is in $2. */
3952 if (name
[19] >= '0' && name
[19] <= '9')
3953 return read_signed_register (2);
3955 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3956 before the jal instruction, this is effectively a call stub
3957 and the the target PC is in $2. Otherwise this is effectively
3958 a return stub and the target PC is in $18. */
3959 else if (name
[19] == 's' || name
[19] == 'd')
3961 if (pc
== start_addr
)
3963 /* Check if the target of the stub is a compiler-generated
3964 stub. Such a stub for a function bar might have a name
3965 like __fn_stub_bar, and might look like this:
3970 la $1,bar (becomes a lui/addiu pair)
3972 So scan down to the lui/addi and extract the target
3973 address from those two instructions. */
3975 CORE_ADDR target_pc
= read_signed_register (2);
3979 /* See if the name of the target function is __fn_stub_*. */
3980 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3982 if (strncmp (name
, "__fn_stub_", 10) != 0
3983 && strcmp (name
, "etext") != 0
3984 && strcmp (name
, "_etext") != 0)
3987 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3988 The limit on the search is arbitrarily set to 20
3989 instructions. FIXME. */
3990 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3992 inst
= mips_fetch_instruction (target_pc
);
3993 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3994 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3995 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3996 return pc
| (inst
& 0xffff); /* low word */
3999 /* Couldn't find the lui/addui pair, so return stub address. */
4003 /* This is the 'return' part of a call stub. The return
4004 address is in $r18. */
4005 return read_signed_register (18);
4008 return 0; /* not a stub */
4012 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
4013 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
4016 mips_in_call_stub (CORE_ADDR pc
, char *name
)
4018 CORE_ADDR start_addr
;
4020 /* Find the starting address of the function containing the PC. If the
4021 caller didn't give us a name, look it up at the same time. */
4022 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
4025 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4027 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
4028 if (name
[19] >= '0' && name
[19] <= '9')
4030 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4031 before the jal instruction, this is effectively a call stub. */
4032 else if (name
[19] == 's' || name
[19] == 'd')
4033 return pc
== start_addr
;
4036 return 0; /* not a stub */
4040 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
4041 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
4044 mips_in_return_stub (CORE_ADDR pc
, char *name
)
4046 CORE_ADDR start_addr
;
4048 /* Find the starting address of the function containing the PC. */
4049 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
4052 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
4053 if (strcmp (name
, "__mips16_ret_sf") == 0
4054 || strcmp (name
, "__mips16_ret_df") == 0)
4057 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
4058 i.e. after the jal instruction, this is effectively a return stub. */
4059 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
4060 && (name
[19] == 's' || name
[19] == 'd')
4061 && pc
!= start_addr
)
4064 return 0; /* not a stub */
4068 /* Return non-zero if the PC is in a library helper function that should
4069 be ignored. This implements the IGNORE_HELPER_CALL macro. */
4072 mips_ignore_helper (CORE_ADDR pc
)
4076 /* Find the starting address and name of the function containing the PC. */
4077 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
4080 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
4081 that we want to ignore. */
4082 return (strcmp (name
, "__mips16_ret_sf") == 0
4083 || strcmp (name
, "__mips16_ret_df") == 0);
4087 /* Return a location where we can set a breakpoint that will be hit
4088 when an inferior function call returns. This is normally the
4089 program's entry point. Executables that don't have an entry
4090 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
4091 whose address is the location where the breakpoint should be placed. */
4094 mips_call_dummy_address (void)
4096 struct minimal_symbol
*sym
;
4098 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
4100 return SYMBOL_VALUE_ADDRESS (sym
);
4102 return entry_point_address ();
4106 /* If the current gcc for this target does not produce correct debugging
4107 information for float parameters, both prototyped and unprototyped, then
4108 define this macro. This forces gdb to always assume that floats are
4109 passed as doubles and then converted in the callee.
4111 For the mips chip, it appears that the debug info marks the parameters as
4112 floats regardless of whether the function is prototyped, but the actual
4113 values are passed as doubles for the non-prototyped case and floats for
4114 the prototyped case. Thus we choose to make the non-prototyped case work
4115 for C and break the prototyped case, since the non-prototyped case is
4116 probably much more common. (FIXME). */
4119 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
4121 return current_language
->la_language
== language_c
;
4124 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
4125 the register stored on the stack (32) is different to its real raw
4126 size (64). The below ensures that registers are fetched from the
4127 stack using their ABI size and then stored into the RAW_BUFFER
4128 using their raw size.
4130 The alternative to adding this function would be to add an ABI
4131 macro - REGISTER_STACK_SIZE(). */
4134 mips_get_saved_register (char *raw_buffer
,
4137 struct frame_info
*frame
,
4139 enum lval_type
*lval
)
4143 if (!target_has_registers
)
4144 error ("No registers.");
4146 /* Normal systems don't optimize out things with register numbers. */
4147 if (optimized
!= NULL
)
4149 addr
= find_saved_register (frame
, regnum
);
4153 *lval
= lval_memory
;
4154 if (regnum
== SP_REGNUM
)
4156 if (raw_buffer
!= NULL
)
4158 /* Put it back in target format. */
4159 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
4166 if (raw_buffer
!= NULL
)
4170 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
4172 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
4174 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
4175 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
4181 *lval
= lval_register
;
4182 addr
= REGISTER_BYTE (regnum
);
4183 if (raw_buffer
!= NULL
)
4184 read_register_gen (regnum
, raw_buffer
);
4190 /* Immediately after a function call, return the saved pc.
4191 Can't always go through the frames for this because on some machines
4192 the new frame is not set up until the new function executes
4193 some instructions. */
4196 mips_saved_pc_after_call (struct frame_info
*frame
)
4198 return read_signed_register (RA_REGNUM
);
4202 /* Convert a dbx stab register number (from `r' declaration) to a gdb
4206 mips_stab_reg_to_regnum (int num
)
4211 return num
+ FP0_REGNUM
- 38;
4214 /* Convert a ecoff register number to a gdb REGNUM */
4217 mips_ecoff_reg_to_regnum (int num
)
4222 return num
+ FP0_REGNUM
- 32;
4225 /* Convert an integer into an address. By first converting the value
4226 into a pointer and then extracting it signed, the address is
4227 guarenteed to be correctly sign extended. */
4230 mips_integer_to_address (struct type
*type
, void *buf
)
4232 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
4233 LONGEST val
= unpack_long (type
, buf
);
4234 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
4235 return extract_signed_integer (tmp
,
4236 TYPE_LENGTH (builtin_type_void_data_ptr
));
4240 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4242 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4243 const char *name
= bfd_get_section_name (abfd
, sect
);
4245 if (*abip
!= MIPS_ABI_UNKNOWN
)
4248 if (strncmp (name
, ".mdebug.", 8) != 0)
4251 if (strcmp (name
, ".mdebug.abi32") == 0)
4252 *abip
= MIPS_ABI_O32
;
4253 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4254 *abip
= MIPS_ABI_N32
;
4255 else if (strcmp (name
, ".mdebug.abiN64") == 0)
4256 *abip
= MIPS_ABI_N64
;
4257 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4258 *abip
= MIPS_ABI_O64
;
4259 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4260 *abip
= MIPS_ABI_EABI32
;
4261 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4262 *abip
= MIPS_ABI_EABI64
;
4264 warning ("unsupported ABI %s.", name
+ 8);
4267 static enum mips_abi
4268 global_mips_abi (void)
4272 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4273 if (mips_abi_strings
[i
] == mips_abi_string
)
4274 return (enum mips_abi
) i
;
4276 internal_error (__FILE__
, __LINE__
,
4277 "unknown ABI string");
4280 static struct gdbarch
*
4281 mips_gdbarch_init (struct gdbarch_info info
,
4282 struct gdbarch_list
*arches
)
4284 static LONGEST mips_call_dummy_words
[] =
4286 struct gdbarch
*gdbarch
;
4287 struct gdbarch_tdep
*tdep
;
4289 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4290 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4292 /* Reset the disassembly info, in case it was set to something
4294 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
4295 tm_print_insn_info
.arch
= bfd_arch_unknown
;
4296 tm_print_insn_info
.mach
= 0;
4302 /* First of all, extract the elf_flags, if available. */
4303 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4304 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4306 /* Try to determine the OS ABI of the object we are loading. If
4307 we end up with `unknown', just leave it that way. */
4308 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4311 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4312 switch ((elf_flags
& EF_MIPS_ABI
))
4314 case E_MIPS_ABI_O32
:
4315 mips_abi
= MIPS_ABI_O32
;
4317 case E_MIPS_ABI_O64
:
4318 mips_abi
= MIPS_ABI_O64
;
4320 case E_MIPS_ABI_EABI32
:
4321 mips_abi
= MIPS_ABI_EABI32
;
4323 case E_MIPS_ABI_EABI64
:
4324 mips_abi
= MIPS_ABI_EABI64
;
4327 if ((elf_flags
& EF_MIPS_ABI2
))
4328 mips_abi
= MIPS_ABI_N32
;
4330 mips_abi
= MIPS_ABI_UNKNOWN
;
4334 /* GCC creates a pseudo-section whose name describes the ABI. */
4335 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4336 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
4338 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
4339 Use the ABI from the last architecture if there is one. */
4340 if (info
.abfd
== NULL
&& arches
!= NULL
)
4341 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4343 /* Try the architecture for any hint of the corect ABI */
4344 if (mips_abi
== MIPS_ABI_UNKNOWN
4345 && info
.bfd_arch_info
!= NULL
4346 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4348 switch (info
.bfd_arch_info
->mach
)
4350 case bfd_mach_mips3900
:
4351 mips_abi
= MIPS_ABI_EABI32
;
4353 case bfd_mach_mips4100
:
4354 case bfd_mach_mips5000
:
4355 mips_abi
= MIPS_ABI_EABI64
;
4357 case bfd_mach_mips8000
:
4358 case bfd_mach_mips10000
:
4359 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
4360 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
4361 mips_abi
= MIPS_ABI_N64
;
4363 mips_abi
= MIPS_ABI_N32
;
4368 #ifdef MIPS_DEFAULT_ABI
4369 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4370 mips_abi
= MIPS_DEFAULT_ABI
;
4373 if (mips_abi
== MIPS_ABI_UNKNOWN
)
4374 mips_abi
= MIPS_ABI_O32
;
4376 /* Now that we have found what the ABI for this binary would be,
4377 check whether the user is overriding it. */
4378 found_abi
= mips_abi
;
4379 wanted_abi
= global_mips_abi ();
4380 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
4381 mips_abi
= wanted_abi
;
4385 fprintf_unfiltered (gdb_stdlog
,
4386 "mips_gdbarch_init: elf_flags = 0x%08x\n",
4388 fprintf_unfiltered (gdb_stdlog
,
4389 "mips_gdbarch_init: mips_abi = %d\n",
4391 fprintf_unfiltered (gdb_stdlog
,
4392 "mips_gdbarch_init: found_mips_abi = %d\n",
4396 /* try to find a pre-existing architecture */
4397 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4399 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4401 /* MIPS needs to be pedantic about which ABI the object is
4403 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
4405 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
4407 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
4408 return arches
->gdbarch
;
4411 /* Need a new architecture. Fill in a target specific vector. */
4412 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
4413 gdbarch
= gdbarch_alloc (&info
, tdep
);
4414 tdep
->elf_flags
= elf_flags
;
4415 tdep
->osabi
= osabi
;
4417 /* Initially set everything according to the default ABI/ISA. */
4418 set_gdbarch_short_bit (gdbarch
, 16);
4419 set_gdbarch_int_bit (gdbarch
, 32);
4420 set_gdbarch_float_bit (gdbarch
, 32);
4421 set_gdbarch_double_bit (gdbarch
, 64);
4422 set_gdbarch_long_double_bit (gdbarch
, 64);
4423 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
4424 tdep
->found_abi
= found_abi
;
4425 tdep
->mips_abi
= mips_abi
;
4430 tdep
->mips_default_saved_regsize
= 4;
4431 tdep
->mips_default_stack_argsize
= 4;
4432 tdep
->mips_fp_register_double
= 0;
4433 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4434 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4435 tdep
->mips_regs_have_home_p
= 1;
4436 tdep
->gdb_target_is_mips64
= 0;
4437 tdep
->default_mask_address_p
= 0;
4438 set_gdbarch_long_bit (gdbarch
, 32);
4439 set_gdbarch_ptr_bit (gdbarch
, 32);
4440 set_gdbarch_long_long_bit (gdbarch
, 64);
4443 tdep
->mips_default_saved_regsize
= 8;
4444 tdep
->mips_default_stack_argsize
= 8;
4445 tdep
->mips_fp_register_double
= 1;
4446 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4447 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4448 tdep
->mips_regs_have_home_p
= 1;
4449 tdep
->gdb_target_is_mips64
= 1;
4450 tdep
->default_mask_address_p
= 0;
4451 set_gdbarch_long_bit (gdbarch
, 32);
4452 set_gdbarch_ptr_bit (gdbarch
, 32);
4453 set_gdbarch_long_long_bit (gdbarch
, 64);
4455 case MIPS_ABI_EABI32
:
4456 tdep
->mips_default_saved_regsize
= 4;
4457 tdep
->mips_default_stack_argsize
= 4;
4458 tdep
->mips_fp_register_double
= 0;
4459 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4460 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4461 tdep
->mips_regs_have_home_p
= 0;
4462 tdep
->gdb_target_is_mips64
= 0;
4463 tdep
->default_mask_address_p
= 0;
4464 set_gdbarch_long_bit (gdbarch
, 32);
4465 set_gdbarch_ptr_bit (gdbarch
, 32);
4466 set_gdbarch_long_long_bit (gdbarch
, 64);
4468 case MIPS_ABI_EABI64
:
4469 tdep
->mips_default_saved_regsize
= 8;
4470 tdep
->mips_default_stack_argsize
= 8;
4471 tdep
->mips_fp_register_double
= 1;
4472 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4473 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4474 tdep
->mips_regs_have_home_p
= 0;
4475 tdep
->gdb_target_is_mips64
= 1;
4476 tdep
->default_mask_address_p
= 0;
4477 set_gdbarch_long_bit (gdbarch
, 64);
4478 set_gdbarch_ptr_bit (gdbarch
, 64);
4479 set_gdbarch_long_long_bit (gdbarch
, 64);
4482 tdep
->mips_default_saved_regsize
= 4;
4483 tdep
->mips_default_stack_argsize
= 8;
4484 tdep
->mips_fp_register_double
= 1;
4485 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4486 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4487 tdep
->mips_regs_have_home_p
= 0;
4488 tdep
->gdb_target_is_mips64
= 0;
4489 tdep
->default_mask_address_p
= 0;
4490 set_gdbarch_long_bit (gdbarch
, 32);
4491 set_gdbarch_ptr_bit (gdbarch
, 32);
4492 set_gdbarch_long_long_bit (gdbarch
, 64);
4494 /* Set up the disassembler info, so that we get the right
4495 register names from libopcodes. */
4496 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4497 tm_print_insn_info
.arch
= bfd_arch_mips
;
4498 if (info
.bfd_arch_info
!= NULL
4499 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4500 && info
.bfd_arch_info
->mach
)
4501 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4503 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4506 tdep
->mips_default_saved_regsize
= 8;
4507 tdep
->mips_default_stack_argsize
= 8;
4508 tdep
->mips_fp_register_double
= 1;
4509 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4510 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4511 tdep
->mips_regs_have_home_p
= 0;
4512 tdep
->gdb_target_is_mips64
= 1;
4513 tdep
->default_mask_address_p
= 0;
4514 set_gdbarch_long_bit (gdbarch
, 64);
4515 set_gdbarch_ptr_bit (gdbarch
, 64);
4516 set_gdbarch_long_long_bit (gdbarch
, 64);
4518 /* Set up the disassembler info, so that we get the right
4519 register names from libopcodes. */
4520 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4521 tm_print_insn_info
.arch
= bfd_arch_mips
;
4522 if (info
.bfd_arch_info
!= NULL
4523 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4524 && info
.bfd_arch_info
->mach
)
4525 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4527 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4530 internal_error (__FILE__
, __LINE__
,
4531 "unknown ABI in switch");
4534 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4535 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4538 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4539 flag in object files because to do so would make it impossible to
4540 link with libraries compiled without "-gp32". This is
4541 unnecessarily restrictive.
4543 We could solve this problem by adding "-gp32" multilibs to gcc,
4544 but to set this flag before gcc is built with such multilibs will
4545 break too many systems.''
4547 But even more unhelpfully, the default linker output target for
4548 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4549 for 64-bit programs - you need to change the ABI to change this,
4550 and not all gcc targets support that currently. Therefore using
4551 this flag to detect 32-bit mode would do the wrong thing given
4552 the current gcc - it would make GDB treat these 64-bit programs
4553 as 32-bit programs by default. */
4555 /* enable/disable the MIPS FPU */
4556 if (!mips_fpu_type_auto
)
4557 tdep
->mips_fpu_type
= mips_fpu_type
;
4558 else if (info
.bfd_arch_info
!= NULL
4559 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4560 switch (info
.bfd_arch_info
->mach
)
4562 case bfd_mach_mips3900
:
4563 case bfd_mach_mips4100
:
4564 case bfd_mach_mips4111
:
4565 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4567 case bfd_mach_mips4650
:
4568 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4571 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4575 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4577 /* MIPS version of register names. NOTE: At present the MIPS
4578 register name management is part way between the old -
4579 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4580 Further work on it is required. */
4581 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4582 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4583 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4584 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4585 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4586 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4588 /* Add/remove bits from an address. The MIPS needs be careful to
4589 ensure that all 32 bit addresses are sign extended to 64 bits. */
4590 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4592 /* There's a mess in stack frame creation. See comments in
4593 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4594 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4595 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4597 /* Map debug register numbers onto internal register numbers. */
4598 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4599 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4601 /* Initialize a frame */
4602 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4604 /* MIPS version of CALL_DUMMY */
4606 set_gdbarch_call_dummy_p (gdbarch
, 1);
4607 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4608 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4609 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4610 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4611 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4612 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4613 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4614 set_gdbarch_call_dummy_length (gdbarch
, 0);
4615 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4616 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4617 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4618 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4619 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4620 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4621 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4623 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4624 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4626 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4627 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4628 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4630 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4631 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4633 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
4634 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
4635 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
4637 /* Hook in OS ABI-specific overrides, if they have been registered. */
4638 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4644 mips_abi_update (char *ignore_args
, int from_tty
,
4645 struct cmd_list_element
*c
)
4647 struct gdbarch_info info
;
4649 /* Force the architecture to update, and (if it's a MIPS architecture)
4650 mips_gdbarch_init will take care of the rest. */
4651 gdbarch_info_init (&info
);
4652 gdbarch_update_p (info
);
4656 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4658 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4662 int ef_mips_32bitmode
;
4663 /* determine the ISA */
4664 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4682 /* determine the size of a pointer */
4683 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4684 fprintf_unfiltered (file
,
4685 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4687 fprintf_unfiltered (file
,
4688 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4690 fprintf_unfiltered (file
,
4691 "mips_dump_tdep: ef_mips_arch = %d\n",
4693 fprintf_unfiltered (file
,
4694 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4696 mips_abi_strings
[tdep
->mips_abi
]);
4697 fprintf_unfiltered (file
,
4698 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4699 mips_mask_address_p (),
4700 tdep
->default_mask_address_p
);
4702 fprintf_unfiltered (file
,
4703 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4704 FP_REGISTER_DOUBLE
);
4705 fprintf_unfiltered (file
,
4706 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4707 MIPS_DEFAULT_FPU_TYPE
,
4708 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4709 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4710 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4712 fprintf_unfiltered (file
,
4713 "mips_dump_tdep: MIPS_EABI = %d\n",
4715 fprintf_unfiltered (file
,
4716 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4717 MIPS_LAST_FP_ARG_REGNUM
,
4718 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4719 fprintf_unfiltered (file
,
4720 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4722 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4723 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4724 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4726 fprintf_unfiltered (file
,
4727 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4728 MIPS_DEFAULT_SAVED_REGSIZE
);
4729 fprintf_unfiltered (file
,
4730 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4731 FP_REGISTER_DOUBLE
);
4732 fprintf_unfiltered (file
,
4733 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4734 MIPS_REGS_HAVE_HOME_P
);
4735 fprintf_unfiltered (file
,
4736 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4737 MIPS_DEFAULT_STACK_ARGSIZE
);
4738 fprintf_unfiltered (file
,
4739 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4740 MIPS_STACK_ARGSIZE
);
4741 fprintf_unfiltered (file
,
4742 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4744 fprintf_unfiltered (file
,
4745 "mips_dump_tdep: A0_REGNUM = %d\n",
4747 fprintf_unfiltered (file
,
4748 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4749 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4750 fprintf_unfiltered (file
,
4751 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4752 XSTRING (ATTACH_DETACH
));
4753 fprintf_unfiltered (file
,
4754 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4756 fprintf_unfiltered (file
,
4757 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4758 fprintf_unfiltered (file
,
4759 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4761 fprintf_unfiltered (file
,
4762 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4764 fprintf_unfiltered (file
,
4765 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4767 fprintf_unfiltered (file
,
4768 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4769 XSTRING (DO_REGISTERS_INFO
));
4770 fprintf_unfiltered (file
,
4771 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4772 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4773 fprintf_unfiltered (file
,
4774 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4775 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4776 fprintf_unfiltered (file
,
4777 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4778 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4779 fprintf_unfiltered (file
,
4780 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4782 fprintf_unfiltered (file
,
4783 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4785 fprintf_unfiltered (file
,
4786 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4787 FIRST_EMBED_REGNUM
);
4788 fprintf_unfiltered (file
,
4789 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4791 fprintf_unfiltered (file
,
4792 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4793 GDB_TARGET_IS_MIPS64
);
4794 fprintf_unfiltered (file
,
4795 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4796 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4797 fprintf_unfiltered (file
,
4798 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4799 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4800 fprintf_unfiltered (file
,
4801 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4803 fprintf_unfiltered (file
,
4804 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4805 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4806 fprintf_unfiltered (file
,
4807 "mips_dump_tdep: HI_REGNUM = %d\n",
4809 fprintf_unfiltered (file
,
4810 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4811 fprintf_unfiltered (file
,
4812 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4813 fprintf_unfiltered (file
,
4814 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4815 XSTRING (IGNORE_HELPER_CALL (PC
)));
4816 fprintf_unfiltered (file
,
4817 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4818 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4819 fprintf_unfiltered (file
,
4820 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4821 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4822 fprintf_unfiltered (file
,
4823 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4824 fprintf_unfiltered (file
,
4825 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4827 fprintf_unfiltered (file
,
4828 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4829 fprintf_unfiltered (file
,
4830 "mips_dump_tdep: LO_REGNUM = %d\n",
4832 #ifdef MACHINE_CPROC_FP_OFFSET
4833 fprintf_unfiltered (file
,
4834 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4835 MACHINE_CPROC_FP_OFFSET
);
4837 #ifdef MACHINE_CPROC_PC_OFFSET
4838 fprintf_unfiltered (file
,
4839 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4840 MACHINE_CPROC_PC_OFFSET
);
4842 #ifdef MACHINE_CPROC_SP_OFFSET
4843 fprintf_unfiltered (file
,
4844 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4845 MACHINE_CPROC_SP_OFFSET
);
4847 fprintf_unfiltered (file
,
4848 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4849 fprintf_unfiltered (file
,
4850 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4851 fprintf_unfiltered (file
,
4852 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4854 fprintf_unfiltered (file
,
4855 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4856 fprintf_unfiltered (file
,
4857 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4858 fprintf_unfiltered (file
,
4859 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4860 fprintf_unfiltered (file
,
4861 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4863 fprintf_unfiltered (file
,
4864 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4865 MIPS_LAST_ARG_REGNUM
,
4866 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4867 fprintf_unfiltered (file
,
4868 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4870 fprintf_unfiltered (file
,
4871 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4872 fprintf_unfiltered (file
,
4873 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4874 MIPS_SAVED_REGSIZE
);
4875 fprintf_unfiltered (file
,
4876 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4877 fprintf_unfiltered (file
,
4878 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4879 XSTRING (MSYMBOL_SIZE (MSYM
)));
4880 fprintf_unfiltered (file
,
4881 "mips_dump_tdep: OP_LDFPR = used?\n");
4882 fprintf_unfiltered (file
,
4883 "mips_dump_tdep: OP_LDGPR = used?\n");
4884 fprintf_unfiltered (file
,
4885 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4886 fprintf_unfiltered (file
,
4887 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4888 fprintf_unfiltered (file
,
4889 "mips_dump_tdep: PRID_REGNUM = %d\n",
4891 fprintf_unfiltered (file
,
4892 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4893 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4894 fprintf_unfiltered (file
,
4895 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4896 fprintf_unfiltered (file
,
4897 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4898 fprintf_unfiltered (file
,
4899 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4900 fprintf_unfiltered (file
,
4901 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4902 fprintf_unfiltered (file
,
4903 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4904 fprintf_unfiltered (file
,
4905 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4906 fprintf_unfiltered (file
,
4907 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4908 fprintf_unfiltered (file
,
4909 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4910 fprintf_unfiltered (file
,
4911 "mips_dump_tdep: PROC_PC_REG = function?\n");
4912 fprintf_unfiltered (file
,
4913 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4914 fprintf_unfiltered (file
,
4915 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4916 fprintf_unfiltered (file
,
4917 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4918 fprintf_unfiltered (file
,
4919 "mips_dump_tdep: PS_REGNUM = %d\n",
4921 fprintf_unfiltered (file
,
4922 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4924 fprintf_unfiltered (file
,
4925 "mips_dump_tdep: RA_REGNUM = %d\n",
4927 fprintf_unfiltered (file
,
4928 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4929 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4930 fprintf_unfiltered (file
,
4931 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4932 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4933 fprintf_unfiltered (file
,
4934 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4935 fprintf_unfiltered (file
,
4936 "mips_dump_tdep: ROUND_DOWN = function?\n");
4937 fprintf_unfiltered (file
,
4938 "mips_dump_tdep: ROUND_UP = function?\n");
4940 fprintf_unfiltered (file
,
4941 "mips_dump_tdep: SAVED_BYTES = %d\n",
4945 fprintf_unfiltered (file
,
4946 "mips_dump_tdep: SAVED_FP = %d\n",
4950 fprintf_unfiltered (file
,
4951 "mips_dump_tdep: SAVED_PC = %d\n",
4954 fprintf_unfiltered (file
,
4955 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4956 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4957 fprintf_unfiltered (file
,
4958 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4959 fprintf_unfiltered (file
,
4960 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4962 fprintf_unfiltered (file
,
4963 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4964 SIGFRAME_FPREGSAVE_OFF
);
4965 fprintf_unfiltered (file
,
4966 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4968 fprintf_unfiltered (file
,
4969 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4970 SIGFRAME_REGSAVE_OFF
);
4971 fprintf_unfiltered (file
,
4972 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4974 fprintf_unfiltered (file
,
4975 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4976 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4977 fprintf_unfiltered (file
,
4978 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4979 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4980 fprintf_unfiltered (file
,
4981 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4982 SOFTWARE_SINGLE_STEP_P ());
4983 fprintf_unfiltered (file
,
4984 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4985 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4986 #ifdef STACK_END_ADDR
4987 fprintf_unfiltered (file
,
4988 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4991 fprintf_unfiltered (file
,
4992 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4993 XSTRING (STEP_SKIPS_DELAY (PC
)));
4994 fprintf_unfiltered (file
,
4995 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4996 STEP_SKIPS_DELAY_P
);
4997 fprintf_unfiltered (file
,
4998 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4999 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5000 fprintf_unfiltered (file
,
5001 "mips_dump_tdep: T9_REGNUM = %d\n",
5003 fprintf_unfiltered (file
,
5004 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5005 fprintf_unfiltered (file
,
5006 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5007 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
5008 fprintf_unfiltered (file
,
5009 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
5010 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
5011 fprintf_unfiltered (file
,
5012 "mips_dump_tdep: TARGET_MIPS = used?\n");
5013 fprintf_unfiltered (file
,
5014 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
5015 XSTRING (TM_PRINT_INSN_MACH
));
5017 fprintf_unfiltered (file
,
5018 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5019 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5022 fprintf_unfiltered (file
,
5023 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
5026 #ifdef TRACE_FLAVOR_SIZE
5027 fprintf_unfiltered (file
,
5028 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5032 fprintf_unfiltered (file
,
5033 "mips_dump_tdep: TRACE_SET # %s\n",
5034 XSTRING (TRACE_SET (X
,STATE
)));
5036 fprintf_unfiltered (file
,
5037 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
5038 #ifdef UNUSED_REGNUM
5039 fprintf_unfiltered (file
,
5040 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
5043 fprintf_unfiltered (file
,
5044 "mips_dump_tdep: V0_REGNUM = %d\n",
5046 fprintf_unfiltered (file
,
5047 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
5048 (long) VM_MIN_ADDRESS
);
5050 fprintf_unfiltered (file
,
5051 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
5054 fprintf_unfiltered (file
,
5055 "mips_dump_tdep: ZERO_REGNUM = %d\n",
5057 fprintf_unfiltered (file
,
5058 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
5061 fprintf_unfiltered (file
,
5062 "mips_dump_tdep: OS ABI = %s\n",
5063 gdbarch_osabi_name (tdep
->osabi
));
5067 _initialize_mips_tdep (void)
5069 static struct cmd_list_element
*mipsfpulist
= NULL
;
5070 struct cmd_list_element
*c
;
5072 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5073 if (MIPS_ABI_LAST
+ 1
5074 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5075 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
5077 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5078 if (!tm_print_insn
) /* Someone may have already set it */
5079 tm_print_insn
= gdb_print_insn_mips
;
5081 /* Add root prefix command for all "set mips"/"show mips" commands */
5082 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5083 "Various MIPS specific commands.",
5084 &setmipscmdlist
, "set mips ", 0, &setlist
);
5086 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5087 "Various MIPS specific commands.",
5088 &showmipscmdlist
, "show mips ", 0, &showlist
);
5090 /* Allow the user to override the saved register size. */
5091 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
5094 &mips_saved_regsize_string
, "\
5095 Set size of general purpose registers saved on the stack.\n\
5096 This option can be set to one of:\n\
5097 32 - Force GDB to treat saved GP registers as 32-bit\n\
5098 64 - Force GDB to treat saved GP registers as 64-bit\n\
5099 auto - Allow GDB to use the target's default setting or autodetect the\n\
5100 saved GP register size from information contained in the executable.\n\
5105 /* Allow the user to override the argument stack size. */
5106 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
5109 &mips_stack_argsize_string
, "\
5110 Set the amount of stack space reserved for each argument.\n\
5111 This option can be set to one of:\n\
5112 32 - Force GDB to allocate 32-bit chunks per argument\n\
5113 64 - Force GDB to allocate 64-bit chunks per argument\n\
5114 auto - Allow GDB to determine the correct setting from the current\n\
5115 target and executable (default)",
5119 /* Allow the user to override the ABI. */
5120 c
= add_set_enum_cmd
5121 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
5122 "Set the ABI used by this program.\n"
5123 "This option can be set to one of:\n"
5124 " auto - the default ABI associated with the current binary\n"
5131 add_show_from_set (c
, &showmipscmdlist
);
5132 set_cmd_sfunc (c
, mips_abi_update
);
5134 /* Let the user turn off floating point and set the fence post for
5135 heuristic_proc_start. */
5137 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5138 "Set use of MIPS floating-point coprocessor.",
5139 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5140 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5141 "Select single-precision MIPS floating-point coprocessor.",
5143 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5144 "Select double-precision MIPS floating-point coprocessor.",
5146 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5147 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5148 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5149 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5150 "Select no MIPS floating-point coprocessor.",
5152 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5153 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5154 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5155 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5156 "Select MIPS floating-point coprocessor automatically.",
5158 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5159 "Show current use of MIPS floating-point coprocessor target.",
5162 /* We really would like to have both "0" and "unlimited" work, but
5163 command.c doesn't deal with that. So make it a var_zinteger
5164 because the user can always use "999999" or some such for unlimited. */
5165 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
5166 (char *) &heuristic_fence_post
,
5168 Set the distance searched for the start of a function.\n\
5169 If you are debugging a stripped executable, GDB needs to search through the\n\
5170 program for the start of a function. This command sets the distance of the\n\
5171 search. The only need to set it is when debugging a stripped executable.",
5173 /* We need to throw away the frame cache when we set this, since it
5174 might change our ability to get backtraces. */
5175 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
5176 add_show_from_set (c
, &showlist
);
5178 /* Allow the user to control whether the upper bits of 64-bit
5179 addresses should be zeroed. */
5180 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
5181 Set zeroing of upper 32 bits of 64-bit addresses.\n\
5182 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5183 allow GDB to determine the correct value.\n", "\
5184 Show zeroing of upper 32 bits of 64-bit addresses.",
5185 NULL
, show_mask_address
,
5186 &setmipscmdlist
, &showmipscmdlist
);
5188 /* Allow the user to control the size of 32 bit registers within the
5189 raw remote packet. */
5190 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
5193 (char *)&mips64_transfers_32bit_regs_p
, "\
5194 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
5195 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5196 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5197 64 bits for others. Use \"off\" to disable compatibility mode",
5201 /* Debug this files internals. */
5202 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
5203 &mips_debug
, "Set mips debugging.\n\
5204 When non-zero, mips specific debugging is enabled.", &setdebuglist
),