1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
235 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
237 return mips_regnum (gdbarch
)->fp0
+ 12;
240 /* Return 1 if REGNUM refers to a floating-point general register, raw
241 or cooked. Otherwise return 0. */
244 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
246 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
248 return (rawnum
>= mips_regnum (gdbarch
)->fp0
249 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
253 mips_eabi (gdbarch
*arch
)
255 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
256 return (tdep
->mips_abi
== MIPS_ABI_EABI32 \
257 || tdep
->mips_abi
== MIPS_ABI_EABI64
);
261 mips_last_fp_arg_regnum (gdbarch
*arch
)
263 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
264 return tdep
->mips_last_fp_arg_regnum
;
268 mips_last_arg_regnum (gdbarch
*arch
)
270 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
271 return tdep
->mips_last_arg_regnum
;
274 static enum mips_fpu_type
275 mips_get_fpu_type (gdbarch
*arch
)
277 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (arch
);
278 return tdep
->mips_fpu_type
;
281 /* Return the MIPS ABI associated with GDBARCH. */
283 mips_abi (struct gdbarch
*gdbarch
)
285 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
286 return tdep
->mips_abi
;
290 mips_isa_regsize (struct gdbarch
*gdbarch
)
292 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
294 /* If we know how big the registers are, use that size. */
295 if (tdep
->register_size_valid_p
)
296 return tdep
->register_size
;
298 /* Fall back to the previous behavior. */
299 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
300 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
303 /* Max saved register size. */
304 #define MAX_MIPS_ABI_REGSIZE 8
306 /* Return the currently configured (or set) saved register size. */
309 mips_abi_regsize (struct gdbarch
*gdbarch
)
311 switch (mips_abi (gdbarch
))
313 case MIPS_ABI_EABI32
:
319 case MIPS_ABI_EABI64
:
321 case MIPS_ABI_UNKNOWN
:
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
329 are some functions to handle addresses associated with compressed
330 code including but not limited to testing, setting, or clearing
331 bit 0 of such addresses. */
333 /* Return one iff compressed code is the MIPS16 instruction set. */
336 is_mips16_isa (struct gdbarch
*gdbarch
)
338 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
339 return tdep
->mips_isa
== ISA_MIPS16
;
342 /* Return one iff compressed code is the microMIPS instruction set. */
345 is_micromips_isa (struct gdbarch
*gdbarch
)
347 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
348 return tdep
->mips_isa
== ISA_MICROMIPS
;
351 /* Return one iff ADDR denotes compressed code. */
354 is_compact_addr (CORE_ADDR addr
)
359 /* Return one iff ADDR denotes standard ISA code. */
362 is_mips_addr (CORE_ADDR addr
)
364 return !is_compact_addr (addr
);
367 /* Return one iff ADDR denotes MIPS16 code. */
370 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
372 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
375 /* Return one iff ADDR denotes microMIPS code. */
378 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
380 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
383 /* Strip the ISA (compression) bit off from ADDR. */
386 unmake_compact_addr (CORE_ADDR addr
)
388 return ((addr
) & ~(CORE_ADDR
) 1);
391 /* Add the ISA (compression) bit to ADDR. */
394 make_compact_addr (CORE_ADDR addr
)
396 return ((addr
) | (CORE_ADDR
) 1);
399 /* Extern version of unmake_compact_addr; we use a separate function
400 so that unmake_compact_addr can be inlined throughout this file. */
403 mips_unmake_compact_addr (CORE_ADDR addr
)
405 return unmake_compact_addr (addr
);
408 /* Functions for setting and testing a bit in a minimal symbol that
409 marks it as MIPS16 or microMIPS function. The MSB of the minimal
410 symbol's "info" field is used for this purpose.
412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
414 one of the "special" bits in a minimal symbol to mark it accordingly.
415 The test checks an ELF-private flag that is valid for true function
416 symbols only; for synthetic symbols such as for PLT stubs that have
417 no ELF-private part at all the MIPS BFD backend arranges for this
418 information to be carried in the asymbol's udata field instead.
420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
421 in a minimal symbol. */
424 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
426 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
427 unsigned char st_other
;
429 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
430 st_other
= elfsym
->internal_elf_sym
.st_other
;
431 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
432 st_other
= sym
->udata
.i
;
436 if (ELF_ST_IS_MICROMIPS (st_other
))
438 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
439 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
441 else if (ELF_ST_IS_MIPS16 (st_other
))
443 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
444 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
448 /* Return one iff MSYM refers to standard ISA code. */
451 msymbol_is_mips (struct minimal_symbol
*msym
)
453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
454 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
457 /* Return one iff MSYM refers to MIPS16 code. */
460 msymbol_is_mips16 (struct minimal_symbol
*msym
)
462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
465 /* Return one iff MSYM refers to microMIPS code. */
468 msymbol_is_micromips (struct minimal_symbol
*msym
)
470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
473 /* Set the ISA bit in the main symbol too, complementing the corresponding
474 minimal symbol setting and reflecting the run-time value of the symbol.
475 The need for comes from the ISA bit having been cleared as code in
476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
478 of symbols referring to compressed code different in GDB to the values
479 used by actual code. That in turn makes them evaluate incorrectly in
480 expressions, producing results different to what the same expressions
481 yield when compiled into the program being debugged. */
484 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
486 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
488 /* We are in symbol reading so it is OK to cast away constness. */
489 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
490 CORE_ADDR compact_block_start
;
491 struct bound_minimal_symbol msym
;
493 compact_block_start
= BLOCK_START (block
) | 1;
494 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
495 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
497 BLOCK_START (block
) = compact_block_start
;
502 /* XFER a value from the big/little/left end of the register.
503 Depending on the size of the value it might occupy the entire
504 register or just part of it. Make an allowance for this, aligning
505 things accordingly. */
508 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
509 int reg_num
, int length
,
510 enum bfd_endian endian
, gdb_byte
*in
,
511 const gdb_byte
*out
, int buf_offset
)
515 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
516 /* Need to transfer the left or right part of the register, based on
517 the targets byte order. */
521 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
523 case BFD_ENDIAN_LITTLE
:
526 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
530 internal_error (__FILE__
, __LINE__
, _("bad switch"));
533 fprintf_unfiltered (gdb_stderr
,
534 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
535 reg_num
, reg_offset
, buf_offset
, length
);
536 if (mips_debug
&& out
!= NULL
)
539 fprintf_unfiltered (gdb_stdlog
, "out ");
540 for (i
= 0; i
< length
; i
++)
541 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
544 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
546 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
547 if (mips_debug
&& in
!= NULL
)
550 fprintf_unfiltered (gdb_stdlog
, "in ");
551 for (i
= 0; i
< length
; i
++)
552 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
555 fprintf_unfiltered (gdb_stdlog
, "\n");
558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
559 compatiblity mode. A return value of 1 means that we have
560 physical 64-bit registers, but should treat them as 32-bit registers. */
563 mips2_fp_compat (struct frame_info
*frame
)
565 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
568 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
573 in all the places we deal with FP registers. PR gdb/413. */
574 /* Otherwise check the FR bit in the status register - it controls
575 the FP compatiblity mode. If it is clear we are in compatibility
577 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
586 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
588 /* The list of available "set mips " and "show mips " commands. */
590 static struct cmd_list_element
*setmipscmdlist
= NULL
;
591 static struct cmd_list_element
*showmipscmdlist
= NULL
;
593 /* Integer registers 0 thru 31 are handled explicitly by
594 mips_register_name(). Processor specific registers 32 and above
595 are listed in the following tables. */
598 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
602 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
603 "sr", "lo", "hi", "bad", "cause", "pc",
604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
611 /* Names of tx39 registers. */
613 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
614 "sr", "lo", "hi", "bad", "cause", "pc",
615 "", "", "", "", "", "", "", "",
616 "", "", "", "", "", "", "", "",
617 "", "", "", "", "", "", "", "",
618 "", "", "", "", "", "", "", "",
620 "", "", "", "", "", "", "", "",
621 "", "", "config", "cache", "debug", "depc", "epc",
624 /* Names of registers with Linux kernels. */
625 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
626 "sr", "lo", "hi", "bad", "cause", "pc",
627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
635 /* Return the name of the register corresponding to REGNO. */
637 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
639 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
640 /* GPR names for all ABIs other than n32/n64. */
641 static const char *mips_gpr_names
[] = {
642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
648 /* GPR names for n32 and n64 ABIs. */
649 static const char *mips_n32_n64_gpr_names
[] = {
650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
656 enum mips_abi abi
= mips_abi (gdbarch
);
658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
659 but then don't make the raw register names visible. This (upper)
660 range of user visible register numbers are the pseudo-registers.
662 This approach was adopted accommodate the following scenario:
663 It is possible to debug a 64-bit device using a 32-bit
664 programming model. In such instances, the raw registers are
665 configured to be 64-bits wide, while the pseudo registers are
666 configured to be 32-bits wide. The registers that the user
667 sees - the pseudo registers - match the users expectations
668 given the programming model being used. */
669 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
670 if (regno
< gdbarch_num_regs (gdbarch
))
673 /* The MIPS integer registers are always mapped from 0 to 31. The
674 names of the registers (which reflects the conventions regarding
675 register use) vary depending on the ABI. */
676 if (0 <= rawnum
&& rawnum
< 32)
678 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
679 return mips_n32_n64_gpr_names
[rawnum
];
681 return mips_gpr_names
[rawnum
];
683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
684 return tdesc_register_name (gdbarch
, rawnum
);
685 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
687 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
688 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
689 return tdep
->mips_processor_reg_names
[rawnum
- 32];
693 internal_error (__FILE__
, __LINE__
,
694 _("mips_register_name: bad register number %d"), rawnum
);
697 /* Return the groups that a MIPS register can be categorised into. */
700 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
701 struct reggroup
*reggroup
)
706 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
707 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
708 if (reggroup
== all_reggroup
)
710 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
711 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
712 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
713 (gdbarch), as not all architectures are multi-arch. */
714 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
715 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
716 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
718 if (reggroup
== float_reggroup
)
719 return float_p
&& pseudo
;
720 if (reggroup
== vector_reggroup
)
721 return vector_p
&& pseudo
;
722 if (reggroup
== general_reggroup
)
723 return (!vector_p
&& !float_p
) && pseudo
;
724 /* Save the pseudo registers. Need to make certain that any code
725 extracting register values from a saved register cache also uses
727 if (reggroup
== save_reggroup
)
728 return raw_p
&& pseudo
;
729 /* Restore the same pseudo register. */
730 if (reggroup
== restore_reggroup
)
731 return raw_p
&& pseudo
;
735 /* Return the groups that a MIPS register can be categorised into.
736 This version is only used if we have a target description which
737 describes real registers (and their groups). */
740 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
741 struct reggroup
*reggroup
)
743 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
744 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
747 /* Only save, restore, and display the pseudo registers. Need to
748 make certain that any code extracting register values from a
749 saved register cache also uses pseudo registers.
751 Note: saving and restoring the pseudo registers is slightly
752 strange; if we have 64 bits, we should save and restore all
753 64 bits. But this is hard and has little benefit. */
757 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
761 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
764 /* Map the symbol table registers which live in the range [1 *
765 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
766 registers. Take care of alignment and size problems. */
768 static enum register_status
769 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
770 int cookednum
, gdb_byte
*buf
)
772 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
773 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
774 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
775 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
776 return regcache
->raw_read (rawnum
, buf
);
777 else if (register_size (gdbarch
, rawnum
) >
778 register_size (gdbarch
, cookednum
))
780 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
782 if (tdep
->mips64_transfers_32bit_regs_p
)
783 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
786 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
788 enum register_status status
;
790 status
= regcache
->raw_read (rawnum
, ®val
);
791 if (status
== REG_VALID
)
792 store_signed_integer (buf
, 4, byte_order
, regval
);
797 internal_error (__FILE__
, __LINE__
, _("bad register size"));
801 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
802 struct regcache
*regcache
, int cookednum
,
805 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
807 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
808 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
809 regcache
->raw_write (rawnum
, buf
);
810 else if (register_size (gdbarch
, rawnum
) >
811 register_size (gdbarch
, cookednum
))
813 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
815 if (tdep
->mips64_transfers_32bit_regs_p
)
816 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
819 /* Sign extend the shortened version of the register prior
820 to placing it in the raw register. This is required for
821 some mips64 parts in order to avoid unpredictable behavior. */
822 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
823 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
824 regcache_raw_write_signed (regcache
, rawnum
, regval
);
828 internal_error (__FILE__
, __LINE__
, _("bad register size"));
832 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
833 struct agent_expr
*ax
, int reg
)
835 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
836 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
837 && reg
< 2 * gdbarch_num_regs (gdbarch
));
839 ax_reg_mask (ax
, rawnum
);
845 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
846 struct agent_expr
*ax
, int reg
)
848 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
849 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
850 && reg
< 2 * gdbarch_num_regs (gdbarch
));
851 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
855 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
857 mips_gdbarch_tdep
*tdep
858 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
860 if (!tdep
->mips64_transfers_32bit_regs_p
861 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
864 ax_simple (ax
, aop_lsh
);
867 ax_simple (ax
, aop_rsh_signed
);
871 internal_error (__FILE__
, __LINE__
, _("bad register size"));
876 /* Table to translate 3-bit register field to actual register number. */
877 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
879 /* Heuristic_proc_start may hunt through the text section for a long
880 time across a 2400 baud serial line. Allows the user to limit this
883 static int heuristic_fence_post
= 0;
885 /* Number of bytes of storage in the actual machine representation for
886 register N. NOTE: This defines the pseudo register type so need to
887 rebuild the architecture vector. */
889 static bool mips64_transfers_32bit_regs_p
= false;
892 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
893 struct cmd_list_element
*c
)
895 struct gdbarch_info info
;
896 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
897 instead of relying on globals. Doing that would let generic code
898 handle the search for this specific architecture. */
899 if (!gdbarch_update_p (info
))
901 mips64_transfers_32bit_regs_p
= 0;
902 error (_("32-bit compatibility mode not supported"));
906 /* Convert to/from a register and the corresponding memory value. */
908 /* This predicate tests for the case of an 8 byte floating point
909 value that is being transferred to or from a pair of floating point
910 registers each of which are (or are considered to be) only 4 bytes
913 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
916 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
917 && register_size (gdbarch
, regnum
) == 4
918 && mips_float_register_p (gdbarch
, regnum
)
919 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
922 /* This predicate tests for the case of a value of less than 8
923 bytes in width that is being transfered to or from an 8 byte
924 general purpose register. */
926 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
929 int num_regs
= gdbarch_num_regs (gdbarch
);
931 return (register_size (gdbarch
, regnum
) == 8
932 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
933 && TYPE_LENGTH (type
) < 8);
937 mips_convert_register_p (struct gdbarch
*gdbarch
,
938 int regnum
, struct type
*type
)
940 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
941 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
945 mips_register_to_value (struct frame_info
*frame
, int regnum
,
946 struct type
*type
, gdb_byte
*to
,
947 int *optimizedp
, int *unavailablep
)
949 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
951 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
953 get_frame_register (frame
, regnum
+ 0, to
+ 4);
954 get_frame_register (frame
, regnum
+ 1, to
+ 0);
956 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
957 optimizedp
, unavailablep
))
960 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
961 optimizedp
, unavailablep
))
963 *optimizedp
= *unavailablep
= 0;
966 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 size_t len
= TYPE_LENGTH (type
);
971 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
972 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
973 optimizedp
, unavailablep
))
976 *optimizedp
= *unavailablep
= 0;
981 internal_error (__FILE__
, __LINE__
,
982 _("mips_register_to_value: unrecognized case"));
987 mips_value_to_register (struct frame_info
*frame
, int regnum
,
988 struct type
*type
, const gdb_byte
*from
)
990 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
992 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
994 put_frame_register (frame
, regnum
+ 0, from
+ 4);
995 put_frame_register (frame
, regnum
+ 1, from
+ 0);
997 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
1000 size_t len
= TYPE_LENGTH (type
);
1002 /* Sign extend values, irrespective of type, that are stored to
1003 a 64-bit general purpose register. (32-bit unsigned values
1004 are stored as signed quantities within a 64-bit register.
1005 When performing an operation, in compiled code, that combines
1006 a 32-bit unsigned value with a signed 64-bit value, a type
1007 conversion is first performed that zeroes out the high 32 bits.) */
1008 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1011 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
1013 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
1014 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
1015 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
1019 if (from
[len
-1] & 0x80)
1020 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
1022 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
1023 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
1024 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1029 internal_error (__FILE__
, __LINE__
,
1030 _("mips_value_to_register: unrecognized case"));
1034 /* Return the GDB type object for the "standard" data type of data in
1037 static struct type
*
1038 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1040 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1041 if (mips_float_register_p (gdbarch
, regnum
))
1043 /* The floating-point registers raw, or cooked, always match
1044 mips_isa_regsize(), and also map 1:1, byte for byte. */
1045 if (mips_isa_regsize (gdbarch
) == 4)
1046 return builtin_type (gdbarch
)->builtin_float
;
1048 return builtin_type (gdbarch
)->builtin_double
;
1050 else if (regnum
< gdbarch_num_regs (gdbarch
))
1052 /* The raw or ISA registers. These are all sized according to
1054 if (mips_isa_regsize (gdbarch
) == 4)
1055 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1062 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1064 /* The cooked or ABI registers. These are sized according to
1065 the ABI (with a few complications). */
1066 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1067 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1068 return builtin_type (gdbarch
)->builtin_int32
;
1069 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1070 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1071 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1072 /* The pseudo/cooked view of the embedded registers is always
1073 32-bit. The raw view is handled below. */
1074 return builtin_type (gdbarch
)->builtin_int32
;
1075 else if (tdep
->mips64_transfers_32bit_regs_p
)
1076 /* The target, while possibly using a 64-bit register buffer,
1077 is only transfering 32-bits of each integer register.
1078 Reflect this in the cooked/pseudo (ABI) register value. */
1079 return builtin_type (gdbarch
)->builtin_int32
;
1080 else if (mips_abi_regsize (gdbarch
) == 4)
1081 /* The ABI is restricted to 32-bit registers (the ISA could be
1083 return builtin_type (gdbarch
)->builtin_int32
;
1086 return builtin_type (gdbarch
)->builtin_int64
;
1090 /* Return the GDB type for the pseudo register REGNUM, which is the
1091 ABI-level view. This function is only called if there is a target
1092 description which includes registers, so we know precisely the
1093 types of hardware registers. */
1095 static struct type
*
1096 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1098 const int num_regs
= gdbarch_num_regs (gdbarch
);
1099 int rawnum
= regnum
% num_regs
;
1100 struct type
*rawtype
;
1102 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1104 /* Absent registers are still absent. */
1105 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1106 if (TYPE_LENGTH (rawtype
) == 0)
1109 /* Present the floating point registers however the hardware did;
1110 do not try to convert between FPU layouts. */
1111 if (mips_float_register_p (gdbarch
, rawnum
))
1114 /* Floating-point control registers are always 32-bit even though for
1115 backwards compatibility reasons 64-bit targets will transfer them
1116 as 64-bit quantities even if using XML descriptions. */
1117 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1118 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1119 return builtin_type (gdbarch
)->builtin_int32
;
1121 /* Use pointer types for registers if we can. For n32 we can not,
1122 since we do not have a 64-bit pointer type. */
1123 if (mips_abi_regsize (gdbarch
)
1124 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1126 if (rawnum
== MIPS_SP_REGNUM
1127 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1128 return builtin_type (gdbarch
)->builtin_data_ptr
;
1129 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1130 return builtin_type (gdbarch
)->builtin_func_ptr
;
1133 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1134 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1135 || rawnum
== mips_regnum (gdbarch
)->lo
1136 || rawnum
== mips_regnum (gdbarch
)->hi
1137 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1138 || rawnum
== mips_regnum (gdbarch
)->cause
1139 || rawnum
== mips_regnum (gdbarch
)->pc
1140 || (mips_regnum (gdbarch
)->dspacc
!= -1
1141 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1142 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1143 return builtin_type (gdbarch
)->builtin_int32
;
1145 /* The pseudo/cooked view of embedded registers is always
1146 32-bit, even if the target transfers 64-bit values for them.
1147 New targets relying on XML descriptions should only transfer
1148 the necessary 32 bits, but older versions of GDB expected 64,
1149 so allow the target to provide 64 bits without interfering
1150 with the displayed type. */
1151 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1152 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1153 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1154 return builtin_type (gdbarch
)->builtin_int32
;
1156 /* For all other registers, pass through the hardware type. */
1160 /* Should the upper word of 64-bit addresses be zeroed? */
1161 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1164 mips_mask_address_p (mips_gdbarch_tdep
*tdep
)
1166 switch (mask_address_var
)
1168 case AUTO_BOOLEAN_TRUE
:
1170 case AUTO_BOOLEAN_FALSE
:
1173 case AUTO_BOOLEAN_AUTO
:
1174 return tdep
->default_mask_address_p
;
1176 internal_error (__FILE__
, __LINE__
,
1177 _("mips_mask_address_p: bad switch"));
1183 show_mask_address (struct ui_file
*file
, int from_tty
,
1184 struct cmd_list_element
*c
, const char *value
)
1186 mips_gdbarch_tdep
*tdep
1187 = (mips_gdbarch_tdep
*) gdbarch_tdep (target_gdbarch ());
1189 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1190 switch (mask_address_var
)
1192 case AUTO_BOOLEAN_TRUE
:
1193 printf_filtered ("The 32 bit mips address mask is enabled\n");
1195 case AUTO_BOOLEAN_FALSE
:
1196 printf_filtered ("The 32 bit mips address mask is disabled\n");
1198 case AUTO_BOOLEAN_AUTO
:
1200 ("The 32 bit address mask is set automatically. Currently %s\n",
1201 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1204 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1209 /* Tell if the program counter value in MEMADDR is in a standard ISA
1213 mips_pc_is_mips (CORE_ADDR memaddr
)
1215 struct bound_minimal_symbol sym
;
1217 /* Flags indicating that this is a MIPS16 or microMIPS function is
1218 stored by elfread.c in the high bit of the info field. Use this
1219 to decide if the function is standard MIPS. Otherwise if bit 0
1220 of the address is clear, then this is a standard MIPS function. */
1221 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1223 return msymbol_is_mips (sym
.minsym
);
1225 return is_mips_addr (memaddr
);
1228 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1231 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1233 struct bound_minimal_symbol sym
;
1235 /* A flag indicating that this is a MIPS16 function is stored by
1236 elfread.c in the high bit of the info field. Use this to decide
1237 if the function is MIPS16. Otherwise if bit 0 of the address is
1238 set, then ELF file flags will tell if this is a MIPS16 function. */
1239 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1241 return msymbol_is_mips16 (sym
.minsym
);
1243 return is_mips16_addr (gdbarch
, memaddr
);
1246 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1249 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1251 struct bound_minimal_symbol sym
;
1253 /* A flag indicating that this is a microMIPS function is stored by
1254 elfread.c in the high bit of the info field. Use this to decide
1255 if the function is microMIPS. Otherwise if bit 0 of the address
1256 is set, then ELF file flags will tell if this is a microMIPS
1258 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1260 return msymbol_is_micromips (sym
.minsym
);
1262 return is_micromips_addr (gdbarch
, memaddr
);
1265 /* Tell the ISA type of the function the program counter value in MEMADDR
1268 static enum mips_isa
1269 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1271 struct bound_minimal_symbol sym
;
1273 /* A flag indicating that this is a MIPS16 or a microMIPS function
1274 is stored by elfread.c in the high bit of the info field. Use
1275 this to decide if the function is MIPS16 or microMIPS or normal
1276 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1277 flags will tell if this is a MIPS16 or a microMIPS function. */
1278 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1281 if (msymbol_is_micromips (sym
.minsym
))
1282 return ISA_MICROMIPS
;
1283 else if (msymbol_is_mips16 (sym
.minsym
))
1290 if (is_mips_addr (memaddr
))
1292 else if (is_micromips_addr (gdbarch
, memaddr
))
1293 return ISA_MICROMIPS
;
1299 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1300 The need for comes from the ISA bit having been cleared, making
1301 addresses in FDE, range records, etc. referring to compressed code
1302 different to those in line information, the symbol table and finally
1303 the PC register. That in turn confuses many operations. */
1306 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1308 pc
= unmake_compact_addr (pc
);
1309 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1312 /* Recalculate the line record requested so that the resulting PC has
1313 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1314 this adjustment comes from some records associated with compressed
1315 code having the ISA bit cleared, most notably at function prologue
1316 ends. The ISA bit is in this context retrieved from the minimal
1317 symbol covering the address requested, which in turn has been
1318 constructed from the binary's symbol table rather than DWARF-2
1319 information. The correct setting of the ISA bit is required for
1320 breakpoint addresses to correctly match against the stop PC.
1322 As line entries can specify relative address adjustments we need to
1323 keep track of the absolute value of the last line address recorded
1324 in line information, so that we can calculate the actual address to
1325 apply the ISA bit adjustment to. We use PC for this tracking and
1326 keep the original address there.
1328 As such relative address adjustments can be odd within compressed
1329 code we need to keep track of the last line address with the ISA
1330 bit adjustment applied too, as the original address may or may not
1331 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1332 the adjusted address there.
1334 For relative address adjustments we then use these variables to
1335 calculate the address intended by line information, which will be
1336 PC-relative, and return an updated adjustment carrying ISA bit
1337 information, which will be ADJ_PC-relative. For absolute address
1338 adjustments we just return the same address that we store in ADJ_PC
1341 As the first line entry can be relative to an implied address value
1342 of 0 we need to have the initial address set up that we store in PC
1343 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1344 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1347 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1349 static CORE_ADDR adj_pc
;
1350 static CORE_ADDR pc
;
1353 pc
= rel
? pc
+ addr
: addr
;
1354 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1355 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1360 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1362 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1363 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1364 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1365 static const char mips_str_call_stub
[] = "__call_stub_";
1366 static const char mips_str_fn_stub
[] = "__fn_stub_";
1368 /* This is used as a PIC thunk prefix. */
1370 static const char mips_str_pic
[] = ".pic.";
1372 /* Return non-zero if the PC is inside a call thunk (aka stub or
1373 trampoline) that should be treated as a temporary frame. */
1376 mips_in_frame_stub (CORE_ADDR pc
)
1378 CORE_ADDR start_addr
;
1381 /* Find the starting address of the function containing the PC. */
1382 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1385 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1386 if (startswith (name
, mips_str_mips16_call_stub
))
1388 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1389 if (startswith (name
, mips_str_call_stub
))
1391 /* If the PC is in __fn_stub_*, this is a call stub. */
1392 if (startswith (name
, mips_str_fn_stub
))
1395 return 0; /* Not a stub. */
1398 /* MIPS believes that the PC has a sign extended value. Perhaps the
1399 all registers should be sign extended for simplicity? */
1402 mips_read_pc (readable_regcache
*regcache
)
1404 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1407 regcache
->cooked_read (regnum
, &pc
);
1412 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1416 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1417 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1418 intermediate frames. In this case we can get the caller's address
1419 from $ra, or if $ra contains an address within a thunk as well, then
1420 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1421 and thus the caller's address is in $s2. */
1422 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1424 pc
= frame_unwind_register_signed
1425 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1426 if (mips_in_frame_stub (pc
))
1427 pc
= frame_unwind_register_signed
1428 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1434 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1436 return frame_unwind_register_signed
1437 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1440 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1441 dummy frame. The frame ID's base needs to match the TOS value
1442 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1445 static struct frame_id
1446 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1448 return frame_id_build
1449 (get_frame_register_signed (this_frame
,
1450 gdbarch_num_regs (gdbarch
)
1452 get_frame_pc (this_frame
));
1455 /* Implement the "write_pc" gdbarch method. */
1458 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1460 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1462 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1465 /* Fetch and return instruction from the specified location. Handle
1466 MIPS16/microMIPS as appropriate. */
1469 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1470 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1472 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1473 gdb_byte buf
[MIPS_INSN32_SIZE
];
1481 instlen
= MIPS_INSN16_SIZE
;
1482 addr
= unmake_compact_addr (addr
);
1485 instlen
= MIPS_INSN32_SIZE
;
1488 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1491 err
= target_read_memory (addr
, buf
, instlen
);
1497 memory_error (TARGET_XFER_E_IO
, addr
);
1500 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1503 /* These are the fields of 32 bit mips instructions. */
1504 #define mips32_op(x) (x >> 26)
1505 #define itype_op(x) (x >> 26)
1506 #define itype_rs(x) ((x >> 21) & 0x1f)
1507 #define itype_rt(x) ((x >> 16) & 0x1f)
1508 #define itype_immediate(x) (x & 0xffff)
1510 #define jtype_op(x) (x >> 26)
1511 #define jtype_target(x) (x & 0x03ffffff)
1513 #define rtype_op(x) (x >> 26)
1514 #define rtype_rs(x) ((x >> 21) & 0x1f)
1515 #define rtype_rt(x) ((x >> 16) & 0x1f)
1516 #define rtype_rd(x) ((x >> 11) & 0x1f)
1517 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1518 #define rtype_funct(x) (x & 0x3f)
1520 /* MicroMIPS instruction fields. */
1521 #define micromips_op(x) ((x) >> 10)
1523 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1524 bit and the size respectively of the field extracted. */
1525 #define b0s4_imm(x) ((x) & 0xf)
1526 #define b0s5_imm(x) ((x) & 0x1f)
1527 #define b0s5_reg(x) ((x) & 0x1f)
1528 #define b0s7_imm(x) ((x) & 0x7f)
1529 #define b0s10_imm(x) ((x) & 0x3ff)
1530 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1531 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1532 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1533 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1534 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1535 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1536 #define b6s4_op(x) (((x) >> 6) & 0xf)
1537 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1539 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1540 respectively of the field extracted. */
1541 #define b0s6_op(x) ((x) & 0x3f)
1542 #define b0s11_op(x) ((x) & 0x7ff)
1543 #define b0s12_imm(x) ((x) & 0xfff)
1544 #define b0s16_imm(x) ((x) & 0xffff)
1545 #define b0s26_imm(x) ((x) & 0x3ffffff)
1546 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1547 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1548 #define b12s4_op(x) (((x) >> 12) & 0xf)
1550 /* Return the size in bytes of the instruction INSN encoded in the ISA
1554 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1559 if ((micromips_op (insn
) & 0x4) == 0x4
1560 || (micromips_op (insn
) & 0x7) == 0x0)
1561 return 2 * MIPS_INSN16_SIZE
;
1563 return MIPS_INSN16_SIZE
;
1565 if ((insn
& 0xf800) == 0xf000)
1566 return 2 * MIPS_INSN16_SIZE
;
1568 return MIPS_INSN16_SIZE
;
1570 return MIPS_INSN32_SIZE
;
1572 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1576 mips32_relative_offset (ULONGEST inst
)
1578 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1581 /* Determine the address of the next instruction executed after the INST
1582 floating condition branch instruction at PC. COUNT specifies the
1583 number of the floating condition bits tested by the branch. */
1586 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1587 ULONGEST inst
, CORE_ADDR pc
, int count
)
1589 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1590 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1591 int tf
= itype_rt (inst
) & 1;
1592 int mask
= (1 << count
) - 1;
1597 /* No way to handle; it'll most likely trap anyway. */
1600 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1601 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1603 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1604 pc
+= mips32_relative_offset (inst
);
1611 /* Return nonzero if the gdbarch is an Octeon series. */
1614 is_octeon (struct gdbarch
*gdbarch
)
1616 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1618 return (info
->mach
== bfd_mach_mips_octeon
1619 || info
->mach
== bfd_mach_mips_octeonp
1620 || info
->mach
== bfd_mach_mips_octeon2
);
1623 /* Return true if the OP represents the Octeon's BBIT instruction. */
1626 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1628 if (!is_octeon (gdbarch
))
1630 /* BBIT0 is encoded as LWC2: 110 010. */
1631 /* BBIT032 is encoded as LDC2: 110 110. */
1632 /* BBIT1 is encoded as SWC2: 111 010. */
1633 /* BBIT132 is encoded as SDC2: 111 110. */
1634 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1640 /* Determine where to set a single step breakpoint while considering
1641 branch prediction. */
1644 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1646 struct gdbarch
*gdbarch
= regcache
->arch ();
1649 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1650 op
= itype_op (inst
);
1651 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1655 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1666 goto greater_branch
;
1671 else if (op
== 17 && itype_rs (inst
) == 8)
1672 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1673 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1674 else if (op
== 17 && itype_rs (inst
) == 9
1675 && (itype_rt (inst
) & 2) == 0)
1676 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1677 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1678 else if (op
== 17 && itype_rs (inst
) == 10
1679 && (itype_rt (inst
) & 2) == 0)
1680 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1681 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1684 /* The new PC will be alternate mode. */
1688 reg
= jtype_target (inst
) << 2;
1689 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1690 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1692 else if (is_octeon_bbit_op (op
, gdbarch
))
1696 branch_if
= op
== 58 || op
== 62;
1697 bit
= itype_rt (inst
);
1699 /* Take into account the *32 instructions. */
1700 if (op
== 54 || op
== 62)
1703 if (((regcache_raw_get_signed (regcache
,
1704 itype_rs (inst
)) >> bit
) & 1)
1706 pc
+= mips32_relative_offset (inst
) + 4;
1708 pc
+= 8; /* After the delay slot. */
1712 pc
+= 4; /* Not a branch, next instruction is easy. */
1715 { /* This gets way messy. */
1717 /* Further subdivide into SPECIAL, REGIMM and other. */
1718 switch (op
& 0x07) /* Extract bits 28,27,26. */
1720 case 0: /* SPECIAL */
1721 op
= rtype_funct (inst
);
1726 /* Set PC to that address. */
1727 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1729 case 12: /* SYSCALL */
1731 mips_gdbarch_tdep
*tdep
1732 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1734 if (tdep
->syscall_next_pc
!= NULL
)
1735 pc
= tdep
->syscall_next_pc (get_current_frame ());
1744 break; /* end SPECIAL */
1745 case 1: /* REGIMM */
1747 op
= itype_rt (inst
); /* branch condition */
1752 case 16: /* BLTZAL */
1753 case 18: /* BLTZALL */
1755 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1756 pc
+= mips32_relative_offset (inst
) + 4;
1758 pc
+= 8; /* after the delay slot */
1762 case 17: /* BGEZAL */
1763 case 19: /* BGEZALL */
1764 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1765 pc
+= mips32_relative_offset (inst
) + 4;
1767 pc
+= 8; /* after the delay slot */
1769 case 0x1c: /* BPOSGE32 */
1770 case 0x1e: /* BPOSGE64 */
1772 if (itype_rs (inst
) == 0)
1774 unsigned int pos
= (op
& 2) ? 64 : 32;
1775 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1778 /* No way to handle; it'll most likely trap anyway. */
1781 if ((regcache_raw_get_unsigned (regcache
,
1782 dspctl
) & 0x7f) >= pos
)
1783 pc
+= mips32_relative_offset (inst
);
1788 /* All of the other instructions in the REGIMM category */
1793 break; /* end REGIMM */
1798 reg
= jtype_target (inst
) << 2;
1799 /* Upper four bits get never changed... */
1800 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1803 case 4: /* BEQ, BEQL */
1805 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1806 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1807 pc
+= mips32_relative_offset (inst
) + 4;
1811 case 5: /* BNE, BNEL */
1813 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1814 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1815 pc
+= mips32_relative_offset (inst
) + 4;
1819 case 6: /* BLEZ, BLEZL */
1820 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1821 pc
+= mips32_relative_offset (inst
) + 4;
1827 greater_branch
: /* BGTZ, BGTZL */
1828 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1829 pc
+= mips32_relative_offset (inst
) + 4;
1836 } /* mips32_next_pc */
1838 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1842 micromips_relative_offset7 (ULONGEST insn
)
1844 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1847 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1851 micromips_relative_offset10 (ULONGEST insn
)
1853 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1856 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1860 micromips_relative_offset16 (ULONGEST insn
)
1862 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1865 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1868 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1872 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1873 return mips_insn_size (ISA_MICROMIPS
, insn
);
1876 /* Calculate the address of the next microMIPS instruction to execute
1877 after the INSN coprocessor 1 conditional branch instruction at the
1878 address PC. COUNT denotes the number of coprocessor condition bits
1879 examined by the branch. */
1882 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1883 ULONGEST insn
, CORE_ADDR pc
, int count
)
1885 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1886 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1887 int tf
= b5s5_op (insn
>> 16) & 1;
1888 int mask
= (1 << count
) - 1;
1893 /* No way to handle; it'll most likely trap anyway. */
1896 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1897 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1899 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1900 pc
+= micromips_relative_offset16 (insn
);
1902 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1907 /* Calculate the address of the next microMIPS instruction to execute
1908 after the instruction at the address PC. */
1911 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1913 struct gdbarch
*gdbarch
= regcache
->arch ();
1916 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1917 pc
+= MIPS_INSN16_SIZE
;
1918 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1920 /* 32-bit instructions. */
1921 case 2 * MIPS_INSN16_SIZE
:
1923 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1924 pc
+= MIPS_INSN16_SIZE
;
1925 switch (micromips_op (insn
>> 16))
1927 case 0x00: /* POOL32A: bits 000000 */
1928 switch (b0s6_op (insn
))
1930 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1931 switch (b6s10_ext (insn
))
1933 case 0x3c: /* JALR: 000000 0000111100 111100 */
1934 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1935 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1936 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1937 pc
= regcache_raw_get_signed (regcache
,
1938 b0s5_reg (insn
>> 16));
1940 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1942 mips_gdbarch_tdep
*tdep
1943 = (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
1945 if (tdep
->syscall_next_pc
!= NULL
)
1946 pc
= tdep
->syscall_next_pc (get_current_frame ());
1954 case 0x10: /* POOL32I: bits 010000 */
1955 switch (b5s5_op (insn
>> 16))
1957 case 0x00: /* BLTZ: bits 010000 00000 */
1958 case 0x01: /* BLTZAL: bits 010000 00001 */
1959 case 0x11: /* BLTZALS: bits 010000 10001 */
1960 if (regcache_raw_get_signed (regcache
,
1961 b0s5_reg (insn
>> 16)) < 0)
1962 pc
+= micromips_relative_offset16 (insn
);
1964 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1967 case 0x02: /* BGEZ: bits 010000 00010 */
1968 case 0x03: /* BGEZAL: bits 010000 00011 */
1969 case 0x13: /* BGEZALS: bits 010000 10011 */
1970 if (regcache_raw_get_signed (regcache
,
1971 b0s5_reg (insn
>> 16)) >= 0)
1972 pc
+= micromips_relative_offset16 (insn
);
1974 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1977 case 0x04: /* BLEZ: bits 010000 00100 */
1978 if (regcache_raw_get_signed (regcache
,
1979 b0s5_reg (insn
>> 16)) <= 0)
1980 pc
+= micromips_relative_offset16 (insn
);
1982 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1985 case 0x05: /* BNEZC: bits 010000 00101 */
1986 if (regcache_raw_get_signed (regcache
,
1987 b0s5_reg (insn
>> 16)) != 0)
1988 pc
+= micromips_relative_offset16 (insn
);
1991 case 0x06: /* BGTZ: bits 010000 00110 */
1992 if (regcache_raw_get_signed (regcache
,
1993 b0s5_reg (insn
>> 16)) > 0)
1994 pc
+= micromips_relative_offset16 (insn
);
1996 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1999 case 0x07: /* BEQZC: bits 010000 00111 */
2000 if (regcache_raw_get_signed (regcache
,
2001 b0s5_reg (insn
>> 16)) == 0)
2002 pc
+= micromips_relative_offset16 (insn
);
2005 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
2006 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
2007 if (((insn
>> 16) & 0x3) == 0x0)
2008 /* BC2F, BC2T: don't know how to handle these. */
2012 case 0x1a: /* BPOSGE64: bits 010000 11010 */
2013 case 0x1b: /* BPOSGE32: bits 010000 11011 */
2015 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
2016 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
2019 /* No way to handle; it'll most likely trap anyway. */
2022 if ((regcache_raw_get_unsigned (regcache
,
2023 dspctl
) & 0x7f) >= pos
)
2024 pc
+= micromips_relative_offset16 (insn
);
2026 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2030 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2031 /* BC1ANY2F: bits 010000 11100 xxx01 */
2032 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2033 /* BC1ANY2T: bits 010000 11101 xxx01 */
2034 if (((insn
>> 16) & 0x2) == 0x0)
2035 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2036 ((insn
>> 16) & 0x1) + 1);
2039 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2040 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2041 if (((insn
>> 16) & 0x3) == 0x1)
2042 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2047 case 0x1d: /* JALS: bits 011101 */
2048 case 0x35: /* J: bits 110101 */
2049 case 0x3d: /* JAL: bits 111101 */
2050 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2053 case 0x25: /* BEQ: bits 100101 */
2054 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2055 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2056 pc
+= micromips_relative_offset16 (insn
);
2058 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2061 case 0x2d: /* BNE: bits 101101 */
2062 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2063 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2064 pc
+= micromips_relative_offset16 (insn
);
2066 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2069 case 0x3c: /* JALX: bits 111100 */
2070 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2075 /* 16-bit instructions. */
2076 case MIPS_INSN16_SIZE
:
2077 switch (micromips_op (insn
))
2079 case 0x11: /* POOL16C: bits 010001 */
2080 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2081 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2082 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2083 else if (b5s5_op (insn
) == 0x18)
2084 /* JRADDIUSP: bits 010001 11000 */
2085 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2088 case 0x23: /* BEQZ16: bits 100011 */
2090 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2092 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2093 pc
+= micromips_relative_offset7 (insn
);
2095 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2099 case 0x2b: /* BNEZ16: bits 101011 */
2101 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2103 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2104 pc
+= micromips_relative_offset7 (insn
);
2106 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2110 case 0x33: /* B16: bits 110011 */
2111 pc
+= micromips_relative_offset10 (insn
);
2120 /* Decoding the next place to set a breakpoint is irregular for the
2121 mips 16 variant, but fortunately, there fewer instructions. We have
2122 to cope ith extensions for 16 bit instructions and a pair of actual
2123 32 bit instructions. We dont want to set a single step instruction
2124 on the extend instruction either. */
2126 /* Lots of mips16 instruction formats */
2127 /* Predicting jumps requires itype,ritype,i8type
2128 and their extensions extItype,extritype,extI8type. */
2129 enum mips16_inst_fmts
2131 itype
, /* 0 immediate 5,10 */
2132 ritype
, /* 1 5,3,8 */
2133 rrtype
, /* 2 5,3,3,5 */
2134 rritype
, /* 3 5,3,3,5 */
2135 rrrtype
, /* 4 5,3,3,3,2 */
2136 rriatype
, /* 5 5,3,3,1,4 */
2137 shifttype
, /* 6 5,3,3,3,2 */
2138 i8type
, /* 7 5,3,8 */
2139 i8movtype
, /* 8 5,3,3,5 */
2140 i8mov32rtype
, /* 9 5,3,5,3 */
2141 i64type
, /* 10 5,3,8 */
2142 ri64type
, /* 11 5,3,3,5 */
2143 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2144 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2145 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2146 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2147 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2148 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2149 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2150 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2151 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2152 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2154 /* I am heaping all the fields of the formats into one structure and
2155 then, only the fields which are involved in instruction extension. */
2159 unsigned int regx
; /* Function in i8 type. */
2164 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2165 for the bits which make up the immediate extension. */
2168 extended_offset (unsigned int extension
)
2172 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2174 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2176 value
|= extension
& 0x1f; /* Extract 4:0. */
2181 /* Only call this function if you know that this is an extendable
2182 instruction. It won't malfunction, but why make excess remote memory
2183 references? If the immediate operands get sign extended or something,
2184 do it after the extension is performed. */
2185 /* FIXME: Every one of these cases needs to worry about sign extension
2186 when the offset is to be used in relative addressing. */
2189 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2194 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2195 target_read_memory (pc
, buf
, 2);
2196 return extract_unsigned_integer (buf
, 2, byte_order
);
2200 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2201 unsigned int extension
,
2203 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2208 switch (insn_format
)
2215 value
= extended_offset ((extension
<< 16) | inst
);
2216 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2220 value
= inst
& 0x7ff;
2221 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2230 { /* A register identifier and an offset. */
2231 /* Most of the fields are the same as I type but the
2232 immediate value is of a different length. */
2236 value
= extended_offset ((extension
<< 16) | inst
);
2237 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2241 value
= inst
& 0xff; /* 8 bits */
2242 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2245 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2251 unsigned long value
;
2252 unsigned int nexthalf
;
2253 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2254 value
= value
<< 16;
2255 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2256 /* Low bit still set. */
2264 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2266 upk
->offset
= offset
;
2272 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2273 and having a signed 16-bit OFFSET. */
2276 add_offset_16 (CORE_ADDR pc
, int offset
)
2278 return pc
+ (offset
<< 1) + 2;
2282 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2283 unsigned int extension
, unsigned int insn
)
2285 struct gdbarch
*gdbarch
= regcache
->arch ();
2286 int op
= (insn
>> 11);
2289 case 2: /* Branch */
2291 struct upk_mips16 upk
;
2292 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2293 pc
= add_offset_16 (pc
, upk
.offset
);
2296 case 3: /* JAL , JALX - Watch out, these are 32 bit
2299 struct upk_mips16 upk
;
2300 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2301 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2302 if ((insn
>> 10) & 0x01) /* Exchange mode */
2303 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2310 struct upk_mips16 upk
;
2312 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2313 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2315 pc
= add_offset_16 (pc
, upk
.offset
);
2322 struct upk_mips16 upk
;
2324 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2325 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2327 pc
= add_offset_16 (pc
, upk
.offset
);
2332 case 12: /* I8 Formats btez btnez */
2334 struct upk_mips16 upk
;
2336 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2337 /* upk.regx contains the opcode */
2338 /* Test register is 24 */
2339 reg
= regcache_raw_get_signed (regcache
, 24);
2340 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2341 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2342 pc
= add_offset_16 (pc
, upk
.offset
);
2347 case 29: /* RR Formats JR, JALR, JALR-RA */
2349 struct upk_mips16 upk
;
2350 /* upk.fmt = rrtype; */
2355 upk
.regx
= (insn
>> 8) & 0x07;
2356 upk
.regy
= (insn
>> 5) & 0x07;
2357 if ((upk
.regy
& 1) == 0)
2358 reg
= mips_reg3_to_reg
[upk
.regx
];
2360 reg
= 31; /* Function return instruction. */
2361 pc
= regcache_raw_get_signed (regcache
, reg
);
2368 /* This is an instruction extension. Fetch the real instruction
2369 (which follows the extension) and decode things based on
2373 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2374 fetch_mips_16 (gdbarch
, pc
));
2387 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2389 struct gdbarch
*gdbarch
= regcache
->arch ();
2390 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2391 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2394 /* The mips_next_pc function supports single_step when the remote
2395 target monitor or stub is not developed enough to do a single_step.
2396 It works by decoding the current instruction and predicting where a
2397 branch will go. This isn't hard because all the data is available.
2398 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2400 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2402 struct gdbarch
*gdbarch
= regcache
->arch ();
2404 if (mips_pc_is_mips16 (gdbarch
, pc
))
2405 return mips16_next_pc (regcache
, pc
);
2406 else if (mips_pc_is_micromips (gdbarch
, pc
))
2407 return micromips_next_pc (regcache
, pc
);
2409 return mips32_next_pc (regcache
, pc
);
2412 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2416 mips16_instruction_is_compact_branch (unsigned short insn
)
2418 switch (insn
& 0xf800)
2421 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2423 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2424 case 0x2800: /* BNEZ */
2425 case 0x2000: /* BEQZ */
2426 case 0x1000: /* B */
2433 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2437 micromips_instruction_is_compact_branch (unsigned short insn
)
2439 switch (micromips_op (insn
))
2441 case 0x11: /* POOL16C: bits 010001 */
2442 return (b5s5_op (insn
) == 0x18
2443 /* JRADDIUSP: bits 010001 11000 */
2444 || b5s5_op (insn
) == 0xd);
2445 /* JRC: bits 010011 01101 */
2446 case 0x10: /* POOL32I: bits 010000 */
2447 return (b5s5_op (insn
) & 0x1d) == 0x5;
2448 /* BEQZC/BNEZC: bits 010000 001x1 */
2454 struct mips_frame_cache
2457 trad_frame_saved_reg
*saved_regs
;
2460 /* Set a register's saved stack address in temp_saved_regs. If an
2461 address has already been set for this register, do nothing; this
2462 way we will only recognize the first save of a given register in a
2465 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2466 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2467 Strictly speaking, only the second range is used as it is only second
2468 range (the ABI instead of ISA registers) that comes into play when finding
2469 saved registers in a frame. */
2472 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2473 int regnum
, CORE_ADDR offset
)
2475 if (this_cache
!= NULL
2476 && this_cache
->saved_regs
[regnum
].is_realreg ()
2477 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2479 this_cache
->saved_regs
[regnum
+ 0
2480 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2481 this_cache
->saved_regs
[regnum
+ 1
2482 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2487 /* Fetch the immediate value from a MIPS16 instruction.
2488 If the previous instruction was an EXTEND, use it to extend
2489 the upper bits of the immediate value. This is a helper function
2490 for mips16_scan_prologue. */
2493 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2494 unsigned short inst
, /* current instruction */
2495 int nbits
, /* number of bits in imm field */
2496 int scale
, /* scale factor to be applied to imm */
2497 int is_signed
) /* is the imm field signed? */
2501 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2503 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2504 if (offset
& 0x8000) /* check for negative extend */
2505 offset
= 0 - (0x10000 - (offset
& 0xffff));
2506 return offset
| (inst
& 0x1f);
2510 int max_imm
= 1 << nbits
;
2511 int mask
= max_imm
- 1;
2512 int sign_bit
= max_imm
>> 1;
2514 offset
= inst
& mask
;
2515 if (is_signed
&& (offset
& sign_bit
))
2516 offset
= 0 - (max_imm
- offset
);
2517 return offset
* scale
;
2522 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2523 the associated FRAME_CACHE if not null.
2524 Return the address of the first instruction past the prologue. */
2527 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2528 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2529 struct frame_info
*this_frame
,
2530 struct mips_frame_cache
*this_cache
)
2532 int prev_non_prologue_insn
= 0;
2533 int this_non_prologue_insn
;
2534 int non_prologue_insns
= 0;
2537 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2539 long frame_offset
= 0; /* Size of stack frame. */
2540 long frame_adjust
= 0; /* Offset of FP from SP. */
2541 int frame_reg
= MIPS_SP_REGNUM
;
2542 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2543 unsigned inst
= 0; /* current instruction */
2544 unsigned entry_inst
= 0; /* the entry instruction */
2545 unsigned save_inst
= 0; /* the save instruction */
2546 int prev_delay_slot
= 0;
2550 int extend_bytes
= 0;
2551 int prev_extend_bytes
= 0;
2552 CORE_ADDR end_prologue_addr
;
2554 /* Can be called when there's no process, and hence when there's no
2556 if (this_frame
!= NULL
)
2557 sp
= get_frame_register_signed (this_frame
,
2558 gdbarch_num_regs (gdbarch
)
2563 if (limit_pc
> start_pc
+ 200)
2564 limit_pc
= start_pc
+ 200;
2567 /* Permit at most one non-prologue non-control-transfer instruction
2568 in the middle which may have been reordered by the compiler for
2570 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2572 this_non_prologue_insn
= 0;
2575 /* Save the previous instruction. If it's an EXTEND, we'll extract
2576 the immediate offset extension from it in mips16_get_imm. */
2579 /* Fetch and decode the instruction. */
2580 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2583 /* Normally we ignore extend instructions. However, if it is
2584 not followed by a valid prologue instruction, then this
2585 instruction is not part of the prologue either. We must
2586 remember in this case to adjust the end_prologue_addr back
2588 if ((inst
& 0xf800) == 0xf000) /* extend */
2590 extend_bytes
= MIPS_INSN16_SIZE
;
2594 prev_extend_bytes
= extend_bytes
;
2597 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2598 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2600 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2601 if (offset
< 0) /* Negative stack adjustment? */
2602 frame_offset
-= offset
;
2604 /* Exit loop if a positive stack adjustment is found, which
2605 usually means that the stack cleanup code in the function
2606 epilogue is reached. */
2609 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2611 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2612 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2613 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2615 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2617 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2618 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2619 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2621 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2623 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2624 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2626 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2628 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2629 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2631 else if (inst
== 0x673d) /* move $s1, $sp */
2636 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2638 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2639 frame_addr
= sp
+ offset
;
2641 frame_adjust
= offset
;
2643 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2645 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2646 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2647 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2649 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2651 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2652 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2653 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2655 else if ((inst
& 0xf81f) == 0xe809
2656 && (inst
& 0x700) != 0x700) /* entry */
2657 entry_inst
= inst
; /* Save for later processing. */
2658 else if ((inst
& 0xff80) == 0x6480) /* save */
2660 save_inst
= inst
; /* Save for later processing. */
2661 if (prev_extend_bytes
) /* extend */
2662 save_inst
|= prev_inst
<< 16;
2664 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2666 /* This instruction is part of the prologue, but we don't
2667 need to do anything special to handle it. */
2669 else if (mips16_instruction_has_delay_slot (inst
, 0))
2670 /* JAL/JALR/JALX/JR */
2672 /* The instruction in the delay slot can be a part
2673 of the prologue, so move forward once more. */
2675 if (mips16_instruction_has_delay_slot (inst
, 1))
2678 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2679 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2684 this_non_prologue_insn
= 1;
2687 non_prologue_insns
+= this_non_prologue_insn
;
2689 /* A jump or branch, or enough non-prologue insns seen? If so,
2690 then we must have reached the end of the prologue by now. */
2691 if (prev_delay_slot
|| non_prologue_insns
> 1
2692 || mips16_instruction_is_compact_branch (inst
))
2695 prev_non_prologue_insn
= this_non_prologue_insn
;
2696 prev_delay_slot
= in_delay_slot
;
2697 prev_pc
= cur_pc
- prev_extend_bytes
;
2700 /* The entry instruction is typically the first instruction in a function,
2701 and it stores registers at offsets relative to the value of the old SP
2702 (before the prologue). But the value of the sp parameter to this
2703 function is the new SP (after the prologue has been executed). So we
2704 can't calculate those offsets until we've seen the entire prologue,
2705 and can calculate what the old SP must have been. */
2706 if (entry_inst
!= 0)
2708 int areg_count
= (entry_inst
>> 8) & 7;
2709 int sreg_count
= (entry_inst
>> 6) & 3;
2711 /* The entry instruction always subtracts 32 from the SP. */
2714 /* Now we can calculate what the SP must have been at the
2715 start of the function prologue. */
2718 /* Check if a0-a3 were saved in the caller's argument save area. */
2719 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2721 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2722 offset
+= mips_abi_regsize (gdbarch
);
2725 /* Check if the ra register was pushed on the stack. */
2727 if (entry_inst
& 0x20)
2729 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2730 offset
-= mips_abi_regsize (gdbarch
);
2733 /* Check if the s0 and s1 registers were pushed on the stack. */
2734 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2737 offset
-= mips_abi_regsize (gdbarch
);
2741 /* The SAVE instruction is similar to ENTRY, except that defined by the
2742 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2743 size of the frame is specified as an immediate field of instruction
2744 and an extended variation exists which lets additional registers and
2745 frame space to be specified. The instruction always treats registers
2746 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2747 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2749 static int args_table
[16] = {
2750 0, 0, 0, 0, 1, 1, 1, 1,
2751 2, 2, 2, 0, 3, 3, 4, -1,
2753 static int astatic_table
[16] = {
2754 0, 1, 2, 3, 0, 1, 2, 3,
2755 0, 1, 2, 4, 0, 1, 0, -1,
2757 int aregs
= (save_inst
>> 16) & 0xf;
2758 int xsregs
= (save_inst
>> 24) & 0x7;
2759 int args
= args_table
[aregs
];
2760 int astatic
= astatic_table
[aregs
];
2765 warning (_("Invalid number of argument registers encoded in SAVE."));
2770 warning (_("Invalid number of static registers encoded in SAVE."));
2774 /* For standard SAVE the frame size of 0 means 128. */
2775 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2776 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2779 frame_offset
+= frame_size
;
2781 /* Now we can calculate what the SP must have been at the
2782 start of the function prologue. */
2785 /* Check if A0-A3 were saved in the caller's argument save area. */
2786 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2788 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2789 offset
+= mips_abi_regsize (gdbarch
);
2794 /* Check if the RA register was pushed on the stack. */
2795 if (save_inst
& 0x40)
2797 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2798 offset
-= mips_abi_regsize (gdbarch
);
2801 /* Check if the S8 register was pushed on the stack. */
2804 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2805 offset
-= mips_abi_regsize (gdbarch
);
2808 /* Check if S2-S7 were pushed on the stack. */
2809 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2811 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2812 offset
-= mips_abi_regsize (gdbarch
);
2815 /* Check if the S1 register was pushed on the stack. */
2816 if (save_inst
& 0x10)
2818 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2819 offset
-= mips_abi_regsize (gdbarch
);
2821 /* Check if the S0 register was pushed on the stack. */
2822 if (save_inst
& 0x20)
2824 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2825 offset
-= mips_abi_regsize (gdbarch
);
2828 /* Check if A0-A3 were pushed on the stack. */
2829 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2831 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2832 offset
-= mips_abi_regsize (gdbarch
);
2836 if (this_cache
!= NULL
)
2839 (get_frame_register_signed (this_frame
,
2840 gdbarch_num_regs (gdbarch
) + frame_reg
)
2841 + frame_offset
- frame_adjust
);
2842 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2843 be able to get rid of the assignment below, evetually. But it's
2844 still needed for now. */
2845 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2846 + mips_regnum (gdbarch
)->pc
]
2847 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2850 /* Set end_prologue_addr to the address of the instruction immediately
2851 after the last one we scanned. Unless the last one looked like a
2852 non-prologue instruction (and we looked ahead), in which case use
2853 its address instead. */
2854 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2855 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2857 return end_prologue_addr
;
2860 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2861 Procedures that use the 32-bit instruction set are handled by the
2862 mips_insn32 unwinder. */
2864 static struct mips_frame_cache
*
2865 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2867 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2868 struct mips_frame_cache
*cache
;
2870 if ((*this_cache
) != NULL
)
2871 return (struct mips_frame_cache
*) (*this_cache
);
2872 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2873 (*this_cache
) = cache
;
2874 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2876 /* Analyze the function prologue. */
2878 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2879 CORE_ADDR start_addr
;
2881 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2882 if (start_addr
== 0)
2883 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2884 /* We can't analyze the prologue if we couldn't find the begining
2886 if (start_addr
== 0)
2889 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2890 (struct mips_frame_cache
*) *this_cache
);
2893 /* gdbarch_sp_regnum contains the value and not the address. */
2894 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2895 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2897 return (struct mips_frame_cache
*) (*this_cache
);
2901 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2902 struct frame_id
*this_id
)
2904 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2906 /* This marks the outermost frame. */
2907 if (info
->base
== 0)
2909 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2912 static struct value
*
2913 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2914 void **this_cache
, int regnum
)
2916 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2918 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2922 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2923 struct frame_info
*this_frame
, void **this_cache
)
2925 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2926 CORE_ADDR pc
= get_frame_pc (this_frame
);
2927 if (mips_pc_is_mips16 (gdbarch
, pc
))
2932 static const struct frame_unwind mips_insn16_frame_unwind
=
2934 "mips insn16 prologue",
2936 default_frame_unwind_stop_reason
,
2937 mips_insn16_frame_this_id
,
2938 mips_insn16_frame_prev_register
,
2940 mips_insn16_frame_sniffer
2944 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2947 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2952 static const struct frame_base mips_insn16_frame_base
=
2954 &mips_insn16_frame_unwind
,
2955 mips_insn16_frame_base_address
,
2956 mips_insn16_frame_base_address
,
2957 mips_insn16_frame_base_address
2960 static const struct frame_base
*
2961 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2963 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2964 CORE_ADDR pc
= get_frame_pc (this_frame
);
2965 if (mips_pc_is_mips16 (gdbarch
, pc
))
2966 return &mips_insn16_frame_base
;
2971 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2972 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2973 interpreted directly, and then multiplied by 4. */
2976 micromips_decode_imm9 (int imm
)
2978 imm
= (imm
^ 0x100) - 0x100;
2979 if (imm
> -3 && imm
< 2)
2984 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2985 the address of the first instruction past the prologue. */
2988 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2989 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2990 struct frame_info
*this_frame
,
2991 struct mips_frame_cache
*this_cache
)
2993 CORE_ADDR end_prologue_addr
;
2994 int prev_non_prologue_insn
= 0;
2995 int frame_reg
= MIPS_SP_REGNUM
;
2996 int this_non_prologue_insn
;
2997 int non_prologue_insns
= 0;
2998 long frame_offset
= 0; /* Size of stack frame. */
2999 long frame_adjust
= 0; /* Offset of FP from SP. */
3000 int prev_delay_slot
= 0;
3004 ULONGEST insn
; /* current instruction */
3008 long v1_off
= 0; /* The assumption is LUI will replace it. */
3019 /* Can be called when there's no process, and hence when there's no
3021 if (this_frame
!= NULL
)
3022 sp
= get_frame_register_signed (this_frame
,
3023 gdbarch_num_regs (gdbarch
)
3028 if (limit_pc
> start_pc
+ 200)
3029 limit_pc
= start_pc
+ 200;
3032 /* Permit at most one non-prologue non-control-transfer instruction
3033 in the middle which may have been reordered by the compiler for
3035 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3037 this_non_prologue_insn
= 0;
3041 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3042 loc
+= MIPS_INSN16_SIZE
;
3043 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3045 /* 32-bit instructions. */
3046 case 2 * MIPS_INSN16_SIZE
:
3048 insn
|= mips_fetch_instruction (gdbarch
,
3049 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3050 loc
+= MIPS_INSN16_SIZE
;
3051 switch (micromips_op (insn
>> 16))
3053 /* Record $sp/$fp adjustment. */
3054 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3055 case 0x0: /* POOL32A: bits 000000 */
3056 case 0x16: /* POOL32S: bits 010110 */
3057 op
= b0s11_op (insn
);
3058 sreg
= b0s5_reg (insn
>> 16);
3059 treg
= b5s5_reg (insn
>> 16);
3060 dreg
= b11s5_reg (insn
);
3062 /* SUBU: bits 000000 00111010000 */
3063 /* DSUBU: bits 010110 00111010000 */
3064 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3066 /* (D)SUBU $sp, $v1 */
3068 else if (op
!= 0x150
3069 /* ADDU: bits 000000 00101010000 */
3070 /* DADDU: bits 010110 00101010000 */
3071 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3072 this_non_prologue_insn
= 1;
3075 case 0x8: /* POOL32B: bits 001000 */
3076 op
= b12s4_op (insn
);
3077 breg
= b0s5_reg (insn
>> 16);
3078 reglist
= sreg
= b5s5_reg (insn
>> 16);
3079 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3080 if ((op
== 0x9 || op
== 0xc)
3081 /* SWP: bits 001000 1001 */
3082 /* SDP: bits 001000 1100 */
3083 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3084 /* S[DW]P reg,offset($sp) */
3086 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3087 set_reg_offset (gdbarch
, this_cache
,
3089 set_reg_offset (gdbarch
, this_cache
,
3090 sreg
+ 1, sp
+ offset
+ s
);
3092 else if ((op
== 0xd || op
== 0xf)
3093 /* SWM: bits 001000 1101 */
3094 /* SDM: bits 001000 1111 */
3095 && breg
== MIPS_SP_REGNUM
3096 /* SWM reglist,offset($sp) */
3097 && ((reglist
>= 1 && reglist
<= 9)
3098 || (reglist
>= 16 && reglist
<= 25)))
3100 int sreglist
= std::min(reglist
& 0xf, 8);
3102 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3103 for (i
= 0; i
< sreglist
; i
++)
3104 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3105 if ((reglist
& 0xf) > 8)
3106 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3107 if ((reglist
& 0x10) == 0x10)
3108 set_reg_offset (gdbarch
, this_cache
,
3109 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3112 this_non_prologue_insn
= 1;
3115 /* Record $sp/$fp adjustment. */
3116 /* Discard (D)ADDIU $gp used for PIC code. */
3117 case 0xc: /* ADDIU: bits 001100 */
3118 case 0x17: /* DADDIU: bits 010111 */
3119 sreg
= b0s5_reg (insn
>> 16);
3120 dreg
= b5s5_reg (insn
>> 16);
3121 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3122 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3123 /* (D)ADDIU $sp, imm */
3125 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3126 /* (D)ADDIU $fp, $sp, imm */
3128 frame_adjust
= offset
;
3131 else if (sreg
!= 28 || dreg
!= 28)
3132 /* (D)ADDIU $gp, imm */
3133 this_non_prologue_insn
= 1;
3136 /* LUI $v1 is used for larger $sp adjustments. */
3137 /* Discard LUI $gp used for PIC code. */
3138 case 0x10: /* POOL32I: bits 010000 */
3139 if (b5s5_op (insn
>> 16) == 0xd
3140 /* LUI: bits 010000 001101 */
3141 && b0s5_reg (insn
>> 16) == 3)
3143 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3144 else if (b5s5_op (insn
>> 16) != 0xd
3145 /* LUI: bits 010000 001101 */
3146 || b0s5_reg (insn
>> 16) != 28)
3148 this_non_prologue_insn
= 1;
3151 /* ORI $v1 is used for larger $sp adjustments. */
3152 case 0x14: /* ORI: bits 010100 */
3153 sreg
= b0s5_reg (insn
>> 16);
3154 dreg
= b5s5_reg (insn
>> 16);
3155 if (sreg
== 3 && dreg
== 3)
3157 v1_off
|= b0s16_imm (insn
);
3159 this_non_prologue_insn
= 1;
3162 case 0x26: /* SWC1: bits 100110 */
3163 case 0x2e: /* SDC1: bits 101110 */
3164 breg
= b0s5_reg (insn
>> 16);
3165 if (breg
!= MIPS_SP_REGNUM
)
3166 /* S[DW]C1 reg,offset($sp) */
3167 this_non_prologue_insn
= 1;
3170 case 0x36: /* SD: bits 110110 */
3171 case 0x3e: /* SW: bits 111110 */
3172 breg
= b0s5_reg (insn
>> 16);
3173 sreg
= b5s5_reg (insn
>> 16);
3174 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3175 if (breg
== MIPS_SP_REGNUM
)
3176 /* S[DW] reg,offset($sp) */
3177 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3179 this_non_prologue_insn
= 1;
3183 /* The instruction in the delay slot can be a part
3184 of the prologue, so move forward once more. */
3185 if (micromips_instruction_has_delay_slot (insn
, 0))
3188 this_non_prologue_insn
= 1;
3194 /* 16-bit instructions. */
3195 case MIPS_INSN16_SIZE
:
3196 switch (micromips_op (insn
))
3198 case 0x3: /* MOVE: bits 000011 */
3199 sreg
= b0s5_reg (insn
);
3200 dreg
= b5s5_reg (insn
);
3201 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3204 else if ((sreg
& 0x1c) != 0x4)
3205 /* MOVE reg, $a0-$a3 */
3206 this_non_prologue_insn
= 1;
3209 case 0x11: /* POOL16C: bits 010001 */
3210 if (b6s4_op (insn
) == 0x5)
3211 /* SWM: bits 010001 0101 */
3213 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3214 reglist
= b4s2_regl (insn
);
3215 for (i
= 0; i
<= reglist
; i
++)
3216 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3217 set_reg_offset (gdbarch
, this_cache
,
3218 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3221 this_non_prologue_insn
= 1;
3224 case 0x13: /* POOL16D: bits 010011 */
3225 if ((insn
& 0x1) == 0x1)
3226 /* ADDIUSP: bits 010011 1 */
3227 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3228 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3229 /* ADDIUS5: bits 010011 0 */
3230 /* ADDIUS5 $sp, imm */
3231 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3233 this_non_prologue_insn
= 1;
3236 case 0x32: /* SWSP: bits 110010 */
3237 offset
= b0s5_imm (insn
) << 2;
3238 sreg
= b5s5_reg (insn
);
3239 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3243 /* The instruction in the delay slot can be a part
3244 of the prologue, so move forward once more. */
3245 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3248 this_non_prologue_insn
= 1;
3254 frame_offset
-= sp_adj
;
3256 non_prologue_insns
+= this_non_prologue_insn
;
3258 /* A jump or branch, enough non-prologue insns seen or positive
3259 stack adjustment? If so, then we must have reached the end
3260 of the prologue by now. */
3261 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3262 || micromips_instruction_is_compact_branch (insn
))
3265 prev_non_prologue_insn
= this_non_prologue_insn
;
3266 prev_delay_slot
= in_delay_slot
;
3270 if (this_cache
!= NULL
)
3273 (get_frame_register_signed (this_frame
,
3274 gdbarch_num_regs (gdbarch
) + frame_reg
)
3275 + frame_offset
- frame_adjust
);
3276 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3277 be able to get rid of the assignment below, evetually. But it's
3278 still needed for now. */
3279 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3280 + mips_regnum (gdbarch
)->pc
]
3281 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3284 /* Set end_prologue_addr to the address of the instruction immediately
3285 after the last one we scanned. Unless the last one looked like a
3286 non-prologue instruction (and we looked ahead), in which case use
3287 its address instead. */
3289 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3291 return end_prologue_addr
;
3294 /* Heuristic unwinder for procedures using microMIPS instructions.
3295 Procedures that use the 32-bit instruction set are handled by the
3296 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3298 static struct mips_frame_cache
*
3299 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3301 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3302 struct mips_frame_cache
*cache
;
3304 if ((*this_cache
) != NULL
)
3305 return (struct mips_frame_cache
*) (*this_cache
);
3307 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3308 (*this_cache
) = cache
;
3309 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3311 /* Analyze the function prologue. */
3313 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3314 CORE_ADDR start_addr
;
3316 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3317 if (start_addr
== 0)
3318 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3319 /* We can't analyze the prologue if we couldn't find the begining
3321 if (start_addr
== 0)
3324 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3325 (struct mips_frame_cache
*) *this_cache
);
3328 /* gdbarch_sp_regnum contains the value and not the address. */
3329 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3330 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3332 return (struct mips_frame_cache
*) (*this_cache
);
3336 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3337 struct frame_id
*this_id
)
3339 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3341 /* This marks the outermost frame. */
3342 if (info
->base
== 0)
3344 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3347 static struct value
*
3348 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3349 void **this_cache
, int regnum
)
3351 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3353 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3357 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3358 struct frame_info
*this_frame
, void **this_cache
)
3360 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3361 CORE_ADDR pc
= get_frame_pc (this_frame
);
3363 if (mips_pc_is_micromips (gdbarch
, pc
))
3368 static const struct frame_unwind mips_micro_frame_unwind
=
3370 "mips micro prologue",
3372 default_frame_unwind_stop_reason
,
3373 mips_micro_frame_this_id
,
3374 mips_micro_frame_prev_register
,
3376 mips_micro_frame_sniffer
3380 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3383 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3388 static const struct frame_base mips_micro_frame_base
=
3390 &mips_micro_frame_unwind
,
3391 mips_micro_frame_base_address
,
3392 mips_micro_frame_base_address
,
3393 mips_micro_frame_base_address
3396 static const struct frame_base
*
3397 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3399 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3400 CORE_ADDR pc
= get_frame_pc (this_frame
);
3402 if (mips_pc_is_micromips (gdbarch
, pc
))
3403 return &mips_micro_frame_base
;
3408 /* Mark all the registers as unset in the saved_regs array
3409 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3412 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3414 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3418 const int num_regs
= gdbarch_num_regs (gdbarch
);
3421 /* Reset the register values to their default state. Register i's value
3422 is in register i. */
3423 for (i
= 0; i
< num_regs
; i
++)
3424 this_cache
->saved_regs
[i
].set_realreg (i
);
3428 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3429 the associated FRAME_CACHE if not null.
3430 Return the address of the first instruction past the prologue. */
3433 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3434 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3435 struct frame_info
*this_frame
,
3436 struct mips_frame_cache
*this_cache
)
3438 int prev_non_prologue_insn
;
3439 int this_non_prologue_insn
;
3440 int non_prologue_insns
;
3441 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3443 int prev_delay_slot
;
3448 int frame_reg
= MIPS_SP_REGNUM
;
3450 CORE_ADDR end_prologue_addr
;
3451 int seen_sp_adjust
= 0;
3452 int load_immediate_bytes
= 0;
3454 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3456 /* Can be called when there's no process, and hence when there's no
3458 if (this_frame
!= NULL
)
3459 sp
= get_frame_register_signed (this_frame
,
3460 gdbarch_num_regs (gdbarch
)
3465 if (limit_pc
> start_pc
+ 200)
3466 limit_pc
= start_pc
+ 200;
3469 prev_non_prologue_insn
= 0;
3470 non_prologue_insns
= 0;
3471 prev_delay_slot
= 0;
3474 /* Permit at most one non-prologue non-control-transfer instruction
3475 in the middle which may have been reordered by the compiler for
3478 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3480 unsigned long inst
, high_word
;
3484 this_non_prologue_insn
= 0;
3487 /* Fetch the instruction. */
3488 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3491 /* Save some code by pre-extracting some useful fields. */
3492 high_word
= (inst
>> 16) & 0xffff;
3493 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3494 reg
= high_word
& 0x1f;
3496 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3497 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3498 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3500 if (offset
< 0) /* Negative stack adjustment? */
3501 frame_offset
-= offset
;
3503 /* Exit loop if a positive stack adjustment is found, which
3504 usually means that the stack cleanup code in the function
3505 epilogue is reached. */
3509 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3510 && !regsize_is_64_bits
)
3512 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3514 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3515 && regsize_is_64_bits
)
3517 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3518 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3520 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3522 /* Old gcc frame, r30 is virtual frame pointer. */
3523 if (offset
!= frame_offset
)
3524 frame_addr
= sp
+ offset
;
3525 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3527 unsigned alloca_adjust
;
3530 frame_addr
= get_frame_register_signed
3531 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3534 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3535 if (alloca_adjust
> 0)
3537 /* FP > SP + frame_size. This may be because of
3538 an alloca or somethings similar. Fix sp to
3539 "pre-alloca" value, and try again. */
3540 sp
+= alloca_adjust
;
3541 /* Need to reset the status of all registers. Otherwise,
3542 we will hit a guard that prevents the new address
3543 for each register to be recomputed during the second
3545 reset_saved_regs (gdbarch
, this_cache
);
3550 /* move $30,$sp. With different versions of gas this will be either
3551 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3552 Accept any one of these. */
3553 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3555 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3556 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3558 unsigned alloca_adjust
;
3561 frame_addr
= get_frame_register_signed
3562 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3564 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3565 if (alloca_adjust
> 0)
3567 /* FP > SP + frame_size. This may be because of
3568 an alloca or somethings similar. Fix sp to
3569 "pre-alloca" value, and try again. */
3571 /* Need to reset the status of all registers. Otherwise,
3572 we will hit a guard that prevents the new address
3573 for each register to be recomputed during the second
3575 reset_saved_regs (gdbarch
, this_cache
);
3580 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3581 && !regsize_is_64_bits
)
3583 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3585 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3586 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3587 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3588 || high_word
== 0x3c1c /* lui $gp,n */
3589 || high_word
== 0x279c /* addiu $gp,$gp,n */
3590 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3591 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3594 /* These instructions are part of the prologue, but we don't
3595 need to do anything special to handle them. */
3597 /* The instructions below load $at or $t0 with an immediate
3598 value in preparation for a stack adjustment via
3599 subu $sp,$sp,[$at,$t0]. These instructions could also
3600 initialize a local variable, so we accept them only before
3601 a stack adjustment instruction was seen. */
3602 else if (!seen_sp_adjust
3604 && (high_word
== 0x3c01 /* lui $at,n */
3605 || high_word
== 0x3c08 /* lui $t0,n */
3606 || high_word
== 0x3421 /* ori $at,$at,n */
3607 || high_word
== 0x3508 /* ori $t0,$t0,n */
3608 || high_word
== 0x3401 /* ori $at,$zero,n */
3609 || high_word
== 0x3408 /* ori $t0,$zero,n */
3612 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3614 /* Check for branches and jumps. The instruction in the delay
3615 slot can be a part of the prologue, so move forward once more. */
3616 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3620 /* This instruction is not an instruction typically found
3621 in a prologue, so we must have reached the end of the
3625 this_non_prologue_insn
= 1;
3628 non_prologue_insns
+= this_non_prologue_insn
;
3630 /* A jump or branch, or enough non-prologue insns seen? If so,
3631 then we must have reached the end of the prologue by now. */
3632 if (prev_delay_slot
|| non_prologue_insns
> 1)
3635 prev_non_prologue_insn
= this_non_prologue_insn
;
3636 prev_delay_slot
= in_delay_slot
;
3640 if (this_cache
!= NULL
)
3643 (get_frame_register_signed (this_frame
,
3644 gdbarch_num_regs (gdbarch
) + frame_reg
)
3646 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3647 this assignment below, eventually. But it's still needed
3649 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3650 + mips_regnum (gdbarch
)->pc
]
3651 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3655 /* Set end_prologue_addr to the address of the instruction immediately
3656 after the last one we scanned. Unless the last one looked like a
3657 non-prologue instruction (and we looked ahead), in which case use
3658 its address instead. */
3660 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3662 /* In a frameless function, we might have incorrectly
3663 skipped some load immediate instructions. Undo the skipping
3664 if the load immediate was not followed by a stack adjustment. */
3665 if (load_immediate_bytes
&& !seen_sp_adjust
)
3666 end_prologue_addr
-= load_immediate_bytes
;
3668 return end_prologue_addr
;
3671 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3672 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3673 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3674 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3676 static struct mips_frame_cache
*
3677 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3679 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3680 struct mips_frame_cache
*cache
;
3682 if ((*this_cache
) != NULL
)
3683 return (struct mips_frame_cache
*) (*this_cache
);
3685 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3686 (*this_cache
) = cache
;
3687 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3689 /* Analyze the function prologue. */
3691 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3692 CORE_ADDR start_addr
;
3694 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3695 if (start_addr
== 0)
3696 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3697 /* We can't analyze the prologue if we couldn't find the begining
3699 if (start_addr
== 0)
3702 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3703 (struct mips_frame_cache
*) *this_cache
);
3706 /* gdbarch_sp_regnum contains the value and not the address. */
3707 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3708 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3710 return (struct mips_frame_cache
*) (*this_cache
);
3714 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3715 struct frame_id
*this_id
)
3717 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3719 /* This marks the outermost frame. */
3720 if (info
->base
== 0)
3722 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3725 static struct value
*
3726 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3727 void **this_cache
, int regnum
)
3729 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3731 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3735 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3736 struct frame_info
*this_frame
, void **this_cache
)
3738 CORE_ADDR pc
= get_frame_pc (this_frame
);
3739 if (mips_pc_is_mips (pc
))
3744 static const struct frame_unwind mips_insn32_frame_unwind
=
3746 "mips insn32 prologue",
3748 default_frame_unwind_stop_reason
,
3749 mips_insn32_frame_this_id
,
3750 mips_insn32_frame_prev_register
,
3752 mips_insn32_frame_sniffer
3756 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3759 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3764 static const struct frame_base mips_insn32_frame_base
=
3766 &mips_insn32_frame_unwind
,
3767 mips_insn32_frame_base_address
,
3768 mips_insn32_frame_base_address
,
3769 mips_insn32_frame_base_address
3772 static const struct frame_base
*
3773 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3775 CORE_ADDR pc
= get_frame_pc (this_frame
);
3776 if (mips_pc_is_mips (pc
))
3777 return &mips_insn32_frame_base
;
3782 static struct trad_frame_cache
*
3783 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3786 CORE_ADDR start_addr
;
3787 CORE_ADDR stack_addr
;
3788 struct trad_frame_cache
*this_trad_cache
;
3789 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3790 int num_regs
= gdbarch_num_regs (gdbarch
);
3792 if ((*this_cache
) != NULL
)
3793 return (struct trad_frame_cache
*) (*this_cache
);
3794 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3795 (*this_cache
) = this_trad_cache
;
3797 /* The return address is in the link register. */
3798 trad_frame_set_reg_realreg (this_trad_cache
,
3799 gdbarch_pc_regnum (gdbarch
),
3800 num_regs
+ MIPS_RA_REGNUM
);
3802 /* Frame ID, since it's a frameless / stackless function, no stack
3803 space is allocated and SP on entry is the current SP. */
3804 pc
= get_frame_pc (this_frame
);
3805 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3806 stack_addr
= get_frame_register_signed (this_frame
,
3807 num_regs
+ MIPS_SP_REGNUM
);
3808 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3810 /* Assume that the frame's base is the same as the
3812 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3814 return this_trad_cache
;
3818 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3819 struct frame_id
*this_id
)
3821 struct trad_frame_cache
*this_trad_cache
3822 = mips_stub_frame_cache (this_frame
, this_cache
);
3823 trad_frame_get_id (this_trad_cache
, this_id
);
3826 static struct value
*
3827 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3828 void **this_cache
, int regnum
)
3830 struct trad_frame_cache
*this_trad_cache
3831 = mips_stub_frame_cache (this_frame
, this_cache
);
3832 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3836 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3837 struct frame_info
*this_frame
, void **this_cache
)
3840 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3841 struct bound_minimal_symbol msym
;
3843 /* Use the stub unwinder for unreadable code. */
3844 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3847 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3850 /* Calling a PIC function from a non-PIC function passes through a
3851 stub. The stub for foo is named ".pic.foo". */
3852 msym
= lookup_minimal_symbol_by_pc (pc
);
3853 if (msym
.minsym
!= NULL
3854 && msym
.minsym
->linkage_name () != NULL
3855 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3861 static const struct frame_unwind mips_stub_frame_unwind
=
3865 default_frame_unwind_stop_reason
,
3866 mips_stub_frame_this_id
,
3867 mips_stub_frame_prev_register
,
3869 mips_stub_frame_sniffer
3873 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3876 struct trad_frame_cache
*this_trad_cache
3877 = mips_stub_frame_cache (this_frame
, this_cache
);
3878 return trad_frame_get_this_base (this_trad_cache
);
3881 static const struct frame_base mips_stub_frame_base
=
3883 &mips_stub_frame_unwind
,
3884 mips_stub_frame_base_address
,
3885 mips_stub_frame_base_address
,
3886 mips_stub_frame_base_address
3889 static const struct frame_base
*
3890 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3892 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3893 return &mips_stub_frame_base
;
3898 /* mips_addr_bits_remove - remove useless address bits */
3901 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3903 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
3905 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3906 /* This hack is a work-around for existing boards using PMON, the
3907 simulator, and any other 64-bit targets that doesn't have true
3908 64-bit addressing. On these targets, the upper 32 bits of
3909 addresses are ignored by the hardware. Thus, the PC or SP are
3910 likely to have been sign extended to all 1s by instruction
3911 sequences that load 32-bit addresses. For example, a typical
3912 piece of code that loads an address is this:
3914 lui $r2, <upper 16 bits>
3915 ori $r2, <lower 16 bits>
3917 But the lui sign-extends the value such that the upper 32 bits
3918 may be all 1s. The workaround is simply to mask off these
3919 bits. In the future, gcc may be changed to support true 64-bit
3920 addressing, and this masking will have to be disabled. */
3921 return addr
&= 0xffffffffUL
;
3927 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3928 instruction and ending with a SC/SCD instruction. If such a sequence
3929 is found, attempt to step through it. A breakpoint is placed at the end of
3932 /* Instructions used during single-stepping of atomic sequences, standard
3934 #define LL_OPCODE 0x30
3935 #define LLD_OPCODE 0x34
3936 #define SC_OPCODE 0x38
3937 #define SCD_OPCODE 0x3c
3939 static std::vector
<CORE_ADDR
>
3940 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3942 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3944 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3948 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3949 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3951 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3952 /* Assume all atomic sequences start with a ll/lld instruction. */
3953 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3956 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3958 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3961 loc
+= MIPS_INSN32_SIZE
;
3962 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3964 /* Assume that there is at most one branch in the atomic
3965 sequence. If a branch is found, put a breakpoint in its
3966 destination address. */
3967 switch (itype_op (insn
))
3969 case 0: /* SPECIAL */
3970 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3971 return {}; /* fallback to the standard single-step code. */
3973 case 1: /* REGIMM */
3974 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3975 || ((itype_rt (insn
) & 0x1e) == 0
3976 && itype_rs (insn
) == 0)); /* BPOSGE* */
3980 return {}; /* fallback to the standard single-step code. */
3987 case 22: /* BLEZL */
3988 case 23: /* BGTTL */
3992 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3993 && (itype_rt (insn
) & 0x2) == 0);
3994 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3999 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
4004 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
4005 if (last_breakpoint
>= 1)
4006 return {}; /* More than one branch found, fallback to the
4007 standard single-step code. */
4008 breaks
[1] = branch_bp
;
4012 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
4016 /* Assume that the atomic sequence ends with a sc/scd instruction. */
4017 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
4020 loc
+= MIPS_INSN32_SIZE
;
4022 /* Insert a breakpoint right after the end of the atomic sequence. */
4025 /* Check for duplicated breakpoints. Check also for a breakpoint
4026 placed (branch instruction's destination) in the atomic sequence. */
4027 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4028 last_breakpoint
= 0;
4030 std::vector
<CORE_ADDR
> next_pcs
;
4032 /* Effectively inserts the breakpoints. */
4033 for (index
= 0; index
<= last_breakpoint
; index
++)
4034 next_pcs
.push_back (breaks
[index
]);
4039 static std::vector
<CORE_ADDR
>
4040 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4043 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4044 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4045 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4046 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4054 /* Assume all atomic sequences start with a ll/lld instruction. */
4055 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4056 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4058 loc
+= MIPS_INSN16_SIZE
;
4060 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4061 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4063 loc
+= MIPS_INSN16_SIZE
;
4065 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4066 that no atomic sequence is longer than "atomic_sequence_length"
4068 for (insn_count
= 0;
4069 !sc_found
&& insn_count
< atomic_sequence_length
;
4074 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4075 loc
+= MIPS_INSN16_SIZE
;
4077 /* Assume that there is at most one conditional branch in the
4078 atomic sequence. If a branch is found, put a breakpoint in
4079 its destination address. */
4080 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4082 /* 32-bit instructions. */
4083 case 2 * MIPS_INSN16_SIZE
:
4084 switch (micromips_op (insn
))
4086 case 0x10: /* POOL32I: bits 010000 */
4087 if ((b5s5_op (insn
) & 0x18) != 0x0
4088 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4089 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4090 && (b5s5_op (insn
) & 0x1d) != 0x11
4091 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4092 && ((b5s5_op (insn
) & 0x1e) != 0x14
4093 || (insn
& 0x3) != 0x0)
4094 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4095 && (b5s5_op (insn
) & 0x1e) != 0x1a
4096 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4097 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4098 || (insn
& 0x3) != 0x0)
4099 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4100 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4101 || (insn
& 0x3) != 0x1))
4102 /* BC1ANY*: bits 010000 111xx xxx01 */
4106 case 0x25: /* BEQ: bits 100101 */
4107 case 0x2d: /* BNE: bits 101101 */
4109 insn
|= mips_fetch_instruction (gdbarch
,
4110 ISA_MICROMIPS
, loc
, NULL
);
4111 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4112 + micromips_relative_offset16 (insn
));
4116 case 0x00: /* POOL32A: bits 000000 */
4118 insn
|= mips_fetch_instruction (gdbarch
,
4119 ISA_MICROMIPS
, loc
, NULL
);
4120 if (b0s6_op (insn
) != 0x3c
4121 /* POOL32Axf: bits 000000 ... 111100 */
4122 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4123 /* JALR, JALR.HB: 000000 000x111100 111100 */
4124 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4128 case 0x1d: /* JALS: bits 011101 */
4129 case 0x35: /* J: bits 110101 */
4130 case 0x3d: /* JAL: bits 111101 */
4131 case 0x3c: /* JALX: bits 111100 */
4132 return {}; /* Fall back to the standard single-step code. */
4134 case 0x18: /* POOL32C: bits 011000 */
4135 if ((b12s4_op (insn
) & 0xb) == 0xb)
4136 /* SC, SCD: bits 011000 1x11 */
4140 loc
+= MIPS_INSN16_SIZE
;
4143 /* 16-bit instructions. */
4144 case MIPS_INSN16_SIZE
:
4145 switch (micromips_op (insn
))
4147 case 0x23: /* BEQZ16: bits 100011 */
4148 case 0x2b: /* BNEZ16: bits 101011 */
4149 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4153 case 0x11: /* POOL16C: bits 010001 */
4154 if ((b5s5_op (insn
) & 0x1c) != 0xc
4155 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4156 && b5s5_op (insn
) != 0x18)
4157 /* JRADDIUSP: bits 010001 11000 */
4159 return {}; /* Fall back to the standard single-step code. */
4161 case 0x33: /* B16: bits 110011 */
4162 return {}; /* Fall back to the standard single-step code. */
4168 if (last_breakpoint
>= 1)
4169 return {}; /* More than one branch found, fallback to the
4170 standard single-step code. */
4171 breaks
[1] = branch_bp
;
4178 /* Insert a breakpoint right after the end of the atomic sequence. */
4181 /* Check for duplicated breakpoints. Check also for a breakpoint
4182 placed (branch instruction's destination) in the atomic sequence */
4183 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4184 last_breakpoint
= 0;
4186 std::vector
<CORE_ADDR
> next_pcs
;
4188 /* Effectively inserts the breakpoints. */
4189 for (index
= 0; index
<= last_breakpoint
; index
++)
4190 next_pcs
.push_back (breaks
[index
]);
4195 static std::vector
<CORE_ADDR
>
4196 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4198 if (mips_pc_is_mips (pc
))
4199 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4200 else if (mips_pc_is_micromips (gdbarch
, pc
))
4201 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4206 /* mips_software_single_step() is called just before we want to resume
4207 the inferior, if we want to single-step it but there is no hardware
4208 or kernel single-step support (MIPS on GNU/Linux for example). We find
4209 the target of the coming instruction and breakpoint it. */
4211 std::vector
<CORE_ADDR
>
4212 mips_software_single_step (struct regcache
*regcache
)
4214 struct gdbarch
*gdbarch
= regcache
->arch ();
4215 CORE_ADDR pc
, next_pc
;
4217 pc
= regcache_read_pc (regcache
);
4218 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4220 if (!next_pcs
.empty ())
4223 next_pc
= mips_next_pc (regcache
, pc
);
4228 /* Test whether the PC points to the return instruction at the
4229 end of a function. */
4232 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4237 /* This used to check for MIPS16, but this piece of code is never
4238 called for MIPS16 functions. And likewise microMIPS ones. */
4239 gdb_assert (mips_pc_is_mips (pc
));
4241 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4243 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4247 /* This fencepost looks highly suspicious to me. Removing it also
4248 seems suspicious as it could affect remote debugging across serial
4252 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4258 struct inferior
*inf
;
4260 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4262 fence
= start_pc
- heuristic_fence_post
;
4266 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4267 fence
= VM_MIN_ADDRESS
;
4269 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4271 inf
= current_inferior ();
4273 /* Search back for previous return. */
4274 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4275 if (start_pc
< fence
)
4277 /* It's not clear to me why we reach this point when
4278 stop_soon, but with this test, at least we
4279 don't print out warnings for every child forked (eg, on
4280 decstation). 22apr93 rich@cygnus.com. */
4281 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4283 static int blurb_printed
= 0;
4285 warning (_("GDB can't find the start of the function at %s."),
4286 paddress (gdbarch
, pc
));
4290 /* This actually happens frequently in embedded
4291 development, when you first connect to a board
4292 and your stack pointer and pc are nowhere in
4293 particular. This message needs to give people
4294 in that situation enough information to
4295 determine that it's no big deal. */
4296 printf_filtered ("\n\
4297 GDB is unable to find the start of the function at %s\n\
4298 and thus can't determine the size of that function's stack frame.\n\
4299 This means that GDB may be unable to access that stack frame, or\n\
4300 the frames below it.\n\
4301 This problem is most likely caused by an invalid program counter or\n\
4303 However, if you think GDB should simply search farther back\n\
4304 from %s for code which looks like the beginning of a\n\
4305 function, you can increase the range of the search using the `set\n\
4306 heuristic-fence-post' command.\n",
4307 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4314 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4316 unsigned short inst
;
4318 /* On MIPS16, any one of the following is likely to be the
4319 start of a function:
4325 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4326 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4327 if ((inst
& 0xff80) == 0x6480) /* save */
4329 if (start_pc
- instlen
>= fence
)
4331 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4332 start_pc
- instlen
, NULL
);
4333 if ((inst
& 0xf800) == 0xf000) /* extend */
4334 start_pc
-= instlen
;
4338 else if (((inst
& 0xf81f) == 0xe809
4339 && (inst
& 0x700) != 0x700) /* entry */
4340 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4341 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4342 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4344 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4345 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4350 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4358 /* On microMIPS, any one of the following is likely to be the
4359 start of a function:
4363 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4364 switch (micromips_op (insn
))
4366 case 0xc: /* ADDIU: bits 001100 */
4367 case 0x17: /* DADDIU: bits 010111 */
4368 sreg
= b0s5_reg (insn
);
4369 dreg
= b5s5_reg (insn
);
4371 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4372 pc
+ MIPS_INSN16_SIZE
, NULL
);
4373 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4374 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4375 /* (D)ADDIU $sp, imm */
4380 case 0x10: /* POOL32I: bits 010000 */
4381 if (b5s5_op (insn
) == 0xd
4382 /* LUI: bits 010000 001101 */
4383 && b0s5_reg (insn
>> 16) == 28)
4388 case 0x13: /* POOL16D: bits 010011 */
4389 if ((insn
& 0x1) == 0x1)
4390 /* ADDIUSP: bits 010011 1 */
4392 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4398 /* ADDIUS5: bits 010011 0 */
4400 dreg
= b5s5_reg (insn
);
4401 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4402 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4403 /* ADDIUS5 $sp, -imm */
4411 else if (mips_about_to_return (gdbarch
, start_pc
))
4413 /* Skip return and its delay slot. */
4414 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4421 struct mips_objfile_private
4427 /* According to the current ABI, should the type be passed in a
4428 floating-point register (assuming that there is space)? When there
4429 is no FPU, FP are not even considered as possible candidates for
4430 FP registers and, consequently this returns false - forces FP
4431 arguments into integer registers. */
4434 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4435 struct type
*arg_type
)
4437 return ((typecode
== TYPE_CODE_FLT
4438 || (mips_eabi (gdbarch
)
4439 && (typecode
== TYPE_CODE_STRUCT
4440 || typecode
== TYPE_CODE_UNION
)
4441 && arg_type
->num_fields () == 1
4442 && check_typedef (arg_type
->field (0).type ())->code ()
4444 && mips_get_fpu_type (gdbarch
) != MIPS_FPU_NONE
);
4447 /* On o32, argument passing in GPRs depends on the alignment of the type being
4448 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4451 mips_type_needs_double_align (struct type
*type
)
4453 enum type_code typecode
= type
->code ();
4455 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4457 else if (typecode
== TYPE_CODE_STRUCT
)
4459 if (type
->num_fields () < 1)
4461 return mips_type_needs_double_align (type
->field (0).type ());
4463 else if (typecode
== TYPE_CODE_UNION
)
4467 n
= type
->num_fields ();
4468 for (i
= 0; i
< n
; i
++)
4469 if (mips_type_needs_double_align (type
->field (i
).type ()))
4476 /* Adjust the address downward (direction of stack growth) so that it
4477 is correctly aligned for a new stack frame. */
4479 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4481 return align_down (addr
, 16);
4484 /* Implement the "push_dummy_code" gdbarch method. */
4487 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4488 CORE_ADDR funaddr
, struct value
**args
,
4489 int nargs
, struct type
*value_type
,
4490 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4491 struct regcache
*regcache
)
4493 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4497 /* Reserve enough room on the stack for our breakpoint instruction. */
4498 bp_slot
= sp
- sizeof (nop_insn
);
4500 /* Return to microMIPS mode if calling microMIPS code to avoid
4501 triggering an address error exception on processors that only
4502 support microMIPS execution. */
4503 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4504 ? make_compact_addr (bp_slot
) : bp_slot
);
4506 /* The breakpoint layer automatically adjusts the address of
4507 breakpoints inserted in a branch delay slot. With enough
4508 bad luck, the 4 bytes located just before our breakpoint
4509 instruction could look like a branch instruction, and thus
4510 trigger the adjustement, and break the function call entirely.
4511 So, we reserve those 4 bytes and write a nop instruction
4512 to prevent that from happening. */
4513 nop_addr
= bp_slot
- sizeof (nop_insn
);
4514 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4515 sp
= mips_frame_align (gdbarch
, nop_addr
);
4517 /* Inferior resumes at the function entry point. */
4524 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4525 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4526 int nargs
, struct value
**args
, CORE_ADDR sp
,
4527 function_call_return_method return_method
,
4528 CORE_ADDR struct_addr
)
4534 int stack_offset
= 0;
4535 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4536 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4537 int abi_regsize
= mips_abi_regsize (gdbarch
);
4539 /* For shared libraries, "t9" needs to point at the function
4541 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4543 /* Set the return address register to point to the entry point of
4544 the program, where a breakpoint lies in wait. */
4545 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4547 /* First ensure that the stack and structure return address (if any)
4548 are properly aligned. The stack has to be at least 64-bit
4549 aligned even on 32-bit machines, because doubles must be 64-bit
4550 aligned. For n32 and n64, stack frames need to be 128-bit
4551 aligned, so we round to this widest known alignment. */
4553 sp
= align_down (sp
, 16);
4554 struct_addr
= align_down (struct_addr
, 16);
4556 /* Now make space on the stack for the args. We allocate more
4557 than necessary for EABI, because the first few arguments are
4558 passed in registers, but that's OK. */
4559 for (argnum
= 0; argnum
< nargs
; argnum
++)
4560 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4561 sp
-= align_up (arg_space
, 16);
4564 fprintf_unfiltered (gdb_stdlog
,
4565 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4566 paddress (gdbarch
, sp
),
4567 (long) align_up (arg_space
, 16));
4569 /* Initialize the integer and float register pointers. */
4570 argreg
= MIPS_A0_REGNUM
;
4571 float_argreg
= mips_fpa0_regnum (gdbarch
);
4573 /* The struct_return pointer occupies the first parameter-passing reg. */
4574 if (return_method
== return_method_struct
)
4577 fprintf_unfiltered (gdb_stdlog
,
4578 "mips_eabi_push_dummy_call: "
4579 "struct_return reg=%d %s\n",
4580 argreg
, paddress (gdbarch
, struct_addr
));
4581 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4584 /* Now load as many as possible of the first arguments into
4585 registers, and push the rest onto the stack. Loop thru args
4586 from first to last. */
4587 for (argnum
= 0; argnum
< nargs
; argnum
++)
4589 const gdb_byte
*val
;
4590 /* This holds the address of structures that are passed by
4592 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4593 struct value
*arg
= args
[argnum
];
4594 struct type
*arg_type
= check_typedef (value_type (arg
));
4595 int len
= TYPE_LENGTH (arg_type
);
4596 enum type_code typecode
= arg_type
->code ();
4599 fprintf_unfiltered (gdb_stdlog
,
4600 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4601 argnum
+ 1, len
, (int) typecode
);
4603 /* The EABI passes structures that do not fit in a register by
4605 if (len
> abi_regsize
4606 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4608 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4609 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4610 value_address (arg
));
4611 typecode
= TYPE_CODE_PTR
;
4615 fprintf_unfiltered (gdb_stdlog
, " push");
4618 val
= value_contents (arg
).data ();
4620 /* 32-bit ABIs always start floating point arguments in an
4621 even-numbered floating point register. Round the FP register
4622 up before the check to see if there are any FP registers
4623 left. Non MIPS_EABI targets also pass the FP in the integer
4624 registers so also round up normal registers. */
4625 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4627 if ((float_argreg
& 1))
4631 /* Floating point arguments passed in registers have to be
4632 treated specially. On 32-bit architectures, doubles
4633 are passed in register pairs; the even register gets
4634 the low word, and the odd register gets the high word.
4635 On non-EABI processors, the first two floating point arguments are
4636 also copied to general registers, because MIPS16 functions
4637 don't use float registers for arguments. This duplication of
4638 arguments in general registers can't hurt non-MIPS16 functions
4639 because those registers are normally skipped. */
4640 /* MIPS_EABI squeezes a struct that contains a single floating
4641 point value into an FP register instead of pushing it onto the
4643 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4644 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
4646 /* EABI32 will pass doubles in consecutive registers, even on
4647 64-bit cores. At one time, we used to check the size of
4648 `float_argreg' to determine whether or not to pass doubles
4649 in consecutive registers, but this is not sufficient for
4650 making the ABI determination. */
4651 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4653 int low_offset
= gdbarch_byte_order (gdbarch
)
4654 == BFD_ENDIAN_BIG
? 4 : 0;
4657 /* Write the low word of the double to the even register(s). */
4658 regval
= extract_signed_integer (val
+ low_offset
,
4661 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4662 float_argreg
, phex (regval
, 4));
4663 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4665 /* Write the high word of the double to the odd register(s). */
4666 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4669 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4670 float_argreg
, phex (regval
, 4));
4671 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4675 /* This is a floating point value that fits entirely
4676 in a single register. */
4677 /* On 32 bit ABI's the float_argreg is further adjusted
4678 above to ensure that it is even register aligned. */
4679 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4681 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4682 float_argreg
, phex (regval
, len
));
4683 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4688 /* Copy the argument to general registers or the stack in
4689 register-sized pieces. Large arguments are split between
4690 registers and stack. */
4691 /* Note: structs whose size is not a multiple of abi_regsize
4692 are treated specially: Irix cc passes
4693 them in registers where gcc sometimes puts them on the
4694 stack. For maximum compatibility, we will put them in
4696 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4698 /* Note: Floating-point values that didn't fit into an FP
4699 register are only written to memory. */
4702 /* Remember if the argument was written to the stack. */
4703 int stack_used_p
= 0;
4704 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4707 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4710 /* Write this portion of the argument to the stack. */
4711 if (argreg
> mips_last_arg_regnum (gdbarch
)
4713 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4715 /* Should shorter than int integer values be
4716 promoted to int before being stored? */
4717 int longword_offset
= 0;
4720 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4722 if (abi_regsize
== 8
4723 && (typecode
== TYPE_CODE_INT
4724 || typecode
== TYPE_CODE_PTR
4725 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4726 longword_offset
= abi_regsize
- len
;
4727 else if ((typecode
== TYPE_CODE_STRUCT
4728 || typecode
== TYPE_CODE_UNION
)
4729 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4730 longword_offset
= abi_regsize
- len
;
4735 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4736 paddress (gdbarch
, stack_offset
));
4737 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4738 paddress (gdbarch
, longword_offset
));
4741 addr
= sp
+ stack_offset
+ longword_offset
;
4746 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4747 paddress (gdbarch
, addr
));
4748 for (i
= 0; i
< partial_len
; i
++)
4750 fprintf_unfiltered (gdb_stdlog
, "%02x",
4754 write_memory (addr
, val
, partial_len
);
4757 /* Note!!! This is NOT an else clause. Odd sized
4758 structs may go thru BOTH paths. Floating point
4759 arguments will not. */
4760 /* Write this portion of the argument to a general
4761 purpose register. */
4762 if (argreg
<= mips_last_arg_regnum (gdbarch
)
4763 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4766 extract_signed_integer (val
, partial_len
, byte_order
);
4769 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4771 phex (regval
, abi_regsize
));
4772 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4779 /* Compute the offset into the stack at which we will
4780 copy the next parameter.
4782 In the new EABI (and the NABI32), the stack_offset
4783 only needs to be adjusted when it has been used. */
4786 stack_offset
+= align_up (partial_len
, abi_regsize
);
4790 fprintf_unfiltered (gdb_stdlog
, "\n");
4793 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4795 /* Return adjusted stack pointer. */
4799 /* Determine the return value convention being used. */
4801 static enum return_value_convention
4802 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4803 struct type
*type
, struct regcache
*regcache
,
4804 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4806 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
4807 int fp_return_type
= 0;
4808 int offset
, regnum
, xfer
;
4810 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4811 return RETURN_VALUE_STRUCT_CONVENTION
;
4813 /* Floating point type? */
4814 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4816 if (type
->code () == TYPE_CODE_FLT
)
4818 /* Structs with a single field of float type
4819 are returned in a floating point register. */
4820 if ((type
->code () == TYPE_CODE_STRUCT
4821 || type
->code () == TYPE_CODE_UNION
)
4822 && type
->num_fields () == 1)
4824 struct type
*fieldtype
= type
->field (0).type ();
4826 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4833 /* A floating-point value belongs in the least significant part
4836 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4837 regnum
= mips_regnum (gdbarch
)->fp0
;
4841 /* An integer value goes in V0/V1. */
4843 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4844 regnum
= MIPS_V0_REGNUM
;
4847 offset
< TYPE_LENGTH (type
);
4848 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4850 xfer
= mips_abi_regsize (gdbarch
);
4851 if (offset
+ xfer
> TYPE_LENGTH (type
))
4852 xfer
= TYPE_LENGTH (type
) - offset
;
4853 mips_xfer_register (gdbarch
, regcache
,
4854 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4855 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4859 return RETURN_VALUE_REGISTER_CONVENTION
;
4863 /* N32/N64 ABI stuff. */
4865 /* Search for a naturally aligned double at OFFSET inside a struct
4866 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4870 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4875 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4878 if (mips_get_fpu_type (gdbarch
) != MIPS_FPU_DOUBLE
)
4881 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4884 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4887 struct type
*field_type
;
4889 /* We're only looking at normal fields. */
4890 if (field_is_static (&arg_type
->field (i
))
4891 || (arg_type
->field (i
).loc_bitpos () % 8) != 0)
4894 /* If we have gone past the offset, there is no double to pass. */
4895 pos
= arg_type
->field (i
).loc_bitpos () / 8;
4899 field_type
= check_typedef (arg_type
->field (i
).type ());
4901 /* If this field is entirely before the requested offset, go
4902 on to the next one. */
4903 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4906 /* If this is our special aligned double, we can stop. */
4907 if (field_type
->code () == TYPE_CODE_FLT
4908 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4911 /* This field starts at or before the requested offset, and
4912 overlaps it. If it is a structure, recurse inwards. */
4913 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4920 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4921 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4922 int nargs
, struct value
**args
, CORE_ADDR sp
,
4923 function_call_return_method return_method
,
4924 CORE_ADDR struct_addr
)
4930 int stack_offset
= 0;
4931 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4932 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4934 /* For shared libraries, "t9" needs to point at the function
4936 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4938 /* Set the return address register to point to the entry point of
4939 the program, where a breakpoint lies in wait. */
4940 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4942 /* First ensure that the stack and structure return address (if any)
4943 are properly aligned. The stack has to be at least 64-bit
4944 aligned even on 32-bit machines, because doubles must be 64-bit
4945 aligned. For n32 and n64, stack frames need to be 128-bit
4946 aligned, so we round to this widest known alignment. */
4948 sp
= align_down (sp
, 16);
4949 struct_addr
= align_down (struct_addr
, 16);
4951 /* Now make space on the stack for the args. */
4952 for (argnum
= 0; argnum
< nargs
; argnum
++)
4953 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4954 sp
-= align_up (arg_space
, 16);
4957 fprintf_unfiltered (gdb_stdlog
,
4958 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4959 paddress (gdbarch
, sp
),
4960 (long) align_up (arg_space
, 16));
4962 /* Initialize the integer and float register pointers. */
4963 argreg
= MIPS_A0_REGNUM
;
4964 float_argreg
= mips_fpa0_regnum (gdbarch
);
4966 /* The struct_return pointer occupies the first parameter-passing reg. */
4967 if (return_method
== return_method_struct
)
4970 fprintf_unfiltered (gdb_stdlog
,
4971 "mips_n32n64_push_dummy_call: "
4972 "struct_return reg=%d %s\n",
4973 argreg
, paddress (gdbarch
, struct_addr
));
4974 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4977 /* Now load as many as possible of the first arguments into
4978 registers, and push the rest onto the stack. Loop thru args
4979 from first to last. */
4980 for (argnum
= 0; argnum
< nargs
; argnum
++)
4982 const gdb_byte
*val
;
4983 struct value
*arg
= args
[argnum
];
4984 struct type
*arg_type
= check_typedef (value_type (arg
));
4985 int len
= TYPE_LENGTH (arg_type
);
4986 enum type_code typecode
= arg_type
->code ();
4989 fprintf_unfiltered (gdb_stdlog
,
4990 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4991 argnum
+ 1, len
, (int) typecode
);
4993 val
= value_contents (arg
).data ();
4995 /* A 128-bit long double value requires an even-odd pair of
4996 floating-point registers. */
4998 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4999 && (float_argreg
& 1))
5005 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5006 && argreg
<= mips_last_arg_regnum (gdbarch
))
5008 /* This is a floating point value that fits entirely
5009 in a single register or a pair of registers. */
5010 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5011 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
5013 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5014 float_argreg
, phex (regval
, reglen
));
5015 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5018 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5019 argreg
, phex (regval
, reglen
));
5020 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5025 regval
= extract_unsigned_integer (val
+ reglen
,
5026 reglen
, byte_order
);
5028 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5029 float_argreg
, phex (regval
, reglen
));
5030 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5033 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5034 argreg
, phex (regval
, reglen
));
5035 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5042 /* Copy the argument to general registers or the stack in
5043 register-sized pieces. Large arguments are split between
5044 registers and stack. */
5045 /* For N32/N64, structs, unions, or other composite types are
5046 treated as a sequence of doublewords, and are passed in integer
5047 or floating point registers as though they were simple scalar
5048 parameters to the extent that they fit, with any excess on the
5049 stack packed according to the normal memory layout of the
5051 The caller does not reserve space for the register arguments;
5052 the callee is responsible for reserving it if required. */
5053 /* Note: Floating-point values that didn't fit into an FP
5054 register are only written to memory. */
5057 /* Remember if the argument was written to the stack. */
5058 int stack_used_p
= 0;
5059 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5062 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5065 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5066 gdb_assert (argreg
> mips_last_arg_regnum (gdbarch
));
5068 /* Write this portion of the argument to the stack. */
5069 if (argreg
> mips_last_arg_regnum (gdbarch
))
5071 /* Should shorter than int integer values be
5072 promoted to int before being stored? */
5073 int longword_offset
= 0;
5076 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5078 if ((typecode
== TYPE_CODE_INT
5079 || typecode
== TYPE_CODE_PTR
)
5081 longword_offset
= MIPS64_REGSIZE
- len
;
5086 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5087 paddress (gdbarch
, stack_offset
));
5088 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5089 paddress (gdbarch
, longword_offset
));
5092 addr
= sp
+ stack_offset
+ longword_offset
;
5097 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5098 paddress (gdbarch
, addr
));
5099 for (i
= 0; i
< partial_len
; i
++)
5101 fprintf_unfiltered (gdb_stdlog
, "%02x",
5105 write_memory (addr
, val
, partial_len
);
5108 /* Note!!! This is NOT an else clause. Odd sized
5109 structs may go thru BOTH paths. */
5110 /* Write this portion of the argument to a general
5111 purpose register. */
5112 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5116 /* Sign extend pointers, 32-bit integers and signed
5117 16-bit and 8-bit integers; everything else is taken
5120 if ((partial_len
== 4
5121 && (typecode
== TYPE_CODE_PTR
5122 || typecode
== TYPE_CODE_INT
))
5124 && typecode
== TYPE_CODE_INT
5125 && !arg_type
->is_unsigned ()))
5126 regval
= extract_signed_integer (val
, partial_len
,
5129 regval
= extract_unsigned_integer (val
, partial_len
,
5132 /* A non-floating-point argument being passed in a
5133 general register. If a struct or union, and if
5134 the remaining length is smaller than the register
5135 size, we have to adjust the register value on
5138 It does not seem to be necessary to do the
5139 same for integral types. */
5141 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5142 && partial_len
< MIPS64_REGSIZE
5143 && (typecode
== TYPE_CODE_STRUCT
5144 || typecode
== TYPE_CODE_UNION
))
5145 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5149 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5151 phex (regval
, MIPS64_REGSIZE
));
5152 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5154 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5155 TYPE_LENGTH (arg_type
) - len
))
5158 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5160 phex (regval
, MIPS64_REGSIZE
));
5161 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5172 /* Compute the offset into the stack at which we will
5173 copy the next parameter.
5175 In N32 (N64?), the stack_offset only needs to be
5176 adjusted when it has been used. */
5179 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5183 fprintf_unfiltered (gdb_stdlog
, "\n");
5186 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5188 /* Return adjusted stack pointer. */
5192 static enum return_value_convention
5193 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5194 struct type
*type
, struct regcache
*regcache
,
5195 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5197 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5199 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5201 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5202 if needed), as appropriate for the type. Composite results (struct,
5203 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5206 * A struct with only one or two floating point fields is returned in $f0
5207 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5210 * Any other composite results of at most 128 bits are returned in
5211 $2 (first 64 bits) and $3 (remainder, if necessary).
5213 * Larger composite results are handled by converting the function to a
5214 procedure with an implicit first parameter, which is a pointer to an area
5215 reserved by the caller to receive the result. [The o32-bit ABI requires
5216 that all composite results be handled by conversion to implicit first
5217 parameters. The MIPS/SGI Fortran implementation has always made a
5218 specific exception to return COMPLEX results in the floating point
5221 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5222 return RETURN_VALUE_STRUCT_CONVENTION
;
5223 else if (type
->code () == TYPE_CODE_FLT
5224 && TYPE_LENGTH (type
) == 16
5225 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5227 /* A 128-bit floating-point value fills both $f0 and $f2. The
5228 two registers are used in the same as memory order, so the
5229 eight bytes with the lower memory address are in $f0. */
5231 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5232 mips_xfer_register (gdbarch
, regcache
,
5233 (gdbarch_num_regs (gdbarch
)
5234 + mips_regnum (gdbarch
)->fp0
),
5235 8, gdbarch_byte_order (gdbarch
),
5236 readbuf
, writebuf
, 0);
5237 mips_xfer_register (gdbarch
, regcache
,
5238 (gdbarch_num_regs (gdbarch
)
5239 + mips_regnum (gdbarch
)->fp0
+ 2),
5240 8, gdbarch_byte_order (gdbarch
),
5241 readbuf
? readbuf
+ 8 : readbuf
,
5242 writebuf
? writebuf
+ 8 : writebuf
, 0);
5243 return RETURN_VALUE_REGISTER_CONVENTION
;
5245 else if (type
->code () == TYPE_CODE_FLT
5246 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5248 /* A single or double floating-point value that fits in FP0. */
5250 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5251 mips_xfer_register (gdbarch
, regcache
,
5252 (gdbarch_num_regs (gdbarch
)
5253 + mips_regnum (gdbarch
)->fp0
),
5255 gdbarch_byte_order (gdbarch
),
5256 readbuf
, writebuf
, 0);
5257 return RETURN_VALUE_REGISTER_CONVENTION
;
5259 else if (type
->code () == TYPE_CODE_STRUCT
5260 && type
->num_fields () <= 2
5261 && type
->num_fields () >= 1
5262 && ((type
->num_fields () == 1
5263 && (check_typedef (type
->field (0).type ())->code ()
5265 || (type
->num_fields () == 2
5266 && (check_typedef (type
->field (0).type ())->code ()
5268 && (check_typedef (type
->field (1).type ())->code ()
5269 == TYPE_CODE_FLT
))))
5271 /* A struct that contains one or two floats. Each value is part
5272 in the least significant part of their floating point
5273 register (or GPR, for soft float). */
5276 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5277 ? mips_regnum (gdbarch
)->fp0
5279 field
< type
->num_fields (); field
++, regnum
+= 2)
5281 int offset
= type
->field (field
).loc_bitpos () / TARGET_CHAR_BIT
;
5283 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5285 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5287 /* A 16-byte long double field goes in two consecutive
5289 mips_xfer_register (gdbarch
, regcache
,
5290 gdbarch_num_regs (gdbarch
) + regnum
,
5292 gdbarch_byte_order (gdbarch
),
5293 readbuf
, writebuf
, offset
);
5294 mips_xfer_register (gdbarch
, regcache
,
5295 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5297 gdbarch_byte_order (gdbarch
),
5298 readbuf
, writebuf
, offset
+ 8);
5301 mips_xfer_register (gdbarch
, regcache
,
5302 gdbarch_num_regs (gdbarch
) + regnum
,
5303 TYPE_LENGTH (type
->field (field
).type ()),
5304 gdbarch_byte_order (gdbarch
),
5305 readbuf
, writebuf
, offset
);
5307 return RETURN_VALUE_REGISTER_CONVENTION
;
5309 else if (type
->code () == TYPE_CODE_STRUCT
5310 || type
->code () == TYPE_CODE_UNION
5311 || type
->code () == TYPE_CODE_ARRAY
)
5313 /* A composite type. Extract the left justified value,
5314 regardless of the byte order. I.e. DO NOT USE
5318 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5319 offset
< TYPE_LENGTH (type
);
5320 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5322 int xfer
= register_size (gdbarch
, regnum
);
5323 if (offset
+ xfer
> TYPE_LENGTH (type
))
5324 xfer
= TYPE_LENGTH (type
) - offset
;
5326 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5327 offset
, xfer
, regnum
);
5328 mips_xfer_register (gdbarch
, regcache
,
5329 gdbarch_num_regs (gdbarch
) + regnum
,
5330 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5333 return RETURN_VALUE_REGISTER_CONVENTION
;
5337 /* A scalar extract each part but least-significant-byte
5341 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5342 offset
< TYPE_LENGTH (type
);
5343 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5345 int xfer
= register_size (gdbarch
, regnum
);
5346 if (offset
+ xfer
> TYPE_LENGTH (type
))
5347 xfer
= TYPE_LENGTH (type
) - offset
;
5349 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5350 offset
, xfer
, regnum
);
5351 mips_xfer_register (gdbarch
, regcache
,
5352 gdbarch_num_regs (gdbarch
) + regnum
,
5353 xfer
, gdbarch_byte_order (gdbarch
),
5354 readbuf
, writebuf
, offset
);
5356 return RETURN_VALUE_REGISTER_CONVENTION
;
5360 /* Which registers to use for passing floating-point values between
5361 function calls, one of floating-point, general and both kinds of
5362 registers. O32 and O64 use different register kinds for standard
5363 MIPS and MIPS16 code; to make the handling of cases where we may
5364 not know what kind of code is being used (e.g. no debug information)
5365 easier we sometimes use both kinds. */
5374 /* O32 ABI stuff. */
5377 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5378 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5379 int nargs
, struct value
**args
, CORE_ADDR sp
,
5380 function_call_return_method return_method
,
5381 CORE_ADDR struct_addr
)
5387 int stack_offset
= 0;
5388 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5389 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5391 /* For shared libraries, "t9" needs to point at the function
5393 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5395 /* Set the return address register to point to the entry point of
5396 the program, where a breakpoint lies in wait. */
5397 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5399 /* First ensure that the stack and structure return address (if any)
5400 are properly aligned. The stack has to be at least 64-bit
5401 aligned even on 32-bit machines, because doubles must be 64-bit
5402 aligned. For n32 and n64, stack frames need to be 128-bit
5403 aligned, so we round to this widest known alignment. */
5405 sp
= align_down (sp
, 16);
5406 struct_addr
= align_down (struct_addr
, 16);
5408 /* Now make space on the stack for the args. */
5409 for (argnum
= 0; argnum
< nargs
; argnum
++)
5411 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5413 /* Align to double-word if necessary. */
5414 if (mips_type_needs_double_align (arg_type
))
5415 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5416 /* Allocate space on the stack. */
5417 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5419 sp
-= align_up (arg_space
, 16);
5422 fprintf_unfiltered (gdb_stdlog
,
5423 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5424 paddress (gdbarch
, sp
),
5425 (long) align_up (arg_space
, 16));
5427 /* Initialize the integer and float register pointers. */
5428 argreg
= MIPS_A0_REGNUM
;
5429 float_argreg
= mips_fpa0_regnum (gdbarch
);
5431 /* The struct_return pointer occupies the first parameter-passing reg. */
5432 if (return_method
== return_method_struct
)
5435 fprintf_unfiltered (gdb_stdlog
,
5436 "mips_o32_push_dummy_call: "
5437 "struct_return reg=%d %s\n",
5438 argreg
, paddress (gdbarch
, struct_addr
));
5439 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5440 stack_offset
+= MIPS32_REGSIZE
;
5443 /* Now load as many as possible of the first arguments into
5444 registers, and push the rest onto the stack. Loop thru args
5445 from first to last. */
5446 for (argnum
= 0; argnum
< nargs
; argnum
++)
5448 const gdb_byte
*val
;
5449 struct value
*arg
= args
[argnum
];
5450 struct type
*arg_type
= check_typedef (value_type (arg
));
5451 int len
= TYPE_LENGTH (arg_type
);
5452 enum type_code typecode
= arg_type
->code ();
5455 fprintf_unfiltered (gdb_stdlog
,
5456 "mips_o32_push_dummy_call: %d len=%d type=%d",
5457 argnum
+ 1, len
, (int) typecode
);
5459 val
= value_contents (arg
).data ();
5461 /* 32-bit ABIs always start floating point arguments in an
5462 even-numbered floating point register. Round the FP register
5463 up before the check to see if there are any FP registers
5464 left. O32 targets also pass the FP in the integer registers
5465 so also round up normal registers. */
5466 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5468 if ((float_argreg
& 1))
5472 /* Floating point arguments passed in registers have to be
5473 treated specially. On 32-bit architectures, doubles are
5474 passed in register pairs; the even FP register gets the
5475 low word, and the odd FP register gets the high word.
5476 On O32, the first two floating point arguments are also
5477 copied to general registers, following their memory order,
5478 because MIPS16 functions don't use float registers for
5479 arguments. This duplication of arguments in general
5480 registers can't hurt non-MIPS16 functions, because those
5481 registers are normally skipped. */
5483 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5484 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5486 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5488 int freg_offset
= gdbarch_byte_order (gdbarch
)
5489 == BFD_ENDIAN_BIG
? 1 : 0;
5490 unsigned long regval
;
5493 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5495 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5496 float_argreg
+ freg_offset
,
5498 regcache_cooked_write_unsigned (regcache
,
5499 float_argreg
++ + freg_offset
,
5502 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5503 argreg
, phex (regval
, 4));
5504 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5507 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5509 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5510 float_argreg
- freg_offset
,
5512 regcache_cooked_write_unsigned (regcache
,
5513 float_argreg
++ - freg_offset
,
5516 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5517 argreg
, phex (regval
, 4));
5518 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5522 /* This is a floating point value that fits entirely
5523 in a single register. */
5524 /* On 32 bit ABI's the float_argreg is further adjusted
5525 above to ensure that it is even register aligned. */
5526 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5528 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5529 float_argreg
, phex (regval
, len
));
5530 regcache_cooked_write_unsigned (regcache
,
5531 float_argreg
++, regval
);
5532 /* Although two FP registers are reserved for each
5533 argument, only one corresponding integer register is
5536 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5537 argreg
, phex (regval
, len
));
5538 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5540 /* Reserve space for the FP register. */
5541 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5545 /* Copy the argument to general registers or the stack in
5546 register-sized pieces. Large arguments are split between
5547 registers and stack. */
5548 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5549 are treated specially: Irix cc passes
5550 them in registers where gcc sometimes puts them on the
5551 stack. For maximum compatibility, we will put them in
5553 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5554 && len
% MIPS32_REGSIZE
!= 0);
5555 /* Structures should be aligned to eight bytes (even arg registers)
5556 on MIPS_ABI_O32, if their first member has double precision. */
5557 if (mips_type_needs_double_align (arg_type
))
5562 stack_offset
+= MIPS32_REGSIZE
;
5567 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5570 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5573 /* Write this portion of the argument to the stack. */
5574 if (argreg
> mips_last_arg_regnum (gdbarch
)
5575 || odd_sized_struct
)
5577 /* Should shorter than int integer values be
5578 promoted to int before being stored? */
5579 int longword_offset
= 0;
5584 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5585 paddress (gdbarch
, stack_offset
));
5586 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5587 paddress (gdbarch
, longword_offset
));
5590 addr
= sp
+ stack_offset
+ longword_offset
;
5595 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5596 paddress (gdbarch
, addr
));
5597 for (i
= 0; i
< partial_len
; i
++)
5599 fprintf_unfiltered (gdb_stdlog
, "%02x",
5603 write_memory (addr
, val
, partial_len
);
5606 /* Note!!! This is NOT an else clause. Odd sized
5607 structs may go thru BOTH paths. */
5608 /* Write this portion of the argument to a general
5609 purpose register. */
5610 if (argreg
<= mips_last_arg_regnum (gdbarch
))
5612 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5614 /* Value may need to be sign extended, because
5615 mips_isa_regsize() != mips_abi_regsize(). */
5617 /* A non-floating-point argument being passed in a
5618 general register. If a struct or union, and if
5619 the remaining length is smaller than the register
5620 size, we have to adjust the register value on
5623 It does not seem to be necessary to do the
5624 same for integral types.
5626 Also don't do this adjustment on O64 binaries.
5628 cagney/2001-07-23: gdb/179: Also, GCC, when
5629 outputting LE O32 with sizeof (struct) <
5630 mips_abi_regsize(), generates a left shift
5631 as part of storing the argument in a register
5632 (the left shift isn't generated when
5633 sizeof (struct) >= mips_abi_regsize()). Since
5634 it is quite possible that this is GCC
5635 contradicting the LE/O32 ABI, GDB has not been
5636 adjusted to accommodate this. Either someone
5637 needs to demonstrate that the LE/O32 ABI
5638 specifies such a left shift OR this new ABI gets
5639 identified as such and GDB gets tweaked
5642 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5643 && partial_len
< MIPS32_REGSIZE
5644 && (typecode
== TYPE_CODE_STRUCT
5645 || typecode
== TYPE_CODE_UNION
))
5646 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5650 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5652 phex (regval
, MIPS32_REGSIZE
));
5653 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5656 /* Prevent subsequent floating point arguments from
5657 being passed in floating point registers. */
5658 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
5664 /* Compute the offset into the stack at which we will
5665 copy the next parameter.
5667 In older ABIs, the caller reserved space for
5668 registers that contained arguments. This was loosely
5669 refered to as their "home". Consequently, space is
5670 always allocated. */
5672 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5676 fprintf_unfiltered (gdb_stdlog
, "\n");
5679 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5681 /* Return adjusted stack pointer. */
5685 static enum return_value_convention
5686 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5687 struct type
*type
, struct regcache
*regcache
,
5688 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5690 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5691 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5692 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
5693 enum mips_fval_reg fval_reg
;
5695 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5696 if (type
->code () == TYPE_CODE_STRUCT
5697 || type
->code () == TYPE_CODE_UNION
5698 || type
->code () == TYPE_CODE_ARRAY
)
5699 return RETURN_VALUE_STRUCT_CONVENTION
;
5700 else if (type
->code () == TYPE_CODE_FLT
5701 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5703 /* A single-precision floating-point value. If reading in or copying,
5704 then we get it from/put it to FP0 for standard MIPS code or GPR2
5705 for MIPS16 code. If writing out only, then we put it to both FP0
5706 and GPR2. We do not support reading in with no function known, if
5707 this safety check ever triggers, then we'll have to try harder. */
5708 gdb_assert (function
|| !readbuf
);
5713 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5716 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5718 case mips_fval_both
:
5719 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5722 if (fval_reg
!= mips_fval_gpr
)
5723 mips_xfer_register (gdbarch
, regcache
,
5724 (gdbarch_num_regs (gdbarch
)
5725 + mips_regnum (gdbarch
)->fp0
),
5727 gdbarch_byte_order (gdbarch
),
5728 readbuf
, writebuf
, 0);
5729 if (fval_reg
!= mips_fval_fpr
)
5730 mips_xfer_register (gdbarch
, regcache
,
5731 gdbarch_num_regs (gdbarch
) + 2,
5733 gdbarch_byte_order (gdbarch
),
5734 readbuf
, writebuf
, 0);
5735 return RETURN_VALUE_REGISTER_CONVENTION
;
5737 else if (type
->code () == TYPE_CODE_FLT
5738 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5740 /* A double-precision floating-point value. If reading in or copying,
5741 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5742 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5743 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5744 no function known, if this safety check ever triggers, then we'll
5745 have to try harder. */
5746 gdb_assert (function
|| !readbuf
);
5751 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5754 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5756 case mips_fval_both
:
5757 fprintf_unfiltered (gdb_stderr
,
5758 "Return float in $fp1/$fp0 and $2/$3\n");
5761 if (fval_reg
!= mips_fval_gpr
)
5763 /* The most significant part goes in FP1, and the least significant
5765 switch (gdbarch_byte_order (gdbarch
))
5767 case BFD_ENDIAN_LITTLE
:
5768 mips_xfer_register (gdbarch
, regcache
,
5769 (gdbarch_num_regs (gdbarch
)
5770 + mips_regnum (gdbarch
)->fp0
+ 0),
5771 4, gdbarch_byte_order (gdbarch
),
5772 readbuf
, writebuf
, 0);
5773 mips_xfer_register (gdbarch
, regcache
,
5774 (gdbarch_num_regs (gdbarch
)
5775 + mips_regnum (gdbarch
)->fp0
+ 1),
5776 4, gdbarch_byte_order (gdbarch
),
5777 readbuf
, writebuf
, 4);
5779 case BFD_ENDIAN_BIG
:
5780 mips_xfer_register (gdbarch
, regcache
,
5781 (gdbarch_num_regs (gdbarch
)
5782 + mips_regnum (gdbarch
)->fp0
+ 1),
5783 4, gdbarch_byte_order (gdbarch
),
5784 readbuf
, writebuf
, 0);
5785 mips_xfer_register (gdbarch
, regcache
,
5786 (gdbarch_num_regs (gdbarch
)
5787 + mips_regnum (gdbarch
)->fp0
+ 0),
5788 4, gdbarch_byte_order (gdbarch
),
5789 readbuf
, writebuf
, 4);
5792 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5795 if (fval_reg
!= mips_fval_fpr
)
5797 /* The two 32-bit parts are always placed in GPR2 and GPR3
5798 following these registers' memory order. */
5799 mips_xfer_register (gdbarch
, regcache
,
5800 gdbarch_num_regs (gdbarch
) + 2,
5801 4, gdbarch_byte_order (gdbarch
),
5802 readbuf
, writebuf
, 0);
5803 mips_xfer_register (gdbarch
, regcache
,
5804 gdbarch_num_regs (gdbarch
) + 3,
5805 4, gdbarch_byte_order (gdbarch
),
5806 readbuf
, writebuf
, 4);
5808 return RETURN_VALUE_REGISTER_CONVENTION
;
5811 else if (type
->code () == TYPE_CODE_STRUCT
5812 && type
->num_fields () <= 2
5813 && type
->num_fields () >= 1
5814 && ((type
->num_fields () == 1
5815 && (TYPE_CODE (type
->field (0).type ())
5817 || (type
->num_fields () == 2
5818 && (TYPE_CODE (type
->field (0).type ())
5820 && (TYPE_CODE (type
->field (1).type ())
5822 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5824 /* A struct that contains one or two floats. Each value is part
5825 in the least significant part of their floating point
5829 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5830 field
< type
->num_fields (); field
++, regnum
+= 2)
5832 int offset
= (type
->fields ()[field
].loc_bitpos () / TARGET_CHAR_BIT
);
5834 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5836 mips_xfer_register (gdbarch
, regcache
,
5837 gdbarch_num_regs (gdbarch
) + regnum
,
5838 TYPE_LENGTH (type
->field (field
).type ()),
5839 gdbarch_byte_order (gdbarch
),
5840 readbuf
, writebuf
, offset
);
5842 return RETURN_VALUE_REGISTER_CONVENTION
;
5846 else if (type
->code () == TYPE_CODE_STRUCT
5847 || type
->code () == TYPE_CODE_UNION
)
5849 /* A structure or union. Extract the left justified value,
5850 regardless of the byte order. I.e. DO NOT USE
5854 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5855 offset
< TYPE_LENGTH (type
);
5856 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5858 int xfer
= register_size (gdbarch
, regnum
);
5859 if (offset
+ xfer
> TYPE_LENGTH (type
))
5860 xfer
= TYPE_LENGTH (type
) - offset
;
5862 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5863 offset
, xfer
, regnum
);
5864 mips_xfer_register (gdbarch
, regcache
,
5865 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5866 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5868 return RETURN_VALUE_REGISTER_CONVENTION
;
5873 /* A scalar extract each part but least-significant-byte
5874 justified. o32 thinks registers are 4 byte, regardless of
5878 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5879 offset
< TYPE_LENGTH (type
);
5880 offset
+= MIPS32_REGSIZE
, regnum
++)
5882 int xfer
= MIPS32_REGSIZE
;
5883 if (offset
+ xfer
> TYPE_LENGTH (type
))
5884 xfer
= TYPE_LENGTH (type
) - offset
;
5886 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5887 offset
, xfer
, regnum
);
5888 mips_xfer_register (gdbarch
, regcache
,
5889 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5890 gdbarch_byte_order (gdbarch
),
5891 readbuf
, writebuf
, offset
);
5893 return RETURN_VALUE_REGISTER_CONVENTION
;
5897 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5901 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5902 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5904 struct value
**args
, CORE_ADDR sp
,
5905 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5911 int stack_offset
= 0;
5912 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5913 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5915 /* For shared libraries, "t9" needs to point at the function
5917 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5919 /* Set the return address register to point to the entry point of
5920 the program, where a breakpoint lies in wait. */
5921 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5923 /* First ensure that the stack and structure return address (if any)
5924 are properly aligned. The stack has to be at least 64-bit
5925 aligned even on 32-bit machines, because doubles must be 64-bit
5926 aligned. For n32 and n64, stack frames need to be 128-bit
5927 aligned, so we round to this widest known alignment. */
5929 sp
= align_down (sp
, 16);
5930 struct_addr
= align_down (struct_addr
, 16);
5932 /* Now make space on the stack for the args. */
5933 for (argnum
= 0; argnum
< nargs
; argnum
++)
5935 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5937 /* Allocate space on the stack. */
5938 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5940 sp
-= align_up (arg_space
, 16);
5943 fprintf_unfiltered (gdb_stdlog
,
5944 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5945 paddress (gdbarch
, sp
),
5946 (long) align_up (arg_space
, 16));
5948 /* Initialize the integer and float register pointers. */
5949 argreg
= MIPS_A0_REGNUM
;
5950 float_argreg
= mips_fpa0_regnum (gdbarch
);
5952 /* The struct_return pointer occupies the first parameter-passing reg. */
5953 if (return_method
== return_method_struct
)
5956 fprintf_unfiltered (gdb_stdlog
,
5957 "mips_o64_push_dummy_call: "
5958 "struct_return reg=%d %s\n",
5959 argreg
, paddress (gdbarch
, struct_addr
));
5960 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5961 stack_offset
+= MIPS64_REGSIZE
;
5964 /* Now load as many as possible of the first arguments into
5965 registers, and push the rest onto the stack. Loop thru args
5966 from first to last. */
5967 for (argnum
= 0; argnum
< nargs
; argnum
++)
5969 const gdb_byte
*val
;
5970 struct value
*arg
= args
[argnum
];
5971 struct type
*arg_type
= check_typedef (value_type (arg
));
5972 int len
= TYPE_LENGTH (arg_type
);
5973 enum type_code typecode
= arg_type
->code ();
5976 fprintf_unfiltered (gdb_stdlog
,
5977 "mips_o64_push_dummy_call: %d len=%d type=%d",
5978 argnum
+ 1, len
, (int) typecode
);
5980 val
= value_contents (arg
).data ();
5982 /* Floating point arguments passed in registers have to be
5983 treated specially. On 32-bit architectures, doubles are
5984 passed in register pairs; the even FP register gets the
5985 low word, and the odd FP register gets the high word.
5986 On O64, the first two floating point arguments are also
5987 copied to general registers, because MIPS16 functions
5988 don't use float registers for arguments. This duplication
5989 of arguments in general registers can't hurt non-MIPS16
5990 functions because those registers are normally skipped. */
5992 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5993 && float_argreg
<= mips_last_fp_arg_regnum (gdbarch
))
5995 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5997 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5998 float_argreg
, phex (regval
, len
));
5999 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
6001 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
6002 argreg
, phex (regval
, len
));
6003 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6005 /* Reserve space for the FP register. */
6006 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
6010 /* Copy the argument to general registers or the stack in
6011 register-sized pieces. Large arguments are split between
6012 registers and stack. */
6013 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
6014 are treated specially: Irix cc passes them in registers
6015 where gcc sometimes puts them on the stack. For maximum
6016 compatibility, we will put them in both places. */
6017 int odd_sized_struct
= (len
> MIPS64_REGSIZE
6018 && len
% MIPS64_REGSIZE
!= 0);
6021 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
6024 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
6027 /* Write this portion of the argument to the stack. */
6028 if (argreg
> mips_last_arg_regnum (gdbarch
)
6029 || odd_sized_struct
)
6031 /* Should shorter than int integer values be
6032 promoted to int before being stored? */
6033 int longword_offset
= 0;
6035 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6037 if ((typecode
== TYPE_CODE_INT
6038 || typecode
== TYPE_CODE_PTR
6039 || typecode
== TYPE_CODE_FLT
)
6041 longword_offset
= MIPS64_REGSIZE
- len
;
6046 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6047 paddress (gdbarch
, stack_offset
));
6048 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6049 paddress (gdbarch
, longword_offset
));
6052 addr
= sp
+ stack_offset
+ longword_offset
;
6057 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6058 paddress (gdbarch
, addr
));
6059 for (i
= 0; i
< partial_len
; i
++)
6061 fprintf_unfiltered (gdb_stdlog
, "%02x",
6065 write_memory (addr
, val
, partial_len
);
6068 /* Note!!! This is NOT an else clause. Odd sized
6069 structs may go thru BOTH paths. */
6070 /* Write this portion of the argument to a general
6071 purpose register. */
6072 if (argreg
<= mips_last_arg_regnum (gdbarch
))
6074 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6076 /* Value may need to be sign extended, because
6077 mips_isa_regsize() != mips_abi_regsize(). */
6079 /* A non-floating-point argument being passed in a
6080 general register. If a struct or union, and if
6081 the remaining length is smaller than the register
6082 size, we have to adjust the register value on
6085 It does not seem to be necessary to do the
6086 same for integral types. */
6088 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6089 && partial_len
< MIPS64_REGSIZE
6090 && (typecode
== TYPE_CODE_STRUCT
6091 || typecode
== TYPE_CODE_UNION
))
6092 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6096 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6098 phex (regval
, MIPS64_REGSIZE
));
6099 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6102 /* Prevent subsequent floating point arguments from
6103 being passed in floating point registers. */
6104 float_argreg
= mips_last_fp_arg_regnum (gdbarch
) + 1;
6110 /* Compute the offset into the stack at which we will
6111 copy the next parameter.
6113 In older ABIs, the caller reserved space for
6114 registers that contained arguments. This was loosely
6115 refered to as their "home". Consequently, space is
6116 always allocated. */
6118 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6122 fprintf_unfiltered (gdb_stdlog
, "\n");
6125 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6127 /* Return adjusted stack pointer. */
6131 static enum return_value_convention
6132 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6133 struct type
*type
, struct regcache
*regcache
,
6134 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6136 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6137 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6138 enum mips_fval_reg fval_reg
;
6140 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6141 if (type
->code () == TYPE_CODE_STRUCT
6142 || type
->code () == TYPE_CODE_UNION
6143 || type
->code () == TYPE_CODE_ARRAY
)
6144 return RETURN_VALUE_STRUCT_CONVENTION
;
6145 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6147 /* A floating-point value. If reading in or copying, then we get it
6148 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6149 If writing out only, then we put it to both FP0 and GPR2. We do
6150 not support reading in with no function known, if this safety
6151 check ever triggers, then we'll have to try harder. */
6152 gdb_assert (function
|| !readbuf
);
6157 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6160 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6162 case mips_fval_both
:
6163 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6166 if (fval_reg
!= mips_fval_gpr
)
6167 mips_xfer_register (gdbarch
, regcache
,
6168 (gdbarch_num_regs (gdbarch
)
6169 + mips_regnum (gdbarch
)->fp0
),
6171 gdbarch_byte_order (gdbarch
),
6172 readbuf
, writebuf
, 0);
6173 if (fval_reg
!= mips_fval_fpr
)
6174 mips_xfer_register (gdbarch
, regcache
,
6175 gdbarch_num_regs (gdbarch
) + 2,
6177 gdbarch_byte_order (gdbarch
),
6178 readbuf
, writebuf
, 0);
6179 return RETURN_VALUE_REGISTER_CONVENTION
;
6183 /* A scalar extract each part but least-significant-byte
6187 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6188 offset
< TYPE_LENGTH (type
);
6189 offset
+= MIPS64_REGSIZE
, regnum
++)
6191 int xfer
= MIPS64_REGSIZE
;
6192 if (offset
+ xfer
> TYPE_LENGTH (type
))
6193 xfer
= TYPE_LENGTH (type
) - offset
;
6195 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6196 offset
, xfer
, regnum
);
6197 mips_xfer_register (gdbarch
, regcache
,
6198 gdbarch_num_regs (gdbarch
) + regnum
,
6199 xfer
, gdbarch_byte_order (gdbarch
),
6200 readbuf
, writebuf
, offset
);
6202 return RETURN_VALUE_REGISTER_CONVENTION
;
6206 /* Floating point register management.
6208 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6209 64bit operations, these early MIPS cpus treat fp register pairs
6210 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6211 registers and offer a compatibility mode that emulates the MIPS2 fp
6212 model. When operating in MIPS2 fp compat mode, later cpu's split
6213 double precision floats into two 32-bit chunks and store them in
6214 consecutive fp regs. To display 64-bit floats stored in this
6215 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6216 Throw in user-configurable endianness and you have a real mess.
6218 The way this works is:
6219 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6220 double-precision value will be split across two logical registers.
6221 The lower-numbered logical register will hold the low-order bits,
6222 regardless of the processor's endianness.
6223 - If we are on a 64-bit processor, and we are looking for a
6224 single-precision value, it will be in the low ordered bits
6225 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6226 save slot in memory.
6227 - If we are in 64-bit mode, everything is straightforward.
6229 Note that this code only deals with "live" registers at the top of the
6230 stack. We will attempt to deal with saved registers later, when
6231 the raw/cooked register interface is in place. (We need a general
6232 interface that can deal with dynamic saved register sizes -- fp
6233 regs could be 32 bits wide in one frame and 64 on the frame above
6236 /* Copy a 32-bit single-precision value from the current frame
6237 into rare_buffer. */
6240 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6241 gdb_byte
*rare_buffer
)
6243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6244 int raw_size
= register_size (gdbarch
, regno
);
6245 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6247 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6248 error (_("can't read register %d (%s)"),
6249 regno
, gdbarch_register_name (gdbarch
, regno
));
6252 /* We have a 64-bit value for this register. Find the low-order
6256 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6261 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6265 memcpy (rare_buffer
, raw_buffer
, 4);
6269 /* Copy a 64-bit double-precision value from the current frame into
6270 rare_buffer. This may include getting half of it from the next
6274 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6275 gdb_byte
*rare_buffer
)
6277 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6278 int raw_size
= register_size (gdbarch
, regno
);
6280 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6282 /* We have a 64-bit value for this register, and we should use
6284 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6285 error (_("can't read register %d (%s)"),
6286 regno
, gdbarch_register_name (gdbarch
, regno
));
6290 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6292 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6293 internal_error (__FILE__
, __LINE__
,
6294 _("mips_read_fp_register_double: bad access to "
6295 "odd-numbered FP register"));
6297 /* mips_read_fp_register_single will find the correct 32 bits from
6299 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6301 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6302 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6306 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6307 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6313 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6315 { /* Do values for FP (float) regs. */
6316 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6317 gdb_byte
*raw_buffer
;
6318 std::string flt_str
, dbl_str
;
6320 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6321 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6325 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6327 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6328 fprintf_filtered (file
, "%*s",
6329 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6332 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6334 struct value_print_options opts
;
6336 /* 4-byte registers: Print hex and floating. Also print even
6337 numbered registers as doubles. */
6338 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6339 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6341 get_formatted_print_options (&opts
, 'x');
6342 print_scalar_formatted (raw_buffer
,
6343 builtin_type (gdbarch
)->builtin_uint32
,
6346 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6348 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6350 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6351 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6353 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6358 struct value_print_options opts
;
6360 /* Eight byte registers: print each one as hex, float and double. */
6361 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6362 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6364 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6365 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6367 get_formatted_print_options (&opts
, 'x');
6368 print_scalar_formatted (raw_buffer
,
6369 builtin_type (gdbarch
)->builtin_uint64
,
6372 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6373 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6378 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6381 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6382 struct value_print_options opts
;
6385 if (mips_float_register_p (gdbarch
, regnum
))
6387 mips_print_fp_register (file
, frame
, regnum
);
6391 val
= get_frame_register_value (frame
, regnum
);
6393 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6395 /* The problem with printing numeric register names (r26, etc.) is that
6396 the user can't use them on input. Probably the best solution is to
6397 fix it so that either the numeric or the funky (a2, etc.) names
6398 are accepted on input. */
6399 if (regnum
< MIPS_NUMREGS
)
6400 fprintf_filtered (file
, "(r%d): ", regnum
);
6402 fprintf_filtered (file
, ": ");
6404 get_formatted_print_options (&opts
, 'x');
6405 value_print_scalar_formatted (val
, &opts
, 0, file
);
6408 /* Print IEEE exception condition bits in FLAGS. */
6411 print_fpu_flags (struct ui_file
*file
, int flags
)
6413 if (flags
& (1 << 0))
6414 fputs_filtered (" inexact", file
);
6415 if (flags
& (1 << 1))
6416 fputs_filtered (" uflow", file
);
6417 if (flags
& (1 << 2))
6418 fputs_filtered (" oflow", file
);
6419 if (flags
& (1 << 3))
6420 fputs_filtered (" div0", file
);
6421 if (flags
& (1 << 4))
6422 fputs_filtered (" inval", file
);
6423 if (flags
& (1 << 5))
6424 fputs_filtered (" unimp", file
);
6425 fputc_filtered ('\n', file
);
6428 /* Print interesting information about the floating point processor
6429 (if present) or emulator. */
6432 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6433 struct frame_info
*frame
, const char *args
)
6435 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6436 enum mips_fpu_type type
= mips_get_fpu_type (gdbarch
);
6440 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6441 type
= MIPS_FPU_NONE
;
6443 fprintf_filtered (file
, "fpu type: %s\n",
6444 type
== MIPS_FPU_DOUBLE
? "double-precision"
6445 : type
== MIPS_FPU_SINGLE
? "single-precision"
6448 if (type
== MIPS_FPU_NONE
)
6451 fprintf_filtered (file
, "reg size: %d bits\n",
6452 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6454 fputs_filtered ("cond :", file
);
6455 if (fcs
& (1 << 23))
6456 fputs_filtered (" 0", file
);
6457 for (i
= 1; i
<= 7; i
++)
6458 if (fcs
& (1 << (24 + i
)))
6459 fprintf_filtered (file
, " %d", i
);
6460 fputc_filtered ('\n', file
);
6462 fputs_filtered ("cause :", file
);
6463 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6464 fputs ("mask :", stdout
);
6465 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6466 fputs ("flags :", stdout
);
6467 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6469 fputs_filtered ("rounding: ", file
);
6472 case 0: fputs_filtered ("nearest\n", file
); break;
6473 case 1: fputs_filtered ("zero\n", file
); break;
6474 case 2: fputs_filtered ("+inf\n", file
); break;
6475 case 3: fputs_filtered ("-inf\n", file
); break;
6478 fputs_filtered ("flush :", file
);
6479 if (fcs
& (1 << 21))
6480 fputs_filtered (" nearest", file
);
6481 if (fcs
& (1 << 22))
6482 fputs_filtered (" override", file
);
6483 if (fcs
& (1 << 24))
6484 fputs_filtered (" zero", file
);
6485 if ((fcs
& (0xb << 21)) == 0)
6486 fputs_filtered (" no", file
);
6487 fputc_filtered ('\n', file
);
6489 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6490 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6491 fputc_filtered ('\n', file
);
6493 default_print_float_info (gdbarch
, file
, frame
, args
);
6496 /* Replacement for generic do_registers_info.
6497 Print regs in pretty columns. */
6500 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6503 fprintf_filtered (file
, " ");
6504 mips_print_fp_register (file
, frame
, regnum
);
6505 fprintf_filtered (file
, "\n");
6510 /* Print a row's worth of GP (int) registers, with name labels above. */
6513 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6516 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6517 /* Do values for GP (int) regs. */
6518 const gdb_byte
*raw_buffer
;
6519 struct value
*value
;
6520 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6525 /* For GP registers, we print a separate row of names above the vals. */
6526 for (col
= 0, regnum
= start_regnum
;
6527 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6530 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6531 continue; /* unused register */
6532 if (mips_float_register_p (gdbarch
, regnum
))
6533 break; /* End the row: reached FP register. */
6534 /* Large registers are handled separately. */
6535 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6538 break; /* End the row before this register. */
6540 /* Print this register on a row by itself. */
6541 mips_print_register (file
, frame
, regnum
);
6542 fprintf_filtered (file
, "\n");
6546 fprintf_filtered (file
, " ");
6547 fprintf_filtered (file
,
6548 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6549 gdbarch_register_name (gdbarch
, regnum
));
6556 /* Print the R0 to R31 names. */
6557 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6558 fprintf_filtered (file
, "\n R%-4d",
6559 start_regnum
% gdbarch_num_regs (gdbarch
));
6561 fprintf_filtered (file
, "\n ");
6563 /* Now print the values in hex, 4 or 8 to the row. */
6564 for (col
= 0, regnum
= start_regnum
;
6565 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6568 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6569 continue; /* unused register */
6570 if (mips_float_register_p (gdbarch
, regnum
))
6571 break; /* End row: reached FP register. */
6572 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6573 break; /* End row: large register. */
6575 /* OK: get the data in raw format. */
6576 value
= get_frame_register_value (frame
, regnum
);
6577 if (value_optimized_out (value
)
6578 || !value_entirely_available (value
))
6580 fprintf_filtered (file
, "%*s ",
6581 (int) mips_abi_regsize (gdbarch
) * 2,
6582 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6583 : "<unavailable>"));
6587 raw_buffer
= value_contents_all (value
).data ();
6588 /* pad small registers */
6590 byte
< (mips_abi_regsize (gdbarch
)
6591 - register_size (gdbarch
, regnum
)); byte
++)
6592 fprintf_filtered (file
, " ");
6593 /* Now print the register value in hex, endian order. */
6594 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6596 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6597 byte
< register_size (gdbarch
, regnum
); byte
++)
6598 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6600 for (byte
= register_size (gdbarch
, regnum
) - 1;
6602 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6603 fprintf_filtered (file
, " ");
6606 if (col
> 0) /* ie. if we actually printed anything... */
6607 fprintf_filtered (file
, "\n");
6612 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6615 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6616 struct frame_info
*frame
, int regnum
, int all
)
6618 if (regnum
!= -1) /* Do one specified register. */
6620 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6621 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6622 error (_("Not a valid register for the current processor type"));
6624 mips_print_register (file
, frame
, regnum
);
6625 fprintf_filtered (file
, "\n");
6628 /* Do all (or most) registers. */
6630 regnum
= gdbarch_num_regs (gdbarch
);
6631 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6633 if (mips_float_register_p (gdbarch
, regnum
))
6635 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6636 regnum
= print_fp_register_row (file
, frame
, regnum
);
6638 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6641 regnum
= print_gp_register_row (file
, frame
, regnum
);
6647 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6648 struct frame_info
*frame
)
6650 CORE_ADDR pc
= get_frame_pc (frame
);
6655 if ((mips_pc_is_mips (pc
)
6656 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6657 || (mips_pc_is_micromips (gdbarch
, pc
)
6658 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6659 || (mips_pc_is_mips16 (gdbarch
, pc
)
6660 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6663 isa
= mips_pc_isa (gdbarch
, pc
);
6664 /* _has_delay_slot above will have validated the read. */
6665 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6666 size
= mips_insn_size (isa
, insn
);
6668 const address_space
*aspace
= get_frame_address_space (frame
);
6670 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6673 /* To skip prologues, I use this predicate. Returns either PC itself
6674 if the code at PC does not look like a function prologue; otherwise
6675 returns an address that (if we're lucky) follows the prologue. If
6676 LENIENT, then we must skip everything which is involved in setting
6677 up the frame (it's OK to skip more, just so long as we don't skip
6678 anything which might clobber the registers which are being saved.
6679 We must skip more in the case where part of the prologue is in the
6680 delay slot of a non-prologue instruction). */
6683 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6686 CORE_ADDR func_addr
;
6688 /* See if we can determine the end of the prologue via the symbol table.
6689 If so, then return either PC, or the PC after the prologue, whichever
6691 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6693 CORE_ADDR post_prologue_pc
6694 = skip_prologue_using_sal (gdbarch
, func_addr
);
6695 if (post_prologue_pc
!= 0)
6696 return std::max (pc
, post_prologue_pc
);
6699 /* Can't determine prologue from the symbol table, need to examine
6702 /* Find an upper limit on the function prologue using the debug
6703 information. If the debug information could not be used to provide
6704 that bound, then use an arbitrary large number as the upper bound. */
6705 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6707 limit_pc
= pc
+ 100; /* Magic. */
6709 if (mips_pc_is_mips16 (gdbarch
, pc
))
6710 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6711 else if (mips_pc_is_micromips (gdbarch
, pc
))
6712 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6714 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6717 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6718 This is a helper function for mips_stack_frame_destroyed_p. */
6721 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6723 CORE_ADDR func_addr
= 0, func_end
= 0;
6725 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6727 /* The MIPS epilogue is max. 12 bytes long. */
6728 CORE_ADDR addr
= func_end
- 12;
6730 if (addr
< func_addr
+ 4)
6731 addr
= func_addr
+ 4;
6735 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6737 unsigned long high_word
;
6740 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6741 high_word
= (inst
>> 16) & 0xffff;
6743 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6744 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6745 && inst
!= 0x03e00008 /* jr $ra */
6746 && inst
!= 0x00000000) /* nop */
6756 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6757 This is a helper function for mips_stack_frame_destroyed_p. */
6760 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6762 CORE_ADDR func_addr
= 0;
6763 CORE_ADDR func_end
= 0;
6771 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6774 /* The microMIPS epilogue is max. 12 bytes long. */
6775 addr
= func_end
- 12;
6777 if (addr
< func_addr
+ 2)
6778 addr
= func_addr
+ 2;
6782 for (; pc
< func_end
; pc
+= loc
)
6785 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6786 loc
+= MIPS_INSN16_SIZE
;
6787 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6789 /* 32-bit instructions. */
6790 case 2 * MIPS_INSN16_SIZE
:
6792 insn
|= mips_fetch_instruction (gdbarch
,
6793 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6794 loc
+= MIPS_INSN16_SIZE
;
6795 switch (micromips_op (insn
>> 16))
6797 case 0xc: /* ADDIU: bits 001100 */
6798 case 0x17: /* DADDIU: bits 010111 */
6799 sreg
= b0s5_reg (insn
>> 16);
6800 dreg
= b5s5_reg (insn
>> 16);
6801 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6802 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6803 /* (D)ADDIU $sp, imm */
6813 /* 16-bit instructions. */
6814 case MIPS_INSN16_SIZE
:
6815 switch (micromips_op (insn
))
6817 case 0x3: /* MOVE: bits 000011 */
6818 sreg
= b0s5_reg (insn
);
6819 dreg
= b5s5_reg (insn
);
6820 if (sreg
== 0 && dreg
== 0)
6821 /* MOVE $zero, $zero aka NOP */
6825 case 0x11: /* POOL16C: bits 010001 */
6826 if (b5s5_op (insn
) == 0x18
6827 /* JRADDIUSP: bits 010011 11000 */
6828 || (b5s5_op (insn
) == 0xd
6829 /* JRC: bits 010011 01101 */
6830 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6835 case 0x13: /* POOL16D: bits 010011 */
6836 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6837 if ((insn
& 0x1) == 0x1
6838 /* ADDIUSP: bits 010011 1 */
6852 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6853 This is a helper function for mips_stack_frame_destroyed_p. */
6856 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6858 CORE_ADDR func_addr
= 0, func_end
= 0;
6860 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6862 /* The MIPS epilogue is max. 12 bytes long. */
6863 CORE_ADDR addr
= func_end
- 12;
6865 if (addr
< func_addr
+ 4)
6866 addr
= func_addr
+ 4;
6870 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6872 unsigned short inst
;
6874 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6876 if ((inst
& 0xf800) == 0xf000) /* extend */
6879 if (inst
!= 0x6300 /* addiu $sp,offset */
6880 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6881 && inst
!= 0xe820 /* jr $ra */
6882 && inst
!= 0xe8a0 /* jrc $ra */
6883 && inst
!= 0x6500) /* nop */
6893 /* Implement the stack_frame_destroyed_p gdbarch method.
6895 The epilogue is defined here as the area at the end of a function,
6896 after an instruction which destroys the function's stack frame. */
6899 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6901 if (mips_pc_is_mips16 (gdbarch
, pc
))
6902 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6903 else if (mips_pc_is_micromips (gdbarch
, pc
))
6904 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6906 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6909 /* Commands to show/set the MIPS FPU type. */
6912 show_mipsfpu_command (const char *args
, int from_tty
)
6916 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6919 ("The MIPS floating-point coprocessor is unknown "
6920 "because the current architecture is not MIPS.\n");
6924 switch (mips_get_fpu_type (target_gdbarch ()))
6926 case MIPS_FPU_SINGLE
:
6927 fpu
= "single-precision";
6929 case MIPS_FPU_DOUBLE
:
6930 fpu
= "double-precision";
6933 fpu
= "absent (none)";
6936 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6938 if (mips_fpu_type_auto
)
6939 printf_unfiltered ("The MIPS floating-point coprocessor "
6940 "is set automatically (currently %s)\n",
6944 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6949 set_mipsfpu_single_command (const char *args
, int from_tty
)
6951 struct gdbarch_info info
;
6952 mips_fpu_type
= MIPS_FPU_SINGLE
;
6953 mips_fpu_type_auto
= 0;
6954 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6955 instead of relying on globals. Doing that would let generic code
6956 handle the search for this specific architecture. */
6957 if (!gdbarch_update_p (info
))
6958 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6962 set_mipsfpu_double_command (const char *args
, int from_tty
)
6964 struct gdbarch_info info
;
6965 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6966 mips_fpu_type_auto
= 0;
6967 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6968 instead of relying on globals. Doing that would let generic code
6969 handle the search for this specific architecture. */
6970 if (!gdbarch_update_p (info
))
6971 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6975 set_mipsfpu_none_command (const char *args
, int from_tty
)
6977 struct gdbarch_info info
;
6978 mips_fpu_type
= MIPS_FPU_NONE
;
6979 mips_fpu_type_auto
= 0;
6980 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6981 instead of relying on globals. Doing that would let generic code
6982 handle the search for this specific architecture. */
6983 if (!gdbarch_update_p (info
))
6984 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6988 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6990 mips_fpu_type_auto
= 1;
6993 /* Just like reinit_frame_cache, but with the right arguments to be
6994 callable as an sfunc. */
6997 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6998 struct cmd_list_element
*c
)
7000 reinit_frame_cache ();
7004 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
7006 gdb_disassembler
*di
7007 = static_cast<gdb_disassembler
*>(info
->application_data
);
7008 struct gdbarch
*gdbarch
= di
->arch ();
7010 /* FIXME: cagney/2003-06-26: Is this even necessary? The
7011 disassembler needs to be able to locally determine the ISA, and
7012 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
7014 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
7015 info
->mach
= bfd_mach_mips16
;
7016 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7017 info
->mach
= bfd_mach_mips_micromips
;
7019 /* Round down the instruction address to the appropriate boundary. */
7020 memaddr
&= (info
->mach
== bfd_mach_mips16
7021 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7023 return default_print_insn (memaddr
, info
);
7026 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7029 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7031 CORE_ADDR pc
= *pcptr
;
7033 if (mips_pc_is_mips16 (gdbarch
, pc
))
7035 *pcptr
= unmake_compact_addr (pc
);
7036 return MIPS_BP_KIND_MIPS16
;
7038 else if (mips_pc_is_micromips (gdbarch
, pc
))
7043 *pcptr
= unmake_compact_addr (pc
);
7044 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7045 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7046 return MIPS_BP_KIND_MICROMIPS16
;
7048 return MIPS_BP_KIND_MICROMIPS32
;
7051 return MIPS_BP_KIND_MIPS32
;
7054 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7056 static const gdb_byte
*
7057 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7059 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7063 case MIPS_BP_KIND_MIPS16
:
7065 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7066 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7069 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7070 return mips16_big_breakpoint
;
7072 return mips16_little_breakpoint
;
7074 case MIPS_BP_KIND_MICROMIPS16
:
7076 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7077 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7081 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7082 return micromips16_big_breakpoint
;
7084 return micromips16_little_breakpoint
;
7086 case MIPS_BP_KIND_MICROMIPS32
:
7088 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7089 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7092 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7093 return micromips32_big_breakpoint
;
7095 return micromips32_little_breakpoint
;
7097 case MIPS_BP_KIND_MIPS32
:
7099 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7100 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7103 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7104 return big_breakpoint
;
7106 return little_breakpoint
;
7109 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7113 /* Return non-zero if the standard MIPS instruction INST has a branch
7114 delay slot (i.e. it is a jump or branch instruction). This function
7115 is based on mips32_next_pc. */
7118 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7124 op
= itype_op (inst
);
7125 if ((inst
& 0xe0000000) != 0)
7127 rs
= itype_rs (inst
);
7128 rt
= itype_rt (inst
);
7129 return (is_octeon_bbit_op (op
, gdbarch
)
7130 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7131 || op
== 29 /* JALX: bits 011101 */
7134 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7135 || (rs
== 9 && (rt
& 0x2) == 0)
7136 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7137 || (rs
== 10 && (rt
& 0x2) == 0))));
7138 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7141 switch (op
& 0x07) /* extract bits 28,27,26 */
7143 case 0: /* SPECIAL */
7144 op
= rtype_funct (inst
);
7145 return (op
== 8 /* JR */
7146 || op
== 9); /* JALR */
7147 break; /* end SPECIAL */
7148 case 1: /* REGIMM */
7149 rs
= itype_rs (inst
);
7150 rt
= itype_rt (inst
); /* branch condition */
7151 return ((rt
& 0xc) == 0
7152 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7153 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7154 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7155 /* BPOSGE32, BPOSGE64: bits 1110x */
7156 break; /* end REGIMM */
7157 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7163 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7164 delay slot (i.e. it is a jump or branch instruction). */
7167 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7172 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7176 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7179 /* Return non-zero if the microMIPS instruction INSN, comprising the
7180 16-bit major opcode word in the high 16 bits and any second word
7181 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7182 jump or branch instruction). The instruction must be 32-bit if
7183 MUSTBE32 is set or can be any instruction otherwise. */
7186 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7188 ULONGEST major
= insn
>> 16;
7190 switch (micromips_op (major
))
7192 /* 16-bit instructions. */
7193 case 0x33: /* B16: bits 110011 */
7194 case 0x2b: /* BNEZ16: bits 101011 */
7195 case 0x23: /* BEQZ16: bits 100011 */
7197 case 0x11: /* POOL16C: bits 010001 */
7199 && ((b5s5_op (major
) == 0xc
7200 /* JR16: bits 010001 01100 */
7201 || (b5s5_op (major
) & 0x1e) == 0xe)));
7202 /* JALR16, JALRS16: bits 010001 0111x */
7203 /* 32-bit instructions. */
7204 case 0x3d: /* JAL: bits 111101 */
7205 case 0x3c: /* JALX: bits 111100 */
7206 case 0x35: /* J: bits 110101 */
7207 case 0x2d: /* BNE: bits 101101 */
7208 case 0x25: /* BEQ: bits 100101 */
7209 case 0x1d: /* JALS: bits 011101 */
7211 case 0x10: /* POOL32I: bits 010000 */
7212 return ((b5s5_op (major
) & 0x1c) == 0x0
7213 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7214 || (b5s5_op (major
) & 0x1d) == 0x4
7215 /* BLEZ, BGTZ: bits 010000 001x0 */
7216 || (b5s5_op (major
) & 0x1d) == 0x11
7217 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7218 || ((b5s5_op (major
) & 0x1e) == 0x14
7219 && (major
& 0x3) == 0x0)
7220 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7221 || (b5s5_op (major
) & 0x1e) == 0x1a
7222 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7223 || ((b5s5_op (major
) & 0x1e) == 0x1c
7224 && (major
& 0x3) == 0x0)
7225 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7226 || ((b5s5_op (major
) & 0x1c) == 0x1c
7227 && (major
& 0x3) == 0x1));
7228 /* BC1ANY*: bits 010000 111xx xxx01 */
7229 case 0x0: /* POOL32A: bits 000000 */
7230 return (b0s6_op (insn
) == 0x3c
7231 /* POOL32Axf: bits 000000 ... 111100 */
7232 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7233 /* JALR, JALR.HB: 000000 000x111100 111100 */
7234 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7240 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7241 slot (i.e. it is a non-compact jump instruction). The instruction
7242 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7245 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7246 CORE_ADDR addr
, int mustbe32
)
7252 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7255 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7257 if (size
== 2 * MIPS_INSN16_SIZE
)
7259 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7264 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7267 /* Return non-zero if the MIPS16 instruction INST, which must be
7268 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7269 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7270 instruction). This function is based on mips16_next_pc. */
7273 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7275 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7277 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7280 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7281 slot (i.e. it is a non-compact jump instruction). The instruction
7282 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7285 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7286 CORE_ADDR addr
, int mustbe32
)
7288 unsigned short insn
;
7291 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7295 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7298 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7299 This assumes KSSEG exists. */
7302 mips_segment_boundary (CORE_ADDR bpaddr
)
7304 CORE_ADDR mask
= CORE_ADDR_MAX
;
7307 if (sizeof (CORE_ADDR
) == 8)
7308 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7309 a compiler warning produced where CORE_ADDR is a 32-bit type even
7310 though in that case this is dead code). */
7311 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7314 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7315 segsize
= 29; /* 32-bit compatibility segment */
7317 segsize
= 62; /* xkseg */
7319 case 2: /* xkphys */
7322 default: /* xksseg (1), xkuseg/kuseg (0) */
7326 else if (bpaddr
& 0x80000000) /* kernel segment */
7329 segsize
= 31; /* user segment */
7331 return bpaddr
& mask
;
7334 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7335 it backwards if necessary. Return the address of the new location. */
7338 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7340 CORE_ADDR prev_addr
;
7342 CORE_ADDR func_addr
;
7344 /* If a breakpoint is set on the instruction in a branch delay slot,
7345 GDB gets confused. When the breakpoint is hit, the PC isn't on
7346 the instruction in the branch delay slot, the PC will point to
7347 the branch instruction. Since the PC doesn't match any known
7348 breakpoints, GDB reports a trap exception.
7350 There are two possible fixes for this problem.
7352 1) When the breakpoint gets hit, see if the BD bit is set in the
7353 Cause register (which indicates the last exception occurred in a
7354 branch delay slot). If the BD bit is set, fix the PC to point to
7355 the instruction in the branch delay slot.
7357 2) When the user sets the breakpoint, don't allow him to set the
7358 breakpoint on the instruction in the branch delay slot. Instead
7359 move the breakpoint to the branch instruction (which will have
7362 The problem with the first solution is that if the user then
7363 single-steps the processor, the branch instruction will get
7364 skipped (since GDB thinks the PC is on the instruction in the
7367 So, we'll use the second solution. To do this we need to know if
7368 the instruction we're trying to set the breakpoint on is in the
7369 branch delay slot. */
7371 boundary
= mips_segment_boundary (bpaddr
);
7373 /* Make sure we don't scan back before the beginning of the current
7374 function, since we may fetch constant data or insns that look like
7375 a jump. Of course we might do that anyway if the compiler has
7376 moved constants inline. :-( */
7377 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7378 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7379 boundary
= func_addr
;
7381 if (mips_pc_is_mips (bpaddr
))
7383 if (bpaddr
== boundary
)
7386 /* If the previous instruction has a branch delay slot, we have
7387 to move the breakpoint to the branch instruction. */
7388 prev_addr
= bpaddr
- 4;
7389 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7394 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7395 CORE_ADDR addr
, jmpaddr
;
7398 boundary
= unmake_compact_addr (boundary
);
7400 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7401 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7402 so try for that first, then try the 2 byte JALR/JR.
7403 The microMIPS ASE has a whole range of jumps and branches
7404 with delay slots, some of which take 4 bytes and some take
7405 2 bytes, so the idea is the same.
7406 FIXME: We have to assume that bpaddr is not the second half
7407 of an extended instruction. */
7408 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7409 ? micromips_insn_at_pc_has_delay_slot
7410 : mips16_insn_at_pc_has_delay_slot
);
7414 for (i
= 1; i
< 4; i
++)
7416 if (unmake_compact_addr (addr
) == boundary
)
7418 addr
-= MIPS_INSN16_SIZE
;
7419 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7420 /* Looks like a JR/JALR at [target-1], but it could be
7421 the second word of a previous JAL/JALX, so record it
7422 and check back one more. */
7424 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7427 /* Looks like a JAL/JALX at [target-2], but it could also
7428 be the second word of a previous JAL/JALX, record it,
7429 and check back one more. */
7432 /* Looks like a JAL/JALX at [target-3], so any previously
7433 recorded JAL/JALX or JR/JALR must be wrong, because:
7436 -2: JAL-ext (can't be JAL/JALX)
7437 -1: bdslot (can't be JR/JALR)
7440 Of course it could be another JAL-ext which looks
7441 like a JAL, but in that case we'd have broken out
7442 of this loop at [target-2]:
7446 -2: bdslot (can't be jmp)
7453 /* Not a jump instruction: if we're at [target-1] this
7454 could be the second word of a JAL/JALX, so continue;
7455 otherwise we're done. */
7468 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7469 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7472 mips_is_stub_suffix (const char *suffix
, int zero
)
7477 return zero
&& suffix
[1] == '\0';
7479 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7484 return suffix
[1] == '\0';
7490 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7491 call stubs, one of sf, df, sc, or dc. */
7494 mips_is_stub_mode (const char *mode
)
7496 return ((mode
[0] == 's' || mode
[0] == 'd')
7497 && (mode
[1] == 'f' || mode
[1] == 'c'));
7500 /* Code at PC is a compiler-generated stub. Such a stub for a function
7501 bar might have a name like __fn_stub_bar, and might look like this:
7508 followed by (or interspersed with):
7515 addiu $25, $25, %lo(bar)
7518 ($1 may be used in old code; for robustness we accept any register)
7521 lui $28, %hi(_gp_disp)
7522 addiu $28, $28, %lo(_gp_disp)
7525 addiu $25, $25, %lo(bar)
7528 In the case of a __call_stub_bar stub, the sequence to set up
7529 arguments might look like this:
7536 followed by (or interspersed with) one of the jump sequences above.
7538 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7539 of J or JR, respectively, followed by:
7545 We are at the beginning of the stub here, and scan down and extract
7546 the target address from the jump immediate instruction or, if a jump
7547 register instruction is used, from the register referred. Return
7548 the value of PC calculated or 0 if inconclusive.
7550 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7553 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7555 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7556 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7557 int addrreg
= MIPS_ZERO_REGNUM
;
7558 CORE_ADDR start_pc
= pc
;
7559 CORE_ADDR target_pc
= 0;
7566 status
== 0 && target_pc
== 0 && i
< 20;
7567 i
++, pc
+= MIPS_INSN32_SIZE
)
7569 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7575 switch (itype_op (inst
))
7577 case 0: /* SPECIAL */
7578 switch (rtype_funct (inst
))
7582 rs
= rtype_rs (inst
);
7583 if (rs
== MIPS_GP_REGNUM
)
7584 target_pc
= gp
; /* Hmm... */
7585 else if (rs
== addrreg
)
7589 case 0x21: /* ADDU */
7590 rt
= rtype_rt (inst
);
7591 rs
= rtype_rs (inst
);
7592 rd
= rtype_rd (inst
);
7593 if (rd
== MIPS_GP_REGNUM
7594 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7595 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7603 target_pc
= jtype_target (inst
) << 2;
7604 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7608 rt
= itype_rt (inst
);
7609 rs
= itype_rs (inst
);
7612 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7613 if (rt
== MIPS_GP_REGNUM
)
7615 else if (rt
== addrreg
)
7621 rt
= itype_rt (inst
);
7622 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7623 if (rt
== MIPS_GP_REGNUM
)
7625 else if (rt
!= MIPS_ZERO_REGNUM
)
7633 rt
= itype_rt (inst
);
7634 rs
= itype_rs (inst
);
7635 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7636 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7640 memset (buf
, 0, sizeof (buf
));
7641 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7643 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7652 /* If PC is in a MIPS16 call or return stub, return the address of the
7653 target PC, which is either the callee or the caller. There are several
7654 cases which must be handled:
7656 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7657 and the target PC is in $31 ($ra).
7658 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7659 and the target PC is in $2.
7660 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7661 i.e. before the JALR instruction, this is effectively a call stub
7662 and the target PC is in $2. Otherwise this is effectively
7663 a return stub and the target PC is in $18.
7664 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7665 JAL or JALR instruction, this is effectively a call stub and the
7666 target PC is buried in the instruction stream. Otherwise this
7667 is effectively a return stub and the target PC is in $18.
7668 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7669 stub and the target PC is buried in the instruction stream.
7671 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7672 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7676 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7678 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7679 CORE_ADDR start_addr
;
7683 /* Find the starting address and name of the function containing the PC. */
7684 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7687 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7688 and the target PC is in $31 ($ra). */
7689 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7690 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7691 && mips_is_stub_mode (name
+ prefixlen
)
7692 && name
[prefixlen
+ 2] == '\0')
7693 return get_frame_register_signed
7694 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7696 /* If the PC is in __mips16_call_stub_*, this is one of the call
7697 call/return stubs. */
7698 prefixlen
= strlen (mips_str_mips16_call_stub
);
7699 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7701 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7702 and the target PC is in $2. */
7703 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7704 return get_frame_register_signed
7705 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7707 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7708 i.e. before the JALR instruction, this is effectively a call stub
7709 and the target PC is in $2. Otherwise this is effectively
7710 a return stub and the target PC is in $18. */
7711 else if (mips_is_stub_mode (name
+ prefixlen
)
7712 && name
[prefixlen
+ 2] == '_'
7713 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7715 if (pc
== start_addr
)
7716 /* This is the 'call' part of a call stub. The return
7717 address is in $2. */
7718 return get_frame_register_signed
7719 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7721 /* This is the 'return' part of a call stub. The return
7722 address is in $18. */
7723 return get_frame_register_signed
7724 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7727 return 0; /* Not a stub. */
7730 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7731 compiler-generated call or call/return stubs. */
7732 if (startswith (name
, mips_str_fn_stub
)
7733 || startswith (name
, mips_str_call_stub
))
7735 if (pc
== start_addr
)
7736 /* This is the 'call' part of a call stub. Call this helper
7737 to scan through this code for interesting instructions
7738 and determine the final PC. */
7739 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7741 /* This is the 'return' part of a call stub. The return address
7743 return get_frame_register_signed
7744 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7747 return 0; /* Not a stub. */
7750 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7751 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7754 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7756 CORE_ADDR start_addr
;
7759 /* Find the starting address of the function containing the PC. */
7760 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7763 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7764 the start, i.e. after the JALR instruction, this is effectively
7766 prefixlen
= strlen (mips_str_mips16_call_stub
);
7767 if (pc
!= start_addr
7768 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7769 && mips_is_stub_mode (name
+ prefixlen
)
7770 && name
[prefixlen
+ 2] == '_'
7771 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7774 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7775 the JAL or JALR instruction, this is effectively a return stub. */
7776 prefixlen
= strlen (mips_str_call_fp_stub
);
7777 if (pc
!= start_addr
7778 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7781 /* Consume the .pic. prefix of any PIC stub, this function must return
7782 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7783 or the call stub path will trigger in handle_inferior_event causing
7785 prefixlen
= strlen (mips_str_pic
);
7786 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7789 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7790 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7791 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7792 && mips_is_stub_mode (name
+ prefixlen
)
7793 && name
[prefixlen
+ 2] == '\0')
7796 return 0; /* Not a stub. */
7799 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7800 PC of the stub target. The stub just loads $t9 and jumps to it,
7801 so that $t9 has the correct value at function entry. */
7804 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7806 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7807 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7808 struct bound_minimal_symbol msym
;
7810 gdb_byte stub_code
[16];
7811 int32_t stub_words
[4];
7813 /* The stub for foo is named ".pic.foo", and is either two
7814 instructions inserted before foo or a three instruction sequence
7815 which jumps to foo. */
7816 msym
= lookup_minimal_symbol_by_pc (pc
);
7817 if (msym
.minsym
== NULL
7818 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7819 || msym
.minsym
->linkage_name () == NULL
7820 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7823 /* A two-instruction header. */
7824 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7827 /* A three-instruction (plus delay slot) trampoline. */
7828 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7830 if (target_read_memory (pc
, stub_code
, 16) != 0)
7832 for (i
= 0; i
< 4; i
++)
7833 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7836 /* A stub contains these instructions:
7839 addiu t9, t9, %lo(target)
7842 This works even for N64, since stubs are only generated with
7844 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7845 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7846 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7847 && stub_words
[3] == 0x00000000)
7848 return ((((stub_words
[0] & 0x0000ffff) << 16)
7849 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7852 /* Not a recognized stub. */
7857 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7859 CORE_ADDR requested_pc
= pc
;
7860 CORE_ADDR target_pc
;
7867 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7871 new_pc
= find_solib_trampoline_target (frame
, pc
);
7875 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7879 while (pc
!= target_pc
);
7881 return pc
!= requested_pc
? pc
: 0;
7884 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7885 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7888 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7891 if (num
>= 0 && num
< 32)
7893 else if (num
>= 38 && num
< 70)
7894 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7896 regnum
= mips_regnum (gdbarch
)->hi
;
7898 regnum
= mips_regnum (gdbarch
)->lo
;
7899 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7900 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7903 return gdbarch_num_regs (gdbarch
) + regnum
;
7907 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7908 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7911 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7914 if (num
>= 0 && num
< 32)
7916 else if (num
>= 32 && num
< 64)
7917 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7919 regnum
= mips_regnum (gdbarch
)->hi
;
7921 regnum
= mips_regnum (gdbarch
)->lo
;
7922 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7923 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7926 return gdbarch_num_regs (gdbarch
) + regnum
;
7930 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7932 /* Only makes sense to supply raw registers. */
7933 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7934 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7935 decide if it is valid. Should instead define a standard sim/gdb
7936 register numbering scheme. */
7937 if (gdbarch_register_name (gdbarch
,
7938 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7939 && gdbarch_register_name (gdbarch
,
7940 gdbarch_num_regs (gdbarch
)
7941 + regnum
)[0] != '\0')
7944 return LEGACY_SIM_REGNO_IGNORE
;
7948 /* Convert an integer into an address. Extracting the value signed
7949 guarantees a correctly sign extended address. */
7952 mips_integer_to_address (struct gdbarch
*gdbarch
,
7953 struct type
*type
, const gdb_byte
*buf
)
7955 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7956 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7959 /* Dummy virtual frame pointer method. This is no more or less accurate
7960 than most other architectures; we just need to be explicit about it,
7961 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7962 an assertion failure. */
7965 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7966 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7968 *reg
= MIPS_SP_REGNUM
;
7973 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7975 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7976 const char *name
= bfd_section_name (sect
);
7978 if (*abip
!= MIPS_ABI_UNKNOWN
)
7981 if (!startswith (name
, ".mdebug."))
7984 if (strcmp (name
, ".mdebug.abi32") == 0)
7985 *abip
= MIPS_ABI_O32
;
7986 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7987 *abip
= MIPS_ABI_N32
;
7988 else if (strcmp (name
, ".mdebug.abi64") == 0)
7989 *abip
= MIPS_ABI_N64
;
7990 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7991 *abip
= MIPS_ABI_O64
;
7992 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7993 *abip
= MIPS_ABI_EABI32
;
7994 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7995 *abip
= MIPS_ABI_EABI64
;
7997 warning (_("unsupported ABI %s."), name
+ 8);
8001 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8003 int *lbp
= (int *) obj
;
8004 const char *name
= bfd_section_name (sect
);
8006 if (startswith (name
, ".gcc_compiled_long32"))
8008 else if (startswith (name
, ".gcc_compiled_long64"))
8010 else if (startswith (name
, ".gcc_compiled_long"))
8011 warning (_("unrecognized .gcc_compiled_longXX"));
8014 static enum mips_abi
8015 global_mips_abi (void)
8019 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8020 if (mips_abi_strings
[i
] == mips_abi_string
)
8021 return (enum mips_abi
) i
;
8023 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8026 /* Return the default compressed instruction set, either of MIPS16
8027 or microMIPS, selected when none could have been determined from
8028 the ELF header of the binary being executed (or no binary has been
8031 static enum mips_isa
8032 global_mips_compression (void)
8036 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8037 if (mips_compression_strings
[i
] == mips_compression_string
)
8038 return (enum mips_isa
) i
;
8040 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8044 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8046 /* If the size matches the set of 32-bit or 64-bit integer registers,
8047 assume that's what we've got. */
8048 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8049 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8051 /* If the size matches the full set of registers GDB traditionally
8052 knows about, including floating point, for either 32-bit or
8053 64-bit, assume that's what we've got. */
8054 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8055 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8057 /* Otherwise we don't have a useful guess. */
8060 static struct value
*
8061 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8063 const int *reg_p
= (const int *) baton
;
8064 return value_of_register (*reg_p
, frame
);
8067 static struct gdbarch
*
8068 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8070 struct gdbarch
*gdbarch
;
8072 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8074 enum mips_fpu_type fpu_type
;
8075 tdesc_arch_data_up tdesc_data
;
8076 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8077 const char * const *reg_names
;
8078 struct mips_regnum mips_regnum
, *regnum
;
8079 enum mips_isa mips_isa
;
8083 /* First of all, extract the elf_flags, if available. */
8084 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8085 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8086 else if (arches
!= NULL
)
8088 mips_gdbarch_tdep
*tdep
8089 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8090 elf_flags
= tdep
->elf_flags
;
8095 fprintf_unfiltered (gdb_stdlog
,
8096 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8098 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8099 switch ((elf_flags
& EF_MIPS_ABI
))
8101 case E_MIPS_ABI_O32
:
8102 found_abi
= MIPS_ABI_O32
;
8104 case E_MIPS_ABI_O64
:
8105 found_abi
= MIPS_ABI_O64
;
8107 case E_MIPS_ABI_EABI32
:
8108 found_abi
= MIPS_ABI_EABI32
;
8110 case E_MIPS_ABI_EABI64
:
8111 found_abi
= MIPS_ABI_EABI64
;
8114 if ((elf_flags
& EF_MIPS_ABI2
))
8115 found_abi
= MIPS_ABI_N32
;
8117 found_abi
= MIPS_ABI_UNKNOWN
;
8121 /* GCC creates a pseudo-section whose name describes the ABI. */
8122 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8123 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8125 /* If we have no useful BFD information, use the ABI from the last
8126 MIPS architecture (if there is one). */
8127 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8129 mips_gdbarch_tdep
*tdep
8130 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8131 found_abi
= tdep
->found_abi
;
8134 /* Try the architecture for any hint of the correct ABI. */
8135 if (found_abi
== MIPS_ABI_UNKNOWN
8136 && info
.bfd_arch_info
!= NULL
8137 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8139 switch (info
.bfd_arch_info
->mach
)
8141 case bfd_mach_mips3900
:
8142 found_abi
= MIPS_ABI_EABI32
;
8144 case bfd_mach_mips4100
:
8145 case bfd_mach_mips5000
:
8146 found_abi
= MIPS_ABI_EABI64
;
8148 case bfd_mach_mips8000
:
8149 case bfd_mach_mips10000
:
8150 /* On Irix, ELF64 executables use the N64 ABI. The
8151 pseudo-sections which describe the ABI aren't present
8152 on IRIX. (Even for executables created by gcc.) */
8153 if (info
.abfd
!= NULL
8154 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8155 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8156 found_abi
= MIPS_ABI_N64
;
8158 found_abi
= MIPS_ABI_N32
;
8163 /* Default 64-bit objects to N64 instead of O32. */
8164 if (found_abi
== MIPS_ABI_UNKNOWN
8165 && info
.abfd
!= NULL
8166 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8167 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8168 found_abi
= MIPS_ABI_N64
;
8171 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8174 /* What has the user specified from the command line? */
8175 wanted_abi
= global_mips_abi ();
8177 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8180 /* Now that we have found what the ABI for this binary would be,
8181 check whether the user is overriding it. */
8182 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8183 mips_abi
= wanted_abi
;
8184 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8185 mips_abi
= found_abi
;
8187 mips_abi
= MIPS_ABI_O32
;
8189 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8192 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8193 if (mips_abi
!= MIPS_ABI_EABI32
8194 && mips_abi
!= MIPS_ABI_O32
8195 && info
.bfd_arch_info
!= NULL
8196 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8197 && info
.bfd_arch_info
->bits_per_word
< 64)
8198 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8200 /* Determine the default compressed ISA. */
8201 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8202 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8203 mips_isa
= ISA_MICROMIPS
;
8204 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8205 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8206 mips_isa
= ISA_MIPS16
;
8208 mips_isa
= global_mips_compression ();
8209 mips_compression_string
= mips_compression_strings
[mips_isa
];
8211 /* Also used when doing an architecture lookup. */
8213 fprintf_unfiltered (gdb_stdlog
,
8214 "mips_gdbarch_init: "
8215 "mips64_transfers_32bit_regs_p = %d\n",
8216 mips64_transfers_32bit_regs_p
);
8218 /* Determine the MIPS FPU type. */
8221 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8222 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8223 Tag_GNU_MIPS_ABI_FP
);
8224 #endif /* HAVE_ELF */
8226 if (!mips_fpu_type_auto
)
8227 fpu_type
= mips_fpu_type
;
8228 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8230 switch (elf_fpu_type
)
8232 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8233 fpu_type
= MIPS_FPU_DOUBLE
;
8235 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8236 fpu_type
= MIPS_FPU_SINGLE
;
8238 case Val_GNU_MIPS_ABI_FP_SOFT
:
8240 /* Soft float or unknown. */
8241 fpu_type
= MIPS_FPU_NONE
;
8245 else if (info
.bfd_arch_info
!= NULL
8246 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8247 switch (info
.bfd_arch_info
->mach
)
8249 case bfd_mach_mips3900
:
8250 case bfd_mach_mips4100
:
8251 case bfd_mach_mips4111
:
8252 case bfd_mach_mips4120
:
8253 fpu_type
= MIPS_FPU_NONE
;
8255 case bfd_mach_mips4650
:
8256 fpu_type
= MIPS_FPU_SINGLE
;
8259 fpu_type
= MIPS_FPU_DOUBLE
;
8262 else if (arches
!= NULL
)
8263 fpu_type
= mips_get_fpu_type (arches
->gdbarch
);
8265 fpu_type
= MIPS_FPU_DOUBLE
;
8267 fprintf_unfiltered (gdb_stdlog
,
8268 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8270 /* Check for blatant incompatibilities. */
8272 /* If we have only 32-bit registers, then we can't debug a 64-bit
8274 if (info
.target_desc
8275 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8276 && mips_abi
!= MIPS_ABI_EABI32
8277 && mips_abi
!= MIPS_ABI_O32
)
8280 /* Fill in the OS dependent register numbers and names. */
8281 if (info
.osabi
== GDB_OSABI_LINUX
)
8283 mips_regnum
.fp0
= 38;
8284 mips_regnum
.pc
= 37;
8285 mips_regnum
.cause
= 36;
8286 mips_regnum
.badvaddr
= 35;
8287 mips_regnum
.hi
= 34;
8288 mips_regnum
.lo
= 33;
8289 mips_regnum
.fp_control_status
= 70;
8290 mips_regnum
.fp_implementation_revision
= 71;
8291 mips_regnum
.dspacc
= -1;
8292 mips_regnum
.dspctl
= -1;
8296 reg_names
= mips_linux_reg_names
;
8300 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8301 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8302 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8303 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8304 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8305 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8306 mips_regnum
.fp_control_status
= 70;
8307 mips_regnum
.fp_implementation_revision
= 71;
8308 mips_regnum
.dspacc
= dspacc
= -1;
8309 mips_regnum
.dspctl
= dspctl
= -1;
8310 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8311 if (info
.bfd_arch_info
!= NULL
8312 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8313 reg_names
= mips_tx39_reg_names
;
8315 reg_names
= mips_generic_reg_names
;
8318 /* Check any target description for validity. */
8319 if (tdesc_has_registers (info
.target_desc
))
8321 static const char *const mips_gprs
[] = {
8322 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8323 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8324 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8325 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8327 static const char *const mips_fprs
[] = {
8328 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8329 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8330 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8331 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8334 const struct tdesc_feature
*feature
;
8337 feature
= tdesc_find_feature (info
.target_desc
,
8338 "org.gnu.gdb.mips.cpu");
8339 if (feature
== NULL
)
8342 tdesc_data
= tdesc_data_alloc ();
8345 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8346 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8350 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8351 mips_regnum
.lo
, "lo");
8352 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8353 mips_regnum
.hi
, "hi");
8354 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8355 mips_regnum
.pc
, "pc");
8360 feature
= tdesc_find_feature (info
.target_desc
,
8361 "org.gnu.gdb.mips.cp0");
8362 if (feature
== NULL
)
8366 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8367 mips_regnum
.badvaddr
, "badvaddr");
8368 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8369 MIPS_PS_REGNUM
, "status");
8370 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8371 mips_regnum
.cause
, "cause");
8376 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8377 backend is not prepared for that, though. */
8378 feature
= tdesc_find_feature (info
.target_desc
,
8379 "org.gnu.gdb.mips.fpu");
8380 if (feature
== NULL
)
8384 for (i
= 0; i
< 32; i
++)
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8388 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8389 mips_regnum
.fp_control_status
,
8392 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8393 mips_regnum
.fp_implementation_revision
,
8399 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8403 feature
= tdesc_find_feature (info
.target_desc
,
8404 "org.gnu.gdb.mips.dsp");
8405 /* The DSP registers are optional; it's OK if they are absent. */
8406 if (feature
!= NULL
)
8410 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8411 dspacc
+ i
++, "hi1");
8412 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8413 dspacc
+ i
++, "lo1");
8414 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8415 dspacc
+ i
++, "hi2");
8416 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8417 dspacc
+ i
++, "lo2");
8418 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8419 dspacc
+ i
++, "hi3");
8420 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8421 dspacc
+ i
++, "lo3");
8423 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8429 mips_regnum
.dspacc
= dspacc
;
8430 mips_regnum
.dspctl
= dspctl
;
8432 num_regs
= mips_regnum
.dspctl
+ 1;
8436 /* It would be nice to detect an attempt to use a 64-bit ABI
8437 when only 32-bit registers are provided. */
8441 /* Try to find a pre-existing architecture. */
8442 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8444 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8446 mips_gdbarch_tdep
*tdep
8447 = (mips_gdbarch_tdep
*) gdbarch_tdep (arches
->gdbarch
);
8449 /* MIPS needs to be pedantic about which ABI and the compressed
8450 ISA variation the object is using. */
8451 if (tdep
->elf_flags
!= elf_flags
)
8453 if (tdep
->mips_abi
!= mips_abi
)
8455 if (tdep
->mips_isa
!= mips_isa
)
8457 /* Need to be pedantic about which register virtual size is
8459 if (tdep
->mips64_transfers_32bit_regs_p
8460 != mips64_transfers_32bit_regs_p
)
8462 /* Be pedantic about which FPU is selected. */
8463 if (mips_get_fpu_type (arches
->gdbarch
) != fpu_type
)
8466 return arches
->gdbarch
;
8469 /* Need a new architecture. Fill in a target specific vector. */
8470 mips_gdbarch_tdep
*tdep
= new mips_gdbarch_tdep
;
8471 gdbarch
= gdbarch_alloc (&info
, tdep
);
8472 tdep
->elf_flags
= elf_flags
;
8473 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8474 tdep
->found_abi
= found_abi
;
8475 tdep
->mips_abi
= mips_abi
;
8476 tdep
->mips_isa
= mips_isa
;
8477 tdep
->mips_fpu_type
= fpu_type
;
8478 tdep
->register_size_valid_p
= 0;
8479 tdep
->register_size
= 0;
8481 if (info
.target_desc
)
8483 /* Some useful properties can be inferred from the target. */
8484 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8486 tdep
->register_size_valid_p
= 1;
8487 tdep
->register_size
= 4;
8489 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8491 tdep
->register_size_valid_p
= 1;
8492 tdep
->register_size
= 8;
8496 /* Initially set everything according to the default ABI/ISA. */
8497 set_gdbarch_short_bit (gdbarch
, 16);
8498 set_gdbarch_int_bit (gdbarch
, 32);
8499 set_gdbarch_float_bit (gdbarch
, 32);
8500 set_gdbarch_double_bit (gdbarch
, 64);
8501 set_gdbarch_long_double_bit (gdbarch
, 64);
8502 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8503 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8504 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8506 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8507 mips_ax_pseudo_register_collect
);
8508 set_gdbarch_ax_pseudo_register_push_stack
8509 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8511 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8512 mips_elf_make_msymbol_special
);
8513 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8514 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8515 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8517 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8518 *regnum
= mips_regnum
;
8519 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8520 set_gdbarch_num_regs (gdbarch
, num_regs
);
8521 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8522 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8523 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8524 tdep
->mips_processor_reg_names
= reg_names
;
8525 tdep
->regnum
= regnum
;
8530 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8531 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8532 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8533 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8534 tdep
->default_mask_address_p
= 0;
8535 set_gdbarch_long_bit (gdbarch
, 32);
8536 set_gdbarch_ptr_bit (gdbarch
, 32);
8537 set_gdbarch_long_long_bit (gdbarch
, 64);
8540 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8541 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8542 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8543 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8544 tdep
->default_mask_address_p
= 0;
8545 set_gdbarch_long_bit (gdbarch
, 32);
8546 set_gdbarch_ptr_bit (gdbarch
, 32);
8547 set_gdbarch_long_long_bit (gdbarch
, 64);
8549 case MIPS_ABI_EABI32
:
8550 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8551 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8552 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8553 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8554 tdep
->default_mask_address_p
= 0;
8555 set_gdbarch_long_bit (gdbarch
, 32);
8556 set_gdbarch_ptr_bit (gdbarch
, 32);
8557 set_gdbarch_long_long_bit (gdbarch
, 64);
8559 case MIPS_ABI_EABI64
:
8560 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8561 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8562 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8563 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8564 tdep
->default_mask_address_p
= 0;
8565 set_gdbarch_long_bit (gdbarch
, 64);
8566 set_gdbarch_ptr_bit (gdbarch
, 64);
8567 set_gdbarch_long_long_bit (gdbarch
, 64);
8570 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8571 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8572 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8573 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8574 tdep
->default_mask_address_p
= 0;
8575 set_gdbarch_long_bit (gdbarch
, 32);
8576 set_gdbarch_ptr_bit (gdbarch
, 32);
8577 set_gdbarch_long_long_bit (gdbarch
, 64);
8578 set_gdbarch_long_double_bit (gdbarch
, 128);
8579 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8582 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8583 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8584 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8585 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8586 tdep
->default_mask_address_p
= 0;
8587 set_gdbarch_long_bit (gdbarch
, 64);
8588 set_gdbarch_ptr_bit (gdbarch
, 64);
8589 set_gdbarch_long_long_bit (gdbarch
, 64);
8590 set_gdbarch_long_double_bit (gdbarch
, 128);
8591 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8594 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8597 /* GCC creates a pseudo-section whose name specifies the size of
8598 longs, since -mlong32 or -mlong64 may be used independent of
8599 other options. How those options affect pointer sizes is ABI and
8600 architecture dependent, so use them to override the default sizes
8601 set by the ABI. This table shows the relationship between ABI,
8602 -mlongXX, and size of pointers:
8604 ABI -mlongXX ptr bits
8605 --- -------- --------
8619 Note that for o32 and eabi32, pointers are always 32 bits
8620 regardless of any -mlongXX option. For all others, pointers and
8621 longs are the same, as set by -mlongXX or set by defaults. */
8623 if (info
.abfd
!= NULL
)
8627 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8630 set_gdbarch_long_bit (gdbarch
, long_bit
);
8634 case MIPS_ABI_EABI32
:
8639 case MIPS_ABI_EABI64
:
8640 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8643 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8648 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8649 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8652 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8653 flag in object files because to do so would make it impossible to
8654 link with libraries compiled without "-gp32". This is
8655 unnecessarily restrictive.
8657 We could solve this problem by adding "-gp32" multilibs to gcc,
8658 but to set this flag before gcc is built with such multilibs will
8659 break too many systems.''
8661 But even more unhelpfully, the default linker output target for
8662 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8663 for 64-bit programs - you need to change the ABI to change this,
8664 and not all gcc targets support that currently. Therefore using
8665 this flag to detect 32-bit mode would do the wrong thing given
8666 the current gcc - it would make GDB treat these 64-bit programs
8667 as 32-bit programs by default. */
8669 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8670 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8672 /* Add/remove bits from an address. The MIPS needs be careful to
8673 ensure that all 32 bit addresses are sign extended to 64 bits. */
8674 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8676 /* Unwind the frame. */
8677 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8678 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8679 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8681 /* Map debug register numbers onto internal register numbers. */
8682 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8683 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8684 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8685 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8686 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8687 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8689 /* MIPS version of CALL_DUMMY. */
8691 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8692 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8693 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8695 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8697 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8698 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8699 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8701 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8702 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8703 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8704 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8705 mips_adjust_breakpoint_address
);
8707 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8709 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8711 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8712 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8713 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8715 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8717 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8719 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8720 if (mips_abi
== MIPS_ABI_N64
)
8721 set_gdbarch_disassembler_options_implicit
8722 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8723 else if (mips_abi
== MIPS_ABI_N32
)
8724 set_gdbarch_disassembler_options_implicit
8725 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8727 set_gdbarch_disassembler_options_implicit
8728 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8729 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8730 set_gdbarch_valid_disassembler_options (gdbarch
,
8731 disassembler_options_mips ());
8733 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8734 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8735 need to all be folded into the target vector. Since they are
8736 being used as guards for target_stopped_by_watchpoint, why not have
8737 target_stopped_by_watchpoint return the type of watchpoint that the code
8739 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8741 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8743 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8744 to support MIPS16. This is a bad thing. Make sure not to do it
8745 if we have an OS ABI that actually supports shared libraries, since
8746 shared library support is more important. If we have an OS someday
8747 that supports both shared libraries and MIPS16, we'll have to find
8748 a better place for these.
8749 macro/2012-04-25: But that applies to return trampolines only and
8750 currently no MIPS OS ABI uses shared libraries that have them. */
8751 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8753 set_gdbarch_single_step_through_delay (gdbarch
,
8754 mips_single_step_through_delay
);
8756 /* Virtual tables. */
8757 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8759 mips_register_g_packet_guesses (gdbarch
);
8761 /* Hook in OS ABI-specific overrides, if they have been registered. */
8762 info
.tdesc_data
= tdesc_data
.get ();
8763 gdbarch_init_osabi (info
, gdbarch
);
8765 /* The hook may have adjusted num_regs, fetch the final value and
8766 set pc_regnum and sp_regnum now that it has been fixed. */
8767 num_regs
= gdbarch_num_regs (gdbarch
);
8768 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8769 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8771 /* Unwind the frame. */
8772 dwarf2_append_unwinders (gdbarch
);
8773 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8774 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8775 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8776 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8777 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8778 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8779 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8780 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8781 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8783 if (tdesc_data
!= nullptr)
8785 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8786 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8788 /* Override the normal target description methods to handle our
8789 dual real and pseudo registers. */
8790 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8791 set_gdbarch_register_reggroup_p (gdbarch
,
8792 mips_tdesc_register_reggroup_p
);
8794 num_regs
= gdbarch_num_regs (gdbarch
);
8795 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8796 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8797 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8800 /* Add ABI-specific aliases for the registers. */
8801 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8802 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8803 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8804 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8806 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8807 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8808 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8810 /* Add some other standard aliases. */
8811 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8812 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8813 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8815 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8816 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8817 value_of_mips_user_reg
,
8818 &mips_numeric_register_aliases
[i
].regnum
);
8824 mips_abi_update (const char *ignore_args
,
8825 int from_tty
, struct cmd_list_element
*c
)
8827 struct gdbarch_info info
;
8829 /* Force the architecture to update, and (if it's a MIPS architecture)
8830 mips_gdbarch_init will take care of the rest. */
8831 gdbarch_update_p (info
);
8834 /* Print out which MIPS ABI is in use. */
8837 show_mips_abi (struct ui_file
*file
,
8839 struct cmd_list_element
*ignored_cmd
,
8840 const char *ignored_value
)
8842 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8845 "The MIPS ABI is unknown because the current architecture "
8849 enum mips_abi global_abi
= global_mips_abi ();
8850 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8851 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8853 if (global_abi
== MIPS_ABI_UNKNOWN
)
8856 "The MIPS ABI is set automatically (currently \"%s\").\n",
8858 else if (global_abi
== actual_abi
)
8861 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8865 /* Probably shouldn't happen... */
8866 fprintf_filtered (file
,
8867 "The (auto detected) MIPS ABI \"%s\" is in use "
8868 "even though the user setting was \"%s\".\n",
8869 actual_abi_str
, mips_abi_strings
[global_abi
]);
8874 /* Print out which MIPS compressed ISA encoding is used. */
8877 show_mips_compression (struct ui_file
*file
, int from_tty
,
8878 struct cmd_list_element
*c
, const char *value
)
8880 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8884 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8887 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8893 case MIPS_FPU_SINGLE
:
8895 case MIPS_FPU_DOUBLE
:
8903 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8905 mips_gdbarch_tdep
*tdep
= (mips_gdbarch_tdep
*) gdbarch_tdep (gdbarch
);
8909 int ef_mips_32bitmode
;
8910 /* Determine the ISA. */
8911 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8929 /* Determine the size of a pointer. */
8930 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8931 fprintf_unfiltered (file
,
8932 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8934 fprintf_unfiltered (file
,
8935 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8937 fprintf_unfiltered (file
,
8938 "mips_dump_tdep: ef_mips_arch = %d\n",
8940 fprintf_unfiltered (file
,
8941 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8942 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8943 fprintf_unfiltered (file
,
8945 "mips_mask_address_p() %d (default %d)\n",
8946 mips_mask_address_p (tdep
),
8947 tdep
->default_mask_address_p
);
8949 fprintf_unfiltered (file
,
8950 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8951 MIPS_DEFAULT_FPU_TYPE
,
8952 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8953 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8954 mips_eabi (gdbarch
));
8955 fprintf_unfiltered (file
,
8956 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8957 mips_get_fpu_type (gdbarch
),
8958 mips_fpu_type_str (mips_get_fpu_type (gdbarch
)));
8961 void _initialize_mips_tdep ();
8963 _initialize_mips_tdep ()
8965 static struct cmd_list_element
*mipsfpulist
= NULL
;
8967 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8968 if (MIPS_ABI_LAST
+ 1
8969 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8970 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8972 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8974 /* Create feature sets with the appropriate properties. The values
8975 are not important. */
8976 mips_tdesc_gp32
= allocate_target_description ().release ();
8977 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8979 mips_tdesc_gp64
= allocate_target_description ().release ();
8980 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8982 /* Add root prefix command for all "set mips"/"show mips" commands. */
8983 add_setshow_prefix_cmd ("mips", no_class
,
8984 _("Various MIPS specific commands."),
8985 _("Various MIPS specific commands."),
8986 &setmipscmdlist
, &showmipscmdlist
,
8987 &setlist
, &showlist
);
8989 /* Allow the user to override the ABI. */
8990 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8991 &mips_abi_string
, _("\
8992 Set the MIPS ABI used by this program."), _("\
8993 Show the MIPS ABI used by this program."), _("\
8994 This option can be set to one of:\n\
8995 auto - the default ABI associated with the current binary\n\
9004 &setmipscmdlist
, &showmipscmdlist
);
9006 /* Allow the user to set the ISA to assume for compressed code if ELF
9007 file flags don't tell or there is no program file selected. This
9008 setting is updated whenever unambiguous ELF file flags are interpreted,
9009 and carried over to subsequent sessions. */
9010 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9011 &mips_compression_string
, _("\
9012 Set the compressed ISA encoding used by MIPS code."), _("\
9013 Show the compressed ISA encoding used by MIPS code."), _("\
9014 Select the compressed ISA encoding used in functions that have no symbol\n\
9015 information available. The encoding can be set to either of:\n\
9018 and is updated automatically from ELF file flags if available."),
9020 show_mips_compression
,
9021 &setmipscmdlist
, &showmipscmdlist
);
9023 /* Let the user turn off floating point and set the fence post for
9024 heuristic_proc_start. */
9026 add_basic_prefix_cmd ("mipsfpu", class_support
,
9027 _("Set use of MIPS floating-point coprocessor."),
9028 &mipsfpulist
, 0, &setlist
);
9029 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9030 _("Select single-precision MIPS floating-point coprocessor."),
9032 cmd_list_element
*set_mipsfpu_double_cmd
9033 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9034 _("Select double-precision MIPS floating-point coprocessor."),
9036 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9037 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9038 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9040 cmd_list_element
*set_mipsfpu_none_cmd
9041 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9042 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9043 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9044 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9045 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9046 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9047 _("Select MIPS floating-point coprocessor automatically."),
9049 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9050 _("Show current use of MIPS floating-point coprocessor target."),
9053 /* We really would like to have both "0" and "unlimited" work, but
9054 command.c doesn't deal with that. So make it a var_zinteger
9055 because the user can always use "999999" or some such for unlimited. */
9056 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9057 &heuristic_fence_post
, _("\
9058 Set the distance searched for the start of a function."), _("\
9059 Show the distance searched for the start of a function."), _("\
9060 If you are debugging a stripped executable, GDB needs to search through the\n\
9061 program for the start of a function. This command sets the distance of the\n\
9062 search. The only need to set it is when debugging a stripped executable."),
9063 reinit_frame_cache_sfunc
,
9064 NULL
, /* FIXME: i18n: The distance searched for
9065 the start of a function is %s. */
9066 &setlist
, &showlist
);
9068 /* Allow the user to control whether the upper bits of 64-bit
9069 addresses should be zeroed. */
9070 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9071 &mask_address_var
, _("\
9072 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9073 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9074 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9075 allow GDB to determine the correct value."),
9076 NULL
, show_mask_address
,
9077 &setmipscmdlist
, &showmipscmdlist
);
9079 /* Allow the user to control the size of 32 bit registers within the
9080 raw remote packet. */
9081 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9082 &mips64_transfers_32bit_regs_p
, _("\
9083 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9085 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9087 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9088 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9089 64 bits for others. Use \"off\" to disable compatibility mode"),
9090 set_mips64_transfers_32bit_regs
,
9091 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9092 MIPS target that transfers 32-bit
9093 quantities is %s. */
9094 &setlist
, &showlist
);
9096 /* Debug this files internals. */
9097 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9099 Set mips debugging."), _("\
9100 Show mips debugging."), _("\
9101 When non-zero, mips specific debugging is enabled."),
9103 NULL
, /* FIXME: i18n: Mips debugging is
9105 &setdebuglist
, &showdebuglist
);