1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
42 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
44 /* FIXME: Put this declaration in frame.h. */
45 extern struct obstack frame_cache_obstack
;
48 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
51 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
53 static void mips_print_register
PARAMS ((int, int));
55 static mips_extra_func_info_t
56 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
58 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
60 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
62 static void mips_set_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 static void mips_show_fpu_command
PARAMS ((char *, int,
66 struct cmd_list_element
*));
68 void mips_set_processor_type_command
PARAMS ((char *, int));
70 int mips_set_processor_type
PARAMS ((char *));
72 static void mips_show_processor_type_command
PARAMS ((char *, int));
74 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
75 struct cmd_list_element
*));
77 static mips_extra_func_info_t
78 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
80 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
81 mips_extra_func_info_t proc_desc
));
83 /* This value is the model of MIPS in use. It is derived from the value
84 of the PrID register. */
86 char *mips_processor_type
;
88 char *tmp_mips_processor_type
;
90 /* Some MIPS boards don't support floating point, so we permit the
91 user to turn it off. */
93 enum mips_fpu_type mips_fpu
;
95 static char *mips_fpu_string
;
97 /* A set of original names, to be used when restoring back to generic
98 registers from a specific set. */
100 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
102 /* Names of IDT R3041 registers. */
104 char *mips_r3041_reg_names
[] = {
105 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
106 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
107 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
108 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
109 "sr", "lo", "hi", "bad", "cause","pc",
110 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
111 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
112 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
113 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
114 "fsr", "fir", "fp", "",
115 "", "", "bus", "ccfg", "", "", "", "",
116 "", "", "port", "cmp", "", "", "epc", "prid",
119 /* Names of IDT R3051 registers. */
121 char *mips_r3051_reg_names
[] = {
122 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
123 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
124 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
125 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
126 "sr", "lo", "hi", "bad", "cause","pc",
127 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
128 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
129 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
130 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
131 "fsr", "fir", "fp", "",
132 "inx", "rand", "elo", "", "ctxt", "", "", "",
133 "", "", "ehi", "", "", "", "epc", "prid",
136 /* Names of IDT R3081 registers. */
138 char *mips_r3081_reg_names
[] = {
139 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
140 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
141 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
142 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
143 "sr", "lo", "hi", "bad", "cause","pc",
144 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
145 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
146 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
147 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
148 "fsr", "fir", "fp", "",
149 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
150 "", "", "ehi", "", "", "", "epc", "prid",
153 /* Names of LSI 33k registers. */
155 char *mips_lsi33k_reg_names
[] = {
156 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
157 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
158 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
159 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
160 "epc", "hi", "lo", "sr", "cause","badvaddr",
161 "dcic", "bpc", "bda", "", "", "", "", "",
162 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
173 } mips_processor_type_table
[] = {
174 { "generic", mips_generic_reg_names
},
175 { "r3041", mips_r3041_reg_names
},
176 { "r3051", mips_r3051_reg_names
},
177 { "r3071", mips_r3081_reg_names
},
178 { "r3081", mips_r3081_reg_names
},
179 { "lsi33k", mips_lsi33k_reg_names
},
183 /* Table to translate MIPS16 register field to actual register number. */
184 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
186 /* Heuristic_proc_start may hunt through the text section for a long
187 time across a 2400 baud serial line. Allows the user to limit this
190 static unsigned int heuristic_fence_post
= 0;
192 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
193 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
194 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
195 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
196 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
197 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
198 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
199 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
200 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
201 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
202 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
203 #define _PROC_MAGIC_ 0x0F0F0F0F
204 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
205 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
207 struct linked_proc_info
209 struct mips_extra_func_info info
;
210 struct linked_proc_info
*next
;
211 } *linked_proc_desc_table
= NULL
;
214 /* Should the upper word of 64-bit addresses be zeroed? */
215 static int mask_address_p
= 1;
217 /* Should call_function allocate stack space for a struct return? */
219 mips_use_struct_convention (gcc_p
, type
)
224 return (TYPE_LENGTH (type
) > 2 * MIPS_REGSIZE
);
226 return 1; /* Structures are returned by ref in extra arg0 */
229 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
232 pc_is_mips16 (bfd_vma memaddr
)
234 struct minimal_symbol
*sym
;
236 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
237 if (IS_MIPS16_ADDR (memaddr
))
240 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
241 the high bit of the info field. Use this to decide if the function is
242 MIPS16 or normal MIPS. */
243 sym
= lookup_minimal_symbol_by_pc (memaddr
);
245 return MSYMBOL_IS_SPECIAL (sym
);
251 /* This returns the PC of the first inst after the prologue. If we can't
252 find the prologue, then return 0. */
255 after_prologue (pc
, proc_desc
)
257 mips_extra_func_info_t proc_desc
;
259 struct symtab_and_line sal
;
260 CORE_ADDR func_addr
, func_end
;
263 proc_desc
= find_proc_desc (pc
, NULL
);
267 /* If function is frameless, then we need to do it the hard way. I
268 strongly suspect that frameless always means prologueless... */
269 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
270 && PROC_FRAME_OFFSET (proc_desc
) == 0)
274 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
275 return 0; /* Unknown */
277 sal
= find_pc_line (func_addr
, 0);
279 if (sal
.end
< func_end
)
282 /* The line after the prologue is after the end of the function. In this
283 case, tell the caller to find the prologue the hard way. */
288 /* Decode a MIPS32 instruction that saves a register in the stack, and
289 set the appropriate bit in the general register mask or float register mask
290 to indicate which register is saved. This is a helper function
291 for mips_find_saved_regs. */
294 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
296 unsigned long *gen_mask
;
297 unsigned long *float_mask
;
301 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
302 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
303 /* start-sanitize-r5900 */
304 || (inst
& 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */
305 /* end-sanitize-r5900 */
306 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
308 /* It might be possible to use the instruction to
309 find the offset, rather than the code below which
310 is based on things being in a certain order in the
311 frame, but figuring out what the instruction's offset
312 is relative to might be a little tricky. */
313 reg
= (inst
& 0x001f0000) >> 16;
314 *gen_mask
|= (1 << reg
);
316 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
317 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
318 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
321 reg
= ((inst
& 0x001f0000) >> 16);
322 *float_mask
|= (1 << reg
);
326 /* Decode a MIPS16 instruction that saves a register in the stack, and
327 set the appropriate bit in the general register or float register mask
328 to indicate which register is saved. This is a helper function
329 for mips_find_saved_regs. */
332 mips16_decode_reg_save (inst
, gen_mask
)
334 unsigned long *gen_mask
;
336 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
338 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
339 *gen_mask
|= (1 << reg
);
341 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
343 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
344 *gen_mask
|= (1 << reg
);
346 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
347 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
348 *gen_mask
|= (1 << RA_REGNUM
);
352 /* Fetch and return instruction from the specified location. If the PC
353 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
356 mips_fetch_instruction (addr
)
359 char buf
[MIPS_INSTLEN
];
363 if (pc_is_mips16 (addr
))
365 instlen
= MIPS16_INSTLEN
;
366 addr
= UNMAKE_MIPS16_ADDR (addr
);
369 instlen
= MIPS_INSTLEN
;
370 status
= read_memory_nobpt (addr
, buf
, instlen
);
372 memory_error (status
, addr
);
373 return extract_unsigned_integer (buf
, instlen
);
377 /* These the fields of 32 bit mips instructions */
378 #define mips32_op(x) (x >> 25)
379 #define itype_op(x) (x >> 25)
380 #define itype_rs(x) ((x >> 21)& 0x1f)
381 #define itype_rt(x) ((x >> 16) & 0x1f)
382 #define itype_immediate(x) ( x & 0xffff)
384 #define jtype_op(x) (x >> 25)
385 #define jtype_target(x) ( x & 0x03fffff)
387 #define rtype_op(x) (x >>25)
388 #define rtype_rs(x) ((x>>21) & 0x1f)
389 #define rtype_rt(x) ((x>>16) & 0x1f)
390 #define rtype_rd(x) ((x>>11) & 0x1f)
391 #define rtype_shamt(x) ((x>>6) & 0x1f)
392 #define rtype_funct(x) (x & 0x3f )
395 mips32_relative_offset(unsigned long inst
)
397 x
= itype_immediate(inst
) ;
398 if (x
& 0x8000) /* sign bit set */
400 x
|= 0xffff0000 ; /* sign extension */
406 /* Determine whate to set a single step breakpoint while considering
409 mips32_next_pc(CORE_ADDR pc
)
413 inst
= mips_fetch_instruction(pc
) ;
414 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
415 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
416 { op
= ((inst
>> 25) & 0x03) ;
419 case 0 : goto equal_branch
; /* BEQL */
420 case 1 : goto neq_branch
; /* BNEZ */
421 case 2 : goto less_branch
; /* BLEZ */
422 case 3 : goto greater_branch
; /* BGTZ */
426 else pc
+= 4 ; /* Not a branch, next instruction is easy */
429 { /* This gets way messy */
431 /* Further subdivide into SPECIAL, REGIMM and other */
432 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
434 case 0 : /* SPECIAL */
435 op
= rtype_funct(inst
) ;
440 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
445 break ; /* end special */
446 case 1 : /* REGIMM */
448 op
= jtype_op(inst
) ; /* branch condition */
449 switch (jtype_op(inst
))
453 case 16 : /* BLTZALL */
454 case 18 : /* BLTZALL */
456 if (read_register(itype_rs(inst
)) < 0)
457 pc
+= mips32_relative_offset(inst
) + 4 ;
458 else pc
+= 8 ; /* after the delay slot */
462 case 17 : /* BGEZAL */
463 case 19 : /* BGEZALL */
464 greater_equal_branch
:
465 if (read_register(itype_rs(inst
)) >= 0)
466 pc
+= mips32_relative_offset(inst
) + 4 ;
467 else pc
+= 8 ; /* after the delay slot */
469 /* All of the other intructions in the REGIMM catagory */
473 break ; /* end REGIMM */
476 { unsigned long reg
;
477 reg
= jtype_target(inst
) << 2 ;
478 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
479 /* Whats this mysterious 0xf000000 adjustment ??? */
482 /* FIXME case JALX :*/
483 { unsigned long reg
;
484 reg
= jtype_target(inst
) << 2 ;
485 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
486 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
488 break ; /* The new PC will be alternate mode */
489 case 4 : /* BEQ , BEQL */
491 if (read_register(itype_rs(inst
)) ==
492 read_register(itype_rt(inst
)))
493 pc
+= mips32_relative_offset(inst
) + 4 ;
496 case 5 : /* BNE , BNEL */
498 if (read_register(itype_rs(inst
)) !=
499 read_register(itype_rs(inst
)))
500 pc
+= mips32_relative_offset(inst
) + 4 ;
503 case 6 : /* BLEZ , BLEZL */
505 if (read_register(itype_rs(inst
) <= 0))
506 pc
+= mips32_relative_offset(inst
) + 4 ;
510 greater_branch
: /* BGTZ BGTZL */
511 if (read_register(itype_rs(inst
) > 0))
512 pc
+= mips32_relative_offset(inst
) + 4 ;
519 } /* mips32_next_pc */
521 /* Decoding the next place to set a breakpoint is irregular for the
522 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
523 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
524 We dont want to set a single step instruction on the extend instruction
528 /* Lots of mips16 instruction formats */
529 /* Predicting jumps requires itype,ritype,i8type
530 and their extensions extItype,extritype,extI8type
532 enum mips16_inst_fmts
534 itype
, /* 0 immediate 5,10 */
535 ritype
, /* 1 5,3,8 */
536 rrtype
, /* 2 5,3,3,5 */
537 rritype
, /* 3 5,3,3,5 */
538 rrrtype
, /* 4 5,3,3,3,2 */
539 rriatype
, /* 5 5,3,3,1,4 */
540 shifttype
, /* 6 5,3,3,3,2 */
541 i8type
, /* 7 5,3,8 */
542 i8movtype
, /* 8 5,3,3,5 */
543 i8mov32rtype
, /* 9 5,3,5,3 */
544 i64type
, /* 10 5,3,8 */
545 ri64type
, /* 11 5,3,3,5 */
546 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
547 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
548 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
549 extRRItype
, /* 15 5,5,5,5,3,3,5 */
550 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
551 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
552 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
553 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
554 extRi64type
, /* 20 5,6,5,5,3,3,5 */
555 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
557 /* I am heaping all the fields of the formats into one structure and then,
558 only the fields which are involved in instruction extension */
561 unsigned short inst
;
562 enum mips16_inst_fmts fmt
;
563 unsigned long offset
;
564 unsigned int regx
; /* Function in i8 type */
570 static void print_unpack(char * comment
,
571 struct upk_mips16
* u
)
573 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
574 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
577 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
578 format for the bits which make up the immediatate extension.
581 extended_offset(unsigned long extension
)
583 unsigned long value
;
584 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
586 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
588 value
|= extension
& 0x01f ; /* extract 4:0 */
592 /* Only call this function if you know that this is an extendable
593 instruction, It wont malfunction, but why make excess remote memory references?
594 If the immediate operands get sign extended or somthing, do it after
595 the extension is performed.
597 /* FIXME: Every one of these cases needs to worry about sign extension
598 when the offset is to be used in relative addressing */
601 static unsigned short fetch_mips_16(CORE_ADDR pc
)
604 pc
&= 0xfffffffe ; /* clear the low order bit */
605 target_read_memory(pc
,buf
,2) ;
606 return extract_unsigned_integer(buf
,2) ;
610 unpack_mips16(CORE_ADDR pc
,
611 struct upk_mips16
* upk
)
614 unsigned long extension
;
616 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
617 /* Decrement to previous address and loose the 16bit mode flag */
618 /* return if the instruction was extendable, but not actually extended */
619 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
620 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
625 unsigned long value
;
627 { value
= extended_offset(extension
) ;
628 value
= value
<< 11 ; /* rom for the original value */
629 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
632 { value
= upk
->inst
& 0x7ff ;
633 /* FIXME : Consider sign extension */
635 upk
->offset
= value
;
640 { /* A register identifier and an offset */
641 /* Most of the fields are the same as I type but the
642 immediate value is of a different length */
643 unsigned long value
;
646 value
= extended_offset(extension
) ;
647 value
= value
<< 8 ; /* from the original instruction */
648 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
649 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
650 if (value
& 0x4000) /* test the sign bit , bit 26 */
651 { value
&= ~ 0x3fff ; /* remove the sign bit */
656 value
= upk
->inst
& 0xff ; /* 8 bits */
657 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
658 /* FIXME: Do sign extension , this format needs it */
659 if (value
& 0x80) /* THIS CONFUSES ME */
660 { value
&= 0xef ; /* remove the sign bit */
665 upk
->offset
= value
;
670 unsigned long value
;
671 unsigned short nexthalf
;
672 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
673 value
= value
<< 16 ;
674 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
676 upk
->offset
= value
;
680 printf_filtered("Decoding unimplemented instruction format type\n") ;
683 /* print_unpack("UPK",upk) ; */
687 #define mips16_op(x) (x >> 11)
689 /* This is a map of the opcodes which ae known to perform branches */
690 static unsigned char map16
[32] =
697 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
699 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
705 static struct upk_mips16 upk
;
707 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
711 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
712 inst
= fetch_mips_16(pc
) ;
714 op
= mips16_op(upk
.inst
) ;
720 case 2 : /* Branch */
722 unpack_mips16(pc
,&upk
) ;
724 offset
= upk
.offset
;
729 pc
+= (offset
<< 1) + 2 ;
732 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
734 unpack_mips16(pc
,&upk
) ;
735 pc
= add_offset_16(pc
,upk
.offset
) ;
736 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
737 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
742 unpack_mips16(pc
,&upk
) ;
743 reg
= read_register(upk
.regx
) ;
745 pc
+= (upk
.offset
<< 1) + 2 ;
750 unpack_mips16(pc
,&upk
) ;
751 reg
= read_register(upk
.regx
) ;
753 pc
+= (upk
.offset
<< 1) + 2 ;
756 case 12 : /* I8 Formats btez btnez */
758 unpack_mips16(pc
,&upk
) ;
759 /* upk.regx contains the opcode */
760 reg
= read_register(24) ; /* Test register is 24 */
761 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
762 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
763 /* pc = add_offset_16(pc,upk.offset) ; */
764 pc
+= (upk
.offset
<< 1) + 2 ;
767 case 29 : /* RR Formats JR, JALR, JALR-RA */
769 op
= upk
.inst
& 0x1f ;
772 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
773 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
776 case 0 : reg
= upk
.regx
; break ;
777 case 1 : reg
= 31 ; break ; /* Function return instruction*/
778 case 2 : reg
= upk
.regx
; break ;
779 default: reg
= 31 ; break ; /* BOGUS Guess */
781 pc
= read_register(reg
) ;
785 case 30 : /* This is an extend instruction */
786 pc
+= 4 ; /* Dont be setting breakpints on the second half */
789 printf("Filtered - next PC probably incorrrect due to jump inst\n");
794 else pc
+= 2 ; /* just a good old instruction */
795 /* See if we CAN actually break on the next instruction */
796 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
798 } /* mips16_next_pc */
800 /* The mips_next_pc function supports single_tep when the remote target monitor or
801 stub is not developed enough to so a single_step.
802 It works by decoding the current instruction and predicting where a branch
803 will go. This isnt hard because all the data is available.
804 The MIPS32 and MIPS16 variants are quite different
806 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
809 /* inst = mips_fetch_instruction(pc) ; */
810 /* if (pc_is_mips16) <----- This is failing */
812 return mips16_next_pc(pc
) ;
813 else return mips32_next_pc(pc
) ;
816 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
820 mips_find_saved_regs (fci
)
821 struct frame_info
*fci
;
824 CORE_ADDR reg_position
;
825 /* r0 bit means kernel trap */
827 /* What registers have been saved? Bitmasks. */
828 unsigned long gen_mask
, float_mask
;
829 mips_extra_func_info_t proc_desc
;
832 fci
->saved_regs
= (struct frame_saved_regs
*)
833 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
834 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
836 /* If it is the frame for sigtramp, the saved registers are located
837 in a sigcontext structure somewhere on the stack.
838 If the stack layout for sigtramp changes we might have to change these
839 constants and the companion fixup_sigtramp in mdebugread.c */
840 #ifndef SIGFRAME_BASE
841 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
842 above the sigtramp frame. */
843 #define SIGFRAME_BASE MIPS_REGSIZE
844 /* FIXME! Are these correct?? */
845 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
846 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
847 #define SIGFRAME_FPREGSAVE_OFF \
848 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
850 #ifndef SIGFRAME_REG_SIZE
851 /* FIXME! Is this correct?? */
852 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
854 if (fci
->signal_handler_caller
)
856 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
858 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
859 + ireg
* SIGFRAME_REG_SIZE
;
860 fci
->saved_regs
->regs
[ireg
] = reg_position
;
862 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
864 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
865 + ireg
* SIGFRAME_REG_SIZE
;
866 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
868 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
872 proc_desc
= fci
->proc_desc
;
873 if (proc_desc
== NULL
)
874 /* I'm not sure how/whether this can happen. Normally when we can't
875 find a proc_desc, we "synthesize" one using heuristic_proc_desc
876 and set the saved_regs right away. */
879 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
880 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
881 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
883 if (/* In any frame other than the innermost or a frame interrupted by
884 a signal, we assume that all registers have been saved.
885 This assumes that all register saves in a function happen before
886 the first function call. */
887 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
889 /* In a dummy frame we know exactly where things are saved. */
890 && !PROC_DESC_IS_DUMMY (proc_desc
)
892 /* Don't bother unless we are inside a function prologue. Outside the
893 prologue, we know where everything is. */
895 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
897 /* Not sure exactly what kernel_trap means, but if it means
898 the kernel saves the registers without a prologue doing it,
899 we better not examine the prologue to see whether registers
900 have been saved yet. */
903 /* We need to figure out whether the registers that the proc_desc
904 claims are saved have been saved yet. */
908 /* Bitmasks; set if we have found a save for the register. */
909 unsigned long gen_save_found
= 0;
910 unsigned long float_save_found
= 0;
913 /* If the address is odd, assume this is MIPS16 code. */
914 addr
= PROC_LOW_ADDR (proc_desc
);
915 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
917 /* Scan through this function's instructions preceding the current
918 PC, and look for those that save registers. */
919 while (addr
< fci
->pc
)
921 inst
= mips_fetch_instruction (addr
);
922 if (pc_is_mips16 (addr
))
923 mips16_decode_reg_save (inst
, &gen_save_found
);
925 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
928 gen_mask
= gen_save_found
;
929 float_mask
= float_save_found
;
932 /* Fill in the offsets for the registers which gen_mask says
934 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
935 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
936 if (gen_mask
& 0x80000000)
938 fci
->saved_regs
->regs
[ireg
] = reg_position
;
939 reg_position
-= MIPS_REGSIZE
;
940 /* start-sanitize-r5900 */
941 #ifdef R5900_128BIT_GPR_HACK
942 /* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is
943 still 64bits. See the comments in tm.h for a discussion of the
944 various problems this causes. */
945 if (ireg
<= RA_REGNUM
)
946 reg_position
-= MIPS_REGSIZE
;
948 /* end-sanitize-r5900 */
951 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
952 of that normally used by gcc. Therefore, we have to fetch the first
953 instruction of the function, and if it's an entry instruction that
954 saves $s0 or $s1, correct their saved addresses. */
955 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
957 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
958 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
961 int sreg_count
= (inst
>> 6) & 3;
963 /* Check if the ra register was pushed on the stack. */
964 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
966 reg_position
-= MIPS_REGSIZE
;
968 /* Check if the s0 and s1 registers were pushed on the stack. */
969 for (reg
= 16; reg
< sreg_count
+16; reg
++)
971 fci
->saved_regs
->regs
[reg
] = reg_position
;
972 reg_position
-= MIPS_REGSIZE
;
977 /* Fill in the offsets for the registers which float_mask says
979 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
981 /* The freg_offset points to where the first *double* register
982 is saved. So skip to the high-order word. */
983 if (! GDB_TARGET_IS_MIPS64
)
984 reg_position
+= MIPS_REGSIZE
;
986 /* Fill in the offsets for the float registers which float_mask says
988 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
989 if (float_mask
& 0x80000000)
991 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
992 reg_position
-= MIPS_REGSIZE
;
995 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
999 read_next_frame_reg(fi
, regno
)
1000 struct frame_info
*fi
;
1003 for (; fi
; fi
= fi
->next
)
1005 /* We have to get the saved sp from the sigcontext
1006 if it is a signal handler frame. */
1007 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1011 if (fi
->saved_regs
== NULL
)
1012 mips_find_saved_regs (fi
);
1013 if (fi
->saved_regs
->regs
[regno
])
1014 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
1017 return read_register (regno
);
1020 /* mips_addr_bits_remove - remove useless address bits */
1023 mips_addr_bits_remove (addr
)
1026 #if GDB_TARGET_IS_MIPS64
1027 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1029 /* This hack is a work-around for existing boards using PMON,
1030 the simulator, and any other 64-bit targets that doesn't have
1031 true 64-bit addressing. On these targets, the upper 32 bits
1032 of addresses are ignored by the hardware. Thus, the PC or SP
1033 are likely to have been sign extended to all 1s by instruction
1034 sequences that load 32-bit addresses. For example, a typical
1035 piece of code that loads an address is this:
1036 lui $r2, <upper 16 bits>
1037 ori $r2, <lower 16 bits>
1038 But the lui sign-extends the value such that the upper 32 bits
1039 may be all 1s. The workaround is simply to mask off these bits.
1040 In the future, gcc may be changed to support true 64-bit
1041 addressing, and this masking will have to be disabled. */
1042 addr
&= (CORE_ADDR
)0xffffffff;
1045 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1046 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1047 So we still have to mask off useless bits from addresses. */
1048 addr
&= (CORE_ADDR
)0xffffffff;
1055 mips_init_frame_pc_first (fromleaf
, prev
)
1057 struct frame_info
*prev
;
1061 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1062 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1063 tmp
= mips_skip_stub (pc
);
1064 prev
->pc
= tmp
? tmp
: pc
;
1069 mips_frame_saved_pc(frame
)
1070 struct frame_info
*frame
;
1073 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1074 /* We have to get the saved pc from the sigcontext
1075 if it is a signal handler frame. */
1076 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1077 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1079 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1080 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1082 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1084 return ADDR_BITS_REMOVE (saved_pc
);
1087 static struct mips_extra_func_info temp_proc_desc
;
1088 static struct frame_saved_regs temp_saved_regs
;
1090 /* Set a register's saved stack address in temp_saved_regs. If an address
1091 has already been set for this register, do nothing; this way we will
1092 only recognize the first save of a given register in a function prologue.
1093 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1096 set_reg_offset (regno
, offset
)
1100 if (temp_saved_regs
.regs
[regno
] == 0)
1101 temp_saved_regs
.regs
[regno
] = offset
;
1105 /* Test whether the PC points to the return instruction at the
1106 end of a function. */
1109 mips_about_to_return (pc
)
1112 if (pc_is_mips16 (pc
))
1113 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1114 generates a "jr $ra"; other times it generates code to load
1115 the return address from the stack to an accessible register (such
1116 as $a3), then a "jr" using that register. This second case
1117 is almost impossible to distinguish from an indirect jump
1118 used for switch statements, so we don't even try. */
1119 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1121 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1125 /* This fencepost looks highly suspicious to me. Removing it also
1126 seems suspicious as it could affect remote debugging across serial
1130 heuristic_proc_start (pc
)
1138 pc
= ADDR_BITS_REMOVE (pc
);
1140 fence
= start_pc
- heuristic_fence_post
;
1141 if (start_pc
== 0) return 0;
1143 if (heuristic_fence_post
== UINT_MAX
1144 || fence
< VM_MIN_ADDRESS
)
1145 fence
= VM_MIN_ADDRESS
;
1147 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1149 /* search back for previous return */
1150 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1151 if (start_pc
< fence
)
1153 /* It's not clear to me why we reach this point when
1154 stop_soon_quietly, but with this test, at least we
1155 don't print out warnings for every child forked (eg, on
1156 decstation). 22apr93 rich@cygnus.com. */
1157 if (!stop_soon_quietly
)
1159 static int blurb_printed
= 0;
1161 if (fence
== VM_MIN_ADDRESS
)
1162 warning("Hit beginning of text section without finding");
1164 warning("Hit heuristic-fence-post without finding");
1166 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1170 This warning occurs if you are debugging a function without any symbols\n\
1171 (for example, in a stripped executable). In that case, you may wish to\n\
1172 increase the size of the search with the `set heuristic-fence-post' command.\n\
1174 Otherwise, you told GDB there was a function where there isn't one, or\n\
1175 (more likely) you have encountered a bug in GDB.\n");
1182 else if (pc_is_mips16 (start_pc
))
1184 unsigned short inst
;
1186 /* On MIPS16, any one of the following is likely to be the
1187 start of a function:
1191 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1192 inst
= mips_fetch_instruction (start_pc
);
1193 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1194 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1195 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1196 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1198 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1199 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1204 else if (mips_about_to_return (start_pc
))
1206 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1211 /* skip nops (usually 1) 0 - is this */
1212 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1213 start_pc
+= MIPS_INSTLEN
;
1218 /* Fetch the immediate value from a MIPS16 instruction.
1219 If the previous instruction was an EXTEND, use it to extend
1220 the upper bits of the immediate value. This is a helper function
1221 for mips16_heuristic_proc_desc. */
1224 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1225 unsigned short prev_inst
; /* previous instruction */
1226 unsigned short inst
; /* current instruction */
1227 int nbits
; /* number of bits in imm field */
1228 int scale
; /* scale factor to be applied to imm */
1229 int is_signed
; /* is the imm field signed? */
1233 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1235 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1236 if (offset
& 0x8000) /* check for negative extend */
1237 offset
= 0 - (0x10000 - (offset
& 0xffff));
1238 return offset
| (inst
& 0x1f);
1242 int max_imm
= 1 << nbits
;
1243 int mask
= max_imm
- 1;
1244 int sign_bit
= max_imm
>> 1;
1246 offset
= inst
& mask
;
1247 if (is_signed
&& (offset
& sign_bit
))
1248 offset
= 0 - (max_imm
- offset
);
1249 return offset
* scale
;
1254 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1255 stream from start_pc to limit_pc. */
1258 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1259 CORE_ADDR start_pc
, limit_pc
;
1260 struct frame_info
*next_frame
;
1264 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1265 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1266 unsigned inst
= 0; /* current instruction */
1267 unsigned entry_inst
= 0; /* the entry instruction */
1270 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1271 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1273 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1275 /* Save the previous instruction. If it's an EXTEND, we'll extract
1276 the immediate offset extension from it in mips16_get_imm. */
1279 /* Fetch and decode the instruction. */
1280 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1281 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1282 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1284 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1285 if (offset
< 0) /* negative stack adjustment? */
1286 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1288 /* Exit loop if a positive stack adjustment is found, which
1289 usually means that the stack cleanup code in the function
1290 epilogue is reached. */
1293 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1295 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1296 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1297 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1298 set_reg_offset (reg
, sp
+ offset
);
1300 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1302 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1303 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1304 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1305 set_reg_offset (reg
, sp
+ offset
);
1307 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1309 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1310 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1311 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1313 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1315 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1316 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1317 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1319 else if (inst
== 0x673d) /* move $s1, $sp */
1322 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1324 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1326 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1327 frame_addr
= sp
+ offset
;
1328 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1329 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1331 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1333 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1334 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1335 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1336 set_reg_offset (reg
, frame_addr
+ offset
);
1338 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1340 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1341 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1342 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1343 set_reg_offset (reg
, frame_addr
+ offset
);
1345 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1346 entry_inst
= inst
; /* save for later processing */
1347 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1348 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1351 /* The entry instruction is typically the first instruction in a function,
1352 and it stores registers at offsets relative to the value of the old SP
1353 (before the prologue). But the value of the sp parameter to this
1354 function is the new SP (after the prologue has been executed). So we
1355 can't calculate those offsets until we've seen the entire prologue,
1356 and can calculate what the old SP must have been. */
1357 if (entry_inst
!= 0)
1359 int areg_count
= (entry_inst
>> 8) & 7;
1360 int sreg_count
= (entry_inst
>> 6) & 3;
1362 /* The entry instruction always subtracts 32 from the SP. */
1363 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1365 /* Now we can calculate what the SP must have been at the
1366 start of the function prologue. */
1367 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1369 /* Check if a0-a3 were saved in the caller's argument save area. */
1370 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1372 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1373 set_reg_offset (reg
, sp
+ offset
);
1374 offset
+= MIPS_REGSIZE
;
1377 /* Check if the ra register was pushed on the stack. */
1379 if (entry_inst
& 0x20)
1381 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1382 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1383 offset
-= MIPS_REGSIZE
;
1386 /* Check if the s0 and s1 registers were pushed on the stack. */
1387 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1389 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1390 set_reg_offset (reg
, sp
+ offset
);
1391 offset
-= MIPS_REGSIZE
;
1397 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1398 CORE_ADDR start_pc
, limit_pc
;
1399 struct frame_info
*next_frame
;
1403 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1405 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1406 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1407 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1409 unsigned long inst
, high_word
, low_word
;
1412 /* Fetch the instruction. */
1413 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1415 /* Save some code by pre-extracting some useful fields. */
1416 high_word
= (inst
>> 16) & 0xffff;
1417 low_word
= inst
& 0xffff;
1418 reg
= high_word
& 0x1f;
1420 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1421 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1422 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1424 if (low_word
& 0x8000) /* negative stack adjustment? */
1425 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1427 /* Exit loop if a positive stack adjustment is found, which
1428 usually means that the stack cleanup code in the function
1429 epilogue is reached. */
1432 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1434 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1435 set_reg_offset (reg
, sp
+ low_word
);
1437 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1439 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1440 but the register size used is only 32 bits. Make the address
1441 for the saved register point to the lower 32 bits. */
1442 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1443 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1445 /* start-sanitize-r5900 */
1446 else if ((high_word
& 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */
1448 /* I don't think we have to worry about the Irix 6.2 N32 ABI
1449 issue noted int he sd reg, offset($sp) case above. */
1450 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1451 set_reg_offset (reg
, sp
+ low_word
);
1453 /* end-sanitize-r5900 */
1454 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1456 /* Old gcc frame, r30 is virtual frame pointer. */
1457 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1458 frame_addr
= sp
+ low_word
;
1459 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1461 unsigned alloca_adjust
;
1462 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1463 frame_addr
= read_next_frame_reg(next_frame
, 30);
1464 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1465 if (alloca_adjust
> 0)
1467 /* FP > SP + frame_size. This may be because
1468 * of an alloca or somethings similar.
1469 * Fix sp to "pre-alloca" value, and try again.
1471 sp
+= alloca_adjust
;
1476 /* move $30,$sp. With different versions of gas this will be either
1477 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1478 Accept any one of these. */
1479 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1481 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1482 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1484 unsigned alloca_adjust
;
1485 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1486 frame_addr
= read_next_frame_reg(next_frame
, 30);
1487 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1488 if (alloca_adjust
> 0)
1490 /* FP > SP + frame_size. This may be because
1491 * of an alloca or somethings similar.
1492 * Fix sp to "pre-alloca" value, and try again.
1494 sp
+= alloca_adjust
;
1499 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1501 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1502 set_reg_offset (reg
, frame_addr
+ low_word
);
1507 static mips_extra_func_info_t
1508 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1509 CORE_ADDR start_pc
, limit_pc
;
1510 struct frame_info
*next_frame
;
1512 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1514 if (start_pc
== 0) return NULL
;
1515 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1516 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1517 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1518 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1519 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1521 if (start_pc
+ 200 < limit_pc
)
1522 limit_pc
= start_pc
+ 200;
1523 if (pc_is_mips16 (start_pc
))
1524 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1526 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1527 return &temp_proc_desc
;
1530 static mips_extra_func_info_t
1531 non_heuristic_proc_desc (pc
, addrptr
)
1535 CORE_ADDR startaddr
;
1536 mips_extra_func_info_t proc_desc
;
1537 struct block
*b
= block_for_pc(pc
);
1540 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1542 *addrptr
= startaddr
;
1543 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1547 if (startaddr
> BLOCK_START (b
))
1548 /* This is the "pathological" case referred to in a comment in
1549 print_frame_info. It might be better to move this check into
1553 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1556 /* If we never found a PDR for this function in symbol reading, then
1557 examine prologues to find the information. */
1560 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1561 if (PROC_FRAME_REG (proc_desc
) == -1)
1571 static mips_extra_func_info_t
1572 find_proc_desc (pc
, next_frame
)
1574 struct frame_info
*next_frame
;
1576 mips_extra_func_info_t proc_desc
;
1577 CORE_ADDR startaddr
;
1579 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1583 /* IF this is the topmost frame AND
1584 * (this proc does not have debugging information OR
1585 * the PC is in the procedure prologue)
1586 * THEN create a "heuristic" proc_desc (by analyzing
1587 * the actual code) to replace the "official" proc_desc.
1589 if (next_frame
== NULL
)
1591 struct symtab_and_line val
;
1592 struct symbol
*proc_symbol
=
1593 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1597 val
= find_pc_line (BLOCK_START
1598 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1600 val
.pc
= val
.end
? val
.end
: pc
;
1602 if (!proc_symbol
|| pc
< val
.pc
)
1604 mips_extra_func_info_t found_heuristic
=
1605 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1607 if (found_heuristic
)
1608 proc_desc
= found_heuristic
;
1614 /* Is linked_proc_desc_table really necessary? It only seems to be used
1615 by procedure call dummys. However, the procedures being called ought
1616 to have their own proc_descs, and even if they don't,
1617 heuristic_proc_desc knows how to create them! */
1619 register struct linked_proc_info
*link
;
1621 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1622 if (PROC_LOW_ADDR(&link
->info
) <= pc
1623 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1627 startaddr
= heuristic_proc_start (pc
);
1630 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1636 get_frame_pointer(frame
, proc_desc
)
1637 struct frame_info
*frame
;
1638 mips_extra_func_info_t proc_desc
;
1640 return ADDR_BITS_REMOVE (
1641 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1642 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1645 mips_extra_func_info_t cached_proc_desc
;
1648 mips_frame_chain(frame
)
1649 struct frame_info
*frame
;
1651 mips_extra_func_info_t proc_desc
;
1653 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1655 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1658 /* Check if the PC is inside a call stub. If it is, fetch the
1659 PC of the caller of that stub. */
1660 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1663 /* Look up the procedure descriptor for this PC. */
1664 proc_desc
= find_proc_desc(saved_pc
, frame
);
1668 cached_proc_desc
= proc_desc
;
1670 /* If no frame pointer and frame size is zero, we must be at end
1671 of stack (or otherwise hosed). If we don't check frame size,
1672 we loop forever if we see a zero size frame. */
1673 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1674 && PROC_FRAME_OFFSET (proc_desc
) == 0
1675 /* The previous frame from a sigtramp frame might be frameless
1676 and have frame size zero. */
1677 && !frame
->signal_handler_caller
)
1680 return get_frame_pointer (frame
, proc_desc
);
1684 init_extra_frame_info(fci
)
1685 struct frame_info
*fci
;
1689 /* Use proc_desc calculated in frame_chain */
1690 mips_extra_func_info_t proc_desc
=
1691 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1693 fci
->saved_regs
= NULL
;
1695 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1698 /* Fixup frame-pointer - only needed for top frame */
1699 /* This may not be quite right, if proc has a real frame register.
1700 Get the value of the frame relative sp, procedure might have been
1701 interrupted by a signal at it's very start. */
1702 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1703 && !PROC_DESC_IS_DUMMY (proc_desc
))
1704 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1706 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1708 if (proc_desc
== &temp_proc_desc
)
1712 /* Do not set the saved registers for a sigtramp frame,
1713 mips_find_saved_registers will do that for us.
1714 We can't use fci->signal_handler_caller, it is not yet set. */
1715 find_pc_partial_function (fci
->pc
, &name
,
1716 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1717 if (!IN_SIGTRAMP (fci
->pc
, name
))
1719 fci
->saved_regs
= (struct frame_saved_regs
*)
1720 obstack_alloc (&frame_cache_obstack
,
1721 sizeof (struct frame_saved_regs
));
1722 *fci
->saved_regs
= temp_saved_regs
;
1723 fci
->saved_regs
->regs
[PC_REGNUM
]
1724 = fci
->saved_regs
->regs
[RA_REGNUM
];
1728 /* hack: if argument regs are saved, guess these contain args */
1729 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1730 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1732 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1734 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1741 /* MIPS stack frames are almost impenetrable. When execution stops,
1742 we basically have to look at symbol information for the function
1743 that we stopped in, which tells us *which* register (if any) is
1744 the base of the frame pointer, and what offset from that register
1745 the frame itself is at.
1747 This presents a problem when trying to examine a stack in memory
1748 (that isn't executing at the moment), using the "frame" command. We
1749 don't have a PC, nor do we have any registers except SP.
1751 This routine takes two arguments, SP and PC, and tries to make the
1752 cached frames look as if these two arguments defined a frame on the
1753 cache. This allows the rest of info frame to extract the important
1754 arguments without difficulty. */
1757 setup_arbitrary_frame (argc
, argv
)
1762 error ("MIPS frame specifications require two arguments: sp and pc");
1764 return create_new_frame (argv
[0], argv
[1]);
1768 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1770 * For n32 ABI, eight.
1771 * For all others, he same as the size of a general register.
1773 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1774 #define MIPS_NABI32 1
1775 #define STACK_ARGSIZE 8
1777 #define MIPS_NABI32 0
1778 #define STACK_ARGSIZE MIPS_REGSIZE
1782 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1787 CORE_ADDR struct_addr
;
1793 int stack_offset
= 0;
1795 /* Macros to round N up or down to the next A boundary; A must be
1797 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1798 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1800 /* First ensure that the stack and structure return address (if any)
1801 are properly aligned. The stack has to be at least 64-bit aligned
1802 even on 32-bit machines, because doubles must be 64-bit aligned.
1803 On at least one MIPS variant, stack frames need to be 128-bit
1804 aligned, so we round to this widest known alignment. */
1805 sp
= ROUND_DOWN (sp
, 16);
1806 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1808 /* Now make space on the stack for the args. We allocate more
1809 than necessary for EABI, because the first few arguments are
1810 passed in registers, but that's OK. */
1811 for (argnum
= 0; argnum
< nargs
; argnum
++)
1812 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1813 sp
-= ROUND_UP (len
, 16);
1815 /* Initialize the integer and float register pointers. */
1817 float_argreg
= FPA0_REGNUM
;
1819 /* the struct_return pointer occupies the first parameter-passing reg */
1821 write_register (argreg
++, struct_addr
);
1823 /* Now load as many as possible of the first arguments into
1824 registers, and push the rest onto the stack. Loop thru args
1825 from first to last. */
1826 for (argnum
= 0; argnum
< nargs
; argnum
++)
1829 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1830 value_ptr arg
= args
[argnum
];
1831 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1832 int len
= TYPE_LENGTH (arg_type
);
1833 enum type_code typecode
= TYPE_CODE (arg_type
);
1835 /* The EABI passes structures that do not fit in a register by
1836 reference. In all other cases, pass the structure by value. */
1837 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1838 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1840 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1841 typecode
= TYPE_CODE_PTR
;
1846 val
= (char *)VALUE_CONTENTS (arg
);
1848 /* 32-bit ABIs always start floating point arguments in an
1849 even-numbered floating point register. */
1850 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1851 && (float_argreg
& 1))
1854 /* Floating point arguments passed in registers have to be
1855 treated specially. On 32-bit architectures, doubles
1856 are passed in register pairs; the even register gets
1857 the low word, and the odd register gets the high word.
1858 On non-EABI processors, the first two floating point arguments are
1859 also copied to general registers, because MIPS16 functions
1860 don't use float registers for arguments. This duplication of
1861 arguments in general registers can't hurt non-MIPS16 functions
1862 because those registers are normally skipped. */
1863 if (typecode
== TYPE_CODE_FLT
1864 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1865 && mips_fpu
!= MIPS_FPU_NONE
)
1867 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1869 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1870 unsigned long regval
;
1872 /* Write the low word of the double to the even register(s). */
1873 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1874 write_register (float_argreg
++, regval
);
1876 write_register (argreg
+1, regval
);
1878 /* Write the high word of the double to the odd register(s). */
1879 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1880 write_register (float_argreg
++, regval
);
1883 write_register (argreg
, regval
);
1890 /* This is a floating point value that fits entirely
1891 in a single register. */
1892 CORE_ADDR regval
= extract_address (val
, len
);
1893 write_register (float_argreg
++, regval
);
1896 write_register (argreg
, regval
);
1897 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1903 /* Copy the argument to general registers or the stack in
1904 register-sized pieces. Large arguments are split between
1905 registers and stack. */
1906 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1907 are treated specially: Irix cc passes them in registers
1908 where gcc sometimes puts them on the stack. For maximum
1909 compatibility, we will put them in both places. */
1911 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1912 (len
% MIPS_REGSIZE
!= 0));
1915 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1917 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1919 /* Write this portion of the argument to the stack. */
1920 /* Should shorter than int integer values be
1921 promoted to int before being stored? */
1923 int longword_offset
= 0;
1924 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1925 if (STACK_ARGSIZE
== 8 &&
1926 (typecode
== TYPE_CODE_INT
||
1927 typecode
== TYPE_CODE_PTR
||
1928 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1929 longword_offset
= STACK_ARGSIZE
- len
;
1930 else if ((typecode
== TYPE_CODE_STRUCT
||
1931 typecode
== TYPE_CODE_UNION
) &&
1932 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1933 longword_offset
= STACK_ARGSIZE
- len
;
1935 write_memory (sp
+ stack_offset
+ longword_offset
,
1939 /* Note!!! This is NOT an else clause.
1940 Odd sized structs may go thru BOTH paths. */
1941 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1943 CORE_ADDR regval
= extract_address (val
, partial_len
);
1945 /* A non-floating-point argument being passed in a
1946 general register. If a struct or union, and if
1947 the remaining length is smaller than the register
1948 size, we have to adjust the register value on
1951 It does not seem to be necessary to do the
1952 same for integral types.
1954 Also don't do this adjustment on EABI targets. */
1957 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1958 partial_len
< MIPS_REGSIZE
&&
1959 (typecode
== TYPE_CODE_STRUCT
||
1960 typecode
== TYPE_CODE_UNION
))
1961 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1964 write_register (argreg
, regval
);
1967 /* If this is the old ABI, prevent subsequent floating
1968 point arguments from being passed in floating point
1971 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1977 /* The offset onto the stack at which we will start
1978 copying parameters (after the registers are used up)
1979 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1980 leaves room for the "home" area for register parameters.
1982 In the new EABI (and the NABI32), the 8 register parameters
1983 do not have "home" stack space reserved for them, so the
1984 stack offset does not get incremented until after
1985 we have used up the 8 parameter registers. */
1987 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
1989 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
1994 /* Set the return address register to point to the entry
1995 point of the program, where a breakpoint lies in wait. */
1996 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1998 /* Return adjusted stack pointer. */
2003 mips_push_register(CORE_ADDR
*sp
, int regno
)
2005 char buffer
[MAX_REGISTER_RAW_SIZE
];
2006 int regsize
= REGISTER_RAW_SIZE (regno
);
2009 read_register_gen (regno
, buffer
);
2010 write_memory (*sp
, buffer
, regsize
);
2013 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2014 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2017 mips_push_dummy_frame()
2020 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2021 xmalloc(sizeof(struct linked_proc_info
));
2022 mips_extra_func_info_t proc_desc
= &link
->info
;
2023 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2024 CORE_ADDR old_sp
= sp
;
2025 link
->next
= linked_proc_desc_table
;
2026 linked_proc_desc_table
= link
;
2028 /* FIXME! are these correct ? */
2029 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2030 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2031 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2032 #define FLOAT_SINGLE_REG_SAVE_MASK \
2033 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2035 * The registers we must save are all those not preserved across
2036 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2037 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2038 * and FP Control/Status registers.
2041 * Dummy frame layout:
2044 * Saved MMHI, MMLO, FPC_CSR
2049 * Saved D18 (i.e. F19, F18)
2051 * Saved D0 (i.e. F1, F0)
2052 * Argument build area and stack arguments written via mips_push_arguments
2056 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2057 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2058 PROC_FRAME_OFFSET(proc_desc
) = 0;
2059 PROC_FRAME_ADJUST(proc_desc
) = 0;
2060 mips_push_register (&sp
, PC_REGNUM
);
2061 mips_push_register (&sp
, HI_REGNUM
);
2062 mips_push_register (&sp
, LO_REGNUM
);
2063 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2065 /* Save general CPU registers */
2066 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2067 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2068 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_REGSIZE
;
2069 for (ireg
= 32; --ireg
>= 0; )
2070 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2071 mips_push_register (&sp
, ireg
);
2073 /* Save floating point registers starting with high order word */
2074 PROC_FREG_MASK(proc_desc
) =
2075 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2076 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2077 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2079 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2080 for (ireg
= 32; --ireg
>= 0; )
2081 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2082 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2084 /* Update the frame pointer for the call dummy and the stack pointer.
2085 Set the procedure's starting and ending addresses to point to the
2086 call dummy address at the entry point. */
2087 write_register (PUSH_FP_REGNUM
, old_sp
);
2088 write_register (SP_REGNUM
, sp
);
2089 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2090 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2091 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2092 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2098 register int regnum
;
2099 struct frame_info
*frame
= get_current_frame ();
2100 CORE_ADDR new_sp
= FRAME_FP (frame
);
2102 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2104 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2105 if (frame
->saved_regs
== NULL
)
2106 mips_find_saved_regs (frame
);
2107 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2109 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2110 && frame
->saved_regs
->regs
[regnum
])
2111 write_register (regnum
,
2112 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
2115 write_register (SP_REGNUM
, new_sp
);
2116 flush_cached_frames ();
2118 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2120 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2122 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2124 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2126 if (&pi_ptr
->info
== proc_desc
)
2131 error ("Can't locate dummy extra frame info\n");
2133 if (prev_ptr
!= NULL
)
2134 prev_ptr
->next
= pi_ptr
->next
;
2136 linked_proc_desc_table
= pi_ptr
->next
;
2140 write_register (HI_REGNUM
,
2141 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2142 write_register (LO_REGNUM
,
2143 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2144 if (mips_fpu
!= MIPS_FPU_NONE
)
2145 write_register (FCRCS_REGNUM
,
2146 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2151 mips_print_register (regnum
, all
)
2154 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2156 /* Get the data in raw format. */
2157 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2159 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2163 /* If an even floating point register, also print as double. */
2164 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2165 && !((regnum
-FP0_REGNUM
) & 1))
2166 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2168 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2170 read_relative_register_raw_bytes (regnum
, dbuffer
);
2171 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2172 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2174 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2175 val_print (builtin_type_double
, dbuffer
, 0,
2176 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2177 printf_filtered ("); ");
2179 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2181 /* The problem with printing numeric register names (r26, etc.) is that
2182 the user can't use them on input. Probably the best solution is to
2183 fix it so that either the numeric or the funky (a2, etc.) names
2184 are accepted on input. */
2185 if (regnum
< MIPS_NUMREGS
)
2186 printf_filtered ("(r%d): ", regnum
);
2188 printf_filtered (": ");
2190 /* If virtual format is floating, print it that way. */
2191 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2192 if (FP_REGISTER_DOUBLE
)
2193 { /* show 8-byte floats as float AND double: */
2194 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2196 printf_filtered (" (float) ");
2197 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
2198 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2199 printf_filtered (", (double) ");
2200 val_print (builtin_type_double
, raw_buffer
, 0,
2201 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2204 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
2205 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2206 /* Else print as integer in hex. */
2208 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2209 'x', 0, gdb_stdout
);
2212 /* Replacement for generic do_registers_info.
2213 Print regs in pretty columns. */
2216 do_fp_register_row (regnum
)
2218 { /* do values for FP (float) regs */
2219 char *raw_buffer
[2];
2221 /* use HI and LO to control the order of combining two flt regs */
2222 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2223 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2224 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2225 int inv1
, inv2
, inv3
;
2227 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2228 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2229 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2231 /* Get the data in raw format. */
2232 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2233 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2234 if (REGISTER_RAW_SIZE(regnum
) == 4)
2236 /* 4-byte registers: we can fit two registers per row. */
2237 /* Also print every pair of 4-byte regs as an 8-byte double. */
2238 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2239 error ("can't read register %d (%s)",
2240 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2242 /* copy the two floats into one double, and unpack both */
2243 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2244 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2245 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2246 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2248 printf_filtered (inv1
? " %-5s: <invalid float>" :
2249 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2250 printf_filtered (inv2
? " %-5s: <invalid float>" :
2251 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2252 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2253 " dbl: %-24.17g\n", doub
);
2254 /* may want to do hex display here (future enhancement) */
2258 { /* eight byte registers: print each one as float AND as double. */
2259 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2261 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2262 flt1
= unpack_double (builtin_type_float
,
2263 &raw_buffer
[HI
][offset
], &inv1
);
2264 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2266 printf_filtered (inv1
? " %-5s: <invalid float>" :
2267 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2268 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2269 " dbl: %-24.17g\n", doub
);
2270 /* may want to do hex display here (future enhancement) */
2276 /* Print a row's worth of GP (int) registers, with name labels above */
2279 do_gp_register_row (regnum
)
2282 /* do values for GP (int) regs */
2283 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2284 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2286 int start_regnum
= regnum
;
2287 int numregs
= NUM_REGS
;
2289 /* start-sanitize-sky */
2290 #ifdef NUM_CORE_REGS
2291 numregs
= NUM_CORE_REGS
;
2293 /* end-sanitize-sky */
2295 /* For GP registers, we print a separate row of names above the vals */
2296 printf_filtered (" ");
2297 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2299 if (*REGISTER_NAME (regnum
) == '\0')
2300 continue; /* unused register */
2301 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2302 break; /* end the row: reached FP register */
2303 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2304 REGISTER_NAME (regnum
));
2307 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2308 start_regnum
); /* print the R0 to R31 names */
2310 regnum
= start_regnum
; /* go back to start of row */
2311 /* now print the values in hex, 4 or 8 to the row */
2312 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2314 if (*REGISTER_NAME (regnum
) == '\0')
2315 continue; /* unused register */
2316 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2317 break; /* end row: reached FP register */
2318 /* OK: get the data in raw format. */
2319 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2320 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2321 /* pad small registers */
2322 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2323 printf_filtered (" ");
2324 /* Now print the register value in hex, endian order. */
2325 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2326 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2327 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2329 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2330 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2331 printf_filtered (" ");
2334 if (col
> 0) /* ie. if we actually printed anything... */
2335 printf_filtered ("\n");
2340 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2343 mips_do_registers_info (regnum
, fpregs
)
2347 if (regnum
!= -1) /* do one specified register */
2349 if (*(REGISTER_NAME (regnum
)) == '\0')
2350 error ("Not a valid register for the current processor type");
2352 mips_print_register (regnum
, 0);
2353 printf_filtered ("\n");
2355 else /* do all (or most) registers */
2358 while (regnum
< NUM_REGS
)
2360 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2361 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2362 regnum
= do_fp_register_row (regnum
); /* FP regs */
2364 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2366 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2367 /* start-sanitize-sky */
2368 #ifdef NUM_CORE_REGS
2369 /* For the sky project, NUM_REGS includes the vector slaves,
2370 which are handled elsewhere */
2371 if (regnum
>= NUM_CORE_REGS
)
2374 /* end-sanitize-sky */
2379 /* Return number of args passed to a frame. described by FIP.
2380 Can return -1, meaning no way to tell. */
2383 mips_frame_num_args (frame
)
2384 struct frame_info
*frame
;
2386 #if 0 /* FIXME Use or lose this! */
2387 struct chain_info_t
*p
;
2389 p
= mips_find_cached_frame (FRAME_FP (frame
));
2391 return p
->the_info
.numargs
;
2396 /* Is this a branch with a delay slot? */
2398 static int is_delayed
PARAMS ((unsigned long));
2405 for (i
= 0; i
< NUMOPCODES
; ++i
)
2406 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2407 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2409 return (i
< NUMOPCODES
2410 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2411 | INSN_COND_BRANCH_DELAY
2412 | INSN_COND_BRANCH_LIKELY
)));
2416 mips_step_skips_delay (pc
)
2419 char buf
[MIPS_INSTLEN
];
2421 /* There is no branch delay slot on MIPS16. */
2422 if (pc_is_mips16 (pc
))
2425 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2426 /* If error reading memory, guess that it is not a delayed branch. */
2428 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2432 /* Skip the PC past function prologue instructions (32-bit version).
2433 This is a helper function for mips_skip_prologue. */
2436 mips32_skip_prologue (pc
, lenient
)
2437 CORE_ADDR pc
; /* starting PC to search from */
2442 int seen_sp_adjust
= 0;
2443 int load_immediate_bytes
= 0;
2445 /* Skip the typical prologue instructions. These are the stack adjustment
2446 instruction and the instructions that save registers on the stack
2447 or in the gcc frame. */
2448 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2450 unsigned long high_word
;
2452 inst
= mips_fetch_instruction (pc
);
2453 high_word
= (inst
>> 16) & 0xffff;
2456 if (lenient
&& is_delayed (inst
))
2460 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2461 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2463 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2464 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2466 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2467 /* start-sanitize-r5900 */
2468 || (inst
& 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */
2469 /* end-sanitize-r5900 */
2470 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2471 && (inst
& 0x001F0000)) /* reg != $zero */
2474 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2476 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2478 continue; /* reg != $zero */
2480 /* move $s8,$sp. With different versions of gas this will be either
2481 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2482 Accept any one of these. */
2483 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2486 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2488 else if (high_word
== 0x3c1c) /* lui $gp,n */
2490 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2492 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2493 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2495 /* The following instructions load $at or $t0 with an immediate
2496 value in preparation for a stack adjustment via
2497 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2498 a local variable, so we accept them only before a stack adjustment
2499 instruction was seen. */
2500 else if (!seen_sp_adjust
)
2502 if (high_word
== 0x3c01 || /* lui $at,n */
2503 high_word
== 0x3c08) /* lui $t0,n */
2505 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2508 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2509 high_word
== 0x3508 || /* ori $t0,$t0,n */
2510 high_word
== 0x3401 || /* ori $at,$zero,n */
2511 high_word
== 0x3408) /* ori $t0,$zero,n */
2513 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2523 /* In a frameless function, we might have incorrectly
2524 skipped some load immediate instructions. Undo the skipping
2525 if the load immediate was not followed by a stack adjustment. */
2526 if (load_immediate_bytes
&& !seen_sp_adjust
)
2527 pc
-= load_immediate_bytes
;
2531 /* Skip the PC past function prologue instructions (16-bit version).
2532 This is a helper function for mips_skip_prologue. */
2535 mips16_skip_prologue (pc
, lenient
)
2536 CORE_ADDR pc
; /* starting PC to search from */
2540 int extend_bytes
= 0;
2541 int prev_extend_bytes
;
2543 /* Table of instructions likely to be found in a function prologue. */
2546 unsigned short inst
;
2547 unsigned short mask
;
2550 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2551 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2552 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2553 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2554 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2555 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2556 { 0x673d, 0xffff }, /* move $s1,sp */
2557 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2558 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2559 { 0xe809, 0xf81f }, /* entry pseudo-op */
2560 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2561 { 0, 0 } /* end of table marker */
2564 /* Skip the typical prologue instructions. These are the stack adjustment
2565 instruction and the instructions that save registers on the stack
2566 or in the gcc frame. */
2567 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2569 unsigned short inst
;
2572 inst
= mips_fetch_instruction (pc
);
2574 /* Normally we ignore an extend instruction. However, if it is
2575 not followed by a valid prologue instruction, we must adjust
2576 the pc back over the extend so that it won't be considered
2577 part of the prologue. */
2578 if ((inst
& 0xf800) == 0xf000) /* extend */
2580 extend_bytes
= MIPS16_INSTLEN
;
2583 prev_extend_bytes
= extend_bytes
;
2586 /* Check for other valid prologue instructions besides extend. */
2587 for (i
= 0; table
[i
].mask
!= 0; i
++)
2588 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2590 if (table
[i
].mask
!= 0) /* it was in table? */
2591 continue; /* ignore it */
2592 else /* non-prologue */
2594 /* Return the current pc, adjusted backwards by 2 if
2595 the previous instruction was an extend. */
2596 return pc
- prev_extend_bytes
;
2602 /* To skip prologues, I use this predicate. Returns either PC itself
2603 if the code at PC does not look like a function prologue; otherwise
2604 returns an address that (if we're lucky) follows the prologue. If
2605 LENIENT, then we must skip everything which is involved in setting
2606 up the frame (it's OK to skip more, just so long as we don't skip
2607 anything which might clobber the registers which are being saved.
2608 We must skip more in the case where part of the prologue is in the
2609 delay slot of a non-prologue instruction). */
2612 mips_skip_prologue (pc
, lenient
)
2616 /* See if we can determine the end of the prologue via the symbol table.
2617 If so, then return either PC, or the PC after the prologue, whichever
2620 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2622 if (post_prologue_pc
!= 0)
2623 return max (pc
, post_prologue_pc
);
2625 /* Can't determine prologue from the symbol table, need to examine
2628 if (pc_is_mips16 (pc
))
2629 return mips16_skip_prologue (pc
, lenient
);
2631 return mips32_skip_prologue (pc
, lenient
);
2635 /* The lenient prologue stuff should be superseded by the code in
2636 init_extra_frame_info which looks to see whether the stores mentioned
2637 in the proc_desc have actually taken place. */
2639 /* Is address PC in the prologue (loosely defined) for function at
2643 mips_in_lenient_prologue (startaddr
, pc
)
2644 CORE_ADDR startaddr
;
2647 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2648 return pc
>= startaddr
&& pc
< end_prologue
;
2652 /* Given a return value in `regbuf' with a type `valtype',
2653 extract and copy its value into `valbuf'. */
2655 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2656 struct type
*valtype
;
2657 char regbuf
[REGISTER_BYTES
];
2662 int len
= TYPE_LENGTH (valtype
);
2665 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2666 && (mips_fpu
== MIPS_FPU_DOUBLE
2667 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2668 regnum
= FP0_REGNUM
;
2670 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2671 { /* "un-left-justify" the value from the register */
2672 if (len
< REGISTER_RAW_SIZE (regnum
))
2673 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2674 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2675 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2676 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2677 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2678 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2680 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2681 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2684 /* Given a return value in `regbuf' with a type `valtype',
2685 write it's value into the appropriate register. */
2687 mips_store_return_value (valtype
, valbuf
)
2688 struct type
*valtype
;
2693 int len
= TYPE_LENGTH (valtype
);
2694 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2697 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2698 && (mips_fpu
== MIPS_FPU_DOUBLE
2699 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2700 regnum
= FP0_REGNUM
;
2702 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2703 { /* "left-justify" the value in the register */
2704 if (len
< REGISTER_RAW_SIZE (regnum
))
2705 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2706 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2707 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2708 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2709 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2710 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2712 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2713 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2714 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2715 len
> REGISTER_RAW_SIZE (regnum
) ?
2716 len
: REGISTER_RAW_SIZE (regnum
));
2719 /* Exported procedure: Is PC in the signal trampoline code */
2722 in_sigtramp (pc
, ignore
)
2724 char *ignore
; /* function name */
2726 if (sigtramp_address
== 0)
2728 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2731 /* Command to set FPU type. mips_fpu_string will have been set to the
2732 user's argument. Set mips_fpu based on mips_fpu_string, and then
2733 canonicalize mips_fpu_string. */
2737 mips_set_fpu_command (args
, from_tty
, c
)
2740 struct cmd_list_element
*c
;
2744 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2745 mips_fpu
= MIPS_FPU_DOUBLE
;
2746 else if (strcasecmp (mips_fpu_string
, "double") == 0
2747 || strcasecmp (mips_fpu_string
, "on") == 0
2748 || strcasecmp (mips_fpu_string
, "1") == 0
2749 || strcasecmp (mips_fpu_string
, "yes") == 0)
2750 mips_fpu
= MIPS_FPU_DOUBLE
;
2751 else if (strcasecmp (mips_fpu_string
, "none") == 0
2752 || strcasecmp (mips_fpu_string
, "off") == 0
2753 || strcasecmp (mips_fpu_string
, "0") == 0
2754 || strcasecmp (mips_fpu_string
, "no") == 0)
2755 mips_fpu
= MIPS_FPU_NONE
;
2756 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2757 mips_fpu
= MIPS_FPU_SINGLE
;
2759 err
= strsave (mips_fpu_string
);
2761 if (mips_fpu_string
!= NULL
)
2762 free (mips_fpu_string
);
2766 case MIPS_FPU_DOUBLE
:
2767 mips_fpu_string
= strsave ("double");
2769 case MIPS_FPU_SINGLE
:
2770 mips_fpu_string
= strsave ("single");
2773 mips_fpu_string
= strsave ("none");
2779 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2780 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2782 do_cleanups (cleanups
);
2787 mips_show_fpu_command (args
, from_tty
, c
)
2790 struct cmd_list_element
*c
;
2794 /* Command to set the processor type. */
2797 mips_set_processor_type_command (args
, from_tty
)
2803 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2805 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2806 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2807 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2809 /* Restore the value. */
2810 tmp_mips_processor_type
= strsave (mips_processor_type
);
2815 if (!mips_set_processor_type (tmp_mips_processor_type
))
2817 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2818 /* Restore its value. */
2819 tmp_mips_processor_type
= strsave (mips_processor_type
);
2824 mips_show_processor_type_command (args
, from_tty
)
2830 /* Modify the actual processor type. */
2833 mips_set_processor_type (str
)
2841 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2843 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2845 mips_processor_type
= str
;
2847 for (j
= 0; j
< NUM_REGS
; ++j
)
2848 /* FIXME - MIPS should be defining REGISTER_NAME() instead */
2849 gdb_register_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2853 /* FIXME tweak fpu flag too */
2860 /* Attempt to identify the particular processor model by reading the
2864 mips_read_processor_type ()
2868 prid
= read_register (PRID_REGNUM
);
2870 if ((prid
& ~0xf) == 0x700)
2871 return savestring ("r3041", strlen("r3041"));
2876 /* Just like reinit_frame_cache, but with the right arguments to be
2877 callable as an sfunc. */
2880 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2883 struct cmd_list_element
*c
;
2885 reinit_frame_cache ();
2889 gdb_print_insn_mips (memaddr
, info
)
2891 disassemble_info
*info
;
2893 mips_extra_func_info_t proc_desc
;
2895 /* Search for the function containing this address. Set the low bit
2896 of the address when searching, in case we were given an even address
2897 that is the start of a 16-bit function. If we didn't do this,
2898 the search would fail because the symbol table says the function
2899 starts at an odd address, i.e. 1 byte past the given address. */
2900 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2901 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2903 /* Make an attempt to determine if this is a 16-bit function. If
2904 the procedure descriptor exists and the address therein is odd,
2905 it's definitely a 16-bit function. Otherwise, we have to just
2906 guess that if the address passed in is odd, it's 16-bits. */
2908 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2910 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2912 /* Round down the instruction address to the appropriate boundary. */
2913 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2915 /* Call the appropriate disassembler based on the target endian-ness. */
2916 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2917 return print_insn_big_mips (memaddr
, info
);
2919 return print_insn_little_mips (memaddr
, info
);
2922 /* Old-style breakpoint macros.
2923 The IDT board uses an unusual breakpoint value, and sometimes gets
2924 confused when it sees the usual MIPS breakpoint instruction. */
2926 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
2927 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
2928 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
2929 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
2930 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
2931 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
2932 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
2933 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
2935 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2936 counter value to determine whether a 16- or 32-bit breakpoint should be
2937 used. It returns a pointer to a string of bytes that encode a breakpoint
2938 instruction, stores the length of the string to *lenptr, and adjusts pc
2939 (if necessary) to point to the actual memory location where the
2940 breakpoint should be inserted. */
2942 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2946 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2948 if (pc_is_mips16 (*pcptr
))
2950 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2951 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2952 *lenptr
= sizeof(mips16_big_breakpoint
);
2953 return mips16_big_breakpoint
;
2957 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2958 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2959 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2961 *lenptr
= sizeof(big_breakpoint
);
2963 if (strcmp (target_shortname
, "mips") == 0)
2964 return idt_big_breakpoint
;
2965 else if (strcmp (target_shortname
, "ddb") == 0
2966 || strcmp (target_shortname
, "pmon") == 0
2967 || strcmp (target_shortname
, "lsi") == 0)
2968 return pmon_big_breakpoint
;
2970 return big_breakpoint
;
2975 if (pc_is_mips16 (*pcptr
))
2977 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2978 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2979 *lenptr
= sizeof(mips16_little_breakpoint
);
2980 return mips16_little_breakpoint
;
2984 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2985 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2986 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2988 *lenptr
= sizeof(little_breakpoint
);
2990 if (strcmp (target_shortname
, "mips") == 0)
2991 return idt_little_breakpoint
;
2992 else if (strcmp (target_shortname
, "ddb") == 0
2993 || strcmp (target_shortname
, "pmon") == 0
2994 || strcmp (target_shortname
, "lsi") == 0)
2995 return pmon_little_breakpoint
;
2997 return little_breakpoint
;
3002 /* If PC is in a mips16 call or return stub, return the address of the target
3003 PC, which is either the callee or the caller. There are several
3004 cases which must be handled:
3006 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3007 target PC is in $31 ($ra).
3008 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3009 and the target PC is in $2.
3010 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3011 before the jal instruction, this is effectively a call stub
3012 and the the target PC is in $2. Otherwise this is effectively
3013 a return stub and the target PC is in $18.
3015 See the source code for the stubs in gcc/config/mips/mips16.S for
3018 This function implements the SKIP_TRAMPOLINE_CODE macro.
3026 CORE_ADDR start_addr
;
3028 /* Find the starting address and name of the function containing the PC. */
3029 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3032 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3033 target PC is in $31 ($ra). */
3034 if (strcmp (name
, "__mips16_ret_sf") == 0
3035 || strcmp (name
, "__mips16_ret_df") == 0)
3036 return read_register (RA_REGNUM
);
3038 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3040 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3041 and the target PC is in $2. */
3042 if (name
[19] >= '0' && name
[19] <= '9')
3043 return read_register (2);
3045 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3046 before the jal instruction, this is effectively a call stub
3047 and the the target PC is in $2. Otherwise this is effectively
3048 a return stub and the target PC is in $18. */
3049 else if (name
[19] == 's' || name
[19] == 'd')
3051 if (pc
== start_addr
)
3053 /* Check if the target of the stub is a compiler-generated
3054 stub. Such a stub for a function bar might have a name
3055 like __fn_stub_bar, and might look like this:
3060 la $1,bar (becomes a lui/addiu pair)
3062 So scan down to the lui/addi and extract the target
3063 address from those two instructions. */
3065 CORE_ADDR target_pc
= read_register (2);
3069 /* See if the name of the target function is __fn_stub_*. */
3070 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3072 if (strncmp (name
, "__fn_stub_", 10) != 0
3073 && strcmp (name
, "etext") != 0
3074 && strcmp (name
, "_etext") != 0)
3077 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3078 The limit on the search is arbitrarily set to 20
3079 instructions. FIXME. */
3080 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3082 inst
= mips_fetch_instruction (target_pc
);
3083 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3084 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3085 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3086 return pc
| (inst
& 0xffff); /* low word */
3089 /* Couldn't find the lui/addui pair, so return stub address. */
3093 /* This is the 'return' part of a call stub. The return
3094 address is in $r18. */
3095 return read_register (18);
3098 return 0; /* not a stub */
3102 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3103 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3106 mips_in_call_stub (pc
, name
)
3110 CORE_ADDR start_addr
;
3112 /* Find the starting address of the function containing the PC. If the
3113 caller didn't give us a name, look it up at the same time. */
3114 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3117 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3119 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3120 if (name
[19] >= '0' && name
[19] <= '9')
3122 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3123 before the jal instruction, this is effectively a call stub. */
3124 else if (name
[19] == 's' || name
[19] == 'd')
3125 return pc
== start_addr
;
3128 return 0; /* not a stub */
3132 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3133 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3136 mips_in_return_stub (pc
, name
)
3140 CORE_ADDR start_addr
;
3142 /* Find the starting address of the function containing the PC. */
3143 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3146 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3147 if (strcmp (name
, "__mips16_ret_sf") == 0
3148 || strcmp (name
, "__mips16_ret_df") == 0)
3151 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3152 i.e. after the jal instruction, this is effectively a return stub. */
3153 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3154 && (name
[19] == 's' || name
[19] == 'd')
3155 && pc
!= start_addr
)
3158 return 0; /* not a stub */
3162 /* Return non-zero if the PC is in a library helper function that should
3163 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3166 mips_ignore_helper (pc
)
3171 /* Find the starting address and name of the function containing the PC. */
3172 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3175 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3176 that we want to ignore. */
3177 return (strcmp (name
, "__mips16_ret_sf") == 0
3178 || strcmp (name
, "__mips16_ret_df") == 0);
3182 /* Return a location where we can set a breakpoint that will be hit
3183 when an inferior function call returns. This is normally the
3184 program's entry point. Executables that don't have an entry
3185 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3186 whose address is the location where the breakpoint should be placed. */
3189 mips_call_dummy_address ()
3191 struct minimal_symbol
*sym
;
3193 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3195 return SYMBOL_VALUE_ADDRESS (sym
);
3197 return entry_point_address ();
3201 _initialize_mips_tdep ()
3203 struct cmd_list_element
*c
;
3205 if (!tm_print_insn
) /* Someone may have already set it */
3206 tm_print_insn
= gdb_print_insn_mips
;
3208 /* Let the user turn off floating point and set the fence post for
3209 heuristic_proc_start. */
3211 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
3212 (char *) &mips_fpu_string
,
3213 "Set use of floating point coprocessor.\n\
3214 Set to `none' to avoid using floating point instructions when calling\n\
3215 functions or dealing with return values. Set to `single' to use only\n\
3216 single precision floating point as on the R4650. Set to `double' for\n\
3217 normal floating point support.",
3219 c
->function
.sfunc
= mips_set_fpu_command
;
3220 c
= add_show_from_set (c
, &showlist
);
3221 c
->function
.sfunc
= mips_show_fpu_command
;
3223 #ifndef MIPS_DEFAULT_FPU_TYPE
3224 mips_fpu
= MIPS_FPU_DOUBLE
;
3225 mips_fpu_string
= strsave ("double");
3227 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
3230 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
3231 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
3232 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
3236 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3237 (char *) &tmp_mips_processor_type
,
3238 "Set the type of MIPS processor in use.\n\
3239 Set this to be able to access processor-type-specific registers.\n\
3242 c
->function
.cfunc
= mips_set_processor_type_command
;
3243 c
= add_show_from_set (c
, &showlist
);
3244 c
->function
.cfunc
= mips_show_processor_type_command
;
3246 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3247 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3249 /* We really would like to have both "0" and "unlimited" work, but
3250 command.c doesn't deal with that. So make it a var_zinteger
3251 because the user can always use "999999" or some such for unlimited. */
3252 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3253 (char *) &heuristic_fence_post
,
3255 Set the distance searched for the start of a function.\n\
3256 If you are debugging a stripped executable, GDB needs to search through the\n\
3257 program for the start of a function. This command sets the distance of the\n\
3258 search. The only need to set it is when debugging a stripped executable.",
3260 /* We need to throw away the frame cache when we set this, since it
3261 might change our ability to get backtraces. */
3262 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3263 add_show_from_set (c
, &showlist
);
3265 /* Allow the user to control whether the upper bits of 64-bit
3266 addresses should be zeroed. */
3268 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3269 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3270 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3271 Without an argument, zeroing of upper address bits is enabled.", &setlist
),