1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
42 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
45 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
48 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
50 static void mips_print_register
PARAMS ((int, int));
52 static mips_extra_func_info_t
53 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
55 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
57 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
59 static void mips_set_fpu_command
PARAMS ((char *, int,
60 struct cmd_list_element
*));
62 static void mips_show_fpu_command
PARAMS ((char *, int,
63 struct cmd_list_element
*));
65 void mips_set_processor_type_command
PARAMS ((char *, int));
67 int mips_set_processor_type
PARAMS ((char *));
69 static void mips_show_processor_type_command
PARAMS ((char *, int));
71 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
72 struct cmd_list_element
*));
74 static mips_extra_func_info_t
75 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
77 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
78 mips_extra_func_info_t proc_desc
));
80 /* This value is the model of MIPS in use. It is derived from the value
81 of the PrID register. */
83 char *mips_processor_type
;
85 char *tmp_mips_processor_type
;
87 /* Some MIPS boards don't support floating point, so we permit the
88 user to turn it off. */
90 enum mips_fpu_type mips_fpu
;
92 static char *mips_fpu_string
;
94 /* A set of original names, to be used when restoring back to generic
95 registers from a specific set. */
97 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
99 /* Names of IDT R3041 registers. */
101 char *mips_r3041_reg_names
[] = {
102 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
103 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
104 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
105 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
106 "sr", "lo", "hi", "bad", "cause","pc",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
111 "fsr", "fir", "fp", "",
112 "", "", "bus", "ccfg", "", "", "", "",
113 "", "", "port", "cmp", "", "", "epc", "prid",
116 /* Names of IDT R3051 registers. */
118 char *mips_r3051_reg_names
[] = {
119 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
120 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
121 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
122 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
123 "sr", "lo", "hi", "bad", "cause","pc",
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
125 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
126 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
127 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
128 "fsr", "fir", "fp", "",
129 "inx", "rand", "elo", "", "ctxt", "", "", "",
130 "", "", "ehi", "", "", "", "epc", "prid",
133 /* Names of IDT R3081 registers. */
135 char *mips_r3081_reg_names
[] = {
136 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
137 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
138 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
139 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
140 "sr", "lo", "hi", "bad", "cause","pc",
141 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
143 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
144 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
145 "fsr", "fir", "fp", "",
146 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
147 "", "", "ehi", "", "", "", "epc", "prid",
150 /* Names of LSI 33k registers. */
152 char *mips_lsi33k_reg_names
[] = {
153 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
154 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
155 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
156 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
157 "epc", "hi", "lo", "sr", "cause","badvaddr",
158 "dcic", "bpc", "bda", "", "", "", "", "",
159 "", "", "", "", "", "", "", "",
160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "",
163 "", "", "", "", "", "", "", "",
164 "", "", "", "", "", "", "", "",
170 } mips_processor_type_table
[] = {
171 { "generic", mips_generic_reg_names
},
172 { "r3041", mips_r3041_reg_names
},
173 { "r3051", mips_r3051_reg_names
},
174 { "r3071", mips_r3081_reg_names
},
175 { "r3081", mips_r3081_reg_names
},
176 { "lsi33k", mips_lsi33k_reg_names
},
180 /* Table to translate MIPS16 register field to actual register number. */
181 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
183 /* Heuristic_proc_start may hunt through the text section for a long
184 time across a 2400 baud serial line. Allows the user to limit this
187 static unsigned int heuristic_fence_post
= 0;
189 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
190 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
191 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
192 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
193 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
194 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
195 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
196 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
197 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
198 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
199 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
200 #define _PROC_MAGIC_ 0x0F0F0F0F
201 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
202 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
204 struct linked_proc_info
206 struct mips_extra_func_info info
;
207 struct linked_proc_info
*next
;
208 } *linked_proc_desc_table
= NULL
;
211 /* Should the upper word of 64-bit addresses be zeroed? */
212 static int mask_address_p
= 1;
214 /* Should call_function allocate stack space for a struct return? */
216 mips_use_struct_convention (gcc_p
, type
)
221 return (TYPE_LENGTH (type
) > 2 * MIPS_REGSIZE
);
223 return 1; /* Structures are returned by ref in extra arg0 */
226 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
229 pc_is_mips16 (bfd_vma memaddr
)
231 struct minimal_symbol
*sym
;
233 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
234 if (IS_MIPS16_ADDR (memaddr
))
237 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
238 the high bit of the info field. Use this to decide if the function is
239 MIPS16 or normal MIPS. */
240 sym
= lookup_minimal_symbol_by_pc (memaddr
);
242 return MSYMBOL_IS_SPECIAL (sym
);
248 /* This returns the PC of the first inst after the prologue. If we can't
249 find the prologue, then return 0. */
252 after_prologue (pc
, proc_desc
)
254 mips_extra_func_info_t proc_desc
;
256 struct symtab_and_line sal
;
257 CORE_ADDR func_addr
, func_end
;
260 proc_desc
= find_proc_desc (pc
, NULL
);
264 /* If function is frameless, then we need to do it the hard way. I
265 strongly suspect that frameless always means prologueless... */
266 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
267 && PROC_FRAME_OFFSET (proc_desc
) == 0)
271 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
272 return 0; /* Unknown */
274 sal
= find_pc_line (func_addr
, 0);
276 if (sal
.end
< func_end
)
279 /* The line after the prologue is after the end of the function. In this
280 case, tell the caller to find the prologue the hard way. */
285 /* Decode a MIPS32 instruction that saves a register in the stack, and
286 set the appropriate bit in the general register mask or float register mask
287 to indicate which register is saved. This is a helper function
288 for mips_find_saved_regs. */
291 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
293 unsigned long *gen_mask
;
294 unsigned long *float_mask
;
298 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
299 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
300 /* start-sanitize-r5900 */
301 || (inst
& 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */
302 /* end-sanitize-r5900 */
303 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
305 /* It might be possible to use the instruction to
306 find the offset, rather than the code below which
307 is based on things being in a certain order in the
308 frame, but figuring out what the instruction's offset
309 is relative to might be a little tricky. */
310 reg
= (inst
& 0x001f0000) >> 16;
311 *gen_mask
|= (1 << reg
);
313 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
314 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
315 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
318 reg
= ((inst
& 0x001f0000) >> 16);
319 *float_mask
|= (1 << reg
);
323 /* Decode a MIPS16 instruction that saves a register in the stack, and
324 set the appropriate bit in the general register or float register mask
325 to indicate which register is saved. This is a helper function
326 for mips_find_saved_regs. */
329 mips16_decode_reg_save (inst
, gen_mask
)
331 unsigned long *gen_mask
;
333 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
335 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
336 *gen_mask
|= (1 << reg
);
338 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
340 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
341 *gen_mask
|= (1 << reg
);
343 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
344 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
345 *gen_mask
|= (1 << RA_REGNUM
);
349 /* Fetch and return instruction from the specified location. If the PC
350 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
353 mips_fetch_instruction (addr
)
356 char buf
[MIPS_INSTLEN
];
360 if (pc_is_mips16 (addr
))
362 instlen
= MIPS16_INSTLEN
;
363 addr
= UNMAKE_MIPS16_ADDR (addr
);
366 instlen
= MIPS_INSTLEN
;
367 status
= read_memory_nobpt (addr
, buf
, instlen
);
369 memory_error (status
, addr
);
370 return extract_unsigned_integer (buf
, instlen
);
374 /* These the fields of 32 bit mips instructions */
375 #define mips32_op(x) (x >> 25)
376 #define itype_op(x) (x >> 25)
377 #define itype_rs(x) ((x >> 21)& 0x1f)
378 #define itype_rt(x) ((x >> 16) & 0x1f)
379 #define itype_immediate(x) ( x & 0xffff)
381 #define jtype_op(x) (x >> 25)
382 #define jtype_target(x) ( x & 0x03fffff)
384 #define rtype_op(x) (x >>25)
385 #define rtype_rs(x) ((x>>21) & 0x1f)
386 #define rtype_rt(x) ((x>>16) & 0x1f)
387 #define rtype_rd(x) ((x>>11) & 0x1f)
388 #define rtype_shamt(x) ((x>>6) & 0x1f)
389 #define rtype_funct(x) (x & 0x3f )
392 mips32_relative_offset(unsigned long inst
)
394 x
= itype_immediate(inst
) ;
395 if (x
& 0x8000) /* sign bit set */
397 x
|= 0xffff0000 ; /* sign extension */
403 /* Determine whate to set a single step breakpoint while considering
406 mips32_next_pc(CORE_ADDR pc
)
410 inst
= mips_fetch_instruction(pc
) ;
411 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
412 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
413 { op
= ((inst
>> 25) & 0x03) ;
416 case 0 : goto equal_branch
; /* BEQL */
417 case 1 : goto neq_branch
; /* BNEZ */
418 case 2 : goto less_branch
; /* BLEZ */
419 case 3 : goto greater_branch
; /* BGTZ */
423 else pc
+= 4 ; /* Not a branch, next instruction is easy */
426 { /* This gets way messy */
428 /* Further subdivide into SPECIAL, REGIMM and other */
429 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
431 case 0 : /* SPECIAL */
432 op
= rtype_funct(inst
) ;
437 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
442 break ; /* end special */
443 case 1 : /* REGIMM */
445 op
= jtype_op(inst
) ; /* branch condition */
446 switch (jtype_op(inst
))
450 case 16 : /* BLTZALL */
451 case 18 : /* BLTZALL */
453 if (read_register(itype_rs(inst
)) < 0)
454 pc
+= mips32_relative_offset(inst
) + 4 ;
455 else pc
+= 8 ; /* after the delay slot */
459 case 17 : /* BGEZAL */
460 case 19 : /* BGEZALL */
461 greater_equal_branch
:
462 if (read_register(itype_rs(inst
)) >= 0)
463 pc
+= mips32_relative_offset(inst
) + 4 ;
464 else pc
+= 8 ; /* after the delay slot */
466 /* All of the other intructions in the REGIMM catagory */
470 break ; /* end REGIMM */
473 { unsigned long reg
;
474 reg
= jtype_target(inst
) << 2 ;
475 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
476 /* Whats this mysterious 0xf000000 adjustment ??? */
479 /* FIXME case JALX :*/
480 { unsigned long reg
;
481 reg
= jtype_target(inst
) << 2 ;
482 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
483 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
485 break ; /* The new PC will be alternate mode */
486 case 4 : /* BEQ , BEQL */
488 if (read_register(itype_rs(inst
)) ==
489 read_register(itype_rt(inst
)))
490 pc
+= mips32_relative_offset(inst
) + 4 ;
493 case 5 : /* BNE , BNEL */
495 if (read_register(itype_rs(inst
)) !=
496 read_register(itype_rs(inst
)))
497 pc
+= mips32_relative_offset(inst
) + 4 ;
500 case 6 : /* BLEZ , BLEZL */
502 if (read_register(itype_rs(inst
) <= 0))
503 pc
+= mips32_relative_offset(inst
) + 4 ;
507 greater_branch
: /* BGTZ BGTZL */
508 if (read_register(itype_rs(inst
) > 0))
509 pc
+= mips32_relative_offset(inst
) + 4 ;
516 } /* mips32_next_pc */
518 /* Decoding the next place to set a breakpoint is irregular for the
519 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
520 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
521 We dont want to set a single step instruction on the extend instruction
525 /* Lots of mips16 instruction formats */
526 /* Predicting jumps requires itype,ritype,i8type
527 and their extensions extItype,extritype,extI8type
529 enum mips16_inst_fmts
531 itype
, /* 0 immediate 5,10 */
532 ritype
, /* 1 5,3,8 */
533 rrtype
, /* 2 5,3,3,5 */
534 rritype
, /* 3 5,3,3,5 */
535 rrrtype
, /* 4 5,3,3,3,2 */
536 rriatype
, /* 5 5,3,3,1,4 */
537 shifttype
, /* 6 5,3,3,3,2 */
538 i8type
, /* 7 5,3,8 */
539 i8movtype
, /* 8 5,3,3,5 */
540 i8mov32rtype
, /* 9 5,3,5,3 */
541 i64type
, /* 10 5,3,8 */
542 ri64type
, /* 11 5,3,3,5 */
543 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
544 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
545 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
546 extRRItype
, /* 15 5,5,5,5,3,3,5 */
547 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
548 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
549 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
550 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
551 extRi64type
, /* 20 5,6,5,5,3,3,5 */
552 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
554 /* I am heaping all the fields of the formats into one structure and then,
555 only the fields which are involved in instruction extension */
558 unsigned short inst
;
559 enum mips16_inst_fmts fmt
;
560 unsigned long offset
;
561 unsigned int regx
; /* Function in i8 type */
567 static void print_unpack(char * comment
,
568 struct upk_mips16
* u
)
570 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
571 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
574 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
575 format for the bits which make up the immediatate extension.
578 extended_offset(unsigned long extension
)
580 unsigned long value
;
581 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
583 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
585 value
|= extension
& 0x01f ; /* extract 4:0 */
589 /* Only call this function if you know that this is an extendable
590 instruction, It wont malfunction, but why make excess remote memory references?
591 If the immediate operands get sign extended or somthing, do it after
592 the extension is performed.
594 /* FIXME: Every one of these cases needs to worry about sign extension
595 when the offset is to be used in relative addressing */
598 static unsigned short fetch_mips_16(CORE_ADDR pc
)
601 pc
&= 0xfffffffe ; /* clear the low order bit */
602 target_read_memory(pc
,buf
,2) ;
603 return extract_unsigned_integer(buf
,2) ;
607 unpack_mips16(CORE_ADDR pc
,
608 struct upk_mips16
* upk
)
611 unsigned long extension
;
613 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
614 /* Decrement to previous address and loose the 16bit mode flag */
615 /* return if the instruction was extendable, but not actually extended */
616 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
617 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
622 unsigned long value
;
624 { value
= extended_offset(extension
) ;
625 value
= value
<< 11 ; /* rom for the original value */
626 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
629 { value
= upk
->inst
& 0x7ff ;
630 /* FIXME : Consider sign extension */
632 upk
->offset
= value
;
637 { /* A register identifier and an offset */
638 /* Most of the fields are the same as I type but the
639 immediate value is of a different length */
640 unsigned long value
;
643 value
= extended_offset(extension
) ;
644 value
= value
<< 8 ; /* from the original instruction */
645 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
646 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
647 if (value
& 0x4000) /* test the sign bit , bit 26 */
648 { value
&= ~ 0x3fff ; /* remove the sign bit */
653 value
= upk
->inst
& 0xff ; /* 8 bits */
654 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
655 /* FIXME: Do sign extension , this format needs it */
656 if (value
& 0x80) /* THIS CONFUSES ME */
657 { value
&= 0xef ; /* remove the sign bit */
662 upk
->offset
= value
;
667 unsigned long value
;
668 unsigned short nexthalf
;
669 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
670 value
= value
<< 16 ;
671 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
673 upk
->offset
= value
;
677 printf_filtered("Decoding unimplemented instruction format type\n") ;
680 /* print_unpack("UPK",upk) ; */
684 #define mips16_op(x) (x >> 11)
686 /* This is a map of the opcodes which ae known to perform branches */
687 static unsigned char map16
[32] =
694 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
696 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
702 static struct upk_mips16 upk
;
704 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
708 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
709 inst
= fetch_mips_16(pc
) ;
711 op
= mips16_op(upk
.inst
) ;
717 case 2 : /* Branch */
719 unpack_mips16(pc
,&upk
) ;
721 offset
= upk
.offset
;
726 pc
+= (offset
<< 1) + 2 ;
729 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
731 unpack_mips16(pc
,&upk
) ;
732 pc
= add_offset_16(pc
,upk
.offset
) ;
733 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
734 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
739 unpack_mips16(pc
,&upk
) ;
740 reg
= read_register(upk
.regx
) ;
742 pc
+= (upk
.offset
<< 1) + 2 ;
747 unpack_mips16(pc
,&upk
) ;
748 reg
= read_register(upk
.regx
) ;
750 pc
+= (upk
.offset
<< 1) + 2 ;
753 case 12 : /* I8 Formats btez btnez */
755 unpack_mips16(pc
,&upk
) ;
756 /* upk.regx contains the opcode */
757 reg
= read_register(24) ; /* Test register is 24 */
758 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
759 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
760 /* pc = add_offset_16(pc,upk.offset) ; */
761 pc
+= (upk
.offset
<< 1) + 2 ;
764 case 29 : /* RR Formats JR, JALR, JALR-RA */
766 op
= upk
.inst
& 0x1f ;
769 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
770 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
773 case 0 : reg
= upk
.regx
; break ;
774 case 1 : reg
= 31 ; break ; /* Function return instruction*/
775 case 2 : reg
= upk
.regx
; break ;
776 default: reg
= 31 ; break ; /* BOGUS Guess */
778 pc
= read_register(reg
) ;
782 case 30 : /* This is an extend instruction */
783 pc
+= 4 ; /* Dont be setting breakpints on the second half */
786 printf("Filtered - next PC probably incorrrect due to jump inst\n");
791 else pc
+= 2 ; /* just a good old instruction */
792 /* See if we CAN actually break on the next instruction */
793 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
795 } /* mips16_next_pc */
797 /* The mips_next_pc function supports single_tep when the remote target monitor or
798 stub is not developed enough to so a single_step.
799 It works by decoding the current instruction and predicting where a branch
800 will go. This isnt hard because all the data is available.
801 The MIPS32 and MIPS16 variants are quite different
803 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
806 /* inst = mips_fetch_instruction(pc) ; */
807 /* if (pc_is_mips16) <----- This is failing */
809 return mips16_next_pc(pc
) ;
810 else return mips32_next_pc(pc
) ;
813 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
817 mips_find_saved_regs (fci
)
818 struct frame_info
*fci
;
821 CORE_ADDR reg_position
;
822 /* r0 bit means kernel trap */
824 /* What registers have been saved? Bitmasks. */
825 unsigned long gen_mask
, float_mask
;
826 mips_extra_func_info_t proc_desc
;
829 frame_saved_regs_zalloc (fci
);
831 /* If it is the frame for sigtramp, the saved registers are located
832 in a sigcontext structure somewhere on the stack.
833 If the stack layout for sigtramp changes we might have to change these
834 constants and the companion fixup_sigtramp in mdebugread.c */
835 #ifndef SIGFRAME_BASE
836 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
837 above the sigtramp frame. */
838 #define SIGFRAME_BASE MIPS_REGSIZE
839 /* FIXME! Are these correct?? */
840 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
841 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
842 #define SIGFRAME_FPREGSAVE_OFF \
843 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
845 #ifndef SIGFRAME_REG_SIZE
846 /* FIXME! Is this correct?? */
847 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
849 if (fci
->signal_handler_caller
)
851 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
853 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
854 + ireg
* SIGFRAME_REG_SIZE
;
855 fci
->saved_regs
[ireg
] = reg_position
;
857 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
859 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
860 + ireg
* SIGFRAME_REG_SIZE
;
861 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
863 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
867 proc_desc
= fci
->proc_desc
;
868 if (proc_desc
== NULL
)
869 /* I'm not sure how/whether this can happen. Normally when we can't
870 find a proc_desc, we "synthesize" one using heuristic_proc_desc
871 and set the saved_regs right away. */
874 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
875 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
876 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
878 if (/* In any frame other than the innermost or a frame interrupted by
879 a signal, we assume that all registers have been saved.
880 This assumes that all register saves in a function happen before
881 the first function call. */
882 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
884 /* In a dummy frame we know exactly where things are saved. */
885 && !PROC_DESC_IS_DUMMY (proc_desc
)
887 /* Don't bother unless we are inside a function prologue. Outside the
888 prologue, we know where everything is. */
890 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
892 /* Not sure exactly what kernel_trap means, but if it means
893 the kernel saves the registers without a prologue doing it,
894 we better not examine the prologue to see whether registers
895 have been saved yet. */
898 /* We need to figure out whether the registers that the proc_desc
899 claims are saved have been saved yet. */
903 /* Bitmasks; set if we have found a save for the register. */
904 unsigned long gen_save_found
= 0;
905 unsigned long float_save_found
= 0;
908 /* If the address is odd, assume this is MIPS16 code. */
909 addr
= PROC_LOW_ADDR (proc_desc
);
910 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
912 /* Scan through this function's instructions preceding the current
913 PC, and look for those that save registers. */
914 while (addr
< fci
->pc
)
916 inst
= mips_fetch_instruction (addr
);
917 if (pc_is_mips16 (addr
))
918 mips16_decode_reg_save (inst
, &gen_save_found
);
920 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
923 gen_mask
= gen_save_found
;
924 float_mask
= float_save_found
;
927 /* Fill in the offsets for the registers which gen_mask says
929 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
930 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
931 if (gen_mask
& 0x80000000)
933 fci
->saved_regs
[ireg
] = reg_position
;
934 reg_position
-= MIPS_REGSIZE
;
935 /* start-sanitize-r5900 */
936 #ifdef R5900_128BIT_GPR_HACK
937 /* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is
938 still 64bits. See the comments in tm.h for a discussion of the
939 various problems this causes. */
940 if (ireg
<= RA_REGNUM
)
941 reg_position
-= MIPS_REGSIZE
;
943 /* end-sanitize-r5900 */
946 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
947 of that normally used by gcc. Therefore, we have to fetch the first
948 instruction of the function, and if it's an entry instruction that
949 saves $s0 or $s1, correct their saved addresses. */
950 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
952 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
953 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
956 int sreg_count
= (inst
>> 6) & 3;
958 /* Check if the ra register was pushed on the stack. */
959 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
961 reg_position
-= MIPS_REGSIZE
;
963 /* Check if the s0 and s1 registers were pushed on the stack. */
964 for (reg
= 16; reg
< sreg_count
+16; reg
++)
966 fci
->saved_regs
[reg
] = reg_position
;
967 reg_position
-= MIPS_REGSIZE
;
972 /* Fill in the offsets for the registers which float_mask says
974 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
976 /* The freg_offset points to where the first *double* register
977 is saved. So skip to the high-order word. */
978 if (! GDB_TARGET_IS_MIPS64
)
979 reg_position
+= MIPS_REGSIZE
;
981 /* Fill in the offsets for the float registers which float_mask says
983 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
984 if (float_mask
& 0x80000000)
986 fci
->saved_regs
[FP0_REGNUM
+ireg
] = reg_position
;
987 reg_position
-= MIPS_REGSIZE
;
990 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
994 read_next_frame_reg(fi
, regno
)
995 struct frame_info
*fi
;
998 for (; fi
; fi
= fi
->next
)
1000 /* We have to get the saved sp from the sigcontext
1001 if it is a signal handler frame. */
1002 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1006 if (fi
->saved_regs
== NULL
)
1007 mips_find_saved_regs (fi
);
1008 if (fi
->saved_regs
[regno
])
1009 return read_memory_integer(fi
->saved_regs
[regno
], MIPS_REGSIZE
);
1012 return read_register (regno
);
1015 /* mips_addr_bits_remove - remove useless address bits */
1018 mips_addr_bits_remove (addr
)
1021 #if GDB_TARGET_IS_MIPS64
1022 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1024 /* This hack is a work-around for existing boards using PMON,
1025 the simulator, and any other 64-bit targets that doesn't have
1026 true 64-bit addressing. On these targets, the upper 32 bits
1027 of addresses are ignored by the hardware. Thus, the PC or SP
1028 are likely to have been sign extended to all 1s by instruction
1029 sequences that load 32-bit addresses. For example, a typical
1030 piece of code that loads an address is this:
1031 lui $r2, <upper 16 bits>
1032 ori $r2, <lower 16 bits>
1033 But the lui sign-extends the value such that the upper 32 bits
1034 may be all 1s. The workaround is simply to mask off these bits.
1035 In the future, gcc may be changed to support true 64-bit
1036 addressing, and this masking will have to be disabled. */
1037 addr
&= (CORE_ADDR
)0xffffffff;
1040 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1041 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1042 So we still have to mask off useless bits from addresses. */
1043 addr
&= (CORE_ADDR
)0xffffffff;
1050 mips_init_frame_pc_first (fromleaf
, prev
)
1052 struct frame_info
*prev
;
1056 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1057 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1058 tmp
= mips_skip_stub (pc
);
1059 prev
->pc
= tmp
? tmp
: pc
;
1064 mips_frame_saved_pc(frame
)
1065 struct frame_info
*frame
;
1068 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1069 /* We have to get the saved pc from the sigcontext
1070 if it is a signal handler frame. */
1071 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1072 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1074 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1075 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
1077 saved_pc
= read_next_frame_reg(frame
, pcreg
);
1079 return ADDR_BITS_REMOVE (saved_pc
);
1082 static struct mips_extra_func_info temp_proc_desc
;
1083 static struct frame_saved_regs temp_saved_regs
;
1085 /* Set a register's saved stack address in temp_saved_regs. If an address
1086 has already been set for this register, do nothing; this way we will
1087 only recognize the first save of a given register in a function prologue.
1088 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1091 set_reg_offset (regno
, offset
)
1095 if (temp_saved_regs
.regs
[regno
] == 0)
1096 temp_saved_regs
.regs
[regno
] = offset
;
1100 /* Test whether the PC points to the return instruction at the
1101 end of a function. */
1104 mips_about_to_return (pc
)
1107 if (pc_is_mips16 (pc
))
1108 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1109 generates a "jr $ra"; other times it generates code to load
1110 the return address from the stack to an accessible register (such
1111 as $a3), then a "jr" using that register. This second case
1112 is almost impossible to distinguish from an indirect jump
1113 used for switch statements, so we don't even try. */
1114 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1116 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1120 /* This fencepost looks highly suspicious to me. Removing it also
1121 seems suspicious as it could affect remote debugging across serial
1125 heuristic_proc_start (pc
)
1133 pc
= ADDR_BITS_REMOVE (pc
);
1135 fence
= start_pc
- heuristic_fence_post
;
1136 if (start_pc
== 0) return 0;
1138 if (heuristic_fence_post
== UINT_MAX
1139 || fence
< VM_MIN_ADDRESS
)
1140 fence
= VM_MIN_ADDRESS
;
1142 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1144 /* search back for previous return */
1145 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1146 if (start_pc
< fence
)
1148 /* It's not clear to me why we reach this point when
1149 stop_soon_quietly, but with this test, at least we
1150 don't print out warnings for every child forked (eg, on
1151 decstation). 22apr93 rich@cygnus.com. */
1152 if (!stop_soon_quietly
)
1154 static int blurb_printed
= 0;
1156 if (fence
== VM_MIN_ADDRESS
)
1157 warning("Hit beginning of text section without finding");
1159 warning("Hit heuristic-fence-post without finding");
1161 warning("enclosing function for address 0x%s", paddr_nz (pc
));
1165 This warning occurs if you are debugging a function without any symbols\n\
1166 (for example, in a stripped executable). In that case, you may wish to\n\
1167 increase the size of the search with the `set heuristic-fence-post' command.\n\
1169 Otherwise, you told GDB there was a function where there isn't one, or\n\
1170 (more likely) you have encountered a bug in GDB.\n");
1177 else if (pc_is_mips16 (start_pc
))
1179 unsigned short inst
;
1181 /* On MIPS16, any one of the following is likely to be the
1182 start of a function:
1186 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1187 inst
= mips_fetch_instruction (start_pc
);
1188 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1189 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1190 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1191 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1193 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1194 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1199 else if (mips_about_to_return (start_pc
))
1201 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1206 /* skip nops (usually 1) 0 - is this */
1207 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1208 start_pc
+= MIPS_INSTLEN
;
1213 /* Fetch the immediate value from a MIPS16 instruction.
1214 If the previous instruction was an EXTEND, use it to extend
1215 the upper bits of the immediate value. This is a helper function
1216 for mips16_heuristic_proc_desc. */
1219 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1220 unsigned short prev_inst
; /* previous instruction */
1221 unsigned short inst
; /* current instruction */
1222 int nbits
; /* number of bits in imm field */
1223 int scale
; /* scale factor to be applied to imm */
1224 int is_signed
; /* is the imm field signed? */
1228 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1230 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1231 if (offset
& 0x8000) /* check for negative extend */
1232 offset
= 0 - (0x10000 - (offset
& 0xffff));
1233 return offset
| (inst
& 0x1f);
1237 int max_imm
= 1 << nbits
;
1238 int mask
= max_imm
- 1;
1239 int sign_bit
= max_imm
>> 1;
1241 offset
= inst
& mask
;
1242 if (is_signed
&& (offset
& sign_bit
))
1243 offset
= 0 - (max_imm
- offset
);
1244 return offset
* scale
;
1249 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1250 stream from start_pc to limit_pc. */
1253 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1254 CORE_ADDR start_pc
, limit_pc
;
1255 struct frame_info
*next_frame
;
1259 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1260 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1261 unsigned inst
= 0; /* current instruction */
1262 unsigned entry_inst
= 0; /* the entry instruction */
1265 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1266 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1268 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1270 /* Save the previous instruction. If it's an EXTEND, we'll extract
1271 the immediate offset extension from it in mips16_get_imm. */
1274 /* Fetch and decode the instruction. */
1275 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1276 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1277 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1279 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1280 if (offset
< 0) /* negative stack adjustment? */
1281 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1283 /* Exit loop if a positive stack adjustment is found, which
1284 usually means that the stack cleanup code in the function
1285 epilogue is reached. */
1288 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1290 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1291 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1292 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1293 set_reg_offset (reg
, sp
+ offset
);
1295 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1297 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1298 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1299 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1300 set_reg_offset (reg
, sp
+ offset
);
1302 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1304 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1305 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1306 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1308 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1310 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1311 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1312 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1314 else if (inst
== 0x673d) /* move $s1, $sp */
1317 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1319 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1321 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1322 frame_addr
= sp
+ offset
;
1323 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1324 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1326 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1328 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1329 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1330 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1331 set_reg_offset (reg
, frame_addr
+ offset
);
1333 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1335 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1336 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1337 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1338 set_reg_offset (reg
, frame_addr
+ offset
);
1340 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1341 entry_inst
= inst
; /* save for later processing */
1342 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1343 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1346 /* The entry instruction is typically the first instruction in a function,
1347 and it stores registers at offsets relative to the value of the old SP
1348 (before the prologue). But the value of the sp parameter to this
1349 function is the new SP (after the prologue has been executed). So we
1350 can't calculate those offsets until we've seen the entire prologue,
1351 and can calculate what the old SP must have been. */
1352 if (entry_inst
!= 0)
1354 int areg_count
= (entry_inst
>> 8) & 7;
1355 int sreg_count
= (entry_inst
>> 6) & 3;
1357 /* The entry instruction always subtracts 32 from the SP. */
1358 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1360 /* Now we can calculate what the SP must have been at the
1361 start of the function prologue. */
1362 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1364 /* Check if a0-a3 were saved in the caller's argument save area. */
1365 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1367 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1368 set_reg_offset (reg
, sp
+ offset
);
1369 offset
+= MIPS_REGSIZE
;
1372 /* Check if the ra register was pushed on the stack. */
1374 if (entry_inst
& 0x20)
1376 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1377 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1378 offset
-= MIPS_REGSIZE
;
1381 /* Check if the s0 and s1 registers were pushed on the stack. */
1382 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1384 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1385 set_reg_offset (reg
, sp
+ offset
);
1386 offset
-= MIPS_REGSIZE
;
1392 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1393 CORE_ADDR start_pc
, limit_pc
;
1394 struct frame_info
*next_frame
;
1398 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1400 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1401 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1402 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1404 unsigned long inst
, high_word
, low_word
;
1407 /* Fetch the instruction. */
1408 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1410 /* Save some code by pre-extracting some useful fields. */
1411 high_word
= (inst
>> 16) & 0xffff;
1412 low_word
= inst
& 0xffff;
1413 reg
= high_word
& 0x1f;
1415 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1416 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1417 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1419 if (low_word
& 0x8000) /* negative stack adjustment? */
1420 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1422 /* Exit loop if a positive stack adjustment is found, which
1423 usually means that the stack cleanup code in the function
1424 epilogue is reached. */
1427 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1429 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1430 set_reg_offset (reg
, sp
+ low_word
);
1432 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1434 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1435 but the register size used is only 32 bits. Make the address
1436 for the saved register point to the lower 32 bits. */
1437 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1438 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1440 /* start-sanitize-r5900 */
1441 else if ((high_word
& 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */
1443 /* I don't think we have to worry about the Irix 6.2 N32 ABI
1444 issue noted int he sd reg, offset($sp) case above. */
1445 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1446 set_reg_offset (reg
, sp
+ low_word
);
1448 /* end-sanitize-r5900 */
1449 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1451 /* Old gcc frame, r30 is virtual frame pointer. */
1452 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1453 frame_addr
= sp
+ low_word
;
1454 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1456 unsigned alloca_adjust
;
1457 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1458 frame_addr
= read_next_frame_reg(next_frame
, 30);
1459 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1460 if (alloca_adjust
> 0)
1462 /* FP > SP + frame_size. This may be because
1463 * of an alloca or somethings similar.
1464 * Fix sp to "pre-alloca" value, and try again.
1466 sp
+= alloca_adjust
;
1471 /* move $30,$sp. With different versions of gas this will be either
1472 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1473 Accept any one of these. */
1474 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1476 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1477 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1479 unsigned alloca_adjust
;
1480 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1481 frame_addr
= read_next_frame_reg(next_frame
, 30);
1482 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1483 if (alloca_adjust
> 0)
1485 /* FP > SP + frame_size. This may be because
1486 * of an alloca or somethings similar.
1487 * Fix sp to "pre-alloca" value, and try again.
1489 sp
+= alloca_adjust
;
1494 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1496 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1497 set_reg_offset (reg
, frame_addr
+ low_word
);
1502 static mips_extra_func_info_t
1503 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1504 CORE_ADDR start_pc
, limit_pc
;
1505 struct frame_info
*next_frame
;
1507 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1509 if (start_pc
== 0) return NULL
;
1510 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1511 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
1512 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1513 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1514 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1516 if (start_pc
+ 200 < limit_pc
)
1517 limit_pc
= start_pc
+ 200;
1518 if (pc_is_mips16 (start_pc
))
1519 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1521 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1522 return &temp_proc_desc
;
1525 static mips_extra_func_info_t
1526 non_heuristic_proc_desc (pc
, addrptr
)
1530 CORE_ADDR startaddr
;
1531 mips_extra_func_info_t proc_desc
;
1532 struct block
*b
= block_for_pc(pc
);
1535 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1537 *addrptr
= startaddr
;
1538 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1542 if (startaddr
> BLOCK_START (b
))
1543 /* This is the "pathological" case referred to in a comment in
1544 print_frame_info. It might be better to move this check into
1548 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1551 /* If we never found a PDR for this function in symbol reading, then
1552 examine prologues to find the information. */
1555 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1556 if (PROC_FRAME_REG (proc_desc
) == -1)
1566 static mips_extra_func_info_t
1567 find_proc_desc (pc
, next_frame
)
1569 struct frame_info
*next_frame
;
1571 mips_extra_func_info_t proc_desc
;
1572 CORE_ADDR startaddr
;
1574 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1578 /* IF this is the topmost frame AND
1579 * (this proc does not have debugging information OR
1580 * the PC is in the procedure prologue)
1581 * THEN create a "heuristic" proc_desc (by analyzing
1582 * the actual code) to replace the "official" proc_desc.
1584 if (next_frame
== NULL
)
1586 struct symtab_and_line val
;
1587 struct symbol
*proc_symbol
=
1588 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1592 val
= find_pc_line (BLOCK_START
1593 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1595 val
.pc
= val
.end
? val
.end
: pc
;
1597 if (!proc_symbol
|| pc
< val
.pc
)
1599 mips_extra_func_info_t found_heuristic
=
1600 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1602 if (found_heuristic
)
1603 proc_desc
= found_heuristic
;
1609 /* Is linked_proc_desc_table really necessary? It only seems to be used
1610 by procedure call dummys. However, the procedures being called ought
1611 to have their own proc_descs, and even if they don't,
1612 heuristic_proc_desc knows how to create them! */
1614 register struct linked_proc_info
*link
;
1616 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1617 if (PROC_LOW_ADDR(&link
->info
) <= pc
1618 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1622 startaddr
= heuristic_proc_start (pc
);
1625 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1631 get_frame_pointer(frame
, proc_desc
)
1632 struct frame_info
*frame
;
1633 mips_extra_func_info_t proc_desc
;
1635 return ADDR_BITS_REMOVE (
1636 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1637 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1640 mips_extra_func_info_t cached_proc_desc
;
1643 mips_frame_chain(frame
)
1644 struct frame_info
*frame
;
1646 mips_extra_func_info_t proc_desc
;
1648 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1650 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1653 /* Check if the PC is inside a call stub. If it is, fetch the
1654 PC of the caller of that stub. */
1655 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1658 /* Look up the procedure descriptor for this PC. */
1659 proc_desc
= find_proc_desc(saved_pc
, frame
);
1663 cached_proc_desc
= proc_desc
;
1665 /* If no frame pointer and frame size is zero, we must be at end
1666 of stack (or otherwise hosed). If we don't check frame size,
1667 we loop forever if we see a zero size frame. */
1668 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1669 && PROC_FRAME_OFFSET (proc_desc
) == 0
1670 /* The previous frame from a sigtramp frame might be frameless
1671 and have frame size zero. */
1672 && !frame
->signal_handler_caller
)
1675 return get_frame_pointer (frame
, proc_desc
);
1679 init_extra_frame_info(fci
)
1680 struct frame_info
*fci
;
1684 /* Use proc_desc calculated in frame_chain */
1685 mips_extra_func_info_t proc_desc
=
1686 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1688 fci
->saved_regs
= NULL
;
1690 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1693 /* Fixup frame-pointer - only needed for top frame */
1694 /* This may not be quite right, if proc has a real frame register.
1695 Get the value of the frame relative sp, procedure might have been
1696 interrupted by a signal at it's very start. */
1697 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1698 && !PROC_DESC_IS_DUMMY (proc_desc
))
1699 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1701 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1703 if (proc_desc
== &temp_proc_desc
)
1707 /* Do not set the saved registers for a sigtramp frame,
1708 mips_find_saved_registers will do that for us.
1709 We can't use fci->signal_handler_caller, it is not yet set. */
1710 find_pc_partial_function (fci
->pc
, &name
,
1711 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1712 if (!IN_SIGTRAMP (fci
->pc
, name
))
1714 fci
->saved_regs
= (CORE_ADDR
*)
1715 frame_obstack_alloc (SIZEOF_FRAME_SAVED_REGS
);
1716 memcpy (fci
->saved_regs
, temp_saved_regs
.regs
, SIZEOF_FRAME_SAVED_REGS
);
1717 fci
->saved_regs
[PC_REGNUM
]
1718 = fci
->saved_regs
[RA_REGNUM
];
1722 /* hack: if argument regs are saved, guess these contain args */
1723 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1724 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1726 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1728 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1735 /* MIPS stack frames are almost impenetrable. When execution stops,
1736 we basically have to look at symbol information for the function
1737 that we stopped in, which tells us *which* register (if any) is
1738 the base of the frame pointer, and what offset from that register
1739 the frame itself is at.
1741 This presents a problem when trying to examine a stack in memory
1742 (that isn't executing at the moment), using the "frame" command. We
1743 don't have a PC, nor do we have any registers except SP.
1745 This routine takes two arguments, SP and PC, and tries to make the
1746 cached frames look as if these two arguments defined a frame on the
1747 cache. This allows the rest of info frame to extract the important
1748 arguments without difficulty. */
1751 setup_arbitrary_frame (argc
, argv
)
1756 error ("MIPS frame specifications require two arguments: sp and pc");
1758 return create_new_frame (argv
[0], argv
[1]);
1762 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1764 * For n32 ABI, eight.
1765 * For all others, he same as the size of a general register.
1767 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1768 #define MIPS_NABI32 1
1769 #define STACK_ARGSIZE 8
1771 #define MIPS_NABI32 0
1772 #define STACK_ARGSIZE MIPS_REGSIZE
1776 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1781 CORE_ADDR struct_addr
;
1787 int stack_offset
= 0;
1789 /* Macros to round N up or down to the next A boundary; A must be
1791 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1792 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1794 /* First ensure that the stack and structure return address (if any)
1795 are properly aligned. The stack has to be at least 64-bit aligned
1796 even on 32-bit machines, because doubles must be 64-bit aligned.
1797 On at least one MIPS variant, stack frames need to be 128-bit
1798 aligned, so we round to this widest known alignment. */
1799 sp
= ROUND_DOWN (sp
, 16);
1800 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1802 /* Now make space on the stack for the args. We allocate more
1803 than necessary for EABI, because the first few arguments are
1804 passed in registers, but that's OK. */
1805 for (argnum
= 0; argnum
< nargs
; argnum
++)
1806 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1807 sp
-= ROUND_UP (len
, 16);
1809 /* Initialize the integer and float register pointers. */
1811 float_argreg
= FPA0_REGNUM
;
1813 /* the struct_return pointer occupies the first parameter-passing reg */
1815 write_register (argreg
++, struct_addr
);
1817 /* Now load as many as possible of the first arguments into
1818 registers, and push the rest onto the stack. Loop thru args
1819 from first to last. */
1820 for (argnum
= 0; argnum
< nargs
; argnum
++)
1823 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1824 value_ptr arg
= args
[argnum
];
1825 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1826 int len
= TYPE_LENGTH (arg_type
);
1827 enum type_code typecode
= TYPE_CODE (arg_type
);
1829 /* The EABI passes structures that do not fit in a register by
1830 reference. In all other cases, pass the structure by value. */
1831 if (MIPS_EABI
&& len
> MIPS_REGSIZE
&&
1832 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1834 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1835 typecode
= TYPE_CODE_PTR
;
1840 val
= (char *)VALUE_CONTENTS (arg
);
1842 /* 32-bit ABIs always start floating point arguments in an
1843 even-numbered floating point register. */
1844 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1845 && (float_argreg
& 1))
1848 /* Floating point arguments passed in registers have to be
1849 treated specially. On 32-bit architectures, doubles
1850 are passed in register pairs; the even register gets
1851 the low word, and the odd register gets the high word.
1852 On non-EABI processors, the first two floating point arguments are
1853 also copied to general registers, because MIPS16 functions
1854 don't use float registers for arguments. This duplication of
1855 arguments in general registers can't hurt non-MIPS16 functions
1856 because those registers are normally skipped. */
1857 if (typecode
== TYPE_CODE_FLT
1858 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1859 && mips_fpu
!= MIPS_FPU_NONE
)
1861 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1863 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1864 unsigned long regval
;
1866 /* Write the low word of the double to the even register(s). */
1867 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1868 write_register (float_argreg
++, regval
);
1870 write_register (argreg
+1, regval
);
1872 /* Write the high word of the double to the odd register(s). */
1873 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1874 write_register (float_argreg
++, regval
);
1877 write_register (argreg
, regval
);
1884 /* This is a floating point value that fits entirely
1885 in a single register. */
1886 CORE_ADDR regval
= extract_address (val
, len
);
1887 write_register (float_argreg
++, regval
);
1890 write_register (argreg
, regval
);
1891 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1897 /* Copy the argument to general registers or the stack in
1898 register-sized pieces. Large arguments are split between
1899 registers and stack. */
1900 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1901 are treated specially: Irix cc passes them in registers
1902 where gcc sometimes puts them on the stack. For maximum
1903 compatibility, we will put them in both places. */
1905 int odd_sized_struct
= ((len
> MIPS_REGSIZE
) &&
1906 (len
% MIPS_REGSIZE
!= 0));
1909 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1911 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1913 /* Write this portion of the argument to the stack. */
1914 /* Should shorter than int integer values be
1915 promoted to int before being stored? */
1917 int longword_offset
= 0;
1918 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1919 if (STACK_ARGSIZE
== 8 &&
1920 (typecode
== TYPE_CODE_INT
||
1921 typecode
== TYPE_CODE_PTR
||
1922 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1923 longword_offset
= STACK_ARGSIZE
- len
;
1924 else if ((typecode
== TYPE_CODE_STRUCT
||
1925 typecode
== TYPE_CODE_UNION
) &&
1926 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1927 longword_offset
= STACK_ARGSIZE
- len
;
1929 write_memory (sp
+ stack_offset
+ longword_offset
,
1933 /* Note!!! This is NOT an else clause.
1934 Odd sized structs may go thru BOTH paths. */
1935 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1937 CORE_ADDR regval
= extract_address (val
, partial_len
);
1939 /* A non-floating-point argument being passed in a
1940 general register. If a struct or union, and if
1941 the remaining length is smaller than the register
1942 size, we have to adjust the register value on
1945 It does not seem to be necessary to do the
1946 same for integral types.
1948 Also don't do this adjustment on EABI targets. */
1951 TARGET_BYTE_ORDER
== BIG_ENDIAN
&&
1952 partial_len
< MIPS_REGSIZE
&&
1953 (typecode
== TYPE_CODE_STRUCT
||
1954 typecode
== TYPE_CODE_UNION
))
1955 regval
<<= ((MIPS_REGSIZE
- partial_len
) *
1958 write_register (argreg
, regval
);
1961 /* If this is the old ABI, prevent subsequent floating
1962 point arguments from being passed in floating point
1965 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1971 /* The offset onto the stack at which we will start
1972 copying parameters (after the registers are used up)
1973 begins at (4 * MIPS_REGSIZE) in the old ABI. This
1974 leaves room for the "home" area for register parameters.
1976 In the new EABI (and the NABI32), the 8 register parameters
1977 do not have "home" stack space reserved for them, so the
1978 stack offset does not get incremented until after
1979 we have used up the 8 parameter registers. */
1981 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
1983 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
1988 /* Set the return address register to point to the entry
1989 point of the program, where a breakpoint lies in wait. */
1990 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1992 /* Return adjusted stack pointer. */
1997 mips_push_register(CORE_ADDR
*sp
, int regno
)
1999 char buffer
[MAX_REGISTER_RAW_SIZE
];
2000 int regsize
= REGISTER_RAW_SIZE (regno
);
2003 read_register_gen (regno
, buffer
);
2004 write_memory (*sp
, buffer
, regsize
);
2007 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2008 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2011 mips_push_dummy_frame()
2014 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2015 xmalloc(sizeof(struct linked_proc_info
));
2016 mips_extra_func_info_t proc_desc
= &link
->info
;
2017 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2018 CORE_ADDR old_sp
= sp
;
2019 link
->next
= linked_proc_desc_table
;
2020 linked_proc_desc_table
= link
;
2022 /* FIXME! are these correct ? */
2023 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2024 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2025 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2026 #define FLOAT_SINGLE_REG_SAVE_MASK \
2027 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2029 * The registers we must save are all those not preserved across
2030 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2031 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2032 * and FP Control/Status registers.
2035 * Dummy frame layout:
2038 * Saved MMHI, MMLO, FPC_CSR
2043 * Saved D18 (i.e. F19, F18)
2045 * Saved D0 (i.e. F1, F0)
2046 * Argument build area and stack arguments written via mips_push_arguments
2050 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2051 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2052 PROC_FRAME_OFFSET(proc_desc
) = 0;
2053 PROC_FRAME_ADJUST(proc_desc
) = 0;
2054 mips_push_register (&sp
, PC_REGNUM
);
2055 mips_push_register (&sp
, HI_REGNUM
);
2056 mips_push_register (&sp
, LO_REGNUM
);
2057 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2059 /* Save general CPU registers */
2060 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2061 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2062 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_REGSIZE
;
2063 for (ireg
= 32; --ireg
>= 0; )
2064 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2065 mips_push_register (&sp
, ireg
);
2067 /* Save floating point registers starting with high order word */
2068 PROC_FREG_MASK(proc_desc
) =
2069 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2070 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2071 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2073 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2074 for (ireg
= 32; --ireg
>= 0; )
2075 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2076 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2078 /* Update the frame pointer for the call dummy and the stack pointer.
2079 Set the procedure's starting and ending addresses to point to the
2080 call dummy address at the entry point. */
2081 write_register (PUSH_FP_REGNUM
, old_sp
);
2082 write_register (SP_REGNUM
, sp
);
2083 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2084 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2085 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2086 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2092 register int regnum
;
2093 struct frame_info
*frame
= get_current_frame ();
2094 CORE_ADDR new_sp
= FRAME_FP (frame
);
2096 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
2098 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2099 if (frame
->saved_regs
== NULL
)
2100 mips_find_saved_regs (frame
);
2101 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2103 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2104 && frame
->saved_regs
[regnum
])
2105 write_register (regnum
,
2106 read_memory_integer (frame
->saved_regs
[regnum
],
2109 write_register (SP_REGNUM
, new_sp
);
2110 flush_cached_frames ();
2112 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2114 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2116 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2118 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2120 if (&pi_ptr
->info
== proc_desc
)
2125 error ("Can't locate dummy extra frame info\n");
2127 if (prev_ptr
!= NULL
)
2128 prev_ptr
->next
= pi_ptr
->next
;
2130 linked_proc_desc_table
= pi_ptr
->next
;
2134 write_register (HI_REGNUM
,
2135 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
2136 write_register (LO_REGNUM
,
2137 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
2138 if (mips_fpu
!= MIPS_FPU_NONE
)
2139 write_register (FCRCS_REGNUM
,
2140 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
2145 mips_print_register (regnum
, all
)
2148 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2150 /* Get the data in raw format. */
2151 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2153 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2157 /* If an even floating point register, also print as double. */
2158 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2159 && !((regnum
-FP0_REGNUM
) & 1))
2160 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2162 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2164 read_relative_register_raw_bytes (regnum
, dbuffer
);
2165 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2166 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2168 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2169 val_print (builtin_type_double
, dbuffer
, 0,
2170 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2171 printf_filtered ("); ");
2173 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2175 /* The problem with printing numeric register names (r26, etc.) is that
2176 the user can't use them on input. Probably the best solution is to
2177 fix it so that either the numeric or the funky (a2, etc.) names
2178 are accepted on input. */
2179 if (regnum
< MIPS_NUMREGS
)
2180 printf_filtered ("(r%d): ", regnum
);
2182 printf_filtered (": ");
2184 /* If virtual format is floating, print it that way. */
2185 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2186 if (FP_REGISTER_DOUBLE
)
2187 { /* show 8-byte floats as float AND double: */
2188 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2190 printf_filtered (" (float) ");
2191 val_print (builtin_type_float
, raw_buffer
+ offset
, 0,
2192 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2193 printf_filtered (", (double) ");
2194 val_print (builtin_type_double
, raw_buffer
, 0,
2195 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2198 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
2199 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2200 /* Else print as integer in hex. */
2202 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2203 'x', 0, gdb_stdout
);
2206 /* Replacement for generic do_registers_info.
2207 Print regs in pretty columns. */
2210 do_fp_register_row (regnum
)
2212 { /* do values for FP (float) regs */
2213 char *raw_buffer
[2];
2215 /* use HI and LO to control the order of combining two flt regs */
2216 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2217 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2218 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2219 int inv1
, inv2
, inv3
;
2221 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2222 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2223 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2225 /* Get the data in raw format. */
2226 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2227 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2228 if (REGISTER_RAW_SIZE(regnum
) == 4)
2230 /* 4-byte registers: we can fit two registers per row. */
2231 /* Also print every pair of 4-byte regs as an 8-byte double. */
2232 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2233 error ("can't read register %d (%s)",
2234 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2236 /* copy the two floats into one double, and unpack both */
2237 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2238 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2239 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2240 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2242 printf_filtered (inv1
? " %-5s: <invalid float>" :
2243 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2244 printf_filtered (inv2
? " %-5s: <invalid float>" :
2245 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2246 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2247 " dbl: %-24.17g\n", doub
);
2248 /* may want to do hex display here (future enhancement) */
2252 { /* eight byte registers: print each one as float AND as double. */
2253 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2255 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2256 flt1
= unpack_double (builtin_type_float
,
2257 &raw_buffer
[HI
][offset
], &inv1
);
2258 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2260 printf_filtered (inv1
? " %-5s: <invalid float>" :
2261 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2262 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2263 " dbl: %-24.17g\n", doub
);
2264 /* may want to do hex display here (future enhancement) */
2270 /* Print a row's worth of GP (int) registers, with name labels above */
2273 do_gp_register_row (regnum
)
2276 /* do values for GP (int) regs */
2277 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2278 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2280 int start_regnum
= regnum
;
2281 int numregs
= NUM_REGS
;
2283 /* start-sanitize-sky */
2284 #ifdef NUM_CORE_REGS
2285 numregs
= NUM_CORE_REGS
;
2287 /* end-sanitize-sky */
2289 /* For GP registers, we print a separate row of names above the vals */
2290 printf_filtered (" ");
2291 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2293 if (*REGISTER_NAME (regnum
) == '\0')
2294 continue; /* unused register */
2295 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2296 break; /* end the row: reached FP register */
2297 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2298 REGISTER_NAME (regnum
));
2301 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2302 start_regnum
); /* print the R0 to R31 names */
2304 regnum
= start_regnum
; /* go back to start of row */
2305 /* now print the values in hex, 4 or 8 to the row */
2306 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2308 if (*REGISTER_NAME (regnum
) == '\0')
2309 continue; /* unused register */
2310 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2311 break; /* end row: reached FP register */
2312 /* OK: get the data in raw format. */
2313 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2314 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2315 /* pad small registers */
2316 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2317 printf_filtered (" ");
2318 /* Now print the register value in hex, endian order. */
2319 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2320 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2321 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2323 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2324 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2325 printf_filtered (" ");
2328 if (col
> 0) /* ie. if we actually printed anything... */
2329 printf_filtered ("\n");
2334 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2337 mips_do_registers_info (regnum
, fpregs
)
2341 if (regnum
!= -1) /* do one specified register */
2343 if (*(REGISTER_NAME (regnum
)) == '\0')
2344 error ("Not a valid register for the current processor type");
2346 mips_print_register (regnum
, 0);
2347 printf_filtered ("\n");
2349 else /* do all (or most) registers */
2352 while (regnum
< NUM_REGS
)
2354 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2355 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2356 regnum
= do_fp_register_row (regnum
); /* FP regs */
2358 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2360 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2361 /* start-sanitize-sky */
2362 #ifdef NUM_CORE_REGS
2363 /* For the sky project, NUM_REGS includes the vector slaves,
2364 which are handled elsewhere */
2365 if (regnum
>= NUM_CORE_REGS
)
2368 /* end-sanitize-sky */
2373 /* Return number of args passed to a frame. described by FIP.
2374 Can return -1, meaning no way to tell. */
2377 mips_frame_num_args (frame
)
2378 struct frame_info
*frame
;
2380 #if 0 /* FIXME Use or lose this! */
2381 struct chain_info_t
*p
;
2383 p
= mips_find_cached_frame (FRAME_FP (frame
));
2385 return p
->the_info
.numargs
;
2390 /* Is this a branch with a delay slot? */
2392 static int is_delayed
PARAMS ((unsigned long));
2399 for (i
= 0; i
< NUMOPCODES
; ++i
)
2400 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2401 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2403 return (i
< NUMOPCODES
2404 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2405 | INSN_COND_BRANCH_DELAY
2406 | INSN_COND_BRANCH_LIKELY
)));
2410 mips_step_skips_delay (pc
)
2413 char buf
[MIPS_INSTLEN
];
2415 /* There is no branch delay slot on MIPS16. */
2416 if (pc_is_mips16 (pc
))
2419 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2420 /* If error reading memory, guess that it is not a delayed branch. */
2422 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2426 /* Skip the PC past function prologue instructions (32-bit version).
2427 This is a helper function for mips_skip_prologue. */
2430 mips32_skip_prologue (pc
, lenient
)
2431 CORE_ADDR pc
; /* starting PC to search from */
2436 int seen_sp_adjust
= 0;
2437 int load_immediate_bytes
= 0;
2439 /* Skip the typical prologue instructions. These are the stack adjustment
2440 instruction and the instructions that save registers on the stack
2441 or in the gcc frame. */
2442 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2444 unsigned long high_word
;
2446 inst
= mips_fetch_instruction (pc
);
2447 high_word
= (inst
>> 16) & 0xffff;
2450 if (lenient
&& is_delayed (inst
))
2454 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2455 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2457 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2458 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2460 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2461 /* start-sanitize-r5900 */
2462 || (inst
& 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */
2463 /* end-sanitize-r5900 */
2464 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2465 && (inst
& 0x001F0000)) /* reg != $zero */
2468 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2470 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2472 continue; /* reg != $zero */
2474 /* move $s8,$sp. With different versions of gas this will be either
2475 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2476 Accept any one of these. */
2477 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2480 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2482 else if (high_word
== 0x3c1c) /* lui $gp,n */
2484 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2486 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2487 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2489 /* The following instructions load $at or $t0 with an immediate
2490 value in preparation for a stack adjustment via
2491 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2492 a local variable, so we accept them only before a stack adjustment
2493 instruction was seen. */
2494 else if (!seen_sp_adjust
)
2496 if (high_word
== 0x3c01 || /* lui $at,n */
2497 high_word
== 0x3c08) /* lui $t0,n */
2499 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2502 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2503 high_word
== 0x3508 || /* ori $t0,$t0,n */
2504 high_word
== 0x3401 || /* ori $at,$zero,n */
2505 high_word
== 0x3408) /* ori $t0,$zero,n */
2507 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2517 /* In a frameless function, we might have incorrectly
2518 skipped some load immediate instructions. Undo the skipping
2519 if the load immediate was not followed by a stack adjustment. */
2520 if (load_immediate_bytes
&& !seen_sp_adjust
)
2521 pc
-= load_immediate_bytes
;
2525 /* Skip the PC past function prologue instructions (16-bit version).
2526 This is a helper function for mips_skip_prologue. */
2529 mips16_skip_prologue (pc
, lenient
)
2530 CORE_ADDR pc
; /* starting PC to search from */
2534 int extend_bytes
= 0;
2535 int prev_extend_bytes
;
2537 /* Table of instructions likely to be found in a function prologue. */
2540 unsigned short inst
;
2541 unsigned short mask
;
2544 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2545 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2546 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2547 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2548 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2549 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2550 { 0x673d, 0xffff }, /* move $s1,sp */
2551 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2552 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2553 { 0xe809, 0xf81f }, /* entry pseudo-op */
2554 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2555 { 0, 0 } /* end of table marker */
2558 /* Skip the typical prologue instructions. These are the stack adjustment
2559 instruction and the instructions that save registers on the stack
2560 or in the gcc frame. */
2561 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2563 unsigned short inst
;
2566 inst
= mips_fetch_instruction (pc
);
2568 /* Normally we ignore an extend instruction. However, if it is
2569 not followed by a valid prologue instruction, we must adjust
2570 the pc back over the extend so that it won't be considered
2571 part of the prologue. */
2572 if ((inst
& 0xf800) == 0xf000) /* extend */
2574 extend_bytes
= MIPS16_INSTLEN
;
2577 prev_extend_bytes
= extend_bytes
;
2580 /* Check for other valid prologue instructions besides extend. */
2581 for (i
= 0; table
[i
].mask
!= 0; i
++)
2582 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2584 if (table
[i
].mask
!= 0) /* it was in table? */
2585 continue; /* ignore it */
2586 else /* non-prologue */
2588 /* Return the current pc, adjusted backwards by 2 if
2589 the previous instruction was an extend. */
2590 return pc
- prev_extend_bytes
;
2596 /* To skip prologues, I use this predicate. Returns either PC itself
2597 if the code at PC does not look like a function prologue; otherwise
2598 returns an address that (if we're lucky) follows the prologue. If
2599 LENIENT, then we must skip everything which is involved in setting
2600 up the frame (it's OK to skip more, just so long as we don't skip
2601 anything which might clobber the registers which are being saved.
2602 We must skip more in the case where part of the prologue is in the
2603 delay slot of a non-prologue instruction). */
2606 mips_skip_prologue (pc
, lenient
)
2610 /* See if we can determine the end of the prologue via the symbol table.
2611 If so, then return either PC, or the PC after the prologue, whichever
2614 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2616 if (post_prologue_pc
!= 0)
2617 return max (pc
, post_prologue_pc
);
2619 /* Can't determine prologue from the symbol table, need to examine
2622 if (pc_is_mips16 (pc
))
2623 return mips16_skip_prologue (pc
, lenient
);
2625 return mips32_skip_prologue (pc
, lenient
);
2629 /* The lenient prologue stuff should be superseded by the code in
2630 init_extra_frame_info which looks to see whether the stores mentioned
2631 in the proc_desc have actually taken place. */
2633 /* Is address PC in the prologue (loosely defined) for function at
2637 mips_in_lenient_prologue (startaddr
, pc
)
2638 CORE_ADDR startaddr
;
2641 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2642 return pc
>= startaddr
&& pc
< end_prologue
;
2646 /* Given a return value in `regbuf' with a type `valtype',
2647 extract and copy its value into `valbuf'. */
2649 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2650 struct type
*valtype
;
2651 char regbuf
[REGISTER_BYTES
];
2656 int len
= TYPE_LENGTH (valtype
);
2659 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2660 && (mips_fpu
== MIPS_FPU_DOUBLE
2661 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2662 regnum
= FP0_REGNUM
;
2664 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2665 { /* "un-left-justify" the value from the register */
2666 if (len
< REGISTER_RAW_SIZE (regnum
))
2667 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2668 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2669 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2670 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2671 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2672 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2674 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2675 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2678 /* Given a return value in `regbuf' with a type `valtype',
2679 write it's value into the appropriate register. */
2681 mips_store_return_value (valtype
, valbuf
)
2682 struct type
*valtype
;
2687 int len
= TYPE_LENGTH (valtype
);
2688 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2691 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2692 && (mips_fpu
== MIPS_FPU_DOUBLE
2693 || (mips_fpu
== MIPS_FPU_SINGLE
&& len
<= MIPS_REGSIZE
)))
2694 regnum
= FP0_REGNUM
;
2696 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2697 { /* "left-justify" the value in the register */
2698 if (len
< REGISTER_RAW_SIZE (regnum
))
2699 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2700 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2701 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2702 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2703 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2704 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2706 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2707 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2708 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2709 len
> REGISTER_RAW_SIZE (regnum
) ?
2710 len
: REGISTER_RAW_SIZE (regnum
));
2713 /* Exported procedure: Is PC in the signal trampoline code */
2716 in_sigtramp (pc
, ignore
)
2718 char *ignore
; /* function name */
2720 if (sigtramp_address
== 0)
2722 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2725 /* Command to set FPU type. mips_fpu_string will have been set to the
2726 user's argument. Set mips_fpu based on mips_fpu_string, and then
2727 canonicalize mips_fpu_string. */
2731 mips_set_fpu_command (args
, from_tty
, c
)
2734 struct cmd_list_element
*c
;
2738 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
2739 mips_fpu
= MIPS_FPU_DOUBLE
;
2740 else if (strcasecmp (mips_fpu_string
, "double") == 0
2741 || strcasecmp (mips_fpu_string
, "on") == 0
2742 || strcasecmp (mips_fpu_string
, "1") == 0
2743 || strcasecmp (mips_fpu_string
, "yes") == 0)
2744 mips_fpu
= MIPS_FPU_DOUBLE
;
2745 else if (strcasecmp (mips_fpu_string
, "none") == 0
2746 || strcasecmp (mips_fpu_string
, "off") == 0
2747 || strcasecmp (mips_fpu_string
, "0") == 0
2748 || strcasecmp (mips_fpu_string
, "no") == 0)
2749 mips_fpu
= MIPS_FPU_NONE
;
2750 else if (strcasecmp (mips_fpu_string
, "single") == 0)
2751 mips_fpu
= MIPS_FPU_SINGLE
;
2753 err
= strsave (mips_fpu_string
);
2755 if (mips_fpu_string
!= NULL
)
2756 free (mips_fpu_string
);
2760 case MIPS_FPU_DOUBLE
:
2761 mips_fpu_string
= strsave ("double");
2763 case MIPS_FPU_SINGLE
:
2764 mips_fpu_string
= strsave ("single");
2767 mips_fpu_string
= strsave ("none");
2773 struct cleanup
*cleanups
= make_cleanup (free
, err
);
2774 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
2776 do_cleanups (cleanups
);
2781 mips_show_fpu_command (args
, from_tty
, c
)
2784 struct cmd_list_element
*c
;
2788 /* Command to set the processor type. */
2791 mips_set_processor_type_command (args
, from_tty
)
2797 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
2799 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
2800 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2801 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
2803 /* Restore the value. */
2804 tmp_mips_processor_type
= strsave (mips_processor_type
);
2809 if (!mips_set_processor_type (tmp_mips_processor_type
))
2811 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
2812 /* Restore its value. */
2813 tmp_mips_processor_type
= strsave (mips_processor_type
);
2818 mips_show_processor_type_command (args
, from_tty
)
2824 /* Modify the actual processor type. */
2827 mips_set_processor_type (str
)
2835 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
2837 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
2839 mips_processor_type
= str
;
2841 for (j
= 0; j
< NUM_REGS
; ++j
)
2842 /* FIXME - MIPS should be defining REGISTER_NAME() instead */
2843 gdb_register_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2847 /* FIXME tweak fpu flag too */
2854 /* Attempt to identify the particular processor model by reading the
2858 mips_read_processor_type ()
2862 prid
= read_register (PRID_REGNUM
);
2864 if ((prid
& ~0xf) == 0x700)
2865 return savestring ("r3041", strlen("r3041"));
2870 /* Just like reinit_frame_cache, but with the right arguments to be
2871 callable as an sfunc. */
2874 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2877 struct cmd_list_element
*c
;
2879 reinit_frame_cache ();
2883 gdb_print_insn_mips (memaddr
, info
)
2885 disassemble_info
*info
;
2887 mips_extra_func_info_t proc_desc
;
2889 /* Search for the function containing this address. Set the low bit
2890 of the address when searching, in case we were given an even address
2891 that is the start of a 16-bit function. If we didn't do this,
2892 the search would fail because the symbol table says the function
2893 starts at an odd address, i.e. 1 byte past the given address. */
2894 memaddr
= ADDR_BITS_REMOVE (memaddr
);
2895 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
2897 /* Make an attempt to determine if this is a 16-bit function. If
2898 the procedure descriptor exists and the address therein is odd,
2899 it's definitely a 16-bit function. Otherwise, we have to just
2900 guess that if the address passed in is odd, it's 16-bits. */
2902 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
2904 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
2906 /* Round down the instruction address to the appropriate boundary. */
2907 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2909 /* Call the appropriate disassembler based on the target endian-ness. */
2910 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2911 return print_insn_big_mips (memaddr
, info
);
2913 return print_insn_little_mips (memaddr
, info
);
2916 /* Old-style breakpoint macros.
2917 The IDT board uses an unusual breakpoint value, and sometimes gets
2918 confused when it sees the usual MIPS breakpoint instruction. */
2920 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
2921 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
2922 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
2923 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
2924 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
2925 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
2926 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
2927 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
2929 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2930 counter value to determine whether a 16- or 32-bit breakpoint should be
2931 used. It returns a pointer to a string of bytes that encode a breakpoint
2932 instruction, stores the length of the string to *lenptr, and adjusts pc
2933 (if necessary) to point to the actual memory location where the
2934 breakpoint should be inserted. */
2936 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2940 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2942 if (pc_is_mips16 (*pcptr
))
2944 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2945 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2946 *lenptr
= sizeof(mips16_big_breakpoint
);
2947 return mips16_big_breakpoint
;
2951 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2952 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
2953 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
2955 *lenptr
= sizeof(big_breakpoint
);
2957 if (strcmp (target_shortname
, "mips") == 0)
2958 return idt_big_breakpoint
;
2959 else if (strcmp (target_shortname
, "ddb") == 0
2960 || strcmp (target_shortname
, "pmon") == 0
2961 || strcmp (target_shortname
, "lsi") == 0)
2962 return pmon_big_breakpoint
;
2964 return big_breakpoint
;
2969 if (pc_is_mips16 (*pcptr
))
2971 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2972 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
2973 *lenptr
= sizeof(mips16_little_breakpoint
);
2974 return mips16_little_breakpoint
;
2978 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2979 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
2980 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
2982 *lenptr
= sizeof(little_breakpoint
);
2984 if (strcmp (target_shortname
, "mips") == 0)
2985 return idt_little_breakpoint
;
2986 else if (strcmp (target_shortname
, "ddb") == 0
2987 || strcmp (target_shortname
, "pmon") == 0
2988 || strcmp (target_shortname
, "lsi") == 0)
2989 return pmon_little_breakpoint
;
2991 return little_breakpoint
;
2996 /* If PC is in a mips16 call or return stub, return the address of the target
2997 PC, which is either the callee or the caller. There are several
2998 cases which must be handled:
3000 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3001 target PC is in $31 ($ra).
3002 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3003 and the target PC is in $2.
3004 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3005 before the jal instruction, this is effectively a call stub
3006 and the the target PC is in $2. Otherwise this is effectively
3007 a return stub and the target PC is in $18.
3009 See the source code for the stubs in gcc/config/mips/mips16.S for
3012 This function implements the SKIP_TRAMPOLINE_CODE macro.
3020 CORE_ADDR start_addr
;
3022 /* Find the starting address and name of the function containing the PC. */
3023 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3026 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3027 target PC is in $31 ($ra). */
3028 if (strcmp (name
, "__mips16_ret_sf") == 0
3029 || strcmp (name
, "__mips16_ret_df") == 0)
3030 return read_register (RA_REGNUM
);
3032 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3034 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3035 and the target PC is in $2. */
3036 if (name
[19] >= '0' && name
[19] <= '9')
3037 return read_register (2);
3039 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3040 before the jal instruction, this is effectively a call stub
3041 and the the target PC is in $2. Otherwise this is effectively
3042 a return stub and the target PC is in $18. */
3043 else if (name
[19] == 's' || name
[19] == 'd')
3045 if (pc
== start_addr
)
3047 /* Check if the target of the stub is a compiler-generated
3048 stub. Such a stub for a function bar might have a name
3049 like __fn_stub_bar, and might look like this:
3054 la $1,bar (becomes a lui/addiu pair)
3056 So scan down to the lui/addi and extract the target
3057 address from those two instructions. */
3059 CORE_ADDR target_pc
= read_register (2);
3063 /* See if the name of the target function is __fn_stub_*. */
3064 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3066 if (strncmp (name
, "__fn_stub_", 10) != 0
3067 && strcmp (name
, "etext") != 0
3068 && strcmp (name
, "_etext") != 0)
3071 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3072 The limit on the search is arbitrarily set to 20
3073 instructions. FIXME. */
3074 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3076 inst
= mips_fetch_instruction (target_pc
);
3077 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3078 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3079 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3080 return pc
| (inst
& 0xffff); /* low word */
3083 /* Couldn't find the lui/addui pair, so return stub address. */
3087 /* This is the 'return' part of a call stub. The return
3088 address is in $r18. */
3089 return read_register (18);
3092 return 0; /* not a stub */
3096 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3097 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3100 mips_in_call_stub (pc
, name
)
3104 CORE_ADDR start_addr
;
3106 /* Find the starting address of the function containing the PC. If the
3107 caller didn't give us a name, look it up at the same time. */
3108 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3111 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3113 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3114 if (name
[19] >= '0' && name
[19] <= '9')
3116 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3117 before the jal instruction, this is effectively a call stub. */
3118 else if (name
[19] == 's' || name
[19] == 'd')
3119 return pc
== start_addr
;
3122 return 0; /* not a stub */
3126 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3127 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3130 mips_in_return_stub (pc
, name
)
3134 CORE_ADDR start_addr
;
3136 /* Find the starting address of the function containing the PC. */
3137 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3140 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3141 if (strcmp (name
, "__mips16_ret_sf") == 0
3142 || strcmp (name
, "__mips16_ret_df") == 0)
3145 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3146 i.e. after the jal instruction, this is effectively a return stub. */
3147 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3148 && (name
[19] == 's' || name
[19] == 'd')
3149 && pc
!= start_addr
)
3152 return 0; /* not a stub */
3156 /* Return non-zero if the PC is in a library helper function that should
3157 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3160 mips_ignore_helper (pc
)
3165 /* Find the starting address and name of the function containing the PC. */
3166 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3169 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3170 that we want to ignore. */
3171 return (strcmp (name
, "__mips16_ret_sf") == 0
3172 || strcmp (name
, "__mips16_ret_df") == 0);
3176 /* Return a location where we can set a breakpoint that will be hit
3177 when an inferior function call returns. This is normally the
3178 program's entry point. Executables that don't have an entry
3179 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3180 whose address is the location where the breakpoint should be placed. */
3183 mips_call_dummy_address ()
3185 struct minimal_symbol
*sym
;
3187 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3189 return SYMBOL_VALUE_ADDRESS (sym
);
3191 return entry_point_address ();
3195 _initialize_mips_tdep ()
3197 struct cmd_list_element
*c
;
3199 if (!tm_print_insn
) /* Someone may have already set it */
3200 tm_print_insn
= gdb_print_insn_mips
;
3202 /* Let the user turn off floating point and set the fence post for
3203 heuristic_proc_start. */
3205 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
3206 (char *) &mips_fpu_string
,
3207 "Set use of floating point coprocessor.\n\
3208 Set to `none' to avoid using floating point instructions when calling\n\
3209 functions or dealing with return values. Set to `single' to use only\n\
3210 single precision floating point as on the R4650. Set to `double' for\n\
3211 normal floating point support.",
3213 c
->function
.sfunc
= mips_set_fpu_command
;
3214 c
= add_show_from_set (c
, &showlist
);
3215 c
->function
.sfunc
= mips_show_fpu_command
;
3217 #ifndef MIPS_DEFAULT_FPU_TYPE
3218 mips_fpu
= MIPS_FPU_DOUBLE
;
3219 mips_fpu_string
= strsave ("double");
3221 mips_fpu
= MIPS_DEFAULT_FPU_TYPE
;
3224 case MIPS_FPU_DOUBLE
: mips_fpu_string
= strsave ("double"); break;
3225 case MIPS_FPU_SINGLE
: mips_fpu_string
= strsave ("single"); break;
3226 case MIPS_FPU_NONE
: mips_fpu_string
= strsave ("none"); break;
3230 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3231 (char *) &tmp_mips_processor_type
,
3232 "Set the type of MIPS processor in use.\n\
3233 Set this to be able to access processor-type-specific registers.\n\
3236 c
->function
.cfunc
= mips_set_processor_type_command
;
3237 c
= add_show_from_set (c
, &showlist
);
3238 c
->function
.cfunc
= mips_show_processor_type_command
;
3240 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3241 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3243 /* We really would like to have both "0" and "unlimited" work, but
3244 command.c doesn't deal with that. So make it a var_zinteger
3245 because the user can always use "999999" or some such for unlimited. */
3246 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3247 (char *) &heuristic_fence_post
,
3249 Set the distance searched for the start of a function.\n\
3250 If you are debugging a stripped executable, GDB needs to search through the\n\
3251 program for the start of a function. This command sets the distance of the\n\
3252 search. The only need to set it is when debugging a stripped executable.",
3254 /* We need to throw away the frame cache when we set this, since it
3255 might change our ability to get backtraces. */
3256 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3257 add_show_from_set (c
, &showlist
);
3259 /* Allow the user to control whether the upper bits of 64-bit
3260 addresses should be zeroed. */
3262 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3263 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3264 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3265 Without an argument, zeroing of upper address bits is enabled.", &setlist
),